1 /* 2 * QEMU RISC-V Boot Helper 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/datadir.h" 23 #include "qemu/units.h" 24 #include "qemu/error-report.h" 25 #include "exec/cpu-defs.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/riscv/boot.h" 29 #include "hw/riscv/boot_opensbi.h" 30 #include "elf.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/qtest.h" 33 34 #include <libfdt.h> 35 36 #if defined(TARGET_RISCV32) 37 #define fw_dynamic_info_data(__val) cpu_to_le32(__val) 38 #else 39 #define fw_dynamic_info_data(__val) cpu_to_le64(__val) 40 #endif 41 42 bool riscv_is_32_bit(MachineState *machine) 43 { 44 /* 45 * To determine if the CPU is 32-bit we need to check a few different CPUs. 46 * 47 * If the CPU starts with rv32 48 * If the CPU is a sifive 3 seriries CPU (E31, U34) 49 * If it's the Ibex CPU 50 */ 51 if (!strncmp(machine->cpu_type, "rv32", 4) || 52 (!strncmp(machine->cpu_type, "sifive", 6) && 53 machine->cpu_type[8] == '3') || 54 !strncmp(machine->cpu_type, "lowrisc-ibex", 12)) { 55 return true; 56 } else { 57 return false; 58 } 59 } 60 61 target_ulong riscv_calc_kernel_start_addr(MachineState *machine, 62 target_ulong firmware_end_addr) { 63 if (riscv_is_32_bit(machine)) { 64 return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); 65 } else { 66 return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); 67 } 68 } 69 70 target_ulong riscv_find_and_load_firmware(MachineState *machine, 71 const char *default_machine_firmware, 72 hwaddr firmware_load_addr, 73 symbol_fn_t sym_cb) 74 { 75 char *firmware_filename = NULL; 76 target_ulong firmware_end_addr = firmware_load_addr; 77 78 if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) { 79 /* 80 * The user didn't specify -bios, or has specified "-bios default". 81 * That means we are going to load the OpenSBI binary included in 82 * the QEMU source. 83 */ 84 firmware_filename = riscv_find_firmware(default_machine_firmware); 85 } else if (strcmp(machine->firmware, "none")) { 86 firmware_filename = riscv_find_firmware(machine->firmware); 87 } 88 89 if (firmware_filename) { 90 /* If not "none" load the firmware */ 91 firmware_end_addr = riscv_load_firmware(firmware_filename, 92 firmware_load_addr, sym_cb); 93 g_free(firmware_filename); 94 } 95 96 return firmware_end_addr; 97 } 98 99 char *riscv_find_firmware(const char *firmware_filename) 100 { 101 char *filename; 102 103 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); 104 if (filename == NULL) { 105 if (!qtest_enabled()) { 106 /* 107 * We only ship plain binary bios images in the QEMU source. 108 * With Spike machine that uses ELF images as the default bios, 109 * running QEMU test will complain hence let's suppress the error 110 * report for QEMU testing. 111 */ 112 error_report("Unable to load the RISC-V firmware \"%s\"", 113 firmware_filename); 114 exit(1); 115 } 116 } 117 118 return filename; 119 } 120 121 target_ulong riscv_load_firmware(const char *firmware_filename, 122 hwaddr firmware_load_addr, 123 symbol_fn_t sym_cb) 124 { 125 uint64_t firmware_entry, firmware_size, firmware_end; 126 127 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, 128 &firmware_entry, NULL, &firmware_end, NULL, 129 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 130 return firmware_end; 131 } 132 133 firmware_size = load_image_targphys_as(firmware_filename, 134 firmware_load_addr, 135 current_machine->ram_size, NULL); 136 137 if (firmware_size > 0) { 138 return firmware_load_addr + firmware_size; 139 } 140 141 error_report("could not load firmware '%s'", firmware_filename); 142 exit(1); 143 } 144 145 target_ulong riscv_load_kernel(const char *kernel_filename, 146 target_ulong kernel_start_addr, 147 symbol_fn_t sym_cb) 148 { 149 uint64_t kernel_entry; 150 151 if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, 152 &kernel_entry, NULL, NULL, NULL, 0, 153 EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 154 return kernel_entry; 155 } 156 157 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, 158 NULL, NULL, NULL) > 0) { 159 return kernel_entry; 160 } 161 162 if (load_image_targphys_as(kernel_filename, kernel_start_addr, 163 current_machine->ram_size, NULL) > 0) { 164 return kernel_start_addr; 165 } 166 167 error_report("could not load kernel '%s'", kernel_filename); 168 exit(1); 169 } 170 171 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, 172 uint64_t kernel_entry, hwaddr *start) 173 { 174 int size; 175 176 /* 177 * We want to put the initrd far enough into RAM that when the 178 * kernel is uncompressed it will not clobber the initrd. However 179 * on boards without much RAM we must ensure that we still leave 180 * enough room for a decent sized initrd, and on boards with large 181 * amounts of RAM we must avoid the initrd being so far up in RAM 182 * that it is outside lowmem and inaccessible to the kernel. 183 * So for boards with less than 256MB of RAM we put the initrd 184 * halfway into RAM, and for boards with 256MB of RAM or more we put 185 * the initrd at 128MB. 186 */ 187 *start = kernel_entry + MIN(mem_size / 2, 128 * MiB); 188 189 size = load_ramdisk(filename, *start, mem_size - *start); 190 if (size == -1) { 191 size = load_image_targphys(filename, *start, mem_size - *start); 192 if (size == -1) { 193 error_report("could not load ramdisk '%s'", filename); 194 exit(1); 195 } 196 } 197 198 return *start + size; 199 } 200 201 uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) 202 { 203 uint32_t temp, fdt_addr; 204 hwaddr dram_end = dram_base + mem_size; 205 int fdtsize = fdt_totalsize(fdt); 206 207 if (fdtsize <= 0) { 208 error_report("invalid device-tree"); 209 exit(1); 210 } 211 212 /* 213 * We should put fdt as far as possible to avoid kernel/initrd overwriting 214 * its content. But it should be addressable by 32 bit system as well. 215 * Thus, put it at an aligned address that less than fdt size from end of 216 * dram or 4GB whichever is lesser. 217 */ 218 temp = MIN(dram_end, 4096 * MiB); 219 fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); 220 221 fdt_pack(fdt); 222 /* copy in the device tree */ 223 qemu_fdt_dumpdtb(fdt, fdtsize); 224 225 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, 226 &address_space_memory); 227 228 return fdt_addr; 229 } 230 231 void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size, 232 uint32_t reset_vec_size, uint64_t kernel_entry) 233 { 234 struct fw_dynamic_info dinfo; 235 size_t dinfo_len; 236 237 dinfo.magic = fw_dynamic_info_data(FW_DYNAMIC_INFO_MAGIC_VALUE); 238 dinfo.version = fw_dynamic_info_data(FW_DYNAMIC_INFO_VERSION); 239 dinfo.next_mode = fw_dynamic_info_data(FW_DYNAMIC_INFO_NEXT_MODE_S); 240 dinfo.next_addr = fw_dynamic_info_data(kernel_entry); 241 dinfo.options = 0; 242 dinfo.boot_hart = 0; 243 dinfo_len = sizeof(dinfo); 244 245 /** 246 * copy the dynamic firmware info. This information is specific to 247 * OpenSBI but doesn't break any other firmware as long as they don't 248 * expect any certain value in "a2" register. 249 */ 250 if (dinfo_len > (rom_size - reset_vec_size)) { 251 error_report("not enough space to store dynamic firmware info"); 252 exit(1); 253 } 254 255 rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len, 256 rom_base + reset_vec_size, 257 &address_space_memory); 258 } 259 260 void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, 261 hwaddr rom_size, uint64_t kernel_entry, 262 uint32_t fdt_load_addr, void *fdt) 263 { 264 int i; 265 uint32_t start_addr_hi32 = 0x00000000; 266 267 #if defined(TARGET_RISCV64) 268 start_addr_hi32 = start_addr >> 32; 269 #endif 270 /* reset vector */ 271 uint32_t reset_vec[10] = { 272 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 273 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 274 0xf1402573, /* csrr a0, mhartid */ 275 #if defined(TARGET_RISCV32) 276 0x0202a583, /* lw a1, 32(t0) */ 277 0x0182a283, /* lw t0, 24(t0) */ 278 #elif defined(TARGET_RISCV64) 279 0x0202b583, /* ld a1, 32(t0) */ 280 0x0182b283, /* ld t0, 24(t0) */ 281 #endif 282 0x00028067, /* jr t0 */ 283 start_addr, /* start: .dword */ 284 start_addr_hi32, 285 fdt_load_addr, /* fdt_laddr: .dword */ 286 0x00000000, 287 /* fw_dyn: */ 288 }; 289 290 /* copy in the reset vector in little_endian byte order */ 291 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 292 reset_vec[i] = cpu_to_le32(reset_vec[i]); 293 } 294 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 295 rom_base, &address_space_memory); 296 riscv_rom_copy_firmware_info(rom_base, rom_size, sizeof(reset_vec), 297 kernel_entry); 298 299 return; 300 } 301