1 /* 2 * QEMU RISC-V Boot Helper 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "exec/cpu-defs.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/riscv/boot.h" 28 #include "hw/riscv/boot_opensbi.h" 29 #include "elf.h" 30 #include "sysemu/device_tree.h" 31 #include "sysemu/qtest.h" 32 33 #include <libfdt.h> 34 35 #if defined(TARGET_RISCV32) 36 #define fw_dynamic_info_data(__val) cpu_to_le32(__val) 37 #else 38 #define fw_dynamic_info_data(__val) cpu_to_le64(__val) 39 #endif 40 41 bool riscv_is_32_bit(MachineState *machine) 42 { 43 if (!strncmp(machine->cpu_type, "rv32", 4)) { 44 return true; 45 } else { 46 return false; 47 } 48 } 49 50 target_ulong riscv_calc_kernel_start_addr(MachineState *machine, 51 target_ulong firmware_end_addr) { 52 if (riscv_is_32_bit(machine)) { 53 return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); 54 } else { 55 return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); 56 } 57 } 58 59 target_ulong riscv_find_and_load_firmware(MachineState *machine, 60 const char *default_machine_firmware, 61 hwaddr firmware_load_addr, 62 symbol_fn_t sym_cb) 63 { 64 char *firmware_filename = NULL; 65 target_ulong firmware_end_addr = firmware_load_addr; 66 67 if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) { 68 /* 69 * The user didn't specify -bios, or has specified "-bios default". 70 * That means we are going to load the OpenSBI binary included in 71 * the QEMU source. 72 */ 73 firmware_filename = riscv_find_firmware(default_machine_firmware); 74 } else if (strcmp(machine->firmware, "none")) { 75 firmware_filename = riscv_find_firmware(machine->firmware); 76 } 77 78 if (firmware_filename) { 79 /* If not "none" load the firmware */ 80 firmware_end_addr = riscv_load_firmware(firmware_filename, 81 firmware_load_addr, sym_cb); 82 g_free(firmware_filename); 83 } 84 85 return firmware_end_addr; 86 } 87 88 char *riscv_find_firmware(const char *firmware_filename) 89 { 90 char *filename; 91 92 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); 93 if (filename == NULL) { 94 if (!qtest_enabled()) { 95 /* 96 * We only ship plain binary bios images in the QEMU source. 97 * With Spike machine that uses ELF images as the default bios, 98 * running QEMU test will complain hence let's suppress the error 99 * report for QEMU testing. 100 */ 101 error_report("Unable to load the RISC-V firmware \"%s\"", 102 firmware_filename); 103 exit(1); 104 } 105 } 106 107 return filename; 108 } 109 110 target_ulong riscv_load_firmware(const char *firmware_filename, 111 hwaddr firmware_load_addr, 112 symbol_fn_t sym_cb) 113 { 114 uint64_t firmware_entry, firmware_size, firmware_end; 115 116 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, 117 &firmware_entry, NULL, &firmware_end, NULL, 118 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 119 return firmware_end; 120 } 121 122 firmware_size = load_image_targphys_as(firmware_filename, 123 firmware_load_addr, 124 current_machine->ram_size, NULL); 125 126 if (firmware_size > 0) { 127 return firmware_load_addr + firmware_size; 128 } 129 130 error_report("could not load firmware '%s'", firmware_filename); 131 exit(1); 132 } 133 134 target_ulong riscv_load_kernel(const char *kernel_filename, 135 target_ulong kernel_start_addr, 136 symbol_fn_t sym_cb) 137 { 138 uint64_t kernel_entry; 139 140 if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, 141 &kernel_entry, NULL, NULL, NULL, 0, 142 EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 143 return kernel_entry; 144 } 145 146 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, 147 NULL, NULL, NULL) > 0) { 148 return kernel_entry; 149 } 150 151 if (load_image_targphys_as(kernel_filename, kernel_start_addr, 152 current_machine->ram_size, NULL) > 0) { 153 return kernel_start_addr; 154 } 155 156 error_report("could not load kernel '%s'", kernel_filename); 157 exit(1); 158 } 159 160 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, 161 uint64_t kernel_entry, hwaddr *start) 162 { 163 int size; 164 165 /* 166 * We want to put the initrd far enough into RAM that when the 167 * kernel is uncompressed it will not clobber the initrd. However 168 * on boards without much RAM we must ensure that we still leave 169 * enough room for a decent sized initrd, and on boards with large 170 * amounts of RAM we must avoid the initrd being so far up in RAM 171 * that it is outside lowmem and inaccessible to the kernel. 172 * So for boards with less than 256MB of RAM we put the initrd 173 * halfway into RAM, and for boards with 256MB of RAM or more we put 174 * the initrd at 128MB. 175 */ 176 *start = kernel_entry + MIN(mem_size / 2, 128 * MiB); 177 178 size = load_ramdisk(filename, *start, mem_size - *start); 179 if (size == -1) { 180 size = load_image_targphys(filename, *start, mem_size - *start); 181 if (size == -1) { 182 error_report("could not load ramdisk '%s'", filename); 183 exit(1); 184 } 185 } 186 187 return *start + size; 188 } 189 190 uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) 191 { 192 uint32_t temp, fdt_addr; 193 hwaddr dram_end = dram_base + mem_size; 194 int fdtsize = fdt_totalsize(fdt); 195 196 if (fdtsize <= 0) { 197 error_report("invalid device-tree"); 198 exit(1); 199 } 200 201 /* 202 * We should put fdt as far as possible to avoid kernel/initrd overwriting 203 * its content. But it should be addressable by 32 bit system as well. 204 * Thus, put it at an aligned address that less than fdt size from end of 205 * dram or 4GB whichever is lesser. 206 */ 207 temp = MIN(dram_end, 4096 * MiB); 208 fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); 209 210 fdt_pack(fdt); 211 /* copy in the device tree */ 212 qemu_fdt_dumpdtb(fdt, fdtsize); 213 214 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, 215 &address_space_memory); 216 217 return fdt_addr; 218 } 219 220 void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size, 221 uint32_t reset_vec_size, uint64_t kernel_entry) 222 { 223 struct fw_dynamic_info dinfo; 224 size_t dinfo_len; 225 226 dinfo.magic = fw_dynamic_info_data(FW_DYNAMIC_INFO_MAGIC_VALUE); 227 dinfo.version = fw_dynamic_info_data(FW_DYNAMIC_INFO_VERSION); 228 dinfo.next_mode = fw_dynamic_info_data(FW_DYNAMIC_INFO_NEXT_MODE_S); 229 dinfo.next_addr = fw_dynamic_info_data(kernel_entry); 230 dinfo.options = 0; 231 dinfo.boot_hart = 0; 232 dinfo_len = sizeof(dinfo); 233 234 /** 235 * copy the dynamic firmware info. This information is specific to 236 * OpenSBI but doesn't break any other firmware as long as they don't 237 * expect any certain value in "a2" register. 238 */ 239 if (dinfo_len > (rom_size - reset_vec_size)) { 240 error_report("not enough space to store dynamic firmware info"); 241 exit(1); 242 } 243 244 rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len, 245 rom_base + reset_vec_size, 246 &address_space_memory); 247 } 248 249 void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, 250 hwaddr rom_size, uint64_t kernel_entry, 251 uint32_t fdt_load_addr, void *fdt) 252 { 253 int i; 254 uint32_t start_addr_hi32 = 0x00000000; 255 256 #if defined(TARGET_RISCV64) 257 start_addr_hi32 = start_addr >> 32; 258 #endif 259 /* reset vector */ 260 uint32_t reset_vec[10] = { 261 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 262 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 263 0xf1402573, /* csrr a0, mhartid */ 264 #if defined(TARGET_RISCV32) 265 0x0202a583, /* lw a1, 32(t0) */ 266 0x0182a283, /* lw t0, 24(t0) */ 267 #elif defined(TARGET_RISCV64) 268 0x0202b583, /* ld a1, 32(t0) */ 269 0x0182b283, /* ld t0, 24(t0) */ 270 #endif 271 0x00028067, /* jr t0 */ 272 start_addr, /* start: .dword */ 273 start_addr_hi32, 274 fdt_load_addr, /* fdt_laddr: .dword */ 275 0x00000000, 276 /* fw_dyn: */ 277 }; 278 279 /* copy in the reset vector in little_endian byte order */ 280 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 281 reset_vec[i] = cpu_to_le32(reset_vec[i]); 282 } 283 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 284 rom_base, &address_space_memory); 285 riscv_rom_copy_firmware_info(rom_base, rom_size, sizeof(reset_vec), 286 kernel_entry); 287 288 return; 289 } 290