xref: /openbmc/qemu/hw/riscv/boot.c (revision ad40be27)
1 /*
2  * QEMU RISC-V Boot Helper
3  *
4  * Copyright (c) 2017 SiFive, Inc.
5  * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/datadir.h"
23 #include "qemu/units.h"
24 #include "qemu/error-report.h"
25 #include "exec/cpu-defs.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/riscv/boot.h"
29 #include "hw/riscv/boot_opensbi.h"
30 #include "elf.h"
31 #include "sysemu/device_tree.h"
32 #include "sysemu/qtest.h"
33 #include "sysemu/kvm.h"
34 
35 #include <libfdt.h>
36 
37 bool riscv_is_32bit(RISCVHartArrayState *harts)
38 {
39     return harts->harts[0].env.misa_mxl_max == MXL_RV32;
40 }
41 
42 /*
43  * Return the per-socket PLIC hart topology configuration string
44  * (caller must free with g_free())
45  */
46 char *riscv_plic_hart_config_string(int hart_count)
47 {
48     g_autofree const char **vals = g_new(const char *, hart_count + 1);
49     int i;
50 
51     for (i = 0; i < hart_count; i++) {
52         CPUState *cs = qemu_get_cpu(i);
53         CPURISCVState *env = &RISCV_CPU(cs)->env;
54 
55         if (kvm_enabled()) {
56             vals[i] = "S";
57         } else if (riscv_has_ext(env, RVS)) {
58             vals[i] = "MS";
59         } else {
60             vals[i] = "M";
61         }
62     }
63     vals[i] = NULL;
64 
65     /* g_strjoinv() obliges us to cast away const here */
66     return g_strjoinv(",", (char **)vals);
67 }
68 
69 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
70                                           target_ulong firmware_end_addr) {
71     if (riscv_is_32bit(harts)) {
72         return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
73     } else {
74         return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB);
75     }
76 }
77 
78 target_ulong riscv_find_and_load_firmware(MachineState *machine,
79                                           const char *default_machine_firmware,
80                                           hwaddr firmware_load_addr,
81                                           symbol_fn_t sym_cb)
82 {
83     char *firmware_filename = NULL;
84     target_ulong firmware_end_addr = firmware_load_addr;
85 
86     if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) {
87         /*
88          * The user didn't specify -bios, or has specified "-bios default".
89          * That means we are going to load the OpenSBI binary included in
90          * the QEMU source.
91          */
92         firmware_filename = riscv_find_firmware(default_machine_firmware);
93     } else if (strcmp(machine->firmware, "none")) {
94         firmware_filename = riscv_find_firmware(machine->firmware);
95     }
96 
97     if (firmware_filename) {
98         /* If not "none" load the firmware */
99         firmware_end_addr = riscv_load_firmware(firmware_filename,
100                                                 firmware_load_addr, sym_cb);
101         g_free(firmware_filename);
102     }
103 
104     return firmware_end_addr;
105 }
106 
107 char *riscv_find_firmware(const char *firmware_filename)
108 {
109     char *filename;
110 
111     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename);
112     if (filename == NULL) {
113         if (!qtest_enabled()) {
114             /*
115              * We only ship plain binary bios images in the QEMU source.
116              * With Spike machine that uses ELF images as the default bios,
117              * running QEMU test will complain hence let's suppress the error
118              * report for QEMU testing.
119              */
120             error_report("Unable to load the RISC-V firmware \"%s\"",
121                          firmware_filename);
122             exit(1);
123         }
124     }
125 
126     return filename;
127 }
128 
129 target_ulong riscv_load_firmware(const char *firmware_filename,
130                                  hwaddr firmware_load_addr,
131                                  symbol_fn_t sym_cb)
132 {
133     uint64_t firmware_entry, firmware_size, firmware_end;
134 
135     if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
136                          &firmware_entry, NULL, &firmware_end, NULL,
137                          0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
138         return firmware_end;
139     }
140 
141     firmware_size = load_image_targphys_as(firmware_filename,
142                                            firmware_load_addr,
143                                            current_machine->ram_size, NULL);
144 
145     if (firmware_size > 0) {
146         return firmware_load_addr + firmware_size;
147     }
148 
149     error_report("could not load firmware '%s'", firmware_filename);
150     exit(1);
151 }
152 
153 target_ulong riscv_load_kernel(const char *kernel_filename,
154                                target_ulong kernel_start_addr,
155                                symbol_fn_t sym_cb)
156 {
157     uint64_t kernel_load_base, kernel_entry;
158 
159     /*
160      * NB: Use low address not ELF entry point to ensure that the fw_dynamic
161      * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL
162      * behaviour, as well as fw_dynamic with a raw binary, all of which jump to
163      * the (expected) load address load address. This allows kernels to have
164      * separate SBI and ELF entry points (used by FreeBSD, for example).
165      */
166     if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
167                          NULL, &kernel_load_base, NULL, NULL, 0,
168                          EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
169         return kernel_load_base;
170     }
171 
172     if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
173                        NULL, NULL, NULL) > 0) {
174         return kernel_entry;
175     }
176 
177     if (load_image_targphys_as(kernel_filename, kernel_start_addr,
178                                current_machine->ram_size, NULL) > 0) {
179         return kernel_start_addr;
180     }
181 
182     error_report("could not load kernel '%s'", kernel_filename);
183     exit(1);
184 }
185 
186 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
187                          uint64_t kernel_entry, hwaddr *start)
188 {
189     int size;
190 
191     /*
192      * We want to put the initrd far enough into RAM that when the
193      * kernel is uncompressed it will not clobber the initrd. However
194      * on boards without much RAM we must ensure that we still leave
195      * enough room for a decent sized initrd, and on boards with large
196      * amounts of RAM we must avoid the initrd being so far up in RAM
197      * that it is outside lowmem and inaccessible to the kernel.
198      * So for boards with less  than 256MB of RAM we put the initrd
199      * halfway into RAM, and for boards with 256MB of RAM or more we put
200      * the initrd at 128MB.
201      */
202     *start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
203 
204     size = load_ramdisk(filename, *start, mem_size - *start);
205     if (size == -1) {
206         size = load_image_targphys(filename, *start, mem_size - *start);
207         if (size == -1) {
208             error_report("could not load ramdisk '%s'", filename);
209             exit(1);
210         }
211     }
212 
213     return *start + size;
214 }
215 
216 uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
217 {
218     uint32_t temp, fdt_addr;
219     hwaddr dram_end = dram_base + mem_size;
220     int ret, fdtsize = fdt_totalsize(fdt);
221 
222     if (fdtsize <= 0) {
223         error_report("invalid device-tree");
224         exit(1);
225     }
226 
227     /*
228      * We should put fdt as far as possible to avoid kernel/initrd overwriting
229      * its content. But it should be addressable by 32 bit system as well.
230      * Thus, put it at an 16MB aligned address that less than fdt size from the
231      * end of dram or 3GB whichever is lesser.
232      */
233     temp = MIN(dram_end, 3072 * MiB);
234     fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
235 
236     ret = fdt_pack(fdt);
237     /* Should only fail if we've built a corrupted tree */
238     g_assert(ret == 0);
239     /* copy in the device tree */
240     qemu_fdt_dumpdtb(fdt, fdtsize);
241 
242     rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
243                           &address_space_memory);
244 
245     return fdt_addr;
246 }
247 
248 void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
249                                   hwaddr rom_size, uint32_t reset_vec_size,
250                                   uint64_t kernel_entry)
251 {
252     struct fw_dynamic_info dinfo;
253     size_t dinfo_len;
254 
255     if (sizeof(dinfo.magic) == 4) {
256         dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);
257         dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);
258         dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);
259         dinfo.next_addr = cpu_to_le32(kernel_entry);
260     } else {
261         dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE);
262         dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION);
263         dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S);
264         dinfo.next_addr = cpu_to_le64(kernel_entry);
265     }
266     dinfo.options = 0;
267     dinfo.boot_hart = 0;
268     dinfo_len = sizeof(dinfo);
269 
270     /**
271      * copy the dynamic firmware info. This information is specific to
272      * OpenSBI but doesn't break any other firmware as long as they don't
273      * expect any certain value in "a2" register.
274      */
275     if (dinfo_len > (rom_size - reset_vec_size)) {
276         error_report("not enough space to store dynamic firmware info");
277         exit(1);
278     }
279 
280     rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len,
281                            rom_base + reset_vec_size,
282                            &address_space_memory);
283 }
284 
285 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
286                                hwaddr start_addr,
287                                hwaddr rom_base, hwaddr rom_size,
288                                uint64_t kernel_entry,
289                                uint32_t fdt_load_addr, void *fdt)
290 {
291     int i;
292     uint32_t start_addr_hi32 = 0x00000000;
293 
294     if (!riscv_is_32bit(harts)) {
295         start_addr_hi32 = start_addr >> 32;
296     }
297     /* reset vector */
298     uint32_t reset_vec[10] = {
299         0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
300         0x02828613,                  /*     addi   a2, t0, %pcrel_lo(1b) */
301         0xf1402573,                  /*     csrr   a0, mhartid  */
302         0,
303         0,
304         0x00028067,                  /*     jr     t0 */
305         start_addr,                  /* start: .dword */
306         start_addr_hi32,
307         fdt_load_addr,               /* fdt_laddr: .dword */
308         0x00000000,
309                                      /* fw_dyn: */
310     };
311     if (riscv_is_32bit(harts)) {
312         reset_vec[3] = 0x0202a583;   /*     lw     a1, 32(t0) */
313         reset_vec[4] = 0x0182a283;   /*     lw     t0, 24(t0) */
314     } else {
315         reset_vec[3] = 0x0202b583;   /*     ld     a1, 32(t0) */
316         reset_vec[4] = 0x0182b283;   /*     ld     t0, 24(t0) */
317     }
318 
319     /* copy in the reset vector in little_endian byte order */
320     for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
321         reset_vec[i] = cpu_to_le32(reset_vec[i]);
322     }
323     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
324                           rom_base, &address_space_memory);
325     riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
326                                  kernel_entry);
327 
328     return;
329 }
330 
331 void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
332 {
333     CPUState *cs;
334 
335     for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
336         RISCVCPU *riscv_cpu = RISCV_CPU(cs);
337         riscv_cpu->env.kernel_addr = kernel_addr;
338         riscv_cpu->env.fdt_addr = fdt_addr;
339     }
340 }
341