1 /* 2 * QEMU RISC-V Boot Helper 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "exec/cpu-defs.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/riscv/boot.h" 28 #include "hw/riscv/boot_opensbi.h" 29 #include "elf.h" 30 #include "sysemu/device_tree.h" 31 #include "sysemu/qtest.h" 32 #include "sysemu/kvm.h" 33 #include "sysemu/reset.h" 34 35 #include <libfdt.h> 36 37 bool riscv_is_32bit(RISCVHartArrayState *harts) 38 { 39 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]); 40 return mcc->misa_mxl_max == MXL_RV32; 41 } 42 43 /* 44 * Return the per-socket PLIC hart topology configuration string 45 * (caller must free with g_free()) 46 */ 47 char *riscv_plic_hart_config_string(int hart_count) 48 { 49 g_autofree const char **vals = g_new(const char *, hart_count + 1); 50 int i; 51 52 for (i = 0; i < hart_count; i++) { 53 CPUState *cs = qemu_get_cpu(i); 54 CPURISCVState *env = &RISCV_CPU(cs)->env; 55 56 if (kvm_enabled()) { 57 vals[i] = "S"; 58 } else if (riscv_has_ext(env, RVS)) { 59 vals[i] = "MS"; 60 } else { 61 vals[i] = "M"; 62 } 63 } 64 vals[i] = NULL; 65 66 /* g_strjoinv() obliges us to cast away const here */ 67 return g_strjoinv(",", (char **)vals); 68 } 69 70 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, 71 target_ulong firmware_end_addr) { 72 if (riscv_is_32bit(harts)) { 73 return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); 74 } else { 75 return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); 76 } 77 } 78 79 const char *riscv_default_firmware_name(RISCVHartArrayState *harts) 80 { 81 if (riscv_is_32bit(harts)) { 82 return RISCV32_BIOS_BIN; 83 } 84 85 return RISCV64_BIOS_BIN; 86 } 87 88 static char *riscv_find_bios(const char *bios_filename) 89 { 90 char *filename; 91 92 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_filename); 93 if (filename == NULL) { 94 if (!qtest_enabled()) { 95 /* 96 * We only ship OpenSBI binary bios images in the QEMU source. 97 * For machines that use images other than the default bios, 98 * running QEMU test will complain hence let's suppress the error 99 * report for QEMU testing. 100 */ 101 error_report("Unable to find the RISC-V BIOS \"%s\"", 102 bios_filename); 103 exit(1); 104 } 105 } 106 107 return filename; 108 } 109 110 char *riscv_find_firmware(const char *firmware_filename, 111 const char *default_machine_firmware) 112 { 113 char *filename = NULL; 114 115 if ((!firmware_filename) || (!strcmp(firmware_filename, "default"))) { 116 /* 117 * The user didn't specify -bios, or has specified "-bios default". 118 * That means we are going to load the OpenSBI binary included in 119 * the QEMU source. 120 */ 121 filename = riscv_find_bios(default_machine_firmware); 122 } else if (strcmp(firmware_filename, "none")) { 123 filename = riscv_find_bios(firmware_filename); 124 } 125 126 return filename; 127 } 128 129 target_ulong riscv_find_and_load_firmware(MachineState *machine, 130 const char *default_machine_firmware, 131 hwaddr firmware_load_addr, 132 symbol_fn_t sym_cb) 133 { 134 char *firmware_filename; 135 target_ulong firmware_end_addr = firmware_load_addr; 136 137 firmware_filename = riscv_find_firmware(machine->firmware, 138 default_machine_firmware); 139 140 if (firmware_filename) { 141 /* If not "none" load the firmware */ 142 firmware_end_addr = riscv_load_firmware(firmware_filename, 143 firmware_load_addr, sym_cb); 144 g_free(firmware_filename); 145 } 146 147 return firmware_end_addr; 148 } 149 150 target_ulong riscv_load_firmware(const char *firmware_filename, 151 hwaddr firmware_load_addr, 152 symbol_fn_t sym_cb) 153 { 154 uint64_t firmware_entry, firmware_end; 155 ssize_t firmware_size; 156 157 g_assert(firmware_filename != NULL); 158 159 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, 160 &firmware_entry, NULL, &firmware_end, NULL, 161 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 162 return firmware_end; 163 } 164 165 firmware_size = load_image_targphys_as(firmware_filename, 166 firmware_load_addr, 167 current_machine->ram_size, NULL); 168 169 if (firmware_size > 0) { 170 return firmware_load_addr + firmware_size; 171 } 172 173 error_report("could not load firmware '%s'", firmware_filename); 174 exit(1); 175 } 176 177 static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) 178 { 179 const char *filename = machine->initrd_filename; 180 uint64_t mem_size = machine->ram_size; 181 void *fdt = machine->fdt; 182 hwaddr start, end; 183 ssize_t size; 184 185 g_assert(filename != NULL); 186 187 /* 188 * We want to put the initrd far enough into RAM that when the 189 * kernel is uncompressed it will not clobber the initrd. However 190 * on boards without much RAM we must ensure that we still leave 191 * enough room for a decent sized initrd, and on boards with large 192 * amounts of RAM, we put the initrd at 512MB to allow large kernels 193 * to boot. 194 * So for boards with less than 1GB of RAM we put the initrd 195 * halfway into RAM, and for boards with 1GB of RAM or more we put 196 * the initrd at 512MB. 197 */ 198 start = kernel_entry + MIN(mem_size / 2, 512 * MiB); 199 200 size = load_ramdisk(filename, start, mem_size - start); 201 if (size == -1) { 202 size = load_image_targphys(filename, start, mem_size - start); 203 if (size == -1) { 204 error_report("could not load ramdisk '%s'", filename); 205 exit(1); 206 } 207 } 208 209 /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ 210 if (fdt) { 211 end = start + size; 212 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); 213 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); 214 } 215 } 216 217 target_ulong riscv_load_kernel(MachineState *machine, 218 RISCVHartArrayState *harts, 219 target_ulong kernel_start_addr, 220 bool load_initrd, 221 symbol_fn_t sym_cb) 222 { 223 const char *kernel_filename = machine->kernel_filename; 224 uint64_t kernel_load_base, kernel_entry; 225 void *fdt = machine->fdt; 226 227 g_assert(kernel_filename != NULL); 228 229 /* 230 * NB: Use low address not ELF entry point to ensure that the fw_dynamic 231 * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL 232 * behaviour, as well as fw_dynamic with a raw binary, all of which jump to 233 * the (expected) load address load address. This allows kernels to have 234 * separate SBI and ELF entry points (used by FreeBSD, for example). 235 */ 236 if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, 237 NULL, &kernel_load_base, NULL, NULL, 0, 238 EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 239 kernel_entry = kernel_load_base; 240 goto out; 241 } 242 243 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, 244 NULL, NULL, NULL) > 0) { 245 goto out; 246 } 247 248 if (load_image_targphys_as(kernel_filename, kernel_start_addr, 249 current_machine->ram_size, NULL) > 0) { 250 kernel_entry = kernel_start_addr; 251 goto out; 252 } 253 254 error_report("could not load kernel '%s'", kernel_filename); 255 exit(1); 256 257 out: 258 /* 259 * For 32 bit CPUs 'kernel_entry' can be sign-extended by 260 * load_elf_ram_sym(). 261 */ 262 if (riscv_is_32bit(harts)) { 263 kernel_entry = extract64(kernel_entry, 0, 32); 264 } 265 266 if (load_initrd && machine->initrd_filename) { 267 riscv_load_initrd(machine, kernel_entry); 268 } 269 270 if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { 271 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 272 machine->kernel_cmdline); 273 } 274 275 return kernel_entry; 276 } 277 278 /* 279 * This function makes an assumption that the DRAM interval 280 * 'dram_base' + 'dram_size' is contiguous. 281 * 282 * Considering that 'dram_end' is the lowest value between 283 * the end of the DRAM block and MachineState->ram_size, the 284 * FDT location will vary according to 'dram_base': 285 * 286 * - if 'dram_base' is less that 3072 MiB, the FDT will be 287 * put at the lowest value between 3072 MiB and 'dram_end'; 288 * 289 * - if 'dram_base' is higher than 3072 MiB, the FDT will be 290 * put at 'dram_end'. 291 * 292 * The FDT is fdt_packed() during the calculation. 293 */ 294 uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, 295 MachineState *ms) 296 { 297 int ret = fdt_pack(ms->fdt); 298 hwaddr dram_end, temp; 299 int fdtsize; 300 301 /* Should only fail if we've built a corrupted tree */ 302 g_assert(ret == 0); 303 304 fdtsize = fdt_totalsize(ms->fdt); 305 if (fdtsize <= 0) { 306 error_report("invalid device-tree"); 307 exit(1); 308 } 309 310 /* 311 * A dram_size == 0, usually from a MemMapEntry[].size element, 312 * means that the DRAM block goes all the way to ms->ram_size. 313 */ 314 dram_end = dram_base; 315 dram_end += dram_size ? MIN(ms->ram_size, dram_size) : ms->ram_size; 316 317 /* 318 * We should put fdt as far as possible to avoid kernel/initrd overwriting 319 * its content. But it should be addressable by 32 bit system as well. 320 * Thus, put it at an 2MB aligned address that less than fdt size from the 321 * end of dram or 3GB whichever is lesser. 322 */ 323 temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; 324 325 return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); 326 } 327 328 /* 329 * 'fdt_addr' is received as hwaddr because boards might put 330 * the FDT beyond 32-bit addressing boundary. 331 */ 332 void riscv_load_fdt(hwaddr fdt_addr, void *fdt) 333 { 334 uint32_t fdtsize = fdt_totalsize(fdt); 335 336 /* copy in the device tree */ 337 qemu_fdt_dumpdtb(fdt, fdtsize); 338 339 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, 340 &address_space_memory); 341 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 342 rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); 343 } 344 345 void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, 346 hwaddr rom_size, uint32_t reset_vec_size, 347 uint64_t kernel_entry) 348 { 349 struct fw_dynamic_info dinfo; 350 size_t dinfo_len; 351 352 if (sizeof(dinfo.magic) == 4) { 353 dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); 354 dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION); 355 dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); 356 dinfo.next_addr = cpu_to_le32(kernel_entry); 357 } else { 358 dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); 359 dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION); 360 dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); 361 dinfo.next_addr = cpu_to_le64(kernel_entry); 362 } 363 dinfo.options = 0; 364 dinfo.boot_hart = 0; 365 dinfo_len = sizeof(dinfo); 366 367 /** 368 * copy the dynamic firmware info. This information is specific to 369 * OpenSBI but doesn't break any other firmware as long as they don't 370 * expect any certain value in "a2" register. 371 */ 372 if (dinfo_len > (rom_size - reset_vec_size)) { 373 error_report("not enough space to store dynamic firmware info"); 374 exit(1); 375 } 376 377 rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len, 378 rom_base + reset_vec_size, 379 &address_space_memory); 380 } 381 382 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, 383 hwaddr start_addr, 384 hwaddr rom_base, hwaddr rom_size, 385 uint64_t kernel_entry, 386 uint64_t fdt_load_addr) 387 { 388 int i; 389 uint32_t start_addr_hi32 = 0x00000000; 390 uint32_t fdt_load_addr_hi32 = 0x00000000; 391 392 if (!riscv_is_32bit(harts)) { 393 start_addr_hi32 = start_addr >> 32; 394 fdt_load_addr_hi32 = fdt_load_addr >> 32; 395 } 396 /* reset vector */ 397 uint32_t reset_vec[10] = { 398 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 399 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 400 0xf1402573, /* csrr a0, mhartid */ 401 0, 402 0, 403 0x00028067, /* jr t0 */ 404 start_addr, /* start: .dword */ 405 start_addr_hi32, 406 fdt_load_addr, /* fdt_laddr: .dword */ 407 fdt_load_addr_hi32, 408 /* fw_dyn: */ 409 }; 410 if (riscv_is_32bit(harts)) { 411 reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */ 412 reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */ 413 } else { 414 reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */ 415 reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ 416 } 417 418 if (!harts->harts[0].cfg.ext_zicsr) { 419 /* 420 * The Zicsr extension has been disabled, so let's ensure we don't 421 * run the CSR instruction. Let's fill the address with a non 422 * compressed nop. 423 */ 424 reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */ 425 } 426 427 /* copy in the reset vector in little_endian byte order */ 428 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 429 reset_vec[i] = cpu_to_le32(reset_vec[i]); 430 } 431 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 432 rom_base, &address_space_memory); 433 riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec), 434 kernel_entry); 435 } 436 437 void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr) 438 { 439 CPUState *cs; 440 441 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 442 RISCVCPU *riscv_cpu = RISCV_CPU(cs); 443 riscv_cpu->env.kernel_addr = kernel_addr; 444 riscv_cpu->env.fdt_addr = fdt_addr; 445 } 446 } 447 448 void riscv_setup_firmware_boot(MachineState *machine) 449 { 450 if (machine->kernel_filename) { 451 FWCfgState *fw_cfg; 452 fw_cfg = fw_cfg_find(); 453 454 assert(fw_cfg); 455 /* 456 * Expose the kernel, the command line, and the initrd in fw_cfg. 457 * We don't process them here at all, it's all left to the 458 * firmware. 459 */ 460 load_image_to_fw_cfg(fw_cfg, 461 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 462 machine->kernel_filename, 463 true); 464 load_image_to_fw_cfg(fw_cfg, 465 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 466 machine->initrd_filename, false); 467 468 if (machine->kernel_cmdline) { 469 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 470 strlen(machine->kernel_cmdline) + 1); 471 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 472 machine->kernel_cmdline); 473 } 474 } 475 } 476