1 /* 2 * QEMU RISC-V Boot Helper 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/datadir.h" 23 #include "qemu/units.h" 24 #include "qemu/error-report.h" 25 #include "exec/cpu-defs.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/riscv/boot.h" 29 #include "hw/riscv/boot_opensbi.h" 30 #include "elf.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/qtest.h" 33 34 #include <libfdt.h> 35 36 #if defined(TARGET_RISCV32) 37 #define fw_dynamic_info_data(__val) cpu_to_le32(__val) 38 #else 39 #define fw_dynamic_info_data(__val) cpu_to_le64(__val) 40 #endif 41 42 bool riscv_is_32_bit(MachineState *machine) 43 { 44 if (!strncmp(machine->cpu_type, "rv32", 4)) { 45 return true; 46 } else { 47 return false; 48 } 49 } 50 51 target_ulong riscv_calc_kernel_start_addr(MachineState *machine, 52 target_ulong firmware_end_addr) { 53 if (riscv_is_32_bit(machine)) { 54 return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); 55 } else { 56 return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); 57 } 58 } 59 60 target_ulong riscv_find_and_load_firmware(MachineState *machine, 61 const char *default_machine_firmware, 62 hwaddr firmware_load_addr, 63 symbol_fn_t sym_cb) 64 { 65 char *firmware_filename = NULL; 66 target_ulong firmware_end_addr = firmware_load_addr; 67 68 if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) { 69 /* 70 * The user didn't specify -bios, or has specified "-bios default". 71 * That means we are going to load the OpenSBI binary included in 72 * the QEMU source. 73 */ 74 firmware_filename = riscv_find_firmware(default_machine_firmware); 75 } else if (strcmp(machine->firmware, "none")) { 76 firmware_filename = riscv_find_firmware(machine->firmware); 77 } 78 79 if (firmware_filename) { 80 /* If not "none" load the firmware */ 81 firmware_end_addr = riscv_load_firmware(firmware_filename, 82 firmware_load_addr, sym_cb); 83 g_free(firmware_filename); 84 } 85 86 return firmware_end_addr; 87 } 88 89 char *riscv_find_firmware(const char *firmware_filename) 90 { 91 char *filename; 92 93 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); 94 if (filename == NULL) { 95 if (!qtest_enabled()) { 96 /* 97 * We only ship plain binary bios images in the QEMU source. 98 * With Spike machine that uses ELF images as the default bios, 99 * running QEMU test will complain hence let's suppress the error 100 * report for QEMU testing. 101 */ 102 error_report("Unable to load the RISC-V firmware \"%s\"", 103 firmware_filename); 104 exit(1); 105 } 106 } 107 108 return filename; 109 } 110 111 target_ulong riscv_load_firmware(const char *firmware_filename, 112 hwaddr firmware_load_addr, 113 symbol_fn_t sym_cb) 114 { 115 uint64_t firmware_entry, firmware_size, firmware_end; 116 117 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, 118 &firmware_entry, NULL, &firmware_end, NULL, 119 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 120 return firmware_end; 121 } 122 123 firmware_size = load_image_targphys_as(firmware_filename, 124 firmware_load_addr, 125 current_machine->ram_size, NULL); 126 127 if (firmware_size > 0) { 128 return firmware_load_addr + firmware_size; 129 } 130 131 error_report("could not load firmware '%s'", firmware_filename); 132 exit(1); 133 } 134 135 target_ulong riscv_load_kernel(const char *kernel_filename, 136 target_ulong kernel_start_addr, 137 symbol_fn_t sym_cb) 138 { 139 uint64_t kernel_entry; 140 141 if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, 142 &kernel_entry, NULL, NULL, NULL, 0, 143 EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 144 return kernel_entry; 145 } 146 147 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, 148 NULL, NULL, NULL) > 0) { 149 return kernel_entry; 150 } 151 152 if (load_image_targphys_as(kernel_filename, kernel_start_addr, 153 current_machine->ram_size, NULL) > 0) { 154 return kernel_start_addr; 155 } 156 157 error_report("could not load kernel '%s'", kernel_filename); 158 exit(1); 159 } 160 161 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, 162 uint64_t kernel_entry, hwaddr *start) 163 { 164 int size; 165 166 /* 167 * We want to put the initrd far enough into RAM that when the 168 * kernel is uncompressed it will not clobber the initrd. However 169 * on boards without much RAM we must ensure that we still leave 170 * enough room for a decent sized initrd, and on boards with large 171 * amounts of RAM we must avoid the initrd being so far up in RAM 172 * that it is outside lowmem and inaccessible to the kernel. 173 * So for boards with less than 256MB of RAM we put the initrd 174 * halfway into RAM, and for boards with 256MB of RAM or more we put 175 * the initrd at 128MB. 176 */ 177 *start = kernel_entry + MIN(mem_size / 2, 128 * MiB); 178 179 size = load_ramdisk(filename, *start, mem_size - *start); 180 if (size == -1) { 181 size = load_image_targphys(filename, *start, mem_size - *start); 182 if (size == -1) { 183 error_report("could not load ramdisk '%s'", filename); 184 exit(1); 185 } 186 } 187 188 return *start + size; 189 } 190 191 uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) 192 { 193 uint32_t temp, fdt_addr; 194 hwaddr dram_end = dram_base + mem_size; 195 int fdtsize = fdt_totalsize(fdt); 196 197 if (fdtsize <= 0) { 198 error_report("invalid device-tree"); 199 exit(1); 200 } 201 202 /* 203 * We should put fdt as far as possible to avoid kernel/initrd overwriting 204 * its content. But it should be addressable by 32 bit system as well. 205 * Thus, put it at an aligned address that less than fdt size from end of 206 * dram or 4GB whichever is lesser. 207 */ 208 temp = MIN(dram_end, 4096 * MiB); 209 fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); 210 211 fdt_pack(fdt); 212 /* copy in the device tree */ 213 qemu_fdt_dumpdtb(fdt, fdtsize); 214 215 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, 216 &address_space_memory); 217 218 return fdt_addr; 219 } 220 221 void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size, 222 uint32_t reset_vec_size, uint64_t kernel_entry) 223 { 224 struct fw_dynamic_info dinfo; 225 size_t dinfo_len; 226 227 dinfo.magic = fw_dynamic_info_data(FW_DYNAMIC_INFO_MAGIC_VALUE); 228 dinfo.version = fw_dynamic_info_data(FW_DYNAMIC_INFO_VERSION); 229 dinfo.next_mode = fw_dynamic_info_data(FW_DYNAMIC_INFO_NEXT_MODE_S); 230 dinfo.next_addr = fw_dynamic_info_data(kernel_entry); 231 dinfo.options = 0; 232 dinfo.boot_hart = 0; 233 dinfo_len = sizeof(dinfo); 234 235 /** 236 * copy the dynamic firmware info. This information is specific to 237 * OpenSBI but doesn't break any other firmware as long as they don't 238 * expect any certain value in "a2" register. 239 */ 240 if (dinfo_len > (rom_size - reset_vec_size)) { 241 error_report("not enough space to store dynamic firmware info"); 242 exit(1); 243 } 244 245 rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len, 246 rom_base + reset_vec_size, 247 &address_space_memory); 248 } 249 250 void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, 251 hwaddr rom_size, uint64_t kernel_entry, 252 uint32_t fdt_load_addr, void *fdt) 253 { 254 int i; 255 uint32_t start_addr_hi32 = 0x00000000; 256 257 #if defined(TARGET_RISCV64) 258 start_addr_hi32 = start_addr >> 32; 259 #endif 260 /* reset vector */ 261 uint32_t reset_vec[10] = { 262 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 263 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 264 0xf1402573, /* csrr a0, mhartid */ 265 #if defined(TARGET_RISCV32) 266 0x0202a583, /* lw a1, 32(t0) */ 267 0x0182a283, /* lw t0, 24(t0) */ 268 #elif defined(TARGET_RISCV64) 269 0x0202b583, /* ld a1, 32(t0) */ 270 0x0182b283, /* ld t0, 24(t0) */ 271 #endif 272 0x00028067, /* jr t0 */ 273 start_addr, /* start: .dword */ 274 start_addr_hi32, 275 fdt_load_addr, /* fdt_laddr: .dword */ 276 0x00000000, 277 /* fw_dyn: */ 278 }; 279 280 /* copy in the reset vector in little_endian byte order */ 281 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 282 reset_vec[i] = cpu_to_le32(reset_vec[i]); 283 } 284 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 285 rom_base, &address_space_memory); 286 riscv_rom_copy_firmware_info(rom_base, rom_size, sizeof(reset_vec), 287 kernel_entry); 288 289 return; 290 } 291