1 /* 2 * QEMU RISC-V Boot Helper 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/datadir.h" 23 #include "qemu/units.h" 24 #include "qemu/error-report.h" 25 #include "exec/cpu-defs.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/riscv/boot.h" 29 #include "hw/riscv/boot_opensbi.h" 30 #include "elf.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/qtest.h" 33 34 #include <libfdt.h> 35 36 bool riscv_is_32_bit(MachineState *machine) 37 { 38 /* 39 * To determine if the CPU is 32-bit we need to check a few different CPUs. 40 * 41 * If the CPU starts with rv32 42 * If the CPU is a sifive 3 seriries CPU (E31, U34) 43 * If it's the Ibex CPU 44 */ 45 if (!strncmp(machine->cpu_type, "rv32", 4) || 46 (!strncmp(machine->cpu_type, "sifive", 6) && 47 machine->cpu_type[8] == '3') || 48 !strncmp(machine->cpu_type, "lowrisc-ibex", 12)) { 49 return true; 50 } else { 51 return false; 52 } 53 } 54 55 target_ulong riscv_calc_kernel_start_addr(MachineState *machine, 56 target_ulong firmware_end_addr) { 57 if (riscv_is_32_bit(machine)) { 58 return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); 59 } else { 60 return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); 61 } 62 } 63 64 target_ulong riscv_find_and_load_firmware(MachineState *machine, 65 const char *default_machine_firmware, 66 hwaddr firmware_load_addr, 67 symbol_fn_t sym_cb) 68 { 69 char *firmware_filename = NULL; 70 target_ulong firmware_end_addr = firmware_load_addr; 71 72 if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) { 73 /* 74 * The user didn't specify -bios, or has specified "-bios default". 75 * That means we are going to load the OpenSBI binary included in 76 * the QEMU source. 77 */ 78 firmware_filename = riscv_find_firmware(default_machine_firmware); 79 } else if (strcmp(machine->firmware, "none")) { 80 firmware_filename = riscv_find_firmware(machine->firmware); 81 } 82 83 if (firmware_filename) { 84 /* If not "none" load the firmware */ 85 firmware_end_addr = riscv_load_firmware(firmware_filename, 86 firmware_load_addr, sym_cb); 87 g_free(firmware_filename); 88 } 89 90 return firmware_end_addr; 91 } 92 93 char *riscv_find_firmware(const char *firmware_filename) 94 { 95 char *filename; 96 97 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); 98 if (filename == NULL) { 99 if (!qtest_enabled()) { 100 /* 101 * We only ship plain binary bios images in the QEMU source. 102 * With Spike machine that uses ELF images as the default bios, 103 * running QEMU test will complain hence let's suppress the error 104 * report for QEMU testing. 105 */ 106 error_report("Unable to load the RISC-V firmware \"%s\"", 107 firmware_filename); 108 exit(1); 109 } 110 } 111 112 return filename; 113 } 114 115 target_ulong riscv_load_firmware(const char *firmware_filename, 116 hwaddr firmware_load_addr, 117 symbol_fn_t sym_cb) 118 { 119 uint64_t firmware_entry, firmware_size, firmware_end; 120 121 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, 122 &firmware_entry, NULL, &firmware_end, NULL, 123 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 124 return firmware_end; 125 } 126 127 firmware_size = load_image_targphys_as(firmware_filename, 128 firmware_load_addr, 129 current_machine->ram_size, NULL); 130 131 if (firmware_size > 0) { 132 return firmware_load_addr + firmware_size; 133 } 134 135 error_report("could not load firmware '%s'", firmware_filename); 136 exit(1); 137 } 138 139 target_ulong riscv_load_kernel(const char *kernel_filename, 140 target_ulong kernel_start_addr, 141 symbol_fn_t sym_cb) 142 { 143 uint64_t kernel_entry; 144 145 if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, 146 &kernel_entry, NULL, NULL, NULL, 0, 147 EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 148 return kernel_entry; 149 } 150 151 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, 152 NULL, NULL, NULL) > 0) { 153 return kernel_entry; 154 } 155 156 if (load_image_targphys_as(kernel_filename, kernel_start_addr, 157 current_machine->ram_size, NULL) > 0) { 158 return kernel_start_addr; 159 } 160 161 error_report("could not load kernel '%s'", kernel_filename); 162 exit(1); 163 } 164 165 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, 166 uint64_t kernel_entry, hwaddr *start) 167 { 168 int size; 169 170 /* 171 * We want to put the initrd far enough into RAM that when the 172 * kernel is uncompressed it will not clobber the initrd. However 173 * on boards without much RAM we must ensure that we still leave 174 * enough room for a decent sized initrd, and on boards with large 175 * amounts of RAM we must avoid the initrd being so far up in RAM 176 * that it is outside lowmem and inaccessible to the kernel. 177 * So for boards with less than 256MB of RAM we put the initrd 178 * halfway into RAM, and for boards with 256MB of RAM or more we put 179 * the initrd at 128MB. 180 */ 181 *start = kernel_entry + MIN(mem_size / 2, 128 * MiB); 182 183 size = load_ramdisk(filename, *start, mem_size - *start); 184 if (size == -1) { 185 size = load_image_targphys(filename, *start, mem_size - *start); 186 if (size == -1) { 187 error_report("could not load ramdisk '%s'", filename); 188 exit(1); 189 } 190 } 191 192 return *start + size; 193 } 194 195 uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) 196 { 197 uint32_t temp, fdt_addr; 198 hwaddr dram_end = dram_base + mem_size; 199 int fdtsize = fdt_totalsize(fdt); 200 201 if (fdtsize <= 0) { 202 error_report("invalid device-tree"); 203 exit(1); 204 } 205 206 /* 207 * We should put fdt as far as possible to avoid kernel/initrd overwriting 208 * its content. But it should be addressable by 32 bit system as well. 209 * Thus, put it at an aligned address that less than fdt size from end of 210 * dram or 4GB whichever is lesser. 211 */ 212 temp = MIN(dram_end, 4096 * MiB); 213 fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); 214 215 fdt_pack(fdt); 216 /* copy in the device tree */ 217 qemu_fdt_dumpdtb(fdt, fdtsize); 218 219 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, 220 &address_space_memory); 221 222 return fdt_addr; 223 } 224 225 void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, 226 hwaddr rom_size, uint32_t reset_vec_size, 227 uint64_t kernel_entry) 228 { 229 struct fw_dynamic_info dinfo; 230 size_t dinfo_len; 231 232 if (sizeof(dinfo.magic) == 4) { 233 dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); 234 dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION); 235 dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); 236 dinfo.next_addr = cpu_to_le32(kernel_entry); 237 } else { 238 dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); 239 dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION); 240 dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); 241 dinfo.next_addr = cpu_to_le64(kernel_entry); 242 } 243 dinfo.options = 0; 244 dinfo.boot_hart = 0; 245 dinfo_len = sizeof(dinfo); 246 247 /** 248 * copy the dynamic firmware info. This information is specific to 249 * OpenSBI but doesn't break any other firmware as long as they don't 250 * expect any certain value in "a2" register. 251 */ 252 if (dinfo_len > (rom_size - reset_vec_size)) { 253 error_report("not enough space to store dynamic firmware info"); 254 exit(1); 255 } 256 257 rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len, 258 rom_base + reset_vec_size, 259 &address_space_memory); 260 } 261 262 void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr start_addr, 263 hwaddr rom_base, hwaddr rom_size, 264 uint64_t kernel_entry, 265 uint32_t fdt_load_addr, void *fdt) 266 { 267 int i; 268 uint32_t start_addr_hi32 = 0x00000000; 269 270 if (!riscv_is_32_bit(machine)) { 271 start_addr_hi32 = start_addr >> 32; 272 } 273 /* reset vector */ 274 uint32_t reset_vec[10] = { 275 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 276 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 277 0xf1402573, /* csrr a0, mhartid */ 278 0, 279 0, 280 0x00028067, /* jr t0 */ 281 start_addr, /* start: .dword */ 282 start_addr_hi32, 283 fdt_load_addr, /* fdt_laddr: .dword */ 284 0x00000000, 285 /* fw_dyn: */ 286 }; 287 if (riscv_is_32_bit(machine)) { 288 reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */ 289 reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */ 290 } else { 291 reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */ 292 reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ 293 } 294 295 /* copy in the reset vector in little_endian byte order */ 296 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 297 reset_vec[i] = cpu_to_le32(reset_vec[i]); 298 } 299 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 300 rom_base, &address_space_memory); 301 riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec), 302 kernel_entry); 303 304 return; 305 } 306