xref: /openbmc/qemu/hw/riscv/boot.c (revision 30e702ab)
1 /*
2  * QEMU RISC-V Boot Helper
3  *
4  * Copyright (c) 2017 SiFive, Inc.
5  * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/datadir.h"
23 #include "qemu/units.h"
24 #include "qemu/error-report.h"
25 #include "exec/cpu-defs.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/riscv/boot.h"
29 #include "hw/riscv/boot_opensbi.h"
30 #include "elf.h"
31 #include "sysemu/device_tree.h"
32 #include "sysemu/qtest.h"
33 
34 #include <libfdt.h>
35 
36 bool riscv_is_32bit(RISCVHartArrayState *harts)
37 {
38     return harts->harts[0].env.misa_mxl_max == MXL_RV32;
39 }
40 
41 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
42                                           target_ulong firmware_end_addr) {
43     if (riscv_is_32bit(harts)) {
44         return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
45     } else {
46         return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB);
47     }
48 }
49 
50 target_ulong riscv_find_and_load_firmware(MachineState *machine,
51                                           const char *default_machine_firmware,
52                                           hwaddr firmware_load_addr,
53                                           symbol_fn_t sym_cb)
54 {
55     char *firmware_filename = NULL;
56     target_ulong firmware_end_addr = firmware_load_addr;
57 
58     if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) {
59         /*
60          * The user didn't specify -bios, or has specified "-bios default".
61          * That means we are going to load the OpenSBI binary included in
62          * the QEMU source.
63          */
64         firmware_filename = riscv_find_firmware(default_machine_firmware);
65     } else if (strcmp(machine->firmware, "none")) {
66         firmware_filename = riscv_find_firmware(machine->firmware);
67     }
68 
69     if (firmware_filename) {
70         /* If not "none" load the firmware */
71         firmware_end_addr = riscv_load_firmware(firmware_filename,
72                                                 firmware_load_addr, sym_cb);
73         g_free(firmware_filename);
74     }
75 
76     return firmware_end_addr;
77 }
78 
79 char *riscv_find_firmware(const char *firmware_filename)
80 {
81     char *filename;
82 
83     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename);
84     if (filename == NULL) {
85         if (!qtest_enabled()) {
86             /*
87              * We only ship plain binary bios images in the QEMU source.
88              * With Spike machine that uses ELF images as the default bios,
89              * running QEMU test will complain hence let's suppress the error
90              * report for QEMU testing.
91              */
92             error_report("Unable to load the RISC-V firmware \"%s\"",
93                          firmware_filename);
94             exit(1);
95         }
96     }
97 
98     return filename;
99 }
100 
101 target_ulong riscv_load_firmware(const char *firmware_filename,
102                                  hwaddr firmware_load_addr,
103                                  symbol_fn_t sym_cb)
104 {
105     uint64_t firmware_entry, firmware_size, firmware_end;
106 
107     if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
108                          &firmware_entry, NULL, &firmware_end, NULL,
109                          0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
110         return firmware_end;
111     }
112 
113     firmware_size = load_image_targphys_as(firmware_filename,
114                                            firmware_load_addr,
115                                            current_machine->ram_size, NULL);
116 
117     if (firmware_size > 0) {
118         return firmware_load_addr + firmware_size;
119     }
120 
121     error_report("could not load firmware '%s'", firmware_filename);
122     exit(1);
123 }
124 
125 target_ulong riscv_load_kernel(const char *kernel_filename,
126                                target_ulong kernel_start_addr,
127                                symbol_fn_t sym_cb)
128 {
129     uint64_t kernel_entry;
130 
131     if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
132                          &kernel_entry, NULL, NULL, NULL, 0,
133                          EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
134         return kernel_entry;
135     }
136 
137     if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
138                        NULL, NULL, NULL) > 0) {
139         return kernel_entry;
140     }
141 
142     if (load_image_targphys_as(kernel_filename, kernel_start_addr,
143                                current_machine->ram_size, NULL) > 0) {
144         return kernel_start_addr;
145     }
146 
147     error_report("could not load kernel '%s'", kernel_filename);
148     exit(1);
149 }
150 
151 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
152                          uint64_t kernel_entry, hwaddr *start)
153 {
154     int size;
155 
156     /*
157      * We want to put the initrd far enough into RAM that when the
158      * kernel is uncompressed it will not clobber the initrd. However
159      * on boards without much RAM we must ensure that we still leave
160      * enough room for a decent sized initrd, and on boards with large
161      * amounts of RAM we must avoid the initrd being so far up in RAM
162      * that it is outside lowmem and inaccessible to the kernel.
163      * So for boards with less  than 256MB of RAM we put the initrd
164      * halfway into RAM, and for boards with 256MB of RAM or more we put
165      * the initrd at 128MB.
166      */
167     *start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
168 
169     size = load_ramdisk(filename, *start, mem_size - *start);
170     if (size == -1) {
171         size = load_image_targphys(filename, *start, mem_size - *start);
172         if (size == -1) {
173             error_report("could not load ramdisk '%s'", filename);
174             exit(1);
175         }
176     }
177 
178     return *start + size;
179 }
180 
181 uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
182 {
183     uint32_t temp, fdt_addr;
184     hwaddr dram_end = dram_base + mem_size;
185     int ret, fdtsize = fdt_totalsize(fdt);
186 
187     if (fdtsize <= 0) {
188         error_report("invalid device-tree");
189         exit(1);
190     }
191 
192     /*
193      * We should put fdt as far as possible to avoid kernel/initrd overwriting
194      * its content. But it should be addressable by 32 bit system as well.
195      * Thus, put it at an 16MB aligned address that less than fdt size from the
196      * end of dram or 3GB whichever is lesser.
197      */
198     temp = MIN(dram_end, 3072 * MiB);
199     fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
200 
201     ret = fdt_pack(fdt);
202     /* Should only fail if we've built a corrupted tree */
203     g_assert(ret == 0);
204     /* copy in the device tree */
205     qemu_fdt_dumpdtb(fdt, fdtsize);
206 
207     rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
208                           &address_space_memory);
209 
210     return fdt_addr;
211 }
212 
213 void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
214                                   hwaddr rom_size, uint32_t reset_vec_size,
215                                   uint64_t kernel_entry)
216 {
217     struct fw_dynamic_info dinfo;
218     size_t dinfo_len;
219 
220     if (sizeof(dinfo.magic) == 4) {
221         dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);
222         dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);
223         dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);
224         dinfo.next_addr = cpu_to_le32(kernel_entry);
225     } else {
226         dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE);
227         dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION);
228         dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S);
229         dinfo.next_addr = cpu_to_le64(kernel_entry);
230     }
231     dinfo.options = 0;
232     dinfo.boot_hart = 0;
233     dinfo_len = sizeof(dinfo);
234 
235     /**
236      * copy the dynamic firmware info. This information is specific to
237      * OpenSBI but doesn't break any other firmware as long as they don't
238      * expect any certain value in "a2" register.
239      */
240     if (dinfo_len > (rom_size - reset_vec_size)) {
241         error_report("not enough space to store dynamic firmware info");
242         exit(1);
243     }
244 
245     rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len,
246                            rom_base + reset_vec_size,
247                            &address_space_memory);
248 }
249 
250 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
251                                hwaddr start_addr,
252                                hwaddr rom_base, hwaddr rom_size,
253                                uint64_t kernel_entry,
254                                uint32_t fdt_load_addr, void *fdt)
255 {
256     int i;
257     uint32_t start_addr_hi32 = 0x00000000;
258 
259     if (!riscv_is_32bit(harts)) {
260         start_addr_hi32 = start_addr >> 32;
261     }
262     /* reset vector */
263     uint32_t reset_vec[10] = {
264         0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
265         0x02828613,                  /*     addi   a2, t0, %pcrel_lo(1b) */
266         0xf1402573,                  /*     csrr   a0, mhartid  */
267         0,
268         0,
269         0x00028067,                  /*     jr     t0 */
270         start_addr,                  /* start: .dword */
271         start_addr_hi32,
272         fdt_load_addr,               /* fdt_laddr: .dword */
273         0x00000000,
274                                      /* fw_dyn: */
275     };
276     if (riscv_is_32bit(harts)) {
277         reset_vec[3] = 0x0202a583;   /*     lw     a1, 32(t0) */
278         reset_vec[4] = 0x0182a283;   /*     lw     t0, 24(t0) */
279     } else {
280         reset_vec[3] = 0x0202b583;   /*     ld     a1, 32(t0) */
281         reset_vec[4] = 0x0182b283;   /*     ld     t0, 24(t0) */
282     }
283 
284     /* copy in the reset vector in little_endian byte order */
285     for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
286         reset_vec[i] = cpu_to_le32(reset_vec[i]);
287     }
288     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
289                           rom_base, &address_space_memory);
290     riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
291                                  kernel_entry);
292 
293     return;
294 }
295