1 /* 2 * QEMU RISC-V Boot Helper 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/datadir.h" 23 #include "qemu/units.h" 24 #include "qemu/error-report.h" 25 #include "exec/cpu-defs.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/riscv/boot.h" 29 #include "hw/riscv/boot_opensbi.h" 30 #include "elf.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/qtest.h" 33 34 #include <libfdt.h> 35 36 bool riscv_is_32bit(RISCVHartArrayState harts) 37 { 38 RISCVCPU hart = harts.harts[0]; 39 40 return riscv_cpu_is_32bit(&hart.env); 41 } 42 43 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts, 44 target_ulong firmware_end_addr) { 45 if (riscv_is_32bit(harts)) { 46 return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); 47 } else { 48 return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); 49 } 50 } 51 52 target_ulong riscv_find_and_load_firmware(MachineState *machine, 53 const char *default_machine_firmware, 54 hwaddr firmware_load_addr, 55 symbol_fn_t sym_cb) 56 { 57 char *firmware_filename = NULL; 58 target_ulong firmware_end_addr = firmware_load_addr; 59 60 if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) { 61 /* 62 * The user didn't specify -bios, or has specified "-bios default". 63 * That means we are going to load the OpenSBI binary included in 64 * the QEMU source. 65 */ 66 firmware_filename = riscv_find_firmware(default_machine_firmware); 67 } else if (strcmp(machine->firmware, "none")) { 68 firmware_filename = riscv_find_firmware(machine->firmware); 69 } 70 71 if (firmware_filename) { 72 /* If not "none" load the firmware */ 73 firmware_end_addr = riscv_load_firmware(firmware_filename, 74 firmware_load_addr, sym_cb); 75 g_free(firmware_filename); 76 } 77 78 return firmware_end_addr; 79 } 80 81 char *riscv_find_firmware(const char *firmware_filename) 82 { 83 char *filename; 84 85 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); 86 if (filename == NULL) { 87 if (!qtest_enabled()) { 88 /* 89 * We only ship plain binary bios images in the QEMU source. 90 * With Spike machine that uses ELF images as the default bios, 91 * running QEMU test will complain hence let's suppress the error 92 * report for QEMU testing. 93 */ 94 error_report("Unable to load the RISC-V firmware \"%s\"", 95 firmware_filename); 96 exit(1); 97 } 98 } 99 100 return filename; 101 } 102 103 target_ulong riscv_load_firmware(const char *firmware_filename, 104 hwaddr firmware_load_addr, 105 symbol_fn_t sym_cb) 106 { 107 uint64_t firmware_entry, firmware_size, firmware_end; 108 109 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, 110 &firmware_entry, NULL, &firmware_end, NULL, 111 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 112 return firmware_end; 113 } 114 115 firmware_size = load_image_targphys_as(firmware_filename, 116 firmware_load_addr, 117 current_machine->ram_size, NULL); 118 119 if (firmware_size > 0) { 120 return firmware_load_addr + firmware_size; 121 } 122 123 error_report("could not load firmware '%s'", firmware_filename); 124 exit(1); 125 } 126 127 target_ulong riscv_load_kernel(const char *kernel_filename, 128 target_ulong kernel_start_addr, 129 symbol_fn_t sym_cb) 130 { 131 uint64_t kernel_entry; 132 133 if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, 134 &kernel_entry, NULL, NULL, NULL, 0, 135 EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 136 return kernel_entry; 137 } 138 139 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, 140 NULL, NULL, NULL) > 0) { 141 return kernel_entry; 142 } 143 144 if (load_image_targphys_as(kernel_filename, kernel_start_addr, 145 current_machine->ram_size, NULL) > 0) { 146 return kernel_start_addr; 147 } 148 149 error_report("could not load kernel '%s'", kernel_filename); 150 exit(1); 151 } 152 153 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, 154 uint64_t kernel_entry, hwaddr *start) 155 { 156 int size; 157 158 /* 159 * We want to put the initrd far enough into RAM that when the 160 * kernel is uncompressed it will not clobber the initrd. However 161 * on boards without much RAM we must ensure that we still leave 162 * enough room for a decent sized initrd, and on boards with large 163 * amounts of RAM we must avoid the initrd being so far up in RAM 164 * that it is outside lowmem and inaccessible to the kernel. 165 * So for boards with less than 256MB of RAM we put the initrd 166 * halfway into RAM, and for boards with 256MB of RAM or more we put 167 * the initrd at 128MB. 168 */ 169 *start = kernel_entry + MIN(mem_size / 2, 128 * MiB); 170 171 size = load_ramdisk(filename, *start, mem_size - *start); 172 if (size == -1) { 173 size = load_image_targphys(filename, *start, mem_size - *start); 174 if (size == -1) { 175 error_report("could not load ramdisk '%s'", filename); 176 exit(1); 177 } 178 } 179 180 return *start + size; 181 } 182 183 uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) 184 { 185 uint32_t temp, fdt_addr; 186 hwaddr dram_end = dram_base + mem_size; 187 int fdtsize = fdt_totalsize(fdt); 188 189 if (fdtsize <= 0) { 190 error_report("invalid device-tree"); 191 exit(1); 192 } 193 194 /* 195 * We should put fdt as far as possible to avoid kernel/initrd overwriting 196 * its content. But it should be addressable by 32 bit system as well. 197 * Thus, put it at an aligned address that less than fdt size from end of 198 * dram or 4GB whichever is lesser. 199 */ 200 temp = MIN(dram_end, 4096 * MiB); 201 fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); 202 203 fdt_pack(fdt); 204 /* copy in the device tree */ 205 qemu_fdt_dumpdtb(fdt, fdtsize); 206 207 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, 208 &address_space_memory); 209 210 return fdt_addr; 211 } 212 213 void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, 214 hwaddr rom_size, uint32_t reset_vec_size, 215 uint64_t kernel_entry) 216 { 217 struct fw_dynamic_info dinfo; 218 size_t dinfo_len; 219 220 if (sizeof(dinfo.magic) == 4) { 221 dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); 222 dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION); 223 dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); 224 dinfo.next_addr = cpu_to_le32(kernel_entry); 225 } else { 226 dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); 227 dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION); 228 dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); 229 dinfo.next_addr = cpu_to_le64(kernel_entry); 230 } 231 dinfo.options = 0; 232 dinfo.boot_hart = 0; 233 dinfo_len = sizeof(dinfo); 234 235 /** 236 * copy the dynamic firmware info. This information is specific to 237 * OpenSBI but doesn't break any other firmware as long as they don't 238 * expect any certain value in "a2" register. 239 */ 240 if (dinfo_len > (rom_size - reset_vec_size)) { 241 error_report("not enough space to store dynamic firmware info"); 242 exit(1); 243 } 244 245 rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len, 246 rom_base + reset_vec_size, 247 &address_space_memory); 248 } 249 250 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts, 251 hwaddr start_addr, 252 hwaddr rom_base, hwaddr rom_size, 253 uint64_t kernel_entry, 254 uint32_t fdt_load_addr, void *fdt) 255 { 256 int i; 257 uint32_t start_addr_hi32 = 0x00000000; 258 259 if (!riscv_is_32bit(harts)) { 260 start_addr_hi32 = start_addr >> 32; 261 } 262 /* reset vector */ 263 uint32_t reset_vec[10] = { 264 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 265 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 266 0xf1402573, /* csrr a0, mhartid */ 267 0, 268 0, 269 0x00028067, /* jr t0 */ 270 start_addr, /* start: .dword */ 271 start_addr_hi32, 272 fdt_load_addr, /* fdt_laddr: .dword */ 273 0x00000000, 274 /* fw_dyn: */ 275 }; 276 if (riscv_is_32bit(harts)) { 277 reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */ 278 reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */ 279 } else { 280 reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */ 281 reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ 282 } 283 284 /* copy in the reset vector in little_endian byte order */ 285 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 286 reset_vec[i] = cpu_to_le32(reset_vec[i]); 287 } 288 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 289 rom_base, &address_space_memory); 290 riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec), 291 kernel_entry); 292 293 return; 294 } 295