1 /* 2 * Model of Xilinx Virtex5 ML507 PPC-440 refdesign. 3 * 4 * Copyright (c) 2010 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu-common.h" 27 #include "qemu/units.h" 28 #include "cpu.h" 29 #include "hw/sysbus.h" 30 #include "hw/char/serial.h" 31 #include "hw/block/flash.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/qtest.h" 34 #include "sysemu/reset.h" 35 #include "hw/boards.h" 36 #include "sysemu/device_tree.h" 37 #include "hw/loader.h" 38 #include "elf.h" 39 #include "qemu/error-report.h" 40 #include "qemu/log.h" 41 #include "qemu/option.h" 42 #include "exec/address-spaces.h" 43 44 #include "hw/ppc/ppc.h" 45 #include "hw/ppc/ppc4xx.h" 46 #include "hw/qdev-properties.h" 47 #include "ppc405.h" 48 49 #define EPAPR_MAGIC (0x45504150) 50 #define FLASH_SIZE (16 * MiB) 51 52 #define INTC_BASEADDR 0x81800000 53 #define UART16550_BASEADDR 0x83e01003 54 #define TIMER_BASEADDR 0x83c00000 55 #define PFLASH_BASEADDR 0xfc000000 56 57 #define TIMER_IRQ 3 58 #define UART16550_IRQ 9 59 60 static struct boot_info 61 { 62 uint32_t bootstrap_pc; 63 uint32_t cmdline; 64 uint32_t fdt; 65 uint32_t ima_size; 66 void *vfdt; 67 } boot_info; 68 69 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 70 static void mmubooke_create_initial_mapping(CPUPPCState *env, 71 target_ulong va, 72 hwaddr pa) 73 { 74 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 75 76 tlb->attr = 0; 77 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 78 tlb->size = 1U << 31; /* up to 0x80000000 */ 79 tlb->EPN = va & TARGET_PAGE_MASK; 80 tlb->RPN = pa & TARGET_PAGE_MASK; 81 tlb->PID = 0; 82 83 tlb = &env->tlb.tlbe[1]; 84 tlb->attr = 0; 85 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 86 tlb->size = 1U << 31; /* up to 0xffffffff */ 87 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; 88 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; 89 tlb->PID = 0; 90 } 91 92 static PowerPCCPU *ppc440_init_xilinx(ram_addr_t *ram_size, 93 int do_init, 94 const char *cpu_type, 95 uint32_t sysclk) 96 { 97 PowerPCCPU *cpu; 98 CPUPPCState *env; 99 qemu_irq *irqs; 100 101 cpu = POWERPC_CPU(cpu_create(cpu_type)); 102 env = &cpu->env; 103 104 ppc_booke_timers_init(cpu, sysclk, 0/* no flags */); 105 106 ppc_dcr_init(env, NULL, NULL); 107 108 /* interrupt controller */ 109 irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); 110 irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; 111 irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; 112 ppcuic_init(env, irqs, 0x0C0, 0, 1); 113 return cpu; 114 } 115 116 static void main_cpu_reset(void *opaque) 117 { 118 PowerPCCPU *cpu = opaque; 119 CPUPPCState *env = &cpu->env; 120 struct boot_info *bi = env->load_info; 121 122 cpu_reset(CPU(cpu)); 123 /* Linux Kernel Parameters (passing device tree): 124 * r3: pointer to the fdt 125 * r4: 0 126 * r5: 0 127 * r6: epapr magic 128 * r7: size of IMA in bytes 129 * r8: 0 130 * r9: 0 131 */ 132 env->gpr[1] = (16 * MiB) - 8; 133 /* Provide a device-tree. */ 134 env->gpr[3] = bi->fdt; 135 env->nip = bi->bootstrap_pc; 136 137 /* Create a mapping for the kernel. */ 138 mmubooke_create_initial_mapping(env, 0, 0); 139 env->gpr[6] = tswap32(EPAPR_MAGIC); 140 env->gpr[7] = bi->ima_size; 141 } 142 143 #define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb" 144 static int xilinx_load_device_tree(hwaddr addr, 145 uint32_t ramsize, 146 hwaddr initrd_base, 147 hwaddr initrd_size, 148 const char *kernel_cmdline) 149 { 150 char *path; 151 int fdt_size; 152 void *fdt = NULL; 153 int r; 154 const char *dtb_filename; 155 156 dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 157 if (dtb_filename) { 158 fdt = load_device_tree(dtb_filename, &fdt_size); 159 if (!fdt) { 160 error_report("Error while loading device tree file '%s'", 161 dtb_filename); 162 } 163 } else { 164 /* Try the local "ppc.dtb" override. */ 165 fdt = load_device_tree("ppc.dtb", &fdt_size); 166 if (!fdt) { 167 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 168 if (path) { 169 fdt = load_device_tree(path, &fdt_size); 170 g_free(path); 171 } 172 } 173 } 174 if (!fdt) { 175 return 0; 176 } 177 178 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 179 initrd_base); 180 if (r < 0) { 181 error_report("couldn't set /chosen/linux,initrd-start"); 182 } 183 184 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 185 (initrd_base + initrd_size)); 186 if (r < 0) { 187 error_report("couldn't set /chosen/linux,initrd-end"); 188 } 189 190 r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline); 191 if (r < 0) 192 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 193 cpu_physical_memory_write(addr, fdt, fdt_size); 194 return fdt_size; 195 } 196 197 static void virtex_init(MachineState *machine) 198 { 199 ram_addr_t ram_size = machine->ram_size; 200 const char *kernel_filename = machine->kernel_filename; 201 const char *kernel_cmdline = machine->kernel_cmdline; 202 hwaddr initrd_base = 0; 203 int initrd_size = 0; 204 MemoryRegion *address_space_mem = get_system_memory(); 205 DeviceState *dev; 206 PowerPCCPU *cpu; 207 CPUPPCState *env; 208 hwaddr ram_base = 0; 209 DriveInfo *dinfo; 210 MemoryRegion *phys_ram = g_new(MemoryRegion, 1); 211 qemu_irq irq[32], *cpu_irq; 212 int kernel_size; 213 int i; 214 215 /* init CPUs */ 216 cpu = ppc440_init_xilinx(&ram_size, 1, machine->cpu_type, 400000000); 217 env = &cpu->env; 218 219 if (env->mmu_model != POWERPC_MMU_BOOKE) { 220 error_report("MMU model %i not supported by this machine", 221 env->mmu_model); 222 exit(1); 223 } 224 225 qemu_register_reset(main_cpu_reset, cpu); 226 227 memory_region_allocate_system_memory(phys_ram, NULL, "ram", ram_size); 228 memory_region_add_subregion(address_space_mem, ram_base, phys_ram); 229 230 dinfo = drive_get(IF_PFLASH, 0, 0); 231 pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE, 232 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 233 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); 234 235 cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT]; 236 dev = qdev_create(NULL, "xlnx.xps-intc"); 237 qdev_prop_set_uint32(dev, "kind-of-intr", 0); 238 qdev_init_nofail(dev); 239 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); 240 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]); 241 for (i = 0; i < 32; i++) { 242 irq[i] = qdev_get_gpio_in(dev, i); 243 } 244 245 serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ], 246 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 247 248 /* 2 timers at irq 2 @ 62 Mhz. */ 249 dev = qdev_create(NULL, "xlnx.xps-timer"); 250 qdev_prop_set_uint32(dev, "one-timer-only", 0); 251 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); 252 qdev_init_nofail(dev); 253 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); 254 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); 255 256 if (kernel_filename) { 257 uint64_t entry, low, high; 258 hwaddr boot_offset; 259 260 /* Boots a kernel elf binary. */ 261 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, 262 &entry, &low, &high, 1, PPC_ELF_MACHINE, 263 0, 0); 264 boot_info.bootstrap_pc = entry & 0x00ffffff; 265 266 if (kernel_size < 0) { 267 boot_offset = 0x1200000; 268 /* If we failed loading ELF's try a raw image. */ 269 kernel_size = load_image_targphys(kernel_filename, 270 boot_offset, 271 ram_size); 272 boot_info.bootstrap_pc = boot_offset; 273 high = boot_info.bootstrap_pc + kernel_size + 8192; 274 } 275 276 boot_info.ima_size = kernel_size; 277 278 /* Load initrd. */ 279 if (machine->initrd_filename) { 280 initrd_base = high = ROUND_UP(high, 4); 281 initrd_size = load_image_targphys(machine->initrd_filename, 282 high, ram_size - high); 283 284 if (initrd_size < 0) { 285 error_report("couldn't load ram disk '%s'", 286 machine->initrd_filename); 287 exit(1); 288 } 289 high = ROUND_UP(high + initrd_size, 4); 290 } 291 292 /* Provide a device-tree. */ 293 boot_info.fdt = high + (8192 * 2); 294 boot_info.fdt &= ~8191; 295 296 xilinx_load_device_tree(boot_info.fdt, ram_size, 297 initrd_base, initrd_size, 298 kernel_cmdline); 299 } 300 env->load_info = &boot_info; 301 } 302 303 static void virtex_machine_init(MachineClass *mc) 304 { 305 mc->desc = "Xilinx Virtex ML507 reference design"; 306 mc->init = virtex_init; 307 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440-xilinx"); 308 } 309 310 DEFINE_MACHINE("virtex-ml507", virtex_machine_init) 311