1 /* 2 * Model of Xilinx Virtex5 ML507 PPC-440 refdesign. 3 * 4 * Copyright (c) 2010 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/datadir.h" 27 #include "qemu/units.h" 28 #include "cpu.h" 29 #include "hw/sysbus.h" 30 #include "hw/char/serial.h" 31 #include "hw/block/flash.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/reset.h" 34 #include "hw/boards.h" 35 #include "sysemu/device_tree.h" 36 #include "hw/loader.h" 37 #include "elf.h" 38 #include "qapi/error.h" 39 #include "qemu/error-report.h" 40 #include "qemu/option.h" 41 42 #include "hw/intc/ppc-uic.h" 43 #include "hw/ppc/ppc.h" 44 #include "hw/ppc/ppc4xx.h" 45 #include "hw/qdev-properties.h" 46 #include "ppc405.h" 47 48 #define EPAPR_MAGIC (0x45504150) 49 #define FLASH_SIZE (16 * MiB) 50 51 #define INTC_BASEADDR 0x81800000 52 #define UART16550_BASEADDR 0x83e01003 53 #define TIMER_BASEADDR 0x83c00000 54 #define PFLASH_BASEADDR 0xfc000000 55 56 #define TIMER_IRQ 3 57 #define UART16550_IRQ 9 58 59 static struct boot_info 60 { 61 uint32_t bootstrap_pc; 62 uint32_t cmdline; 63 uint32_t fdt; 64 uint32_t ima_size; 65 void *vfdt; 66 } boot_info; 67 68 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 69 static void mmubooke_create_initial_mapping(CPUPPCState *env, 70 target_ulong va, 71 hwaddr pa) 72 { 73 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 74 75 tlb->attr = 0; 76 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 77 tlb->size = 1U << 31; /* up to 0x80000000 */ 78 tlb->EPN = va & TARGET_PAGE_MASK; 79 tlb->RPN = pa & TARGET_PAGE_MASK; 80 tlb->PID = 0; 81 82 tlb = &env->tlb.tlbe[1]; 83 tlb->attr = 0; 84 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 85 tlb->size = 1U << 31; /* up to 0xffffffff */ 86 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; 87 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; 88 tlb->PID = 0; 89 } 90 91 static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk) 92 { 93 PowerPCCPU *cpu; 94 CPUPPCState *env; 95 DeviceState *uicdev; 96 SysBusDevice *uicsbd; 97 98 cpu = POWERPC_CPU(cpu_create(cpu_type)); 99 env = &cpu->env; 100 101 ppc_booke_timers_init(cpu, sysclk, 0/* no flags */); 102 103 ppc_dcr_init(env, NULL, NULL); 104 105 /* interrupt controller */ 106 uicdev = qdev_new(TYPE_PPC_UIC); 107 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uicdev), cpu, &error_fatal); 108 object_unref(OBJECT(uicdev)); 109 uicsbd = SYS_BUS_DEVICE(uicdev); 110 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, 111 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT)); 112 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, 113 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); 114 115 /* This board doesn't wire anything up to the inputs of the UIC. */ 116 return cpu; 117 } 118 119 static void main_cpu_reset(void *opaque) 120 { 121 PowerPCCPU *cpu = opaque; 122 CPUPPCState *env = &cpu->env; 123 struct boot_info *bi = env->load_info; 124 125 cpu_reset(CPU(cpu)); 126 /* Linux Kernel Parameters (passing device tree): 127 * r3: pointer to the fdt 128 * r4: 0 129 * r5: 0 130 * r6: epapr magic 131 * r7: size of IMA in bytes 132 * r8: 0 133 * r9: 0 134 */ 135 env->gpr[1] = (16 * MiB) - 8; 136 /* Provide a device-tree. */ 137 env->gpr[3] = bi->fdt; 138 env->nip = bi->bootstrap_pc; 139 140 /* Create a mapping for the kernel. */ 141 mmubooke_create_initial_mapping(env, 0, 0); 142 env->gpr[6] = tswap32(EPAPR_MAGIC); 143 env->gpr[7] = bi->ima_size; 144 } 145 146 #define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb" 147 static int xilinx_load_device_tree(hwaddr addr, 148 uint32_t ramsize, 149 hwaddr initrd_base, 150 hwaddr initrd_size, 151 const char *kernel_cmdline) 152 { 153 char *path; 154 int fdt_size; 155 void *fdt = NULL; 156 int r; 157 const char *dtb_filename; 158 159 dtb_filename = current_machine->dtb; 160 if (dtb_filename) { 161 fdt = load_device_tree(dtb_filename, &fdt_size); 162 if (!fdt) { 163 error_report("Error while loading device tree file '%s'", 164 dtb_filename); 165 } 166 } else { 167 /* Try the local "ppc.dtb" override. */ 168 fdt = load_device_tree("ppc.dtb", &fdt_size); 169 if (!fdt) { 170 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 171 if (path) { 172 fdt = load_device_tree(path, &fdt_size); 173 g_free(path); 174 } 175 } 176 } 177 if (!fdt) { 178 return 0; 179 } 180 181 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 182 initrd_base); 183 if (r < 0) { 184 error_report("couldn't set /chosen/linux,initrd-start"); 185 } 186 187 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 188 (initrd_base + initrd_size)); 189 if (r < 0) { 190 error_report("couldn't set /chosen/linux,initrd-end"); 191 } 192 193 r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline); 194 if (r < 0) 195 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 196 cpu_physical_memory_write(addr, fdt, fdt_size); 197 g_free(fdt); 198 return fdt_size; 199 } 200 201 static void virtex_init(MachineState *machine) 202 { 203 const char *kernel_filename = machine->kernel_filename; 204 const char *kernel_cmdline = machine->kernel_cmdline; 205 hwaddr initrd_base = 0; 206 int initrd_size = 0; 207 MemoryRegion *address_space_mem = get_system_memory(); 208 DeviceState *dev; 209 PowerPCCPU *cpu; 210 CPUPPCState *env; 211 hwaddr ram_base = 0; 212 DriveInfo *dinfo; 213 qemu_irq irq[32], cpu_irq; 214 int kernel_size; 215 int i; 216 217 /* init CPUs */ 218 cpu = ppc440_init_xilinx(machine->cpu_type, 400000000); 219 env = &cpu->env; 220 221 if (env->mmu_model != POWERPC_MMU_BOOKE) { 222 error_report("MMU model %i not supported by this machine", 223 env->mmu_model); 224 exit(1); 225 } 226 227 qemu_register_reset(main_cpu_reset, cpu); 228 229 memory_region_add_subregion(address_space_mem, ram_base, machine->ram); 230 231 dinfo = drive_get(IF_PFLASH, 0, 0); 232 pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE, 233 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 234 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); 235 236 cpu_irq = qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT); 237 dev = qdev_new("xlnx.xps-intc"); 238 qdev_prop_set_uint32(dev, "kind-of-intr", 0); 239 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 240 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); 241 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq); 242 for (i = 0; i < 32; i++) { 243 irq[i] = qdev_get_gpio_in(dev, i); 244 } 245 246 serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ], 247 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 248 249 /* 2 timers at irq 2 @ 62 Mhz. */ 250 dev = qdev_new("xlnx.xps-timer"); 251 qdev_prop_set_uint32(dev, "one-timer-only", 0); 252 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); 253 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 254 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); 255 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); 256 257 if (kernel_filename) { 258 uint64_t entry, high; 259 hwaddr boot_offset; 260 261 /* Boots a kernel elf binary. */ 262 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, 263 &entry, NULL, &high, NULL, 1, PPC_ELF_MACHINE, 264 0, 0); 265 boot_info.bootstrap_pc = entry & 0x00ffffff; 266 267 if (kernel_size < 0) { 268 boot_offset = 0x1200000; 269 /* If we failed loading ELF's try a raw image. */ 270 kernel_size = load_image_targphys(kernel_filename, 271 boot_offset, 272 machine->ram_size); 273 boot_info.bootstrap_pc = boot_offset; 274 high = boot_info.bootstrap_pc + kernel_size + 8192; 275 } 276 277 boot_info.ima_size = kernel_size; 278 279 /* Load initrd. */ 280 if (machine->initrd_filename) { 281 initrd_base = high = ROUND_UP(high, 4); 282 initrd_size = load_image_targphys(machine->initrd_filename, 283 high, machine->ram_size - high); 284 285 if (initrd_size < 0) { 286 error_report("couldn't load ram disk '%s'", 287 machine->initrd_filename); 288 exit(1); 289 } 290 high = ROUND_UP(high + initrd_size, 4); 291 } 292 293 /* Provide a device-tree. */ 294 boot_info.fdt = high + (8192 * 2); 295 boot_info.fdt &= ~8191; 296 297 xilinx_load_device_tree(boot_info.fdt, machine->ram_size, 298 initrd_base, initrd_size, 299 kernel_cmdline); 300 } 301 env->load_info = &boot_info; 302 } 303 304 static void virtex_machine_init(MachineClass *mc) 305 { 306 mc->desc = "Xilinx Virtex ML507 reference design"; 307 mc->init = virtex_init; 308 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440-xilinx"); 309 mc->default_ram_id = "ram"; 310 } 311 312 DEFINE_MACHINE("virtex-ml507", virtex_machine_init) 313