1 /* 2 * Model of Xilinx Virtex5 ML507 PPC-440 refdesign. 3 * 4 * Copyright (c) 2010 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu-common.h" 27 #include "qemu/datadir.h" 28 #include "qemu/units.h" 29 #include "cpu.h" 30 #include "hw/sysbus.h" 31 #include "hw/char/serial.h" 32 #include "hw/block/flash.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/reset.h" 35 #include "hw/boards.h" 36 #include "sysemu/device_tree.h" 37 #include "hw/loader.h" 38 #include "elf.h" 39 #include "qapi/error.h" 40 #include "qemu/error-report.h" 41 #include "qemu/option.h" 42 #include "exec/address-spaces.h" 43 44 #include "hw/intc/ppc-uic.h" 45 #include "hw/ppc/ppc.h" 46 #include "hw/ppc/ppc4xx.h" 47 #include "hw/qdev-properties.h" 48 #include "ppc405.h" 49 50 #define EPAPR_MAGIC (0x45504150) 51 #define FLASH_SIZE (16 * MiB) 52 53 #define INTC_BASEADDR 0x81800000 54 #define UART16550_BASEADDR 0x83e01003 55 #define TIMER_BASEADDR 0x83c00000 56 #define PFLASH_BASEADDR 0xfc000000 57 58 #define TIMER_IRQ 3 59 #define UART16550_IRQ 9 60 61 static struct boot_info 62 { 63 uint32_t bootstrap_pc; 64 uint32_t cmdline; 65 uint32_t fdt; 66 uint32_t ima_size; 67 void *vfdt; 68 } boot_info; 69 70 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 71 static void mmubooke_create_initial_mapping(CPUPPCState *env, 72 target_ulong va, 73 hwaddr pa) 74 { 75 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 76 77 tlb->attr = 0; 78 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 79 tlb->size = 1U << 31; /* up to 0x80000000 */ 80 tlb->EPN = va & TARGET_PAGE_MASK; 81 tlb->RPN = pa & TARGET_PAGE_MASK; 82 tlb->PID = 0; 83 84 tlb = &env->tlb.tlbe[1]; 85 tlb->attr = 0; 86 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 87 tlb->size = 1U << 31; /* up to 0xffffffff */ 88 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; 89 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; 90 tlb->PID = 0; 91 } 92 93 static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk) 94 { 95 PowerPCCPU *cpu; 96 CPUPPCState *env; 97 DeviceState *uicdev; 98 SysBusDevice *uicsbd; 99 100 cpu = POWERPC_CPU(cpu_create(cpu_type)); 101 env = &cpu->env; 102 103 ppc_booke_timers_init(cpu, sysclk, 0/* no flags */); 104 105 ppc_dcr_init(env, NULL, NULL); 106 107 /* interrupt controller */ 108 uicdev = qdev_new(TYPE_PPC_UIC); 109 uicsbd = SYS_BUS_DEVICE(uicdev); 110 111 object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), 112 &error_fatal); 113 sysbus_realize_and_unref(uicsbd, &error_fatal); 114 115 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, 116 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); 117 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, 118 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); 119 120 /* This board doesn't wire anything up to the inputs of the UIC. */ 121 return cpu; 122 } 123 124 static void main_cpu_reset(void *opaque) 125 { 126 PowerPCCPU *cpu = opaque; 127 CPUPPCState *env = &cpu->env; 128 struct boot_info *bi = env->load_info; 129 130 cpu_reset(CPU(cpu)); 131 /* Linux Kernel Parameters (passing device tree): 132 * r3: pointer to the fdt 133 * r4: 0 134 * r5: 0 135 * r6: epapr magic 136 * r7: size of IMA in bytes 137 * r8: 0 138 * r9: 0 139 */ 140 env->gpr[1] = (16 * MiB) - 8; 141 /* Provide a device-tree. */ 142 env->gpr[3] = bi->fdt; 143 env->nip = bi->bootstrap_pc; 144 145 /* Create a mapping for the kernel. */ 146 mmubooke_create_initial_mapping(env, 0, 0); 147 env->gpr[6] = tswap32(EPAPR_MAGIC); 148 env->gpr[7] = bi->ima_size; 149 } 150 151 #define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb" 152 static int xilinx_load_device_tree(hwaddr addr, 153 uint32_t ramsize, 154 hwaddr initrd_base, 155 hwaddr initrd_size, 156 const char *kernel_cmdline) 157 { 158 char *path; 159 int fdt_size; 160 void *fdt = NULL; 161 int r; 162 const char *dtb_filename; 163 164 dtb_filename = current_machine->dtb; 165 if (dtb_filename) { 166 fdt = load_device_tree(dtb_filename, &fdt_size); 167 if (!fdt) { 168 error_report("Error while loading device tree file '%s'", 169 dtb_filename); 170 } 171 } else { 172 /* Try the local "ppc.dtb" override. */ 173 fdt = load_device_tree("ppc.dtb", &fdt_size); 174 if (!fdt) { 175 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 176 if (path) { 177 fdt = load_device_tree(path, &fdt_size); 178 g_free(path); 179 } 180 } 181 } 182 if (!fdt) { 183 return 0; 184 } 185 186 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 187 initrd_base); 188 if (r < 0) { 189 error_report("couldn't set /chosen/linux,initrd-start"); 190 } 191 192 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 193 (initrd_base + initrd_size)); 194 if (r < 0) { 195 error_report("couldn't set /chosen/linux,initrd-end"); 196 } 197 198 r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline); 199 if (r < 0) 200 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 201 cpu_physical_memory_write(addr, fdt, fdt_size); 202 g_free(fdt); 203 return fdt_size; 204 } 205 206 static void virtex_init(MachineState *machine) 207 { 208 const char *kernel_filename = machine->kernel_filename; 209 const char *kernel_cmdline = machine->kernel_cmdline; 210 hwaddr initrd_base = 0; 211 int initrd_size = 0; 212 MemoryRegion *address_space_mem = get_system_memory(); 213 DeviceState *dev; 214 PowerPCCPU *cpu; 215 CPUPPCState *env; 216 hwaddr ram_base = 0; 217 DriveInfo *dinfo; 218 qemu_irq irq[32], *cpu_irq; 219 int kernel_size; 220 int i; 221 222 /* init CPUs */ 223 cpu = ppc440_init_xilinx(machine->cpu_type, 400000000); 224 env = &cpu->env; 225 226 if (env->mmu_model != POWERPC_MMU_BOOKE) { 227 error_report("MMU model %i not supported by this machine", 228 env->mmu_model); 229 exit(1); 230 } 231 232 qemu_register_reset(main_cpu_reset, cpu); 233 234 memory_region_add_subregion(address_space_mem, ram_base, machine->ram); 235 236 dinfo = drive_get(IF_PFLASH, 0, 0); 237 pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE, 238 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 239 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); 240 241 cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT]; 242 dev = qdev_new("xlnx.xps-intc"); 243 qdev_prop_set_uint32(dev, "kind-of-intr", 0); 244 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 245 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); 246 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]); 247 for (i = 0; i < 32; i++) { 248 irq[i] = qdev_get_gpio_in(dev, i); 249 } 250 251 serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ], 252 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 253 254 /* 2 timers at irq 2 @ 62 Mhz. */ 255 dev = qdev_new("xlnx.xps-timer"); 256 qdev_prop_set_uint32(dev, "one-timer-only", 0); 257 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); 258 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 259 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); 260 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); 261 262 if (kernel_filename) { 263 uint64_t entry, high; 264 hwaddr boot_offset; 265 266 /* Boots a kernel elf binary. */ 267 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, 268 &entry, NULL, &high, NULL, 1, PPC_ELF_MACHINE, 269 0, 0); 270 boot_info.bootstrap_pc = entry & 0x00ffffff; 271 272 if (kernel_size < 0) { 273 boot_offset = 0x1200000; 274 /* If we failed loading ELF's try a raw image. */ 275 kernel_size = load_image_targphys(kernel_filename, 276 boot_offset, 277 machine->ram_size); 278 boot_info.bootstrap_pc = boot_offset; 279 high = boot_info.bootstrap_pc + kernel_size + 8192; 280 } 281 282 boot_info.ima_size = kernel_size; 283 284 /* Load initrd. */ 285 if (machine->initrd_filename) { 286 initrd_base = high = ROUND_UP(high, 4); 287 initrd_size = load_image_targphys(machine->initrd_filename, 288 high, machine->ram_size - high); 289 290 if (initrd_size < 0) { 291 error_report("couldn't load ram disk '%s'", 292 machine->initrd_filename); 293 exit(1); 294 } 295 high = ROUND_UP(high + initrd_size, 4); 296 } 297 298 /* Provide a device-tree. */ 299 boot_info.fdt = high + (8192 * 2); 300 boot_info.fdt &= ~8191; 301 302 xilinx_load_device_tree(boot_info.fdt, machine->ram_size, 303 initrd_base, initrd_size, 304 kernel_cmdline); 305 } 306 env->load_info = &boot_info; 307 } 308 309 static void virtex_machine_init(MachineClass *mc) 310 { 311 mc->desc = "Xilinx Virtex ML507 reference design"; 312 mc->init = virtex_init; 313 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440-xilinx"); 314 mc->default_ram_id = "ram"; 315 } 316 317 DEFINE_MACHINE("virtex-ml507", virtex_machine_init) 318