1 /* 2 * QEMU sPAPR PCI host originated from Uninorth PCI host 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. 5 * Copyright (C) 2011 David Gibson, IBM Corporation. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "cpu.h" 29 #include "hw/irq.h" 30 #include "hw/sysbus.h" 31 #include "migration/vmstate.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/msi.h" 34 #include "hw/pci/msix.h" 35 #include "hw/pci/pci_host.h" 36 #include "hw/ppc/spapr.h" 37 #include "hw/pci-host/spapr.h" 38 #include "exec/address-spaces.h" 39 #include "exec/ram_addr.h" 40 #include <libfdt.h> 41 #include "trace.h" 42 #include "qemu/error-report.h" 43 #include "qemu/module.h" 44 #include "qapi/qmp/qerror.h" 45 #include "hw/ppc/fdt.h" 46 #include "hw/pci/pci_bridge.h" 47 #include "hw/pci/pci_bus.h" 48 #include "hw/pci/pci_ids.h" 49 #include "hw/ppc/spapr_drc.h" 50 #include "hw/qdev-properties.h" 51 #include "sysemu/device_tree.h" 52 #include "sysemu/kvm.h" 53 #include "sysemu/hostmem.h" 54 #include "sysemu/numa.h" 55 56 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ 57 #define RTAS_QUERY_FN 0 58 #define RTAS_CHANGE_FN 1 59 #define RTAS_RESET_FN 2 60 #define RTAS_CHANGE_MSI_FN 3 61 #define RTAS_CHANGE_MSIX_FN 4 62 63 /* Interrupt types to return on RTAS_CHANGE_* */ 64 #define RTAS_TYPE_MSI 1 65 #define RTAS_TYPE_MSIX 2 66 67 SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid) 68 { 69 SpaprPhbState *sphb; 70 71 QLIST_FOREACH(sphb, &spapr->phbs, list) { 72 if (sphb->buid != buid) { 73 continue; 74 } 75 return sphb; 76 } 77 78 return NULL; 79 } 80 81 PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid, 82 uint32_t config_addr) 83 { 84 SpaprPhbState *sphb = spapr_pci_find_phb(spapr, buid); 85 PCIHostState *phb = PCI_HOST_BRIDGE(sphb); 86 int bus_num = (config_addr >> 16) & 0xFF; 87 int devfn = (config_addr >> 8) & 0xFF; 88 89 if (!phb) { 90 return NULL; 91 } 92 93 return pci_find_device(phb->bus, bus_num, devfn); 94 } 95 96 static uint32_t rtas_pci_cfgaddr(uint32_t arg) 97 { 98 /* This handles the encoding of extended config space addresses */ 99 return ((arg >> 20) & 0xf00) | (arg & 0xff); 100 } 101 102 static void finish_read_pci_config(SpaprMachineState *spapr, uint64_t buid, 103 uint32_t addr, uint32_t size, 104 target_ulong rets) 105 { 106 PCIDevice *pci_dev; 107 uint32_t val; 108 109 if ((size != 1) && (size != 2) && (size != 4)) { 110 /* access must be 1, 2 or 4 bytes */ 111 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 112 return; 113 } 114 115 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 116 addr = rtas_pci_cfgaddr(addr); 117 118 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 119 /* Access must be to a valid device, within bounds and 120 * naturally aligned */ 121 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 122 return; 123 } 124 125 val = pci_host_config_read_common(pci_dev, addr, 126 pci_config_size(pci_dev), size); 127 128 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 129 rtas_st(rets, 1, val); 130 } 131 132 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 133 uint32_t token, uint32_t nargs, 134 target_ulong args, 135 uint32_t nret, target_ulong rets) 136 { 137 uint64_t buid; 138 uint32_t size, addr; 139 140 if ((nargs != 4) || (nret != 2)) { 141 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 142 return; 143 } 144 145 buid = rtas_ldq(args, 1); 146 size = rtas_ld(args, 3); 147 addr = rtas_ld(args, 0); 148 149 finish_read_pci_config(spapr, buid, addr, size, rets); 150 } 151 152 static void rtas_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 153 uint32_t token, uint32_t nargs, 154 target_ulong args, 155 uint32_t nret, target_ulong rets) 156 { 157 uint32_t size, addr; 158 159 if ((nargs != 2) || (nret != 2)) { 160 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 161 return; 162 } 163 164 size = rtas_ld(args, 1); 165 addr = rtas_ld(args, 0); 166 167 finish_read_pci_config(spapr, 0, addr, size, rets); 168 } 169 170 static void finish_write_pci_config(SpaprMachineState *spapr, uint64_t buid, 171 uint32_t addr, uint32_t size, 172 uint32_t val, target_ulong rets) 173 { 174 PCIDevice *pci_dev; 175 176 if ((size != 1) && (size != 2) && (size != 4)) { 177 /* access must be 1, 2 or 4 bytes */ 178 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 179 return; 180 } 181 182 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 183 addr = rtas_pci_cfgaddr(addr); 184 185 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 186 /* Access must be to a valid device, within bounds and 187 * naturally aligned */ 188 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 189 return; 190 } 191 192 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), 193 val, size); 194 195 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 196 } 197 198 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 199 uint32_t token, uint32_t nargs, 200 target_ulong args, 201 uint32_t nret, target_ulong rets) 202 { 203 uint64_t buid; 204 uint32_t val, size, addr; 205 206 if ((nargs != 5) || (nret != 1)) { 207 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 208 return; 209 } 210 211 buid = rtas_ldq(args, 1); 212 val = rtas_ld(args, 4); 213 size = rtas_ld(args, 3); 214 addr = rtas_ld(args, 0); 215 216 finish_write_pci_config(spapr, buid, addr, size, val, rets); 217 } 218 219 static void rtas_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 220 uint32_t token, uint32_t nargs, 221 target_ulong args, 222 uint32_t nret, target_ulong rets) 223 { 224 uint32_t val, size, addr; 225 226 if ((nargs != 3) || (nret != 1)) { 227 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 228 return; 229 } 230 231 232 val = rtas_ld(args, 2); 233 size = rtas_ld(args, 1); 234 addr = rtas_ld(args, 0); 235 236 finish_write_pci_config(spapr, 0, addr, size, val, rets); 237 } 238 239 /* 240 * Set MSI/MSIX message data. 241 * This is required for msi_notify()/msix_notify() which 242 * will write at the addresses via spapr_msi_write(). 243 * 244 * If hwaddr == 0, all entries will have .data == first_irq i.e. 245 * table will be reset. 246 */ 247 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, 248 unsigned first_irq, unsigned req_num) 249 { 250 unsigned i; 251 MSIMessage msg = { .address = addr, .data = first_irq }; 252 253 if (!msix) { 254 msi_set_message(pdev, msg); 255 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); 256 return; 257 } 258 259 for (i = 0; i < req_num; ++i) { 260 msix_set_message(pdev, i, msg); 261 trace_spapr_pci_msi_setup(pdev->name, i, msg.address); 262 if (addr) { 263 ++msg.data; 264 } 265 } 266 } 267 268 static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr, 269 uint32_t token, uint32_t nargs, 270 target_ulong args, uint32_t nret, 271 target_ulong rets) 272 { 273 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 274 uint32_t config_addr = rtas_ld(args, 0); 275 uint64_t buid = rtas_ldq(args, 1); 276 unsigned int func = rtas_ld(args, 3); 277 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ 278 unsigned int seq_num = rtas_ld(args, 5); 279 unsigned int ret_intr_type; 280 unsigned int irq, max_irqs = 0; 281 SpaprPhbState *phb = NULL; 282 PCIDevice *pdev = NULL; 283 SpaprPciMsi *msi; 284 int *config_addr_key; 285 Error *err = NULL; 286 int i; 287 288 /* Fins SpaprPhbState */ 289 phb = spapr_pci_find_phb(spapr, buid); 290 if (phb) { 291 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 292 } 293 if (!phb || !pdev) { 294 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 295 return; 296 } 297 298 switch (func) { 299 case RTAS_CHANGE_FN: 300 if (msi_present(pdev)) { 301 ret_intr_type = RTAS_TYPE_MSI; 302 } else if (msix_present(pdev)) { 303 ret_intr_type = RTAS_TYPE_MSIX; 304 } else { 305 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 306 return; 307 } 308 break; 309 case RTAS_CHANGE_MSI_FN: 310 if (msi_present(pdev)) { 311 ret_intr_type = RTAS_TYPE_MSI; 312 } else { 313 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 314 return; 315 } 316 break; 317 case RTAS_CHANGE_MSIX_FN: 318 if (msix_present(pdev)) { 319 ret_intr_type = RTAS_TYPE_MSIX; 320 } else { 321 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 322 return; 323 } 324 break; 325 default: 326 error_report("rtas_ibm_change_msi(%u) is not implemented", func); 327 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 328 return; 329 } 330 331 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr); 332 333 /* Releasing MSIs */ 334 if (!req_num) { 335 if (!msi) { 336 trace_spapr_pci_msi("Releasing wrong config", config_addr); 337 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 338 return; 339 } 340 341 if (msi_present(pdev)) { 342 spapr_msi_setmsg(pdev, 0, false, 0, 0); 343 } 344 if (msix_present(pdev)) { 345 spapr_msi_setmsg(pdev, 0, true, 0, 0); 346 } 347 g_hash_table_remove(phb->msi, &config_addr); 348 349 trace_spapr_pci_msi("Released MSIs", config_addr); 350 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 351 rtas_st(rets, 1, 0); 352 return; 353 } 354 355 /* Enabling MSI */ 356 357 /* Check if the device supports as many IRQs as requested */ 358 if (ret_intr_type == RTAS_TYPE_MSI) { 359 max_irqs = msi_nr_vectors_allocated(pdev); 360 } else if (ret_intr_type == RTAS_TYPE_MSIX) { 361 max_irqs = pdev->msix_entries_nr; 362 } 363 if (!max_irqs) { 364 error_report("Requested interrupt type %d is not enabled for device %x", 365 ret_intr_type, config_addr); 366 rtas_st(rets, 0, -1); /* Hardware error */ 367 return; 368 } 369 /* Correct the number if the guest asked for too many */ 370 if (req_num > max_irqs) { 371 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); 372 req_num = max_irqs; 373 irq = 0; /* to avoid misleading trace */ 374 goto out; 375 } 376 377 /* Allocate MSIs */ 378 if (smc->legacy_irq_allocation) { 379 irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI, 380 &err); 381 } else { 382 irq = spapr_irq_msi_alloc(spapr, req_num, 383 ret_intr_type == RTAS_TYPE_MSI, &err); 384 } 385 if (err) { 386 error_reportf_err(err, "Can't allocate MSIs for device %x: ", 387 config_addr); 388 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 389 return; 390 } 391 392 for (i = 0; i < req_num; i++) { 393 spapr_irq_claim(spapr, irq + i, false, &err); 394 if (err) { 395 if (i) { 396 spapr_irq_free(spapr, irq, i); 397 } 398 if (!smc->legacy_irq_allocation) { 399 spapr_irq_msi_free(spapr, irq, req_num); 400 } 401 error_reportf_err(err, "Can't allocate MSIs for device %x: ", 402 config_addr); 403 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 404 return; 405 } 406 } 407 408 /* Release previous MSIs */ 409 if (msi) { 410 g_hash_table_remove(phb->msi, &config_addr); 411 } 412 413 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ 414 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, 415 irq, req_num); 416 417 /* Add MSI device to cache */ 418 msi = g_new(SpaprPciMsi, 1); 419 msi->first_irq = irq; 420 msi->num = req_num; 421 config_addr_key = g_new(int, 1); 422 *config_addr_key = config_addr; 423 g_hash_table_insert(phb->msi, config_addr_key, msi); 424 425 out: 426 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 427 rtas_st(rets, 1, req_num); 428 rtas_st(rets, 2, ++seq_num); 429 if (nret > 3) { 430 rtas_st(rets, 3, ret_intr_type); 431 } 432 433 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); 434 } 435 436 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, 437 SpaprMachineState *spapr, 438 uint32_t token, 439 uint32_t nargs, 440 target_ulong args, 441 uint32_t nret, 442 target_ulong rets) 443 { 444 uint32_t config_addr = rtas_ld(args, 0); 445 uint64_t buid = rtas_ldq(args, 1); 446 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); 447 SpaprPhbState *phb = NULL; 448 PCIDevice *pdev = NULL; 449 SpaprPciMsi *msi; 450 451 /* Find SpaprPhbState */ 452 phb = spapr_pci_find_phb(spapr, buid); 453 if (phb) { 454 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 455 } 456 if (!phb || !pdev) { 457 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 458 return; 459 } 460 461 /* Find device descriptor and start IRQ */ 462 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr); 463 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { 464 trace_spapr_pci_msi("Failed to return vector", config_addr); 465 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 466 return; 467 } 468 intr_src_num = msi->first_irq + ioa_intr_num; 469 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, 470 intr_src_num); 471 472 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 473 rtas_st(rets, 1, intr_src_num); 474 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ 475 } 476 477 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, 478 SpaprMachineState *spapr, 479 uint32_t token, uint32_t nargs, 480 target_ulong args, uint32_t nret, 481 target_ulong rets) 482 { 483 SpaprPhbState *sphb; 484 uint32_t addr, option; 485 uint64_t buid; 486 int ret; 487 488 if ((nargs != 4) || (nret != 1)) { 489 goto param_error_exit; 490 } 491 492 buid = rtas_ldq(args, 1); 493 addr = rtas_ld(args, 0); 494 option = rtas_ld(args, 3); 495 496 sphb = spapr_pci_find_phb(spapr, buid); 497 if (!sphb) { 498 goto param_error_exit; 499 } 500 501 if (!spapr_phb_eeh_available(sphb)) { 502 goto param_error_exit; 503 } 504 505 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option); 506 rtas_st(rets, 0, ret); 507 return; 508 509 param_error_exit: 510 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 511 } 512 513 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, 514 SpaprMachineState *spapr, 515 uint32_t token, uint32_t nargs, 516 target_ulong args, uint32_t nret, 517 target_ulong rets) 518 { 519 SpaprPhbState *sphb; 520 PCIDevice *pdev; 521 uint32_t addr, option; 522 uint64_t buid; 523 524 if ((nargs != 4) || (nret != 2)) { 525 goto param_error_exit; 526 } 527 528 buid = rtas_ldq(args, 1); 529 sphb = spapr_pci_find_phb(spapr, buid); 530 if (!sphb) { 531 goto param_error_exit; 532 } 533 534 if (!spapr_phb_eeh_available(sphb)) { 535 goto param_error_exit; 536 } 537 538 /* 539 * We always have PE address of form "00BB0001". "BB" 540 * represents the bus number of PE's primary bus. 541 */ 542 option = rtas_ld(args, 3); 543 switch (option) { 544 case RTAS_GET_PE_ADDR: 545 addr = rtas_ld(args, 0); 546 pdev = spapr_pci_find_dev(spapr, buid, addr); 547 if (!pdev) { 548 goto param_error_exit; 549 } 550 551 rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1); 552 break; 553 case RTAS_GET_PE_MODE: 554 rtas_st(rets, 1, RTAS_PE_MODE_SHARED); 555 break; 556 default: 557 goto param_error_exit; 558 } 559 560 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 561 return; 562 563 param_error_exit: 564 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 565 } 566 567 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, 568 SpaprMachineState *spapr, 569 uint32_t token, uint32_t nargs, 570 target_ulong args, uint32_t nret, 571 target_ulong rets) 572 { 573 SpaprPhbState *sphb; 574 uint64_t buid; 575 int state, ret; 576 577 if ((nargs != 3) || (nret != 4 && nret != 5)) { 578 goto param_error_exit; 579 } 580 581 buid = rtas_ldq(args, 1); 582 sphb = spapr_pci_find_phb(spapr, buid); 583 if (!sphb) { 584 goto param_error_exit; 585 } 586 587 if (!spapr_phb_eeh_available(sphb)) { 588 goto param_error_exit; 589 } 590 591 ret = spapr_phb_vfio_eeh_get_state(sphb, &state); 592 rtas_st(rets, 0, ret); 593 if (ret != RTAS_OUT_SUCCESS) { 594 return; 595 } 596 597 rtas_st(rets, 1, state); 598 rtas_st(rets, 2, RTAS_EEH_SUPPORT); 599 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); 600 if (nret >= 5) { 601 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); 602 } 603 return; 604 605 param_error_exit: 606 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 607 } 608 609 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, 610 SpaprMachineState *spapr, 611 uint32_t token, uint32_t nargs, 612 target_ulong args, uint32_t nret, 613 target_ulong rets) 614 { 615 SpaprPhbState *sphb; 616 uint32_t option; 617 uint64_t buid; 618 int ret; 619 620 if ((nargs != 4) || (nret != 1)) { 621 goto param_error_exit; 622 } 623 624 buid = rtas_ldq(args, 1); 625 option = rtas_ld(args, 3); 626 sphb = spapr_pci_find_phb(spapr, buid); 627 if (!sphb) { 628 goto param_error_exit; 629 } 630 631 if (!spapr_phb_eeh_available(sphb)) { 632 goto param_error_exit; 633 } 634 635 ret = spapr_phb_vfio_eeh_reset(sphb, option); 636 rtas_st(rets, 0, ret); 637 return; 638 639 param_error_exit: 640 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 641 } 642 643 static void rtas_ibm_configure_pe(PowerPCCPU *cpu, 644 SpaprMachineState *spapr, 645 uint32_t token, uint32_t nargs, 646 target_ulong args, uint32_t nret, 647 target_ulong rets) 648 { 649 SpaprPhbState *sphb; 650 uint64_t buid; 651 int ret; 652 653 if ((nargs != 3) || (nret != 1)) { 654 goto param_error_exit; 655 } 656 657 buid = rtas_ldq(args, 1); 658 sphb = spapr_pci_find_phb(spapr, buid); 659 if (!sphb) { 660 goto param_error_exit; 661 } 662 663 if (!spapr_phb_eeh_available(sphb)) { 664 goto param_error_exit; 665 } 666 667 ret = spapr_phb_vfio_eeh_configure(sphb); 668 rtas_st(rets, 0, ret); 669 return; 670 671 param_error_exit: 672 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 673 } 674 675 /* To support it later */ 676 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, 677 SpaprMachineState *spapr, 678 uint32_t token, uint32_t nargs, 679 target_ulong args, uint32_t nret, 680 target_ulong rets) 681 { 682 SpaprPhbState *sphb; 683 int option; 684 uint64_t buid; 685 686 if ((nargs != 8) || (nret != 1)) { 687 goto param_error_exit; 688 } 689 690 buid = rtas_ldq(args, 1); 691 sphb = spapr_pci_find_phb(spapr, buid); 692 if (!sphb) { 693 goto param_error_exit; 694 } 695 696 if (!spapr_phb_eeh_available(sphb)) { 697 goto param_error_exit; 698 } 699 700 option = rtas_ld(args, 7); 701 switch (option) { 702 case RTAS_SLOT_TEMP_ERR_LOG: 703 case RTAS_SLOT_PERM_ERR_LOG: 704 break; 705 default: 706 goto param_error_exit; 707 } 708 709 /* We don't have error log yet */ 710 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); 711 return; 712 713 param_error_exit: 714 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 715 } 716 717 static void pci_spapr_set_irq(void *opaque, int irq_num, int level) 718 { 719 /* 720 * Here we use the number returned by pci_swizzle_map_irq_fn to find a 721 * corresponding qemu_irq. 722 */ 723 SpaprPhbState *phb = opaque; 724 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 725 726 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); 727 qemu_set_irq(spapr_qirq(spapr, phb->lsi_table[irq_num].irq), level); 728 } 729 730 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) 731 { 732 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); 733 PCIINTxRoute route; 734 735 route.mode = PCI_INTX_ENABLED; 736 route.irq = sphb->lsi_table[pin].irq; 737 738 return route; 739 } 740 741 /* 742 * MSI/MSIX memory region implementation. 743 * The handler handles both MSI and MSIX. 744 * The vector number is encoded in least bits in data. 745 */ 746 static void spapr_msi_write(void *opaque, hwaddr addr, 747 uint64_t data, unsigned size) 748 { 749 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 750 uint32_t irq = data; 751 752 trace_spapr_pci_msi_write(addr, data, irq); 753 754 qemu_irq_pulse(spapr_qirq(spapr, irq)); 755 } 756 757 static const MemoryRegionOps spapr_msi_ops = { 758 /* There is no .read as the read result is undefined by PCI spec */ 759 .read = NULL, 760 .write = spapr_msi_write, 761 .endianness = DEVICE_LITTLE_ENDIAN 762 }; 763 764 /* 765 * PHB PCI device 766 */ 767 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 768 { 769 SpaprPhbState *phb = opaque; 770 771 return &phb->iommu_as; 772 } 773 774 static char *spapr_phb_vfio_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) 775 { 776 char *path = NULL, *buf = NULL, *host = NULL; 777 778 /* Get the PCI VFIO host id */ 779 host = object_property_get_str(OBJECT(pdev), "host", NULL); 780 if (!host) { 781 goto err_out; 782 } 783 784 /* Construct the path of the file that will give us the DT location */ 785 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); 786 g_free(host); 787 if (!g_file_get_contents(path, &buf, NULL, NULL)) { 788 goto err_out; 789 } 790 g_free(path); 791 792 /* Construct and read from host device tree the loc-code */ 793 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); 794 g_free(buf); 795 if (!g_file_get_contents(path, &buf, NULL, NULL)) { 796 goto err_out; 797 } 798 return buf; 799 800 err_out: 801 g_free(path); 802 return NULL; 803 } 804 805 static char *spapr_phb_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) 806 { 807 char *buf; 808 const char *devtype = "qemu"; 809 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 810 811 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 812 buf = spapr_phb_vfio_get_loc_code(sphb, pdev); 813 if (buf) { 814 return buf; 815 } 816 devtype = "vfio"; 817 } 818 /* 819 * For emulated devices and VFIO-failure case, make up 820 * the loc-code. 821 */ 822 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", 823 devtype, pdev->name, sphb->index, busnr, 824 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 825 return buf; 826 } 827 828 /* Macros to operate with address in OF binding to PCI */ 829 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) 830 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ 831 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ 832 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ 833 #define b_ss(x) b_x((x), 24, 2) /* the space code */ 834 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ 835 #define b_ddddd(x) b_x((x), 11, 5) /* device number */ 836 #define b_fff(x) b_x((x), 8, 3) /* function number */ 837 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ 838 839 /* for 'reg' OF properties */ 840 #define RESOURCE_CELLS_SIZE 2 841 #define RESOURCE_CELLS_ADDRESS 3 842 843 typedef struct ResourceFields { 844 uint32_t phys_hi; 845 uint32_t phys_mid; 846 uint32_t phys_lo; 847 uint32_t size_hi; 848 uint32_t size_lo; 849 } QEMU_PACKED ResourceFields; 850 851 typedef struct ResourceProps { 852 ResourceFields reg[8]; 853 uint32_t reg_len; 854 } ResourceProps; 855 856 /* fill in the 'reg' OF properties for 857 * a PCI device. 'reg' describes resource requirements for a 858 * device's IO/MEM regions. 859 * 860 * the property is an array of ('phys-addr', 'size') pairs describing 861 * the addressable regions of the PCI device, where 'phys-addr' is a 862 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to 863 * (phys.hi, phys.mid, phys.lo), and 'size' is a 864 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). 865 * 866 * phys.hi = 0xYYXXXXZZ, where: 867 * 0xYY = npt000ss 868 * ||| | 869 * ||| +-- space code 870 * ||| | 871 * ||| + 00 if configuration space 872 * ||| + 01 if IO region, 873 * ||| + 10 if 32-bit MEM region 874 * ||| + 11 if 64-bit MEM region 875 * ||| 876 * ||+------ for non-relocatable IO: 1 if aliased 877 * || for relocatable IO: 1 if below 64KB 878 * || for MEM: 1 if below 1MB 879 * |+------- 1 if region is prefetchable 880 * +-------- 1 if region is non-relocatable 881 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function 882 * bits respectively 883 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding 884 * to the region 885 * 886 * phys.mid and phys.lo correspond respectively to the hi/lo portions 887 * of the actual address of the region. 888 * 889 * note also that addresses defined in this property are, at least 890 * for PAPR guests, relative to the PHBs IO/MEM windows, and 891 * correspond directly to the addresses in the BARs. 892 * 893 * in accordance with PCI Bus Binding to Open Firmware, 894 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, 895 * Appendix C. 896 */ 897 static void populate_resource_props(PCIDevice *d, ResourceProps *rp) 898 { 899 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); 900 uint32_t dev_id = (b_bbbbbbbb(bus_num) | 901 b_ddddd(PCI_SLOT(d->devfn)) | 902 b_fff(PCI_FUNC(d->devfn))); 903 ResourceFields *reg; 904 int i, reg_idx = 0; 905 906 /* config space region */ 907 reg = &rp->reg[reg_idx++]; 908 reg->phys_hi = cpu_to_be32(dev_id); 909 reg->phys_mid = 0; 910 reg->phys_lo = 0; 911 reg->size_hi = 0; 912 reg->size_lo = 0; 913 914 for (i = 0; i < PCI_NUM_REGIONS; i++) { 915 if (!d->io_regions[i].size) { 916 continue; 917 } 918 919 reg = &rp->reg[reg_idx++]; 920 921 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); 922 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 923 reg->phys_hi |= cpu_to_be32(b_ss(1)); 924 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 925 reg->phys_hi |= cpu_to_be32(b_ss(3)); 926 } else { 927 reg->phys_hi |= cpu_to_be32(b_ss(2)); 928 } 929 reg->phys_mid = 0; 930 reg->phys_lo = 0; 931 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); 932 reg->size_lo = cpu_to_be32(d->io_regions[i].size); 933 } 934 935 rp->reg_len = reg_idx * sizeof(ResourceFields); 936 } 937 938 typedef struct PCIClass PCIClass; 939 typedef struct PCISubClass PCISubClass; 940 typedef struct PCIIFace PCIIFace; 941 942 struct PCIIFace { 943 int iface; 944 const char *name; 945 }; 946 947 struct PCISubClass { 948 int subclass; 949 const char *name; 950 const PCIIFace *iface; 951 }; 952 953 struct PCIClass { 954 const char *name; 955 const PCISubClass *subc; 956 }; 957 958 static const PCISubClass undef_subclass[] = { 959 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL }, 960 { 0xFF, NULL, NULL }, 961 }; 962 963 static const PCISubClass mass_subclass[] = { 964 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL }, 965 { PCI_CLASS_STORAGE_IDE, "ide", NULL }, 966 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL }, 967 { PCI_CLASS_STORAGE_IPI, "ipi", NULL }, 968 { PCI_CLASS_STORAGE_RAID, "raid", NULL }, 969 { PCI_CLASS_STORAGE_ATA, "ata", NULL }, 970 { PCI_CLASS_STORAGE_SATA, "sata", NULL }, 971 { PCI_CLASS_STORAGE_SAS, "sas", NULL }, 972 { 0xFF, NULL, NULL }, 973 }; 974 975 static const PCISubClass net_subclass[] = { 976 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL }, 977 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL }, 978 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL }, 979 { PCI_CLASS_NETWORK_ATM, "atm", NULL }, 980 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL }, 981 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL }, 982 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL }, 983 { 0xFF, NULL, NULL }, 984 }; 985 986 static const PCISubClass displ_subclass[] = { 987 { PCI_CLASS_DISPLAY_VGA, "vga", NULL }, 988 { PCI_CLASS_DISPLAY_XGA, "xga", NULL }, 989 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL }, 990 { 0xFF, NULL, NULL }, 991 }; 992 993 static const PCISubClass media_subclass[] = { 994 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL }, 995 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL }, 996 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL }, 997 { 0xFF, NULL, NULL }, 998 }; 999 1000 static const PCISubClass mem_subclass[] = { 1001 { PCI_CLASS_MEMORY_RAM, "memory", NULL }, 1002 { PCI_CLASS_MEMORY_FLASH, "flash", NULL }, 1003 { 0xFF, NULL, NULL }, 1004 }; 1005 1006 static const PCISubClass bridg_subclass[] = { 1007 { PCI_CLASS_BRIDGE_HOST, "host", NULL }, 1008 { PCI_CLASS_BRIDGE_ISA, "isa", NULL }, 1009 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL }, 1010 { PCI_CLASS_BRIDGE_MC, "mca", NULL }, 1011 { PCI_CLASS_BRIDGE_PCI, "pci", NULL }, 1012 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL }, 1013 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL }, 1014 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL }, 1015 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL }, 1016 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL }, 1017 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL }, 1018 { 0xFF, NULL, NULL }, 1019 }; 1020 1021 static const PCISubClass comm_subclass[] = { 1022 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL }, 1023 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL }, 1024 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL }, 1025 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL }, 1026 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL }, 1027 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL }, 1028 { 0xFF, NULL, NULL, }, 1029 }; 1030 1031 static const PCIIFace pic_iface[] = { 1032 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" }, 1033 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" }, 1034 { 0xFF, NULL }, 1035 }; 1036 1037 static const PCISubClass sys_subclass[] = { 1038 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface }, 1039 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL }, 1040 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL }, 1041 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL }, 1042 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL }, 1043 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL }, 1044 { 0xFF, NULL, NULL }, 1045 }; 1046 1047 static const PCISubClass inp_subclass[] = { 1048 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL }, 1049 { PCI_CLASS_INPUT_PEN, "pen", NULL }, 1050 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL }, 1051 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL }, 1052 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL }, 1053 { 0xFF, NULL, NULL }, 1054 }; 1055 1056 static const PCISubClass dock_subclass[] = { 1057 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL }, 1058 { 0xFF, NULL, NULL }, 1059 }; 1060 1061 static const PCISubClass cpu_subclass[] = { 1062 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL }, 1063 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL }, 1064 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL }, 1065 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL }, 1066 { 0xFF, NULL, NULL }, 1067 }; 1068 1069 static const PCIIFace usb_iface[] = { 1070 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" }, 1071 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", }, 1072 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" }, 1073 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" }, 1074 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" }, 1075 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" }, 1076 { 0xFF, NULL }, 1077 }; 1078 1079 static const PCISubClass ser_subclass[] = { 1080 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL }, 1081 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL }, 1082 { PCI_CLASS_SERIAL_SSA, "ssa", NULL }, 1083 { PCI_CLASS_SERIAL_USB, "usb", usb_iface }, 1084 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL }, 1085 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL }, 1086 { PCI_CLASS_SERIAL_IB, "infiniband", NULL }, 1087 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL }, 1088 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL }, 1089 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL }, 1090 { 0xFF, NULL, NULL }, 1091 }; 1092 1093 static const PCISubClass wrl_subclass[] = { 1094 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL }, 1095 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL }, 1096 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL }, 1097 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL }, 1098 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL }, 1099 { 0xFF, NULL, NULL }, 1100 }; 1101 1102 static const PCISubClass sat_subclass[] = { 1103 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL }, 1104 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL }, 1105 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL }, 1106 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL }, 1107 { 0xFF, NULL, NULL }, 1108 }; 1109 1110 static const PCISubClass crypt_subclass[] = { 1111 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL }, 1112 { PCI_CLASS_CRYPT_ENTERTAINMENT, 1113 "entertainment-encryption", NULL }, 1114 { 0xFF, NULL, NULL }, 1115 }; 1116 1117 static const PCISubClass spc_subclass[] = { 1118 { PCI_CLASS_SP_DPIO, "dpio", NULL }, 1119 { PCI_CLASS_SP_PERF, "counter", NULL }, 1120 { PCI_CLASS_SP_SYNCH, "measurement", NULL }, 1121 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL }, 1122 { 0xFF, NULL, NULL }, 1123 }; 1124 1125 static const PCIClass pci_classes[] = { 1126 { "legacy-device", undef_subclass }, 1127 { "mass-storage", mass_subclass }, 1128 { "network", net_subclass }, 1129 { "display", displ_subclass, }, 1130 { "multimedia-device", media_subclass }, 1131 { "memory-controller", mem_subclass }, 1132 { "unknown-bridge", bridg_subclass }, 1133 { "communication-controller", comm_subclass}, 1134 { "system-peripheral", sys_subclass }, 1135 { "input-controller", inp_subclass }, 1136 { "docking-station", dock_subclass }, 1137 { "cpu", cpu_subclass }, 1138 { "serial-bus", ser_subclass }, 1139 { "wireless-controller", wrl_subclass }, 1140 { "intelligent-io", NULL }, 1141 { "satellite-device", sat_subclass }, 1142 { "encryption", crypt_subclass }, 1143 { "data-processing-controller", spc_subclass }, 1144 }; 1145 1146 static const char *dt_name_from_class(uint8_t class, uint8_t subclass, 1147 uint8_t iface) 1148 { 1149 const PCIClass *pclass; 1150 const PCISubClass *psubclass; 1151 const PCIIFace *piface; 1152 const char *name; 1153 1154 if (class >= ARRAY_SIZE(pci_classes)) { 1155 return "pci"; 1156 } 1157 1158 pclass = pci_classes + class; 1159 name = pclass->name; 1160 1161 if (pclass->subc == NULL) { 1162 return name; 1163 } 1164 1165 psubclass = pclass->subc; 1166 while ((psubclass->subclass & 0xff) != 0xff) { 1167 if ((psubclass->subclass & 0xff) == subclass) { 1168 name = psubclass->name; 1169 break; 1170 } 1171 psubclass++; 1172 } 1173 1174 piface = psubclass->iface; 1175 if (piface == NULL) { 1176 return name; 1177 } 1178 while ((piface->iface & 0xff) != 0xff) { 1179 if ((piface->iface & 0xff) == iface) { 1180 name = piface->name; 1181 break; 1182 } 1183 piface++; 1184 } 1185 1186 return name; 1187 } 1188 1189 /* 1190 * DRC helper functions 1191 */ 1192 1193 static uint32_t drc_id_from_devfn(SpaprPhbState *phb, 1194 uint8_t chassis, int32_t devfn) 1195 { 1196 return (phb->index << 16) | (chassis << 8) | devfn; 1197 } 1198 1199 static SpaprDrc *drc_from_devfn(SpaprPhbState *phb, 1200 uint8_t chassis, int32_t devfn) 1201 { 1202 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI, 1203 drc_id_from_devfn(phb, chassis, devfn)); 1204 } 1205 1206 static uint8_t chassis_from_bus(PCIBus *bus) 1207 { 1208 if (pci_bus_is_root(bus)) { 1209 return 0; 1210 } else { 1211 PCIDevice *bridge = pci_bridge_get_device(bus); 1212 1213 return object_property_get_uint(OBJECT(bridge), "chassis_nr", 1214 &error_abort); 1215 } 1216 } 1217 1218 static SpaprDrc *drc_from_dev(SpaprPhbState *phb, PCIDevice *dev) 1219 { 1220 uint8_t chassis = chassis_from_bus(pci_get_bus(dev)); 1221 1222 return drc_from_devfn(phb, chassis, dev->devfn); 1223 } 1224 1225 static void add_drcs(SpaprPhbState *phb, PCIBus *bus) 1226 { 1227 Object *owner; 1228 int i; 1229 uint8_t chassis; 1230 1231 if (!phb->dr_enabled) { 1232 return; 1233 } 1234 1235 chassis = chassis_from_bus(bus); 1236 1237 if (pci_bus_is_root(bus)) { 1238 owner = OBJECT(phb); 1239 } else { 1240 owner = OBJECT(pci_bridge_get_device(bus)); 1241 } 1242 1243 for (i = 0; i < PCI_SLOT_MAX * PCI_FUNC_MAX; i++) { 1244 spapr_dr_connector_new(owner, TYPE_SPAPR_DRC_PCI, 1245 drc_id_from_devfn(phb, chassis, i)); 1246 } 1247 } 1248 1249 static void remove_drcs(SpaprPhbState *phb, PCIBus *bus) 1250 { 1251 int i; 1252 uint8_t chassis; 1253 1254 if (!phb->dr_enabled) { 1255 return; 1256 } 1257 1258 chassis = chassis_from_bus(bus); 1259 1260 for (i = PCI_SLOT_MAX * PCI_FUNC_MAX - 1; i >= 0; i--) { 1261 SpaprDrc *drc = drc_from_devfn(phb, chassis, i); 1262 1263 if (drc) { 1264 object_unparent(OBJECT(drc)); 1265 } 1266 } 1267 } 1268 1269 typedef struct PciWalkFdt { 1270 void *fdt; 1271 int offset; 1272 SpaprPhbState *sphb; 1273 int err; 1274 } PciWalkFdt; 1275 1276 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev, 1277 void *fdt, int parent_offset); 1278 1279 static void spapr_dt_pci_device_cb(PCIBus *bus, PCIDevice *pdev, 1280 void *opaque) 1281 { 1282 PciWalkFdt *p = opaque; 1283 int err; 1284 1285 if (p->err) { 1286 /* Something's already broken, don't keep going */ 1287 return; 1288 } 1289 1290 err = spapr_dt_pci_device(p->sphb, pdev, p->fdt, p->offset); 1291 if (err < 0) { 1292 p->err = err; 1293 } 1294 } 1295 1296 /* Augment PCI device node with bridge specific information */ 1297 static int spapr_dt_pci_bus(SpaprPhbState *sphb, PCIBus *bus, 1298 void *fdt, int offset) 1299 { 1300 Object *owner; 1301 PciWalkFdt cbinfo = { 1302 .fdt = fdt, 1303 .offset = offset, 1304 .sphb = sphb, 1305 .err = 0, 1306 }; 1307 int ret; 1308 1309 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 1310 RESOURCE_CELLS_ADDRESS)); 1311 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1312 RESOURCE_CELLS_SIZE)); 1313 1314 assert(bus); 1315 pci_for_each_device_reverse(bus, pci_bus_num(bus), 1316 spapr_dt_pci_device_cb, &cbinfo); 1317 if (cbinfo.err) { 1318 return cbinfo.err; 1319 } 1320 1321 if (pci_bus_is_root(bus)) { 1322 owner = OBJECT(sphb); 1323 } else { 1324 owner = OBJECT(pci_bridge_get_device(bus)); 1325 } 1326 1327 ret = spapr_dt_drc(fdt, offset, owner, 1328 SPAPR_DR_CONNECTOR_TYPE_PCI); 1329 if (ret) { 1330 return ret; 1331 } 1332 1333 return offset; 1334 } 1335 1336 /* create OF node for pci device and required OF DT properties */ 1337 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev, 1338 void *fdt, int parent_offset) 1339 { 1340 int offset; 1341 const gchar *basename; 1342 gchar *nodename; 1343 int slot = PCI_SLOT(dev->devfn); 1344 int func = PCI_FUNC(dev->devfn); 1345 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1346 ResourceProps rp; 1347 SpaprDrc *drc = drc_from_dev(sphb, dev); 1348 uint32_t vendor_id = pci_default_read_config(dev, PCI_VENDOR_ID, 2); 1349 uint32_t device_id = pci_default_read_config(dev, PCI_DEVICE_ID, 2); 1350 uint32_t revision_id = pci_default_read_config(dev, PCI_REVISION_ID, 1); 1351 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); 1352 uint32_t irq_pin = pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1); 1353 uint32_t subsystem_id = pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2); 1354 uint32_t subsystem_vendor_id = 1355 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2); 1356 uint32_t cache_line_size = 1357 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1); 1358 uint32_t pci_status = pci_default_read_config(dev, PCI_STATUS, 2); 1359 gchar *loc_code; 1360 1361 basename = dt_name_from_class((ccode >> 16) & 0xff, (ccode >> 8) & 0xff, 1362 ccode & 0xff); 1363 1364 if (func != 0) { 1365 nodename = g_strdup_printf("%s@%x,%x", basename, slot, func); 1366 } else { 1367 nodename = g_strdup_printf("%s@%x", basename, slot); 1368 } 1369 1370 _FDT(offset = fdt_add_subnode(fdt, parent_offset, nodename)); 1371 1372 g_free(nodename); 1373 1374 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ 1375 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", vendor_id)); 1376 _FDT(fdt_setprop_cell(fdt, offset, "device-id", device_id)); 1377 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", revision_id)); 1378 1379 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode)); 1380 if (irq_pin) { 1381 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", irq_pin)); 1382 } 1383 1384 if (subsystem_id) { 1385 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", subsystem_id)); 1386 } 1387 1388 if (subsystem_vendor_id) { 1389 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", 1390 subsystem_vendor_id)); 1391 } 1392 1393 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", cache_line_size)); 1394 1395 1396 /* the following fdt cells are masked off the pci status register */ 1397 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", 1398 PCI_STATUS_DEVSEL_MASK & pci_status)); 1399 1400 if (pci_status & PCI_STATUS_FAST_BACK) { 1401 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); 1402 } 1403 if (pci_status & PCI_STATUS_66MHZ) { 1404 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); 1405 } 1406 if (pci_status & PCI_STATUS_UDF) { 1407 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); 1408 } 1409 1410 loc_code = spapr_phb_get_loc_code(sphb, dev); 1411 _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", loc_code)); 1412 g_free(loc_code); 1413 1414 if (drc) { 1415 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", 1416 spapr_drc_index(drc))); 1417 } 1418 1419 if (msi_present(dev)) { 1420 uint32_t max_msi = msi_nr_vectors_allocated(dev); 1421 if (max_msi) { 1422 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi)); 1423 } 1424 } 1425 if (msix_present(dev)) { 1426 uint32_t max_msix = dev->msix_entries_nr; 1427 if (max_msix) { 1428 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix)); 1429 } 1430 } 1431 1432 populate_resource_props(dev, &rp); 1433 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); 1434 1435 if (sphb->pcie_ecs && pci_is_express(dev)) { 1436 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1)); 1437 } 1438 1439 spapr_phb_nvgpu_populate_pcidev_dt(dev, fdt, offset, sphb); 1440 1441 if (!pc->is_bridge) { 1442 /* Properties only for non-bridges */ 1443 uint32_t min_grant = pci_default_read_config(dev, PCI_MIN_GNT, 1); 1444 uint32_t max_latency = pci_default_read_config(dev, PCI_MAX_LAT, 1); 1445 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", min_grant)); 1446 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", max_latency)); 1447 return offset; 1448 } else { 1449 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 1450 1451 return spapr_dt_pci_bus(sphb, sec_bus, fdt, offset); 1452 } 1453 } 1454 1455 /* Callback to be called during DRC release. */ 1456 void spapr_phb_remove_pci_device_cb(DeviceState *dev) 1457 { 1458 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 1459 1460 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 1461 object_unparent(OBJECT(dev)); 1462 } 1463 1464 int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 1465 void *fdt, int *fdt_start_offset, Error **errp) 1466 { 1467 HotplugHandler *plug_handler = qdev_get_hotplug_handler(drc->dev); 1468 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(plug_handler); 1469 PCIDevice *pdev = PCI_DEVICE(drc->dev); 1470 1471 *fdt_start_offset = spapr_dt_pci_device(sphb, pdev, fdt, 0); 1472 return 0; 1473 } 1474 1475 static void spapr_pci_bridge_plug(SpaprPhbState *phb, 1476 PCIBridge *bridge) 1477 { 1478 PCIBus *bus = pci_bridge_get_sec_bus(bridge); 1479 1480 add_drcs(phb, bus); 1481 } 1482 1483 /* Returns non-zero if the value of "chassis_nr" is already in use */ 1484 static int check_chassis_nr(Object *obj, void *opaque) 1485 { 1486 int new_chassis_nr = 1487 object_property_get_uint(opaque, "chassis_nr", &error_abort); 1488 int chassis_nr = 1489 object_property_get_uint(obj, "chassis_nr", NULL); 1490 1491 if (!object_dynamic_cast(obj, TYPE_PCI_BRIDGE)) { 1492 return 0; 1493 } 1494 1495 /* Skip unsupported bridge types */ 1496 if (!chassis_nr) { 1497 return 0; 1498 } 1499 1500 /* Skip self */ 1501 if (obj == opaque) { 1502 return 0; 1503 } 1504 1505 return chassis_nr == new_chassis_nr; 1506 } 1507 1508 static bool bridge_has_valid_chassis_nr(Object *bridge, Error **errp) 1509 { 1510 int chassis_nr = 1511 object_property_get_uint(bridge, "chassis_nr", NULL); 1512 1513 /* 1514 * slotid_cap_init() already ensures that "chassis_nr" isn't null for 1515 * standard PCI bridges, so this really tells if "chassis_nr" is present 1516 * or not. 1517 */ 1518 if (!chassis_nr) { 1519 error_setg(errp, "PCI Bridge lacks a \"chassis_nr\" property"); 1520 error_append_hint(errp, "Try -device pci-bridge instead.\n"); 1521 return false; 1522 } 1523 1524 /* We want unique values for "chassis_nr" */ 1525 if (object_child_foreach_recursive(object_get_root(), check_chassis_nr, 1526 bridge)) { 1527 error_setg(errp, "Bridge chassis %d already in use", chassis_nr); 1528 return false; 1529 } 1530 1531 return true; 1532 } 1533 1534 static void spapr_pci_plug(HotplugHandler *plug_handler, 1535 DeviceState *plugged_dev, Error **errp) 1536 { 1537 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1538 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1539 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1540 SpaprDrc *drc = drc_from_dev(phb, pdev); 1541 Error *local_err = NULL; 1542 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); 1543 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1544 1545 /* if DR is disabled we don't need to do anything in the case of 1546 * hotplug or coldplug callbacks 1547 */ 1548 if (!phb->dr_enabled) { 1549 /* if this is a hotplug operation initiated by the user 1550 * we need to let them know it's not enabled 1551 */ 1552 if (plugged_dev->hotplugged) { 1553 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1554 object_get_typename(OBJECT(phb))); 1555 } 1556 return; 1557 } 1558 1559 g_assert(drc); 1560 1561 if (pc->is_bridge) { 1562 if (!bridge_has_valid_chassis_nr(OBJECT(plugged_dev), errp)) { 1563 return; 1564 } 1565 spapr_pci_bridge_plug(phb, PCI_BRIDGE(plugged_dev)); 1566 } 1567 1568 /* Following the QEMU convention used for PCIe multifunction 1569 * hotplug, we do not allow functions to be hotplugged to a 1570 * slot that already has function 0 present 1571 */ 1572 if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] && 1573 PCI_FUNC(pdev->devfn) != 0) { 1574 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s," 1575 " additional functions can no longer be exposed to guest.", 1576 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name); 1577 return; 1578 } 1579 1580 spapr_drc_attach(drc, DEVICE(pdev), &local_err); 1581 if (local_err) { 1582 error_propagate(errp, local_err); 1583 return; 1584 } 1585 1586 /* If this is function 0, signal hotplug for all the device functions. 1587 * Otherwise defer sending the hotplug event. 1588 */ 1589 if (!spapr_drc_hotplugged(plugged_dev)) { 1590 spapr_drc_reset(drc); 1591 } else if (PCI_FUNC(pdev->devfn) == 0) { 1592 int i; 1593 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev)); 1594 1595 for (i = 0; i < 8; i++) { 1596 SpaprDrc *func_drc; 1597 SpaprDrcClass *func_drck; 1598 SpaprDREntitySense state; 1599 1600 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1601 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1602 state = func_drck->dr_entity_sense(func_drc); 1603 1604 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { 1605 spapr_hotplug_req_add_by_index(func_drc); 1606 } 1607 } 1608 } 1609 } 1610 1611 static void spapr_pci_bridge_unplug(SpaprPhbState *phb, 1612 PCIBridge *bridge) 1613 { 1614 PCIBus *bus = pci_bridge_get_sec_bus(bridge); 1615 1616 remove_drcs(phb, bus); 1617 } 1618 1619 static void spapr_pci_unplug(HotplugHandler *plug_handler, 1620 DeviceState *plugged_dev, Error **errp) 1621 { 1622 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1623 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1624 1625 /* some version guests do not wait for completion of a device 1626 * cleanup (generally done asynchronously by the kernel) before 1627 * signaling to QEMU that the device is safe, but instead sleep 1628 * for some 'safe' period of time. unfortunately on a busy host 1629 * this sleep isn't guaranteed to be long enough, resulting in 1630 * bad things like IRQ lines being left asserted during final 1631 * device removal. to deal with this we call reset just prior 1632 * to finalizing the device, which will put the device back into 1633 * an 'idle' state, as the device cleanup code expects. 1634 */ 1635 pci_device_reset(PCI_DEVICE(plugged_dev)); 1636 1637 if (pc->is_bridge) { 1638 spapr_pci_bridge_unplug(phb, PCI_BRIDGE(plugged_dev)); 1639 return; 1640 } 1641 1642 qdev_unrealize(plugged_dev); 1643 } 1644 1645 static void spapr_pci_unplug_request(HotplugHandler *plug_handler, 1646 DeviceState *plugged_dev, Error **errp) 1647 { 1648 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1649 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1650 SpaprDrc *drc = drc_from_dev(phb, pdev); 1651 1652 if (!phb->dr_enabled) { 1653 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1654 object_get_typename(OBJECT(phb))); 1655 return; 1656 } 1657 1658 g_assert(drc); 1659 g_assert(drc->dev == plugged_dev); 1660 1661 if (!spapr_drc_unplug_requested(drc)) { 1662 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1663 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1664 SpaprDrc *func_drc; 1665 SpaprDrcClass *func_drck; 1666 SpaprDREntitySense state; 1667 int i; 1668 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev)); 1669 1670 if (pc->is_bridge) { 1671 error_setg(errp, "PCI: Hot unplug of PCI bridges not supported"); 1672 return; 1673 } 1674 if (object_property_get_uint(OBJECT(pdev), "nvlink2-tgt", NULL)) { 1675 error_setg(errp, "PCI: Cannot unplug NVLink2 devices"); 1676 return; 1677 } 1678 1679 /* ensure any other present functions are pending unplug */ 1680 if (PCI_FUNC(pdev->devfn) == 0) { 1681 for (i = 1; i < 8; i++) { 1682 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1683 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1684 state = func_drck->dr_entity_sense(func_drc); 1685 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT 1686 && !spapr_drc_unplug_requested(func_drc)) { 1687 /* 1688 * Attempting to remove function 0 of a multifunction 1689 * device will will cascade into removing all child 1690 * functions, even if their unplug weren't requested 1691 * beforehand. 1692 */ 1693 spapr_drc_detach(func_drc); 1694 } 1695 } 1696 } 1697 1698 spapr_drc_detach(drc); 1699 1700 /* if this isn't func 0, defer unplug event. otherwise signal removal 1701 * for all present functions 1702 */ 1703 if (PCI_FUNC(pdev->devfn) == 0) { 1704 for (i = 7; i >= 0; i--) { 1705 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1706 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1707 state = func_drck->dr_entity_sense(func_drc); 1708 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { 1709 spapr_hotplug_req_remove_by_index(func_drc); 1710 } 1711 } 1712 } 1713 } 1714 } 1715 1716 static void spapr_phb_finalizefn(Object *obj) 1717 { 1718 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(obj); 1719 1720 g_free(sphb->dtbusname); 1721 sphb->dtbusname = NULL; 1722 } 1723 1724 static void spapr_phb_unrealize(DeviceState *dev) 1725 { 1726 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1727 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1728 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1729 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(phb); 1730 SpaprTceTable *tcet; 1731 int i; 1732 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 1733 1734 spapr_phb_nvgpu_free(sphb); 1735 1736 if (sphb->msi) { 1737 g_hash_table_unref(sphb->msi); 1738 sphb->msi = NULL; 1739 } 1740 1741 /* 1742 * Remove IO/MMIO subregions and aliases, rest should get cleaned 1743 * via PHB's unrealize->object_finalize 1744 */ 1745 for (i = windows_supported - 1; i >= 0; i--) { 1746 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); 1747 if (tcet) { 1748 memory_region_del_subregion(&sphb->iommu_root, 1749 spapr_tce_get_iommu(tcet)); 1750 } 1751 } 1752 1753 remove_drcs(sphb, phb->bus); 1754 1755 for (i = PCI_NUM_PINS - 1; i >= 0; i--) { 1756 if (sphb->lsi_table[i].irq) { 1757 spapr_irq_free(spapr, sphb->lsi_table[i].irq, 1); 1758 sphb->lsi_table[i].irq = 0; 1759 } 1760 } 1761 1762 QLIST_REMOVE(sphb, list); 1763 1764 memory_region_del_subregion(&sphb->iommu_root, &sphb->msiwindow); 1765 1766 /* 1767 * An attached PCI device may have memory listeners, eg. VFIO PCI. We have 1768 * unmapped all sections. Remove the listeners now, before destroying the 1769 * address space. 1770 */ 1771 address_space_remove_listeners(&sphb->iommu_as); 1772 address_space_destroy(&sphb->iommu_as); 1773 1774 qbus_set_hotplug_handler(BUS(phb->bus), NULL); 1775 pci_unregister_root_bus(phb->bus); 1776 1777 memory_region_del_subregion(get_system_memory(), &sphb->iowindow); 1778 if (sphb->mem64_win_pciaddr != (hwaddr)-1) { 1779 memory_region_del_subregion(get_system_memory(), &sphb->mem64window); 1780 } 1781 memory_region_del_subregion(get_system_memory(), &sphb->mem32window); 1782 } 1783 1784 static void spapr_phb_destroy_msi(gpointer opaque) 1785 { 1786 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1787 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1788 SpaprPciMsi *msi = opaque; 1789 1790 if (!smc->legacy_irq_allocation) { 1791 spapr_irq_msi_free(spapr, msi->first_irq, msi->num); 1792 } 1793 spapr_irq_free(spapr, msi->first_irq, msi->num); 1794 g_free(msi); 1795 } 1796 1797 static void spapr_phb_realize(DeviceState *dev, Error **errp) 1798 { 1799 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 1800 * tries to add a sPAPR PHB to a non-pseries machine. 1801 */ 1802 SpaprMachineState *spapr = 1803 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), 1804 TYPE_SPAPR_MACHINE); 1805 SpaprMachineClass *smc = spapr ? SPAPR_MACHINE_GET_CLASS(spapr) : NULL; 1806 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1807 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(s); 1808 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1809 MachineState *ms = MACHINE(spapr); 1810 char *namebuf; 1811 int i; 1812 PCIBus *bus; 1813 uint64_t msi_window_size = 4096; 1814 SpaprTceTable *tcet; 1815 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 1816 Error *local_err = NULL; 1817 1818 if (!spapr) { 1819 error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine"); 1820 return; 1821 } 1822 1823 assert(sphb->index != (uint32_t)-1); /* checked in spapr_phb_pre_plug() */ 1824 1825 if (sphb->mem64_win_size != 0) { 1826 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { 1827 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx 1828 " (max 2 GiB)", sphb->mem_win_size); 1829 return; 1830 } 1831 1832 /* 64-bit window defaults to identity mapping */ 1833 sphb->mem64_win_pciaddr = sphb->mem64_win_addr; 1834 } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { 1835 /* 1836 * For compatibility with old configuration, if no 64-bit MMIO 1837 * window is specified, but the ordinary (32-bit) memory 1838 * window is specified as > 2GiB, we treat it as a 2GiB 32-bit 1839 * window, with a 64-bit MMIO window following on immediately 1840 * afterwards 1841 */ 1842 sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE; 1843 sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE; 1844 sphb->mem64_win_pciaddr = 1845 SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE; 1846 sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE; 1847 } 1848 1849 if (spapr_pci_find_phb(spapr, sphb->buid)) { 1850 SpaprPhbState *s; 1851 1852 error_setg(errp, "PCI host bridges must have unique indexes"); 1853 error_append_hint(errp, "The following indexes are already in use:"); 1854 QLIST_FOREACH(s, &spapr->phbs, list) { 1855 error_append_hint(errp, " %d", s->index); 1856 } 1857 error_append_hint(errp, "\nTry another value for the index property\n"); 1858 return; 1859 } 1860 1861 if (sphb->numa_node != -1 && 1862 (sphb->numa_node >= MAX_NODES || 1863 !ms->numa_state->nodes[sphb->numa_node].present)) { 1864 error_setg(errp, "Invalid NUMA node ID for PCI host bridge"); 1865 return; 1866 } 1867 1868 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); 1869 1870 /* Initialize memory regions */ 1871 namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname); 1872 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); 1873 g_free(namebuf); 1874 1875 namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname); 1876 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb), 1877 namebuf, &sphb->memspace, 1878 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); 1879 g_free(namebuf); 1880 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, 1881 &sphb->mem32window); 1882 1883 if (sphb->mem64_win_size != 0) { 1884 namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname); 1885 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb), 1886 namebuf, &sphb->memspace, 1887 sphb->mem64_win_pciaddr, sphb->mem64_win_size); 1888 g_free(namebuf); 1889 1890 memory_region_add_subregion(get_system_memory(), 1891 sphb->mem64_win_addr, 1892 &sphb->mem64window); 1893 } 1894 1895 /* Initialize IO regions */ 1896 namebuf = g_strdup_printf("%s.io", sphb->dtbusname); 1897 memory_region_init(&sphb->iospace, OBJECT(sphb), 1898 namebuf, SPAPR_PCI_IO_WIN_SIZE); 1899 g_free(namebuf); 1900 1901 namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname); 1902 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, 1903 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); 1904 g_free(namebuf); 1905 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, 1906 &sphb->iowindow); 1907 1908 bus = pci_register_root_bus(dev, NULL, 1909 pci_spapr_set_irq, pci_swizzle_map_irq_fn, sphb, 1910 &sphb->memspace, &sphb->iospace, 1911 PCI_DEVFN(0, 0), PCI_NUM_PINS, 1912 TYPE_PCI_BUS); 1913 1914 /* 1915 * Despite resembling a vanilla PCI bus in most ways, the PAPR 1916 * para-virtualized PCI bus *does* permit PCI-E extended config 1917 * space access 1918 */ 1919 if (sphb->pcie_ecs) { 1920 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 1921 } 1922 phb->bus = bus; 1923 qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb)); 1924 1925 /* 1926 * Initialize PHB address space. 1927 * By default there will be at least one subregion for default 1928 * 32bit DMA window. 1929 * Later the guest might want to create another DMA window 1930 * which will become another memory subregion. 1931 */ 1932 namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname); 1933 memory_region_init(&sphb->iommu_root, OBJECT(sphb), 1934 namebuf, UINT64_MAX); 1935 g_free(namebuf); 1936 address_space_init(&sphb->iommu_as, &sphb->iommu_root, 1937 sphb->dtbusname); 1938 1939 /* 1940 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, 1941 * we need to allocate some memory to catch those writes coming 1942 * from msi_notify()/msix_notify(). 1943 * As MSIMessage:addr is going to be the same and MSIMessage:data 1944 * is going to be a VIRQ number, 4 bytes of the MSI MR will only 1945 * be used. 1946 * 1947 * For KVM we want to ensure that this memory is a full page so that 1948 * our memory slot is of page size granularity. 1949 */ 1950 if (kvm_enabled()) { 1951 msi_window_size = qemu_real_host_page_size; 1952 } 1953 1954 memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr, 1955 "msi", msi_window_size); 1956 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, 1957 &sphb->msiwindow); 1958 1959 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); 1960 1961 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); 1962 1963 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); 1964 1965 /* Initialize the LSI table */ 1966 for (i = 0; i < PCI_NUM_PINS; i++) { 1967 uint32_t irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i; 1968 1969 if (smc->legacy_irq_allocation) { 1970 irq = spapr_irq_findone(spapr, &local_err); 1971 if (local_err) { 1972 error_propagate_prepend(errp, local_err, 1973 "can't allocate LSIs: "); 1974 /* 1975 * Older machines will never support PHB hotplug, ie, this is an 1976 * init only path and QEMU will terminate. No need to rollback. 1977 */ 1978 return; 1979 } 1980 } 1981 1982 spapr_irq_claim(spapr, irq, true, &local_err); 1983 if (local_err) { 1984 error_propagate_prepend(errp, local_err, "can't allocate LSIs: "); 1985 goto unrealize; 1986 } 1987 1988 sphb->lsi_table[i].irq = irq; 1989 } 1990 1991 /* allocate connectors for child PCI devices */ 1992 add_drcs(sphb, phb->bus); 1993 1994 /* DMA setup */ 1995 for (i = 0; i < windows_supported; ++i) { 1996 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]); 1997 if (!tcet) { 1998 error_setg(errp, "Creating window#%d failed for %s", 1999 i, sphb->dtbusname); 2000 goto unrealize; 2001 } 2002 memory_region_add_subregion(&sphb->iommu_root, 0, 2003 spapr_tce_get_iommu(tcet)); 2004 } 2005 2006 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, 2007 spapr_phb_destroy_msi); 2008 return; 2009 2010 unrealize: 2011 spapr_phb_unrealize(dev); 2012 } 2013 2014 static int spapr_phb_children_reset(Object *child, void *opaque) 2015 { 2016 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); 2017 2018 if (dev) { 2019 device_legacy_reset(dev); 2020 } 2021 2022 return 0; 2023 } 2024 2025 void spapr_phb_dma_reset(SpaprPhbState *sphb) 2026 { 2027 int i; 2028 SpaprTceTable *tcet; 2029 2030 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) { 2031 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); 2032 2033 if (tcet && tcet->nb_table) { 2034 spapr_tce_table_disable(tcet); 2035 } 2036 } 2037 2038 /* Register default 32bit DMA window */ 2039 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]); 2040 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr, 2041 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT); 2042 } 2043 2044 static void spapr_phb_reset(DeviceState *qdev) 2045 { 2046 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev); 2047 Error *err = NULL; 2048 2049 spapr_phb_dma_reset(sphb); 2050 spapr_phb_nvgpu_free(sphb); 2051 spapr_phb_nvgpu_setup(sphb, &err); 2052 if (err) { 2053 error_report_err(err); 2054 } 2055 2056 /* Reset the IOMMU state */ 2057 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); 2058 2059 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) { 2060 spapr_phb_vfio_reset(qdev); 2061 } 2062 2063 g_hash_table_remove_all(sphb->msi); 2064 } 2065 2066 static Property spapr_phb_properties[] = { 2067 DEFINE_PROP_UINT32("index", SpaprPhbState, index, -1), 2068 DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState, mem_win_size, 2069 SPAPR_PCI_MEM32_WIN_SIZE), 2070 DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState, mem64_win_size, 2071 SPAPR_PCI_MEM64_WIN_SIZE), 2072 DEFINE_PROP_UINT64("io_win_size", SpaprPhbState, io_win_size, 2073 SPAPR_PCI_IO_WIN_SIZE), 2074 DEFINE_PROP_BOOL("dynamic-reconfiguration", SpaprPhbState, dr_enabled, 2075 true), 2076 /* Default DMA window is 0..1GB */ 2077 DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState, dma_win_addr, 0), 2078 DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState, dma_win_size, 0x40000000), 2079 DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState, dma64_win_addr, 2080 0x800000000000000ULL), 2081 DEFINE_PROP_BOOL("ddw", SpaprPhbState, ddw_enabled, true), 2082 DEFINE_PROP_UINT64("pgsz", SpaprPhbState, page_size_mask, 2083 (1ULL << 12) | (1ULL << 16) 2084 | (1ULL << 21) | (1ULL << 24)), 2085 DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1), 2086 DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState, 2087 pre_2_8_migration, false), 2088 DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState, 2089 pcie_ecs, true), 2090 DEFINE_PROP_UINT64("gpa", SpaprPhbState, nv2_gpa_win_addr, 0), 2091 DEFINE_PROP_UINT64("atsd", SpaprPhbState, nv2_atsd_win_addr, 0), 2092 DEFINE_PROP_BOOL("pre-5.1-associativity", SpaprPhbState, 2093 pre_5_1_assoc, false), 2094 DEFINE_PROP_END_OF_LIST(), 2095 }; 2096 2097 static const VMStateDescription vmstate_spapr_pci_lsi = { 2098 .name = "spapr_pci/lsi", 2099 .version_id = 1, 2100 .minimum_version_id = 1, 2101 .fields = (VMStateField[]) { 2102 VMSTATE_UINT32_EQUAL(irq, SpaprPciLsi, NULL), 2103 2104 VMSTATE_END_OF_LIST() 2105 }, 2106 }; 2107 2108 static const VMStateDescription vmstate_spapr_pci_msi = { 2109 .name = "spapr_pci/msi", 2110 .version_id = 1, 2111 .minimum_version_id = 1, 2112 .fields = (VMStateField []) { 2113 VMSTATE_UINT32(key, SpaprPciMsiMig), 2114 VMSTATE_UINT32(value.first_irq, SpaprPciMsiMig), 2115 VMSTATE_UINT32(value.num, SpaprPciMsiMig), 2116 VMSTATE_END_OF_LIST() 2117 }, 2118 }; 2119 2120 static int spapr_pci_pre_save(void *opaque) 2121 { 2122 SpaprPhbState *sphb = opaque; 2123 GHashTableIter iter; 2124 gpointer key, value; 2125 int i; 2126 2127 if (sphb->pre_2_8_migration) { 2128 sphb->mig_liobn = sphb->dma_liobn[0]; 2129 sphb->mig_mem_win_addr = sphb->mem_win_addr; 2130 sphb->mig_mem_win_size = sphb->mem_win_size; 2131 sphb->mig_io_win_addr = sphb->io_win_addr; 2132 sphb->mig_io_win_size = sphb->io_win_size; 2133 2134 if ((sphb->mem64_win_size != 0) 2135 && (sphb->mem64_win_addr 2136 == (sphb->mem_win_addr + sphb->mem_win_size))) { 2137 sphb->mig_mem_win_size += sphb->mem64_win_size; 2138 } 2139 } 2140 2141 g_free(sphb->msi_devs); 2142 sphb->msi_devs = NULL; 2143 sphb->msi_devs_num = g_hash_table_size(sphb->msi); 2144 if (!sphb->msi_devs_num) { 2145 return 0; 2146 } 2147 sphb->msi_devs = g_new(SpaprPciMsiMig, sphb->msi_devs_num); 2148 2149 g_hash_table_iter_init(&iter, sphb->msi); 2150 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { 2151 sphb->msi_devs[i].key = *(uint32_t *) key; 2152 sphb->msi_devs[i].value = *(SpaprPciMsi *) value; 2153 } 2154 2155 return 0; 2156 } 2157 2158 static int spapr_pci_post_load(void *opaque, int version_id) 2159 { 2160 SpaprPhbState *sphb = opaque; 2161 gpointer key, value; 2162 int i; 2163 2164 for (i = 0; i < sphb->msi_devs_num; ++i) { 2165 key = g_memdup(&sphb->msi_devs[i].key, 2166 sizeof(sphb->msi_devs[i].key)); 2167 value = g_memdup(&sphb->msi_devs[i].value, 2168 sizeof(sphb->msi_devs[i].value)); 2169 g_hash_table_insert(sphb->msi, key, value); 2170 } 2171 g_free(sphb->msi_devs); 2172 sphb->msi_devs = NULL; 2173 sphb->msi_devs_num = 0; 2174 2175 return 0; 2176 } 2177 2178 static bool pre_2_8_migration(void *opaque, int version_id) 2179 { 2180 SpaprPhbState *sphb = opaque; 2181 2182 return sphb->pre_2_8_migration; 2183 } 2184 2185 static const VMStateDescription vmstate_spapr_pci = { 2186 .name = "spapr_pci", 2187 .version_id = 2, 2188 .minimum_version_id = 2, 2189 .pre_save = spapr_pci_pre_save, 2190 .post_load = spapr_pci_post_load, 2191 .fields = (VMStateField[]) { 2192 VMSTATE_UINT64_EQUAL(buid, SpaprPhbState, NULL), 2193 VMSTATE_UINT32_TEST(mig_liobn, SpaprPhbState, pre_2_8_migration), 2194 VMSTATE_UINT64_TEST(mig_mem_win_addr, SpaprPhbState, pre_2_8_migration), 2195 VMSTATE_UINT64_TEST(mig_mem_win_size, SpaprPhbState, pre_2_8_migration), 2196 VMSTATE_UINT64_TEST(mig_io_win_addr, SpaprPhbState, pre_2_8_migration), 2197 VMSTATE_UINT64_TEST(mig_io_win_size, SpaprPhbState, pre_2_8_migration), 2198 VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0, 2199 vmstate_spapr_pci_lsi, SpaprPciLsi), 2200 VMSTATE_INT32(msi_devs_num, SpaprPhbState), 2201 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, SpaprPhbState, msi_devs_num, 0, 2202 vmstate_spapr_pci_msi, SpaprPciMsiMig), 2203 VMSTATE_END_OF_LIST() 2204 }, 2205 }; 2206 2207 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, 2208 PCIBus *rootbus) 2209 { 2210 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); 2211 2212 return sphb->dtbusname; 2213 } 2214 2215 static void spapr_phb_class_init(ObjectClass *klass, void *data) 2216 { 2217 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 2218 DeviceClass *dc = DEVICE_CLASS(klass); 2219 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); 2220 2221 hc->root_bus_path = spapr_phb_root_bus_path; 2222 dc->realize = spapr_phb_realize; 2223 dc->unrealize = spapr_phb_unrealize; 2224 device_class_set_props(dc, spapr_phb_properties); 2225 dc->reset = spapr_phb_reset; 2226 dc->vmsd = &vmstate_spapr_pci; 2227 /* Supported by TYPE_SPAPR_MACHINE */ 2228 dc->user_creatable = true; 2229 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 2230 hp->plug = spapr_pci_plug; 2231 hp->unplug = spapr_pci_unplug; 2232 hp->unplug_request = spapr_pci_unplug_request; 2233 } 2234 2235 static const TypeInfo spapr_phb_info = { 2236 .name = TYPE_SPAPR_PCI_HOST_BRIDGE, 2237 .parent = TYPE_PCI_HOST_BRIDGE, 2238 .instance_size = sizeof(SpaprPhbState), 2239 .instance_finalize = spapr_phb_finalizefn, 2240 .class_init = spapr_phb_class_init, 2241 .interfaces = (InterfaceInfo[]) { 2242 { TYPE_HOTPLUG_HANDLER }, 2243 { } 2244 } 2245 }; 2246 2247 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, 2248 void *opaque) 2249 { 2250 unsigned int *bus_no = opaque; 2251 PCIBus *sec_bus = NULL; 2252 2253 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 2254 PCI_HEADER_TYPE_BRIDGE)) { 2255 return; 2256 } 2257 2258 (*bus_no)++; 2259 pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1); 2260 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); 2261 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 2262 2263 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 2264 if (!sec_bus) { 2265 return; 2266 } 2267 2268 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 2269 spapr_phb_pci_enumerate_bridge, bus_no); 2270 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 2271 } 2272 2273 static void spapr_phb_pci_enumerate(SpaprPhbState *phb) 2274 { 2275 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 2276 unsigned int bus_no = 0; 2277 2278 pci_for_each_device(bus, pci_bus_num(bus), 2279 spapr_phb_pci_enumerate_bridge, 2280 &bus_no); 2281 2282 } 2283 2284 int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb, 2285 uint32_t intc_phandle, void *fdt, int *node_offset) 2286 { 2287 int bus_off, i, j, ret; 2288 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; 2289 struct { 2290 uint32_t hi; 2291 uint64_t child; 2292 uint64_t parent; 2293 uint64_t size; 2294 } QEMU_PACKED ranges[] = { 2295 { 2296 cpu_to_be32(b_ss(1)), cpu_to_be64(0), 2297 cpu_to_be64(phb->io_win_addr), 2298 cpu_to_be64(memory_region_size(&phb->iospace)), 2299 }, 2300 { 2301 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), 2302 cpu_to_be64(phb->mem_win_addr), 2303 cpu_to_be64(phb->mem_win_size), 2304 }, 2305 { 2306 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr), 2307 cpu_to_be64(phb->mem64_win_addr), 2308 cpu_to_be64(phb->mem64_win_size), 2309 }, 2310 }; 2311 const unsigned sizeof_ranges = 2312 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]); 2313 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; 2314 uint32_t interrupt_map_mask[] = { 2315 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; 2316 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; 2317 uint32_t ddw_applicable[] = { 2318 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW), 2319 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW), 2320 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW) 2321 }; 2322 uint32_t ddw_extensions[] = { 2323 cpu_to_be32(1), 2324 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW) 2325 }; 2326 uint32_t associativity[] = {cpu_to_be32(0x4), 2327 cpu_to_be32(0x0), 2328 cpu_to_be32(0x0), 2329 cpu_to_be32(0x0), 2330 cpu_to_be32(phb->numa_node)}; 2331 SpaprTceTable *tcet; 2332 SpaprDrc *drc; 2333 Error *err = NULL; 2334 2335 /* Start populating the FDT */ 2336 _FDT(bus_off = fdt_add_subnode(fdt, 0, phb->dtbusname)); 2337 if (node_offset) { 2338 *node_offset = bus_off; 2339 } 2340 2341 /* Write PHB properties */ 2342 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); 2343 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); 2344 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); 2345 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); 2346 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); 2347 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); 2348 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); 2349 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); 2350 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", 2351 spapr_irq_nr_msis(spapr))); 2352 2353 /* Dynamic DMA window */ 2354 if (phb->ddw_enabled) { 2355 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable, 2356 sizeof(ddw_applicable))); 2357 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions", 2358 &ddw_extensions, sizeof(ddw_extensions))); 2359 } 2360 2361 /* Advertise NUMA via ibm,associativity */ 2362 if (phb->numa_node != -1) { 2363 _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity, 2364 sizeof(associativity))); 2365 } 2366 2367 /* Build the interrupt-map, this must matches what is done 2368 * in pci_swizzle_map_irq_fn 2369 */ 2370 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", 2371 &interrupt_map_mask, sizeof(interrupt_map_mask))); 2372 for (i = 0; i < PCI_SLOT_MAX; i++) { 2373 for (j = 0; j < PCI_NUM_PINS; j++) { 2374 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; 2375 int lsi_num = pci_swizzle(i, j); 2376 2377 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); 2378 irqmap[1] = 0; 2379 irqmap[2] = 0; 2380 irqmap[3] = cpu_to_be32(j+1); 2381 irqmap[4] = cpu_to_be32(intc_phandle); 2382 spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true); 2383 } 2384 } 2385 /* Write interrupt map */ 2386 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, 2387 sizeof(interrupt_map))); 2388 2389 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]); 2390 if (!tcet) { 2391 return -1; 2392 } 2393 spapr_dma_dt(fdt, bus_off, "ibm,dma-window", 2394 tcet->liobn, tcet->bus_offset, 2395 tcet->nb_table << tcet->page_shift); 2396 2397 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, phb->index); 2398 if (drc) { 2399 uint32_t drc_index = cpu_to_be32(spapr_drc_index(drc)); 2400 2401 _FDT(fdt_setprop(fdt, bus_off, "ibm,my-drc-index", &drc_index, 2402 sizeof(drc_index))); 2403 } 2404 2405 /* Walk the bridges and program the bus numbers*/ 2406 spapr_phb_pci_enumerate(phb); 2407 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); 2408 2409 /* Walk the bridge and subordinate buses */ 2410 ret = spapr_dt_pci_bus(phb, PCI_HOST_BRIDGE(phb)->bus, fdt, bus_off); 2411 if (ret < 0) { 2412 return ret; 2413 } 2414 2415 spapr_phb_nvgpu_populate_dt(phb, fdt, bus_off, &err); 2416 if (err) { 2417 error_report_err(err); 2418 } 2419 spapr_phb_nvgpu_ram_populate_dt(phb, fdt); 2420 2421 return 0; 2422 } 2423 2424 void spapr_pci_rtas_init(void) 2425 { 2426 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", 2427 rtas_read_pci_config); 2428 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", 2429 rtas_write_pci_config); 2430 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", 2431 rtas_ibm_read_pci_config); 2432 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", 2433 rtas_ibm_write_pci_config); 2434 if (msi_nonbroken) { 2435 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, 2436 "ibm,query-interrupt-source-number", 2437 rtas_ibm_query_interrupt_source_number); 2438 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", 2439 rtas_ibm_change_msi); 2440 } 2441 2442 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, 2443 "ibm,set-eeh-option", 2444 rtas_ibm_set_eeh_option); 2445 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, 2446 "ibm,get-config-addr-info2", 2447 rtas_ibm_get_config_addr_info2); 2448 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, 2449 "ibm,read-slot-reset-state2", 2450 rtas_ibm_read_slot_reset_state2); 2451 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, 2452 "ibm,set-slot-reset", 2453 rtas_ibm_set_slot_reset); 2454 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, 2455 "ibm,configure-pe", 2456 rtas_ibm_configure_pe); 2457 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, 2458 "ibm,slot-error-detail", 2459 rtas_ibm_slot_error_detail); 2460 } 2461 2462 static void spapr_pci_register_types(void) 2463 { 2464 type_register_static(&spapr_phb_info); 2465 } 2466 2467 type_init(spapr_pci_register_types) 2468 2469 static int spapr_switch_one_vga(DeviceState *dev, void *opaque) 2470 { 2471 bool be = *(bool *)opaque; 2472 2473 if (object_dynamic_cast(OBJECT(dev), "VGA") 2474 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { 2475 object_property_set_bool(OBJECT(dev), "big-endian-framebuffer", be, 2476 &error_abort); 2477 } 2478 return 0; 2479 } 2480 2481 void spapr_pci_switch_vga(bool big_endian) 2482 { 2483 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 2484 SpaprPhbState *sphb; 2485 2486 /* 2487 * For backward compatibility with existing guests, we switch 2488 * the endianness of the VGA controller when changing the guest 2489 * interrupt mode 2490 */ 2491 QLIST_FOREACH(sphb, &spapr->phbs, list) { 2492 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; 2493 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, 2494 &big_endian); 2495 } 2496 } 2497