1 /* 2 * QEMU sPAPR PCI host originated from Uninorth PCI host 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. 5 * Copyright (C) 2011 David Gibson, IBM Corporation. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "hw/irq.h" 29 #include "hw/sysbus.h" 30 #include "migration/vmstate.h" 31 #include "hw/pci/pci.h" 32 #include "hw/pci/msi.h" 33 #include "hw/pci/msix.h" 34 #include "hw/pci/pci_host.h" 35 #include "hw/ppc/spapr.h" 36 #include "hw/pci-host/spapr.h" 37 #include "exec/ram_addr.h" 38 #include <libfdt.h> 39 #include "trace.h" 40 #include "qemu/error-report.h" 41 #include "qemu/module.h" 42 #include "qapi/qmp/qerror.h" 43 #include "hw/ppc/fdt.h" 44 #include "hw/pci/pci_bridge.h" 45 #include "hw/pci/pci_bus.h" 46 #include "hw/pci/pci_ids.h" 47 #include "hw/ppc/spapr_drc.h" 48 #include "hw/qdev-properties.h" 49 #include "sysemu/device_tree.h" 50 #include "sysemu/kvm.h" 51 #include "sysemu/hostmem.h" 52 #include "sysemu/numa.h" 53 #include "hw/ppc/spapr_numa.h" 54 #include "qemu/log.h" 55 56 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ 57 #define RTAS_QUERY_FN 0 58 #define RTAS_CHANGE_FN 1 59 #define RTAS_RESET_FN 2 60 #define RTAS_CHANGE_MSI_FN 3 61 #define RTAS_CHANGE_MSIX_FN 4 62 63 /* Interrupt types to return on RTAS_CHANGE_* */ 64 #define RTAS_TYPE_MSI 1 65 #define RTAS_TYPE_MSIX 2 66 67 SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid) 68 { 69 SpaprPhbState *sphb; 70 71 QLIST_FOREACH(sphb, &spapr->phbs, list) { 72 if (sphb->buid != buid) { 73 continue; 74 } 75 return sphb; 76 } 77 78 return NULL; 79 } 80 81 PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid, 82 uint32_t config_addr) 83 { 84 SpaprPhbState *sphb = spapr_pci_find_phb(spapr, buid); 85 PCIHostState *phb = PCI_HOST_BRIDGE(sphb); 86 int bus_num = (config_addr >> 16) & 0xFF; 87 int devfn = (config_addr >> 8) & 0xFF; 88 89 if (!phb) { 90 return NULL; 91 } 92 93 return pci_find_device(phb->bus, bus_num, devfn); 94 } 95 96 static uint32_t rtas_pci_cfgaddr(uint32_t arg) 97 { 98 /* This handles the encoding of extended config space addresses */ 99 return ((arg >> 20) & 0xf00) | (arg & 0xff); 100 } 101 102 static void finish_read_pci_config(SpaprMachineState *spapr, uint64_t buid, 103 uint32_t addr, uint32_t size, 104 target_ulong rets) 105 { 106 PCIDevice *pci_dev; 107 uint32_t val; 108 109 if ((size != 1) && (size != 2) && (size != 4)) { 110 /* access must be 1, 2 or 4 bytes */ 111 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 112 return; 113 } 114 115 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 116 addr = rtas_pci_cfgaddr(addr); 117 118 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 119 /* Access must be to a valid device, within bounds and 120 * naturally aligned */ 121 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 122 return; 123 } 124 125 val = pci_host_config_read_common(pci_dev, addr, 126 pci_config_size(pci_dev), size); 127 128 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 129 rtas_st(rets, 1, val); 130 } 131 132 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 133 uint32_t token, uint32_t nargs, 134 target_ulong args, 135 uint32_t nret, target_ulong rets) 136 { 137 uint64_t buid; 138 uint32_t size, addr; 139 140 if ((nargs != 4) || (nret != 2)) { 141 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 142 return; 143 } 144 145 buid = rtas_ldq(args, 1); 146 size = rtas_ld(args, 3); 147 addr = rtas_ld(args, 0); 148 149 finish_read_pci_config(spapr, buid, addr, size, rets); 150 } 151 152 static void rtas_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 153 uint32_t token, uint32_t nargs, 154 target_ulong args, 155 uint32_t nret, target_ulong rets) 156 { 157 uint32_t size, addr; 158 159 if ((nargs != 2) || (nret != 2)) { 160 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 161 return; 162 } 163 164 size = rtas_ld(args, 1); 165 addr = rtas_ld(args, 0); 166 167 finish_read_pci_config(spapr, 0, addr, size, rets); 168 } 169 170 static void finish_write_pci_config(SpaprMachineState *spapr, uint64_t buid, 171 uint32_t addr, uint32_t size, 172 uint32_t val, target_ulong rets) 173 { 174 PCIDevice *pci_dev; 175 176 if ((size != 1) && (size != 2) && (size != 4)) { 177 /* access must be 1, 2 or 4 bytes */ 178 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 179 return; 180 } 181 182 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 183 addr = rtas_pci_cfgaddr(addr); 184 185 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 186 /* Access must be to a valid device, within bounds and 187 * naturally aligned */ 188 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 189 return; 190 } 191 192 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), 193 val, size); 194 195 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 196 } 197 198 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 199 uint32_t token, uint32_t nargs, 200 target_ulong args, 201 uint32_t nret, target_ulong rets) 202 { 203 uint64_t buid; 204 uint32_t val, size, addr; 205 206 if ((nargs != 5) || (nret != 1)) { 207 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 208 return; 209 } 210 211 buid = rtas_ldq(args, 1); 212 val = rtas_ld(args, 4); 213 size = rtas_ld(args, 3); 214 addr = rtas_ld(args, 0); 215 216 finish_write_pci_config(spapr, buid, addr, size, val, rets); 217 } 218 219 static void rtas_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 220 uint32_t token, uint32_t nargs, 221 target_ulong args, 222 uint32_t nret, target_ulong rets) 223 { 224 uint32_t val, size, addr; 225 226 if ((nargs != 3) || (nret != 1)) { 227 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 228 return; 229 } 230 231 232 val = rtas_ld(args, 2); 233 size = rtas_ld(args, 1); 234 addr = rtas_ld(args, 0); 235 236 finish_write_pci_config(spapr, 0, addr, size, val, rets); 237 } 238 239 /* 240 * Set MSI/MSIX message data. 241 * This is required for msi_notify()/msix_notify() which 242 * will write at the addresses via spapr_msi_write(). 243 * 244 * If hwaddr == 0, all entries will have .data == first_irq i.e. 245 * table will be reset. 246 */ 247 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, 248 unsigned first_irq, unsigned req_num) 249 { 250 unsigned i; 251 MSIMessage msg = { .address = addr, .data = first_irq }; 252 253 if (!msix) { 254 msi_set_message(pdev, msg); 255 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); 256 return; 257 } 258 259 for (i = 0; i < req_num; ++i) { 260 msix_set_message(pdev, i, msg); 261 trace_spapr_pci_msi_setup(pdev->name, i, msg.address); 262 if (addr) { 263 ++msg.data; 264 } 265 } 266 } 267 268 static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr, 269 uint32_t token, uint32_t nargs, 270 target_ulong args, uint32_t nret, 271 target_ulong rets) 272 { 273 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 274 uint32_t config_addr = rtas_ld(args, 0); 275 uint64_t buid = rtas_ldq(args, 1); 276 unsigned int func = rtas_ld(args, 3); 277 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ 278 unsigned int seq_num = rtas_ld(args, 5); 279 unsigned int ret_intr_type; 280 unsigned int irq, max_irqs = 0; 281 SpaprPhbState *phb = NULL; 282 PCIDevice *pdev = NULL; 283 SpaprPciMsi *msi; 284 int *config_addr_key; 285 Error *err = NULL; 286 int i; 287 288 /* Fins SpaprPhbState */ 289 phb = spapr_pci_find_phb(spapr, buid); 290 if (phb) { 291 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 292 } 293 if (!phb || !pdev) { 294 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 295 return; 296 } 297 298 switch (func) { 299 case RTAS_CHANGE_FN: 300 if (msi_present(pdev)) { 301 ret_intr_type = RTAS_TYPE_MSI; 302 } else if (msix_present(pdev)) { 303 ret_intr_type = RTAS_TYPE_MSIX; 304 } else { 305 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 306 return; 307 } 308 break; 309 case RTAS_CHANGE_MSI_FN: 310 if (msi_present(pdev)) { 311 ret_intr_type = RTAS_TYPE_MSI; 312 } else { 313 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 314 return; 315 } 316 break; 317 case RTAS_CHANGE_MSIX_FN: 318 if (msix_present(pdev)) { 319 ret_intr_type = RTAS_TYPE_MSIX; 320 } else { 321 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 322 return; 323 } 324 break; 325 default: 326 error_report("rtas_ibm_change_msi(%u) is not implemented", func); 327 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 328 return; 329 } 330 331 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr); 332 333 /* Releasing MSIs */ 334 if (!req_num) { 335 if (!msi) { 336 trace_spapr_pci_msi("Releasing wrong config", config_addr); 337 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 338 return; 339 } 340 341 if (msi_present(pdev)) { 342 spapr_msi_setmsg(pdev, 0, false, 0, 0); 343 } 344 if (msix_present(pdev)) { 345 spapr_msi_setmsg(pdev, 0, true, 0, 0); 346 } 347 g_hash_table_remove(phb->msi, &config_addr); 348 349 trace_spapr_pci_msi("Released MSIs", config_addr); 350 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 351 rtas_st(rets, 1, 0); 352 return; 353 } 354 355 /* Enabling MSI */ 356 357 /* Check if the device supports as many IRQs as requested */ 358 if (ret_intr_type == RTAS_TYPE_MSI) { 359 max_irqs = msi_nr_vectors_allocated(pdev); 360 } else if (ret_intr_type == RTAS_TYPE_MSIX) { 361 max_irqs = pdev->msix_entries_nr; 362 } 363 if (!max_irqs) { 364 error_report("Requested interrupt type %d is not enabled for device %x", 365 ret_intr_type, config_addr); 366 rtas_st(rets, 0, -1); /* Hardware error */ 367 return; 368 } 369 /* Correct the number if the guest asked for too many */ 370 if (req_num > max_irqs) { 371 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); 372 req_num = max_irqs; 373 irq = 0; /* to avoid misleading trace */ 374 goto out; 375 } 376 377 /* Allocate MSIs */ 378 if (smc->legacy_irq_allocation) { 379 irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI, 380 &err); 381 } else { 382 irq = spapr_irq_msi_alloc(spapr, req_num, 383 ret_intr_type == RTAS_TYPE_MSI, &err); 384 } 385 if (err) { 386 error_reportf_err(err, "Can't allocate MSIs for device %x: ", 387 config_addr); 388 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 389 return; 390 } 391 392 for (i = 0; i < req_num; i++) { 393 spapr_irq_claim(spapr, irq + i, false, &err); 394 if (err) { 395 if (i) { 396 spapr_irq_free(spapr, irq, i); 397 } 398 if (!smc->legacy_irq_allocation) { 399 spapr_irq_msi_free(spapr, irq, req_num); 400 } 401 error_reportf_err(err, "Can't allocate MSIs for device %x: ", 402 config_addr); 403 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 404 return; 405 } 406 } 407 408 /* Release previous MSIs */ 409 if (msi) { 410 g_hash_table_remove(phb->msi, &config_addr); 411 } 412 413 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ 414 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, 415 irq, req_num); 416 417 /* Add MSI device to cache */ 418 msi = g_new(SpaprPciMsi, 1); 419 msi->first_irq = irq; 420 msi->num = req_num; 421 config_addr_key = g_new(int, 1); 422 *config_addr_key = config_addr; 423 g_hash_table_insert(phb->msi, config_addr_key, msi); 424 425 out: 426 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 427 rtas_st(rets, 1, req_num); 428 rtas_st(rets, 2, ++seq_num); 429 if (nret > 3) { 430 rtas_st(rets, 3, ret_intr_type); 431 } 432 433 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); 434 } 435 436 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, 437 SpaprMachineState *spapr, 438 uint32_t token, 439 uint32_t nargs, 440 target_ulong args, 441 uint32_t nret, 442 target_ulong rets) 443 { 444 uint32_t config_addr = rtas_ld(args, 0); 445 uint64_t buid = rtas_ldq(args, 1); 446 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); 447 SpaprPhbState *phb = NULL; 448 PCIDevice *pdev = NULL; 449 SpaprPciMsi *msi; 450 451 /* Find SpaprPhbState */ 452 phb = spapr_pci_find_phb(spapr, buid); 453 if (phb) { 454 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 455 } 456 if (!phb || !pdev) { 457 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 458 return; 459 } 460 461 /* Find device descriptor and start IRQ */ 462 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr); 463 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { 464 trace_spapr_pci_msi("Failed to return vector", config_addr); 465 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 466 return; 467 } 468 intr_src_num = msi->first_irq + ioa_intr_num; 469 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, 470 intr_src_num); 471 472 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 473 rtas_st(rets, 1, intr_src_num); 474 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ 475 } 476 477 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, 478 SpaprMachineState *spapr, 479 uint32_t token, uint32_t nargs, 480 target_ulong args, uint32_t nret, 481 target_ulong rets) 482 { 483 SpaprPhbState *sphb; 484 uint32_t addr, option; 485 uint64_t buid; 486 int ret; 487 488 if ((nargs != 4) || (nret != 1)) { 489 goto param_error_exit; 490 } 491 492 buid = rtas_ldq(args, 1); 493 addr = rtas_ld(args, 0); 494 option = rtas_ld(args, 3); 495 496 sphb = spapr_pci_find_phb(spapr, buid); 497 if (!sphb) { 498 goto param_error_exit; 499 } 500 501 if (!spapr_phb_eeh_available(sphb)) { 502 goto param_error_exit; 503 } 504 505 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option); 506 rtas_st(rets, 0, ret); 507 return; 508 509 param_error_exit: 510 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 511 } 512 513 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, 514 SpaprMachineState *spapr, 515 uint32_t token, uint32_t nargs, 516 target_ulong args, uint32_t nret, 517 target_ulong rets) 518 { 519 SpaprPhbState *sphb; 520 PCIDevice *pdev; 521 uint32_t addr, option; 522 uint64_t buid; 523 524 if ((nargs != 4) || (nret != 2)) { 525 goto param_error_exit; 526 } 527 528 buid = rtas_ldq(args, 1); 529 sphb = spapr_pci_find_phb(spapr, buid); 530 if (!sphb) { 531 goto param_error_exit; 532 } 533 534 if (!spapr_phb_eeh_available(sphb)) { 535 goto param_error_exit; 536 } 537 538 /* 539 * We always have PE address of form "00BB0001". "BB" 540 * represents the bus number of PE's primary bus. 541 */ 542 option = rtas_ld(args, 3); 543 switch (option) { 544 case RTAS_GET_PE_ADDR: 545 addr = rtas_ld(args, 0); 546 pdev = spapr_pci_find_dev(spapr, buid, addr); 547 if (!pdev) { 548 goto param_error_exit; 549 } 550 551 rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1); 552 break; 553 case RTAS_GET_PE_MODE: 554 rtas_st(rets, 1, RTAS_PE_MODE_SHARED); 555 break; 556 default: 557 goto param_error_exit; 558 } 559 560 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 561 return; 562 563 param_error_exit: 564 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 565 } 566 567 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, 568 SpaprMachineState *spapr, 569 uint32_t token, uint32_t nargs, 570 target_ulong args, uint32_t nret, 571 target_ulong rets) 572 { 573 SpaprPhbState *sphb; 574 uint64_t buid; 575 int state, ret; 576 577 if ((nargs != 3) || (nret != 4 && nret != 5)) { 578 goto param_error_exit; 579 } 580 581 buid = rtas_ldq(args, 1); 582 sphb = spapr_pci_find_phb(spapr, buid); 583 if (!sphb) { 584 goto param_error_exit; 585 } 586 587 if (!spapr_phb_eeh_available(sphb)) { 588 goto param_error_exit; 589 } 590 591 ret = spapr_phb_vfio_eeh_get_state(sphb, &state); 592 rtas_st(rets, 0, ret); 593 if (ret != RTAS_OUT_SUCCESS) { 594 return; 595 } 596 597 rtas_st(rets, 1, state); 598 rtas_st(rets, 2, RTAS_EEH_SUPPORT); 599 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); 600 if (nret >= 5) { 601 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); 602 } 603 return; 604 605 param_error_exit: 606 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 607 } 608 609 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, 610 SpaprMachineState *spapr, 611 uint32_t token, uint32_t nargs, 612 target_ulong args, uint32_t nret, 613 target_ulong rets) 614 { 615 SpaprPhbState *sphb; 616 uint32_t option; 617 uint64_t buid; 618 int ret; 619 620 if ((nargs != 4) || (nret != 1)) { 621 goto param_error_exit; 622 } 623 624 buid = rtas_ldq(args, 1); 625 option = rtas_ld(args, 3); 626 sphb = spapr_pci_find_phb(spapr, buid); 627 if (!sphb) { 628 goto param_error_exit; 629 } 630 631 if (!spapr_phb_eeh_available(sphb)) { 632 goto param_error_exit; 633 } 634 635 ret = spapr_phb_vfio_eeh_reset(sphb, option); 636 rtas_st(rets, 0, ret); 637 return; 638 639 param_error_exit: 640 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 641 } 642 643 static void rtas_ibm_configure_pe(PowerPCCPU *cpu, 644 SpaprMachineState *spapr, 645 uint32_t token, uint32_t nargs, 646 target_ulong args, uint32_t nret, 647 target_ulong rets) 648 { 649 SpaprPhbState *sphb; 650 uint64_t buid; 651 int ret; 652 653 if ((nargs != 3) || (nret != 1)) { 654 goto param_error_exit; 655 } 656 657 buid = rtas_ldq(args, 1); 658 sphb = spapr_pci_find_phb(spapr, buid); 659 if (!sphb) { 660 goto param_error_exit; 661 } 662 663 if (!spapr_phb_eeh_available(sphb)) { 664 goto param_error_exit; 665 } 666 667 ret = spapr_phb_vfio_eeh_configure(sphb); 668 rtas_st(rets, 0, ret); 669 return; 670 671 param_error_exit: 672 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 673 } 674 675 /* To support it later */ 676 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, 677 SpaprMachineState *spapr, 678 uint32_t token, uint32_t nargs, 679 target_ulong args, uint32_t nret, 680 target_ulong rets) 681 { 682 SpaprPhbState *sphb; 683 int option; 684 uint64_t buid; 685 686 if ((nargs != 8) || (nret != 1)) { 687 goto param_error_exit; 688 } 689 690 buid = rtas_ldq(args, 1); 691 sphb = spapr_pci_find_phb(spapr, buid); 692 if (!sphb) { 693 goto param_error_exit; 694 } 695 696 if (!spapr_phb_eeh_available(sphb)) { 697 goto param_error_exit; 698 } 699 700 option = rtas_ld(args, 7); 701 switch (option) { 702 case RTAS_SLOT_TEMP_ERR_LOG: 703 case RTAS_SLOT_PERM_ERR_LOG: 704 break; 705 default: 706 goto param_error_exit; 707 } 708 709 /* We don't have error log yet */ 710 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); 711 return; 712 713 param_error_exit: 714 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 715 } 716 717 static void pci_spapr_set_irq(void *opaque, int irq_num, int level) 718 { 719 /* 720 * Here we use the number returned by pci_swizzle_map_irq_fn to find a 721 * corresponding qemu_irq. 722 */ 723 SpaprPhbState *phb = opaque; 724 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 725 726 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); 727 qemu_set_irq(spapr_qirq(spapr, phb->lsi_table[irq_num].irq), level); 728 } 729 730 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) 731 { 732 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); 733 PCIINTxRoute route; 734 735 route.mode = PCI_INTX_ENABLED; 736 route.irq = sphb->lsi_table[pin].irq; 737 738 return route; 739 } 740 741 static uint64_t spapr_msi_read(void *opaque, hwaddr addr, unsigned size) 742 { 743 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid access\n", __func__); 744 return 0; 745 } 746 747 /* 748 * MSI/MSIX memory region implementation. 749 * The handler handles both MSI and MSIX. 750 * The vector number is encoded in least bits in data. 751 */ 752 static void spapr_msi_write(void *opaque, hwaddr addr, 753 uint64_t data, unsigned size) 754 { 755 SpaprMachineState *spapr = opaque; 756 uint32_t irq = data; 757 758 trace_spapr_pci_msi_write(addr, data, irq); 759 760 qemu_irq_pulse(spapr_qirq(spapr, irq)); 761 } 762 763 static const MemoryRegionOps spapr_msi_ops = { 764 /* 765 * .read result is undefined by PCI spec. 766 * define .read method to avoid assert failure in memory_region_init_io 767 */ 768 .read = spapr_msi_read, 769 .write = spapr_msi_write, 770 .endianness = DEVICE_LITTLE_ENDIAN 771 }; 772 773 /* 774 * PHB PCI device 775 */ 776 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 777 { 778 SpaprPhbState *phb = opaque; 779 780 return &phb->iommu_as; 781 } 782 783 static const PCIIOMMUOps spapr_iommu_ops = { 784 .get_address_space = spapr_pci_dma_iommu, 785 }; 786 787 static char *spapr_phb_vfio_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) 788 { 789 g_autofree char *path = NULL; 790 g_autofree char *host = NULL; 791 g_autofree char *devspec = NULL; 792 char *buf = NULL; 793 794 /* Get the PCI VFIO host id */ 795 host = object_property_get_str(OBJECT(pdev), "host", NULL); 796 if (!host) { 797 return NULL; 798 } 799 800 /* Construct the path of the file that will give us the DT location */ 801 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); 802 if (!g_file_get_contents(path, &devspec, NULL, NULL)) { 803 return NULL; 804 } 805 806 /* Construct and read from host device tree the loc-code */ 807 g_free(path); 808 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", devspec); 809 if (!g_file_get_contents(path, &buf, NULL, NULL)) { 810 return NULL; 811 } 812 return buf; 813 } 814 815 static char *spapr_phb_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) 816 { 817 char *buf; 818 const char *devtype = "qemu"; 819 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 820 821 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 822 buf = spapr_phb_vfio_get_loc_code(sphb, pdev); 823 if (buf) { 824 return buf; 825 } 826 devtype = "vfio"; 827 } 828 /* 829 * For emulated devices and VFIO-failure case, make up 830 * the loc-code. 831 */ 832 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", 833 devtype, pdev->name, sphb->index, busnr, 834 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 835 return buf; 836 } 837 838 /* Macros to operate with address in OF binding to PCI */ 839 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) 840 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ 841 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ 842 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ 843 #define b_ss(x) b_x((x), 24, 2) /* the space code */ 844 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ 845 #define b_ddddd(x) b_x((x), 11, 5) /* device number */ 846 #define b_fff(x) b_x((x), 8, 3) /* function number */ 847 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ 848 849 /* for 'reg' OF properties */ 850 #define RESOURCE_CELLS_SIZE 2 851 #define RESOURCE_CELLS_ADDRESS 3 852 853 typedef struct ResourceFields { 854 uint32_t phys_hi; 855 uint32_t phys_mid; 856 uint32_t phys_lo; 857 uint32_t size_hi; 858 uint32_t size_lo; 859 } QEMU_PACKED ResourceFields; 860 861 typedef struct ResourceProps { 862 ResourceFields reg[8]; 863 uint32_t reg_len; 864 } ResourceProps; 865 866 /* fill in the 'reg' OF properties for 867 * a PCI device. 'reg' describes resource requirements for a 868 * device's IO/MEM regions. 869 * 870 * the property is an array of ('phys-addr', 'size') pairs describing 871 * the addressable regions of the PCI device, where 'phys-addr' is a 872 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to 873 * (phys.hi, phys.mid, phys.lo), and 'size' is a 874 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). 875 * 876 * phys.hi = 0xYYXXXXZZ, where: 877 * 0xYY = npt000ss 878 * ||| | 879 * ||| +-- space code 880 * ||| | 881 * ||| + 00 if configuration space 882 * ||| + 01 if IO region, 883 * ||| + 10 if 32-bit MEM region 884 * ||| + 11 if 64-bit MEM region 885 * ||| 886 * ||+------ for non-relocatable IO: 1 if aliased 887 * || for relocatable IO: 1 if below 64KB 888 * || for MEM: 1 if below 1MB 889 * |+------- 1 if region is prefetchable 890 * +-------- 1 if region is non-relocatable 891 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function 892 * bits respectively 893 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding 894 * to the region 895 * 896 * phys.mid and phys.lo correspond respectively to the hi/lo portions 897 * of the actual address of the region. 898 * 899 * note also that addresses defined in this property are, at least 900 * for PAPR guests, relative to the PHBs IO/MEM windows, and 901 * correspond directly to the addresses in the BARs. 902 * 903 * in accordance with PCI Bus Binding to Open Firmware, 904 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, 905 * Appendix C. 906 */ 907 static void populate_resource_props(PCIDevice *d, ResourceProps *rp) 908 { 909 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); 910 uint32_t dev_id = (b_bbbbbbbb(bus_num) | 911 b_ddddd(PCI_SLOT(d->devfn)) | 912 b_fff(PCI_FUNC(d->devfn))); 913 ResourceFields *reg; 914 int i, reg_idx = 0; 915 916 /* config space region */ 917 reg = &rp->reg[reg_idx++]; 918 reg->phys_hi = cpu_to_be32(dev_id); 919 reg->phys_mid = 0; 920 reg->phys_lo = 0; 921 reg->size_hi = 0; 922 reg->size_lo = 0; 923 924 for (i = 0; i < PCI_NUM_REGIONS; i++) { 925 if (!d->io_regions[i].size) { 926 continue; 927 } 928 929 reg = &rp->reg[reg_idx++]; 930 931 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); 932 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 933 reg->phys_hi |= cpu_to_be32(b_ss(1)); 934 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 935 reg->phys_hi |= cpu_to_be32(b_ss(3)); 936 } else { 937 reg->phys_hi |= cpu_to_be32(b_ss(2)); 938 } 939 reg->phys_mid = 0; 940 reg->phys_lo = 0; 941 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); 942 reg->size_lo = cpu_to_be32(d->io_regions[i].size); 943 } 944 945 rp->reg_len = reg_idx * sizeof(ResourceFields); 946 } 947 948 typedef struct PCIClass PCIClass; 949 typedef struct PCISubClass PCISubClass; 950 typedef struct PCIIFace PCIIFace; 951 952 struct PCIIFace { 953 int iface; 954 const char *name; 955 }; 956 957 struct PCISubClass { 958 int subclass; 959 const char *name; 960 const PCIIFace *iface; 961 }; 962 963 struct PCIClass { 964 const char *name; 965 const PCISubClass *subc; 966 }; 967 968 static const PCISubClass undef_subclass[] = { 969 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL }, 970 { 0xFF, NULL, NULL }, 971 }; 972 973 static const PCISubClass mass_subclass[] = { 974 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL }, 975 { PCI_CLASS_STORAGE_IDE, "ide", NULL }, 976 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL }, 977 { PCI_CLASS_STORAGE_IPI, "ipi", NULL }, 978 { PCI_CLASS_STORAGE_RAID, "raid", NULL }, 979 { PCI_CLASS_STORAGE_ATA, "ata", NULL }, 980 { PCI_CLASS_STORAGE_SATA, "sata", NULL }, 981 { PCI_CLASS_STORAGE_SAS, "sas", NULL }, 982 { 0xFF, NULL, NULL }, 983 }; 984 985 static const PCISubClass net_subclass[] = { 986 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL }, 987 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL }, 988 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL }, 989 { PCI_CLASS_NETWORK_ATM, "atm", NULL }, 990 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL }, 991 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL }, 992 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL }, 993 { 0xFF, NULL, NULL }, 994 }; 995 996 static const PCISubClass displ_subclass[] = { 997 { PCI_CLASS_DISPLAY_VGA, "vga", NULL }, 998 { PCI_CLASS_DISPLAY_XGA, "xga", NULL }, 999 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL }, 1000 { 0xFF, NULL, NULL }, 1001 }; 1002 1003 static const PCISubClass media_subclass[] = { 1004 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL }, 1005 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL }, 1006 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL }, 1007 { 0xFF, NULL, NULL }, 1008 }; 1009 1010 static const PCISubClass mem_subclass[] = { 1011 { PCI_CLASS_MEMORY_RAM, "memory", NULL }, 1012 { PCI_CLASS_MEMORY_FLASH, "flash", NULL }, 1013 { 0xFF, NULL, NULL }, 1014 }; 1015 1016 static const PCISubClass bridg_subclass[] = { 1017 { PCI_CLASS_BRIDGE_HOST, "host", NULL }, 1018 { PCI_CLASS_BRIDGE_ISA, "isa", NULL }, 1019 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL }, 1020 { PCI_CLASS_BRIDGE_MC, "mca", NULL }, 1021 { PCI_CLASS_BRIDGE_PCI, "pci", NULL }, 1022 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL }, 1023 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL }, 1024 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL }, 1025 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL }, 1026 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL }, 1027 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL }, 1028 { 0xFF, NULL, NULL }, 1029 }; 1030 1031 static const PCISubClass comm_subclass[] = { 1032 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL }, 1033 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL }, 1034 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL }, 1035 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL }, 1036 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL }, 1037 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL }, 1038 { 0xFF, NULL, NULL, }, 1039 }; 1040 1041 static const PCIIFace pic_iface[] = { 1042 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" }, 1043 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" }, 1044 { 0xFF, NULL }, 1045 }; 1046 1047 static const PCISubClass sys_subclass[] = { 1048 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface }, 1049 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL }, 1050 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL }, 1051 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL }, 1052 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL }, 1053 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL }, 1054 { 0xFF, NULL, NULL }, 1055 }; 1056 1057 static const PCISubClass inp_subclass[] = { 1058 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL }, 1059 { PCI_CLASS_INPUT_PEN, "pen", NULL }, 1060 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL }, 1061 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL }, 1062 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL }, 1063 { 0xFF, NULL, NULL }, 1064 }; 1065 1066 static const PCISubClass dock_subclass[] = { 1067 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL }, 1068 { 0xFF, NULL, NULL }, 1069 }; 1070 1071 static const PCISubClass cpu_subclass[] = { 1072 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL }, 1073 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL }, 1074 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL }, 1075 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL }, 1076 { 0xFF, NULL, NULL }, 1077 }; 1078 1079 static const PCIIFace usb_iface[] = { 1080 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" }, 1081 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", }, 1082 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" }, 1083 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" }, 1084 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" }, 1085 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" }, 1086 { 0xFF, NULL }, 1087 }; 1088 1089 static const PCISubClass ser_subclass[] = { 1090 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL }, 1091 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL }, 1092 { PCI_CLASS_SERIAL_SSA, "ssa", NULL }, 1093 { PCI_CLASS_SERIAL_USB, "usb", usb_iface }, 1094 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL }, 1095 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL }, 1096 { PCI_CLASS_SERIAL_IB, "infiniband", NULL }, 1097 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL }, 1098 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL }, 1099 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL }, 1100 { 0xFF, NULL, NULL }, 1101 }; 1102 1103 static const PCISubClass wrl_subclass[] = { 1104 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL }, 1105 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL }, 1106 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL }, 1107 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL }, 1108 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL }, 1109 { 0xFF, NULL, NULL }, 1110 }; 1111 1112 static const PCISubClass sat_subclass[] = { 1113 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL }, 1114 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL }, 1115 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL }, 1116 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL }, 1117 { 0xFF, NULL, NULL }, 1118 }; 1119 1120 static const PCISubClass crypt_subclass[] = { 1121 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL }, 1122 { PCI_CLASS_CRYPT_ENTERTAINMENT, 1123 "entertainment-encryption", NULL }, 1124 { 0xFF, NULL, NULL }, 1125 }; 1126 1127 static const PCISubClass spc_subclass[] = { 1128 { PCI_CLASS_SP_DPIO, "dpio", NULL }, 1129 { PCI_CLASS_SP_PERF, "counter", NULL }, 1130 { PCI_CLASS_SP_SYNCH, "measurement", NULL }, 1131 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL }, 1132 { 0xFF, NULL, NULL }, 1133 }; 1134 1135 static const PCIClass pci_classes[] = { 1136 { "legacy-device", undef_subclass }, 1137 { "mass-storage", mass_subclass }, 1138 { "network", net_subclass }, 1139 { "display", displ_subclass, }, 1140 { "multimedia-device", media_subclass }, 1141 { "memory-controller", mem_subclass }, 1142 { "unknown-bridge", bridg_subclass }, 1143 { "communication-controller", comm_subclass}, 1144 { "system-peripheral", sys_subclass }, 1145 { "input-controller", inp_subclass }, 1146 { "docking-station", dock_subclass }, 1147 { "cpu", cpu_subclass }, 1148 { "serial-bus", ser_subclass }, 1149 { "wireless-controller", wrl_subclass }, 1150 { "intelligent-io", NULL }, 1151 { "satellite-device", sat_subclass }, 1152 { "encryption", crypt_subclass }, 1153 { "data-processing-controller", spc_subclass }, 1154 }; 1155 1156 static const char *dt_name_from_class(uint8_t class, uint8_t subclass, 1157 uint8_t iface) 1158 { 1159 const PCIClass *pclass; 1160 const PCISubClass *psubclass; 1161 const PCIIFace *piface; 1162 const char *name; 1163 1164 if (class >= ARRAY_SIZE(pci_classes)) { 1165 return "pci"; 1166 } 1167 1168 pclass = pci_classes + class; 1169 name = pclass->name; 1170 1171 if (pclass->subc == NULL) { 1172 return name; 1173 } 1174 1175 psubclass = pclass->subc; 1176 while ((psubclass->subclass & 0xff) != 0xff) { 1177 if ((psubclass->subclass & 0xff) == subclass) { 1178 name = psubclass->name; 1179 break; 1180 } 1181 psubclass++; 1182 } 1183 1184 piface = psubclass->iface; 1185 if (piface == NULL) { 1186 return name; 1187 } 1188 while ((piface->iface & 0xff) != 0xff) { 1189 if ((piface->iface & 0xff) == iface) { 1190 name = piface->name; 1191 break; 1192 } 1193 piface++; 1194 } 1195 1196 return name; 1197 } 1198 1199 /* 1200 * DRC helper functions 1201 */ 1202 1203 static uint32_t drc_id_from_devfn(SpaprPhbState *phb, 1204 uint8_t chassis, int32_t devfn) 1205 { 1206 return (phb->index << 16) | (chassis << 8) | devfn; 1207 } 1208 1209 static SpaprDrc *drc_from_devfn(SpaprPhbState *phb, 1210 uint8_t chassis, int32_t devfn) 1211 { 1212 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI, 1213 drc_id_from_devfn(phb, chassis, devfn)); 1214 } 1215 1216 static uint8_t chassis_from_bus(PCIBus *bus) 1217 { 1218 if (pci_bus_is_root(bus)) { 1219 return 0; 1220 } else { 1221 PCIDevice *bridge = pci_bridge_get_device(bus); 1222 1223 return object_property_get_uint(OBJECT(bridge), "chassis_nr", 1224 &error_abort); 1225 } 1226 } 1227 1228 static SpaprDrc *drc_from_dev(SpaprPhbState *phb, PCIDevice *dev) 1229 { 1230 uint8_t chassis = chassis_from_bus(pci_get_bus(dev)); 1231 1232 return drc_from_devfn(phb, chassis, dev->devfn); 1233 } 1234 1235 static void add_drcs(SpaprPhbState *phb, PCIBus *bus) 1236 { 1237 Object *owner; 1238 int i; 1239 uint8_t chassis; 1240 1241 if (!phb->dr_enabled) { 1242 return; 1243 } 1244 1245 chassis = chassis_from_bus(bus); 1246 1247 if (pci_bus_is_root(bus)) { 1248 owner = OBJECT(phb); 1249 } else { 1250 owner = OBJECT(pci_bridge_get_device(bus)); 1251 } 1252 1253 for (i = 0; i < PCI_SLOT_MAX * PCI_FUNC_MAX; i++) { 1254 spapr_dr_connector_new(owner, TYPE_SPAPR_DRC_PCI, 1255 drc_id_from_devfn(phb, chassis, i)); 1256 } 1257 } 1258 1259 static void remove_drcs(SpaprPhbState *phb, PCIBus *bus) 1260 { 1261 int i; 1262 uint8_t chassis; 1263 1264 if (!phb->dr_enabled) { 1265 return; 1266 } 1267 1268 chassis = chassis_from_bus(bus); 1269 1270 for (i = PCI_SLOT_MAX * PCI_FUNC_MAX - 1; i >= 0; i--) { 1271 SpaprDrc *drc = drc_from_devfn(phb, chassis, i); 1272 1273 if (drc) { 1274 object_unparent(OBJECT(drc)); 1275 } 1276 } 1277 } 1278 1279 typedef struct PciWalkFdt { 1280 void *fdt; 1281 int offset; 1282 SpaprPhbState *sphb; 1283 int err; 1284 } PciWalkFdt; 1285 1286 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev, 1287 void *fdt, int parent_offset); 1288 1289 static void spapr_dt_pci_device_cb(PCIBus *bus, PCIDevice *pdev, 1290 void *opaque) 1291 { 1292 PciWalkFdt *p = opaque; 1293 int err; 1294 1295 if (p->err) { 1296 /* Something's already broken, don't keep going */ 1297 return; 1298 } 1299 1300 err = spapr_dt_pci_device(p->sphb, pdev, p->fdt, p->offset); 1301 if (err < 0) { 1302 p->err = err; 1303 } 1304 } 1305 1306 /* Augment PCI device node with bridge specific information */ 1307 static int spapr_dt_pci_bus(SpaprPhbState *sphb, PCIBus *bus, 1308 void *fdt, int offset) 1309 { 1310 Object *owner; 1311 PciWalkFdt cbinfo = { 1312 .fdt = fdt, 1313 .offset = offset, 1314 .sphb = sphb, 1315 .err = 0, 1316 }; 1317 int ret; 1318 1319 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 1320 RESOURCE_CELLS_ADDRESS)); 1321 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1322 RESOURCE_CELLS_SIZE)); 1323 1324 assert(bus); 1325 pci_for_each_device_under_bus_reverse(bus, spapr_dt_pci_device_cb, &cbinfo); 1326 if (cbinfo.err) { 1327 return cbinfo.err; 1328 } 1329 1330 if (pci_bus_is_root(bus)) { 1331 owner = OBJECT(sphb); 1332 } else { 1333 owner = OBJECT(pci_bridge_get_device(bus)); 1334 } 1335 1336 ret = spapr_dt_drc(fdt, offset, owner, 1337 SPAPR_DR_CONNECTOR_TYPE_PCI); 1338 if (ret) { 1339 return ret; 1340 } 1341 1342 return offset; 1343 } 1344 1345 char *spapr_pci_fw_dev_name(PCIDevice *dev) 1346 { 1347 const gchar *basename; 1348 int slot = PCI_SLOT(dev->devfn); 1349 int func = PCI_FUNC(dev->devfn); 1350 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); 1351 1352 basename = dt_name_from_class((ccode >> 16) & 0xff, (ccode >> 8) & 0xff, 1353 ccode & 0xff); 1354 1355 if (func != 0) { 1356 return g_strdup_printf("%s@%x,%x", basename, slot, func); 1357 } else { 1358 return g_strdup_printf("%s@%x", basename, slot); 1359 } 1360 } 1361 1362 /* create OF node for pci device and required OF DT properties */ 1363 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev, 1364 void *fdt, int parent_offset) 1365 { 1366 int offset; 1367 g_autofree gchar *nodename = spapr_pci_fw_dev_name(dev); 1368 ResourceProps rp; 1369 SpaprDrc *drc = drc_from_dev(sphb, dev); 1370 uint32_t vendor_id = pci_default_read_config(dev, PCI_VENDOR_ID, 2); 1371 uint32_t device_id = pci_default_read_config(dev, PCI_DEVICE_ID, 2); 1372 uint32_t revision_id = pci_default_read_config(dev, PCI_REVISION_ID, 1); 1373 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); 1374 uint32_t irq_pin = pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1); 1375 uint32_t subsystem_id = pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2); 1376 uint32_t subsystem_vendor_id = 1377 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2); 1378 uint32_t cache_line_size = 1379 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1); 1380 uint32_t pci_status = pci_default_read_config(dev, PCI_STATUS, 2); 1381 gchar *loc_code; 1382 1383 _FDT(offset = fdt_add_subnode(fdt, parent_offset, nodename)); 1384 1385 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ 1386 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", vendor_id)); 1387 _FDT(fdt_setprop_cell(fdt, offset, "device-id", device_id)); 1388 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", revision_id)); 1389 1390 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode)); 1391 if (irq_pin) { 1392 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", irq_pin)); 1393 } 1394 1395 if (subsystem_id) { 1396 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", subsystem_id)); 1397 } 1398 1399 if (subsystem_vendor_id) { 1400 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", 1401 subsystem_vendor_id)); 1402 } 1403 1404 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", cache_line_size)); 1405 1406 1407 /* the following fdt cells are masked off the pci status register */ 1408 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", 1409 PCI_STATUS_DEVSEL_MASK & pci_status)); 1410 1411 if (pci_status & PCI_STATUS_FAST_BACK) { 1412 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); 1413 } 1414 if (pci_status & PCI_STATUS_66MHZ) { 1415 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); 1416 } 1417 if (pci_status & PCI_STATUS_UDF) { 1418 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); 1419 } 1420 1421 loc_code = spapr_phb_get_loc_code(sphb, dev); 1422 _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", loc_code)); 1423 g_free(loc_code); 1424 1425 if (drc) { 1426 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", 1427 spapr_drc_index(drc))); 1428 } 1429 1430 if (msi_present(dev)) { 1431 uint32_t max_msi = msi_nr_vectors_allocated(dev); 1432 if (max_msi) { 1433 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi)); 1434 } 1435 } 1436 if (msix_present(dev)) { 1437 uint32_t max_msix = dev->msix_entries_nr; 1438 if (max_msix) { 1439 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix)); 1440 } 1441 } 1442 1443 populate_resource_props(dev, &rp); 1444 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); 1445 1446 if (sphb->pcie_ecs && pci_is_express(dev)) { 1447 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1)); 1448 } 1449 1450 if (!IS_PCI_BRIDGE(dev)) { 1451 /* Properties only for non-bridges */ 1452 uint32_t min_grant = pci_default_read_config(dev, PCI_MIN_GNT, 1); 1453 uint32_t max_latency = pci_default_read_config(dev, PCI_MAX_LAT, 1); 1454 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", min_grant)); 1455 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", max_latency)); 1456 return offset; 1457 } else { 1458 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 1459 1460 return spapr_dt_pci_bus(sphb, sec_bus, fdt, offset); 1461 } 1462 } 1463 1464 /* Callback to be called during DRC release. */ 1465 void spapr_phb_remove_pci_device_cb(DeviceState *dev) 1466 { 1467 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 1468 1469 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 1470 object_unparent(OBJECT(dev)); 1471 } 1472 1473 int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 1474 void *fdt, int *fdt_start_offset, Error **errp) 1475 { 1476 HotplugHandler *plug_handler = qdev_get_hotplug_handler(drc->dev); 1477 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(plug_handler); 1478 PCIDevice *pdev = PCI_DEVICE(drc->dev); 1479 1480 *fdt_start_offset = spapr_dt_pci_device(sphb, pdev, fdt, 0); 1481 return 0; 1482 } 1483 1484 static void spapr_pci_bridge_plug(SpaprPhbState *phb, 1485 PCIBridge *bridge) 1486 { 1487 PCIBus *bus = pci_bridge_get_sec_bus(bridge); 1488 1489 add_drcs(phb, bus); 1490 } 1491 1492 /* Returns non-zero if the value of "chassis_nr" is already in use */ 1493 static int check_chassis_nr(Object *obj, void *opaque) 1494 { 1495 int new_chassis_nr = 1496 object_property_get_uint(opaque, "chassis_nr", &error_abort); 1497 int chassis_nr = 1498 object_property_get_uint(obj, "chassis_nr", NULL); 1499 1500 if (!object_dynamic_cast(obj, TYPE_PCI_BRIDGE)) { 1501 return 0; 1502 } 1503 1504 /* Skip unsupported bridge types */ 1505 if (!chassis_nr) { 1506 return 0; 1507 } 1508 1509 /* Skip self */ 1510 if (obj == opaque) { 1511 return 0; 1512 } 1513 1514 return chassis_nr == new_chassis_nr; 1515 } 1516 1517 static bool bridge_has_valid_chassis_nr(Object *bridge, Error **errp) 1518 { 1519 int chassis_nr = 1520 object_property_get_uint(bridge, "chassis_nr", NULL); 1521 1522 /* 1523 * slotid_cap_init() already ensures that "chassis_nr" isn't null for 1524 * standard PCI bridges, so this really tells if "chassis_nr" is present 1525 * or not. 1526 */ 1527 if (!chassis_nr) { 1528 error_setg(errp, "PCI Bridge lacks a \"chassis_nr\" property"); 1529 error_append_hint(errp, "Try -device pci-bridge instead.\n"); 1530 return false; 1531 } 1532 1533 /* We want unique values for "chassis_nr" */ 1534 if (object_child_foreach_recursive(object_get_root(), check_chassis_nr, 1535 bridge)) { 1536 error_setg(errp, "Bridge chassis %d already in use", chassis_nr); 1537 return false; 1538 } 1539 1540 return true; 1541 } 1542 1543 static void spapr_pci_pre_plug(HotplugHandler *plug_handler, 1544 DeviceState *plugged_dev, Error **errp) 1545 { 1546 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1547 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1548 SpaprDrc *drc = drc_from_dev(phb, pdev); 1549 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); 1550 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1551 1552 if (!phb->dr_enabled) { 1553 /* if this is a hotplug operation initiated by the user 1554 * we need to let them know it's not enabled 1555 */ 1556 if (plugged_dev->hotplugged) { 1557 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1558 phb->parent_obj.bus->qbus.name); 1559 return; 1560 } 1561 } 1562 1563 if (IS_PCI_BRIDGE(plugged_dev)) { 1564 if (!bridge_has_valid_chassis_nr(OBJECT(plugged_dev), errp)) { 1565 return; 1566 } 1567 } 1568 1569 /* Following the QEMU convention used for PCIe multifunction 1570 * hotplug, we do not allow functions to be hotplugged to a 1571 * slot that already has function 0 present 1572 */ 1573 if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] && 1574 PCI_FUNC(pdev->devfn) != 0) { 1575 error_setg(errp, "PCI: slot %d function 0 already occupied by %s," 1576 " additional functions can no longer be exposed to guest.", 1577 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name); 1578 } 1579 1580 if (drc && drc->dev) { 1581 error_setg(errp, "PCI: slot %d already occupied by %s", slotnr, 1582 pci_get_function_0(PCI_DEVICE(drc->dev))->name); 1583 return; 1584 } 1585 } 1586 1587 static void spapr_pci_plug(HotplugHandler *plug_handler, 1588 DeviceState *plugged_dev, Error **errp) 1589 { 1590 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1591 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1592 SpaprDrc *drc = drc_from_dev(phb, pdev); 1593 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1594 1595 /* 1596 * If DR is disabled we don't need to do anything in the case of 1597 * hotplug or coldplug callbacks. 1598 */ 1599 if (!phb->dr_enabled) { 1600 return; 1601 } 1602 1603 g_assert(drc); 1604 1605 if (IS_PCI_BRIDGE(plugged_dev)) { 1606 spapr_pci_bridge_plug(phb, PCI_BRIDGE(plugged_dev)); 1607 } 1608 1609 /* spapr_pci_pre_plug() already checked the DRC is attachable */ 1610 spapr_drc_attach(drc, DEVICE(pdev)); 1611 1612 /* If this is function 0, signal hotplug for all the device functions. 1613 * Otherwise defer sending the hotplug event. 1614 */ 1615 if (!spapr_drc_hotplugged(plugged_dev)) { 1616 spapr_drc_reset(drc); 1617 } else if (PCI_FUNC(pdev->devfn) == 0) { 1618 int i; 1619 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev)); 1620 1621 for (i = 0; i < 8; i++) { 1622 SpaprDrc *func_drc; 1623 SpaprDrcClass *func_drck; 1624 SpaprDREntitySense state; 1625 1626 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1627 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1628 state = func_drck->dr_entity_sense(func_drc); 1629 1630 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { 1631 spapr_hotplug_req_add_by_index(func_drc); 1632 } 1633 } 1634 } 1635 } 1636 1637 static void spapr_pci_bridge_unplug(SpaprPhbState *phb, 1638 PCIBridge *bridge) 1639 { 1640 PCIBus *bus = pci_bridge_get_sec_bus(bridge); 1641 1642 remove_drcs(phb, bus); 1643 } 1644 1645 static void spapr_pci_unplug(HotplugHandler *plug_handler, 1646 DeviceState *plugged_dev, Error **errp) 1647 { 1648 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1649 1650 /* some version guests do not wait for completion of a device 1651 * cleanup (generally done asynchronously by the kernel) before 1652 * signaling to QEMU that the device is safe, but instead sleep 1653 * for some 'safe' period of time. unfortunately on a busy host 1654 * this sleep isn't guaranteed to be long enough, resulting in 1655 * bad things like IRQ lines being left asserted during final 1656 * device removal. to deal with this we call reset just prior 1657 * to finalizing the device, which will put the device back into 1658 * an 'idle' state, as the device cleanup code expects. 1659 */ 1660 pci_device_reset(PCI_DEVICE(plugged_dev)); 1661 1662 if (IS_PCI_BRIDGE(plugged_dev)) { 1663 spapr_pci_bridge_unplug(phb, PCI_BRIDGE(plugged_dev)); 1664 return; 1665 } 1666 1667 qdev_unrealize(plugged_dev); 1668 } 1669 1670 static void spapr_pci_unplug_request(HotplugHandler *plug_handler, 1671 DeviceState *plugged_dev, Error **errp) 1672 { 1673 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1674 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1675 SpaprDrc *drc = drc_from_dev(phb, pdev); 1676 1677 if (!phb->dr_enabled) { 1678 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1679 phb->parent_obj.bus->qbus.name); 1680 return; 1681 } 1682 1683 g_assert(drc); 1684 g_assert(drc->dev == plugged_dev); 1685 1686 if (!spapr_drc_unplug_requested(drc)) { 1687 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1688 SpaprDrc *func_drc; 1689 SpaprDrcClass *func_drck; 1690 SpaprDREntitySense state; 1691 int i; 1692 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev)); 1693 1694 if (IS_PCI_BRIDGE(plugged_dev)) { 1695 error_setg(errp, "PCI: Hot unplug of PCI bridges not supported"); 1696 return; 1697 } 1698 if (object_property_get_uint(OBJECT(pdev), "nvlink2-tgt", NULL)) { 1699 error_setg(errp, "PCI: Cannot unplug NVLink2 devices"); 1700 return; 1701 } 1702 1703 /* ensure any other present functions are pending unplug */ 1704 if (PCI_FUNC(pdev->devfn) == 0) { 1705 for (i = 1; i < 8; i++) { 1706 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1707 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1708 state = func_drck->dr_entity_sense(func_drc); 1709 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT 1710 && !spapr_drc_unplug_requested(func_drc)) { 1711 /* 1712 * Attempting to remove function 0 of a multifunction 1713 * device will will cascade into removing all child 1714 * functions, even if their unplug weren't requested 1715 * beforehand. 1716 */ 1717 spapr_drc_unplug_request(func_drc); 1718 } 1719 } 1720 } 1721 1722 spapr_drc_unplug_request(drc); 1723 1724 /* if this isn't func 0, defer unplug event. otherwise signal removal 1725 * for all present functions 1726 */ 1727 if (PCI_FUNC(pdev->devfn) == 0) { 1728 for (i = 7; i >= 0; i--) { 1729 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1730 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1731 state = func_drck->dr_entity_sense(func_drc); 1732 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { 1733 spapr_hotplug_req_remove_by_index(func_drc); 1734 } 1735 } 1736 } 1737 } else { 1738 error_setg(errp, 1739 "PCI device unplug already in progress for device %s", 1740 drc->dev->id); 1741 } 1742 } 1743 1744 static void spapr_phb_finalizefn(Object *obj) 1745 { 1746 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(obj); 1747 1748 g_free(sphb->dtbusname); 1749 sphb->dtbusname = NULL; 1750 } 1751 1752 static void spapr_phb_unrealize(DeviceState *dev) 1753 { 1754 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1755 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1756 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1757 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(phb); 1758 SpaprTceTable *tcet; 1759 int i; 1760 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 1761 1762 if (sphb->msi) { 1763 g_hash_table_unref(sphb->msi); 1764 sphb->msi = NULL; 1765 } 1766 1767 /* 1768 * Remove IO/MMIO subregions and aliases, rest should get cleaned 1769 * via PHB's unrealize->object_finalize 1770 */ 1771 for (i = windows_supported - 1; i >= 0; i--) { 1772 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); 1773 if (tcet) { 1774 memory_region_del_subregion(&sphb->iommu_root, 1775 spapr_tce_get_iommu(tcet)); 1776 } 1777 } 1778 1779 remove_drcs(sphb, phb->bus); 1780 1781 for (i = PCI_NUM_PINS - 1; i >= 0; i--) { 1782 if (sphb->lsi_table[i].irq) { 1783 spapr_irq_free(spapr, sphb->lsi_table[i].irq, 1); 1784 sphb->lsi_table[i].irq = 0; 1785 } 1786 } 1787 1788 QLIST_REMOVE(sphb, list); 1789 1790 memory_region_del_subregion(&sphb->iommu_root, &sphb->msiwindow); 1791 1792 /* 1793 * An attached PCI device may have memory listeners, eg. VFIO PCI. We have 1794 * unmapped all sections. Remove the listeners now, before destroying the 1795 * address space. 1796 */ 1797 address_space_remove_listeners(&sphb->iommu_as); 1798 address_space_destroy(&sphb->iommu_as); 1799 1800 qbus_set_hotplug_handler(BUS(phb->bus), NULL); 1801 pci_unregister_root_bus(phb->bus); 1802 1803 memory_region_del_subregion(get_system_memory(), &sphb->iowindow); 1804 if (sphb->mem64_win_pciaddr != (hwaddr)-1) { 1805 memory_region_del_subregion(get_system_memory(), &sphb->mem64window); 1806 } 1807 memory_region_del_subregion(get_system_memory(), &sphb->mem32window); 1808 } 1809 1810 static void spapr_phb_destroy_msi(gpointer opaque) 1811 { 1812 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1813 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1814 SpaprPciMsi *msi = opaque; 1815 1816 if (!smc->legacy_irq_allocation) { 1817 spapr_irq_msi_free(spapr, msi->first_irq, msi->num); 1818 } 1819 spapr_irq_free(spapr, msi->first_irq, msi->num); 1820 g_free(msi); 1821 } 1822 1823 static void spapr_phb_realize(DeviceState *dev, Error **errp) 1824 { 1825 ERRP_GUARD(); 1826 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 1827 * tries to add a sPAPR PHB to a non-pseries machine. 1828 */ 1829 SpaprMachineState *spapr = 1830 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), 1831 TYPE_SPAPR_MACHINE); 1832 SpaprMachineClass *smc = spapr ? SPAPR_MACHINE_GET_CLASS(spapr) : NULL; 1833 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1834 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(sbd); 1835 PCIHostState *phb = PCI_HOST_BRIDGE(sbd); 1836 MachineState *ms = MACHINE(spapr); 1837 char *namebuf; 1838 int i; 1839 PCIBus *bus; 1840 uint64_t msi_window_size = 4096; 1841 SpaprTceTable *tcet; 1842 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 1843 1844 if (!spapr) { 1845 error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine"); 1846 return; 1847 } 1848 1849 assert(sphb->index != (uint32_t)-1); /* checked in spapr_phb_pre_plug() */ 1850 1851 if (sphb->mem64_win_size != 0) { 1852 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { 1853 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx 1854 " (max 2 GiB)", sphb->mem_win_size); 1855 return; 1856 } 1857 1858 /* 64-bit window defaults to identity mapping */ 1859 sphb->mem64_win_pciaddr = sphb->mem64_win_addr; 1860 } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { 1861 /* 1862 * For compatibility with old configuration, if no 64-bit MMIO 1863 * window is specified, but the ordinary (32-bit) memory 1864 * window is specified as > 2GiB, we treat it as a 2GiB 32-bit 1865 * window, with a 64-bit MMIO window following on immediately 1866 * afterwards 1867 */ 1868 sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE; 1869 sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE; 1870 sphb->mem64_win_pciaddr = 1871 SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE; 1872 sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE; 1873 } 1874 1875 if (spapr_pci_find_phb(spapr, sphb->buid)) { 1876 SpaprPhbState *s; 1877 1878 error_setg(errp, "PCI host bridges must have unique indexes"); 1879 error_append_hint(errp, "The following indexes are already in use:"); 1880 QLIST_FOREACH(s, &spapr->phbs, list) { 1881 error_append_hint(errp, " %d", s->index); 1882 } 1883 error_append_hint(errp, "\nTry another value for the index property\n"); 1884 return; 1885 } 1886 1887 if (sphb->numa_node != -1 && 1888 (sphb->numa_node >= MAX_NODES || 1889 !ms->numa_state->nodes[sphb->numa_node].present)) { 1890 error_setg(errp, "Invalid NUMA node ID for PCI host bridge"); 1891 return; 1892 } 1893 1894 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); 1895 1896 /* Initialize memory regions */ 1897 namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname); 1898 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); 1899 g_free(namebuf); 1900 1901 namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname); 1902 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb), 1903 namebuf, &sphb->memspace, 1904 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); 1905 g_free(namebuf); 1906 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, 1907 &sphb->mem32window); 1908 1909 if (sphb->mem64_win_size != 0) { 1910 namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname); 1911 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb), 1912 namebuf, &sphb->memspace, 1913 sphb->mem64_win_pciaddr, sphb->mem64_win_size); 1914 g_free(namebuf); 1915 1916 memory_region_add_subregion(get_system_memory(), 1917 sphb->mem64_win_addr, 1918 &sphb->mem64window); 1919 } 1920 1921 /* Initialize IO regions */ 1922 namebuf = g_strdup_printf("%s.io", sphb->dtbusname); 1923 memory_region_init(&sphb->iospace, OBJECT(sphb), 1924 namebuf, SPAPR_PCI_IO_WIN_SIZE); 1925 g_free(namebuf); 1926 1927 namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname); 1928 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, 1929 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); 1930 g_free(namebuf); 1931 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, 1932 &sphb->iowindow); 1933 1934 bus = pci_register_root_bus(dev, NULL, 1935 pci_spapr_set_irq, pci_swizzle_map_irq_fn, sphb, 1936 &sphb->memspace, &sphb->iospace, 1937 PCI_DEVFN(0, 0), PCI_NUM_PINS, 1938 TYPE_PCI_BUS); 1939 1940 /* 1941 * Despite resembling a vanilla PCI bus in most ways, the PAPR 1942 * para-virtualized PCI bus *does* permit PCI-E extended config 1943 * space access 1944 */ 1945 if (sphb->pcie_ecs) { 1946 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 1947 } 1948 phb->bus = bus; 1949 qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb)); 1950 1951 /* 1952 * Initialize PHB address space. 1953 * By default there will be at least one subregion for default 1954 * 32bit DMA window. 1955 * Later the guest might want to create another DMA window 1956 * which will become another memory subregion. 1957 */ 1958 namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname); 1959 memory_region_init(&sphb->iommu_root, OBJECT(sphb), 1960 namebuf, UINT64_MAX); 1961 g_free(namebuf); 1962 address_space_init(&sphb->iommu_as, &sphb->iommu_root, 1963 sphb->dtbusname); 1964 1965 /* 1966 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, 1967 * we need to allocate some memory to catch those writes coming 1968 * from msi_notify()/msix_notify(). 1969 * As MSIMessage:addr is going to be the same and MSIMessage:data 1970 * is going to be a VIRQ number, 4 bytes of the MSI MR will only 1971 * be used. 1972 * 1973 * For KVM we want to ensure that this memory is a full page so that 1974 * our memory slot is of page size granularity. 1975 */ 1976 if (kvm_enabled()) { 1977 msi_window_size = qemu_real_host_page_size(); 1978 } 1979 1980 memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr, 1981 "msi", msi_window_size); 1982 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, 1983 &sphb->msiwindow); 1984 1985 pci_setup_iommu(bus, &spapr_iommu_ops, sphb); 1986 1987 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); 1988 1989 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); 1990 1991 /* Initialize the LSI table */ 1992 for (i = 0; i < PCI_NUM_PINS; i++) { 1993 int irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i; 1994 1995 if (smc->legacy_irq_allocation) { 1996 irq = spapr_irq_findone(spapr, errp); 1997 if (irq < 0) { 1998 error_prepend(errp, "can't allocate LSIs: "); 1999 /* 2000 * Older machines will never support PHB hotplug, ie, this is an 2001 * init only path and QEMU will terminate. No need to rollback. 2002 */ 2003 return; 2004 } 2005 } 2006 2007 if (spapr_irq_claim(spapr, irq, true, errp) < 0) { 2008 error_prepend(errp, "can't allocate LSIs: "); 2009 goto unrealize; 2010 } 2011 2012 sphb->lsi_table[i].irq = irq; 2013 } 2014 2015 /* allocate connectors for child PCI devices */ 2016 add_drcs(sphb, phb->bus); 2017 2018 /* DMA setup */ 2019 for (i = 0; i < windows_supported; ++i) { 2020 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]); 2021 if (!tcet) { 2022 error_setg(errp, "Creating window#%d failed for %s", 2023 i, sphb->dtbusname); 2024 goto unrealize; 2025 } 2026 memory_region_add_subregion(&sphb->iommu_root, 0, 2027 spapr_tce_get_iommu(tcet)); 2028 } 2029 2030 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, 2031 spapr_phb_destroy_msi); 2032 return; 2033 2034 unrealize: 2035 spapr_phb_unrealize(dev); 2036 } 2037 2038 static int spapr_phb_children_reset(Object *child, void *opaque) 2039 { 2040 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); 2041 2042 if (dev) { 2043 device_cold_reset(dev); 2044 } 2045 2046 return 0; 2047 } 2048 2049 void spapr_phb_dma_reset(SpaprPhbState *sphb) 2050 { 2051 int i; 2052 SpaprTceTable *tcet; 2053 2054 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) { 2055 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); 2056 2057 if (tcet && tcet->nb_table) { 2058 spapr_tce_table_disable(tcet); 2059 } 2060 } 2061 2062 /* Register default 32bit DMA window */ 2063 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]); 2064 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr, 2065 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT); 2066 tcet->def_win = true; 2067 } 2068 2069 static void spapr_phb_reset(DeviceState *qdev) 2070 { 2071 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev); 2072 2073 spapr_phb_dma_reset(sphb); 2074 2075 /* Reset the IOMMU state */ 2076 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); 2077 2078 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) { 2079 spapr_phb_vfio_reset(qdev); 2080 } 2081 2082 g_hash_table_remove_all(sphb->msi); 2083 } 2084 2085 static Property spapr_phb_properties[] = { 2086 DEFINE_PROP_UINT32("index", SpaprPhbState, index, -1), 2087 DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState, mem_win_size, 2088 SPAPR_PCI_MEM32_WIN_SIZE), 2089 DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState, mem64_win_size, 2090 SPAPR_PCI_MEM64_WIN_SIZE), 2091 DEFINE_PROP_UINT64("io_win_size", SpaprPhbState, io_win_size, 2092 SPAPR_PCI_IO_WIN_SIZE), 2093 DEFINE_PROP_BOOL("dynamic-reconfiguration", SpaprPhbState, dr_enabled, 2094 true), 2095 /* Default DMA window is 0..1GB */ 2096 DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState, dma_win_addr, 0), 2097 DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState, dma_win_size, 0x40000000), 2098 DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState, dma64_win_addr, 2099 0x800000000000000ULL), 2100 DEFINE_PROP_BOOL("ddw", SpaprPhbState, ddw_enabled, true), 2101 DEFINE_PROP_UINT64("pgsz", SpaprPhbState, page_size_mask, 2102 (1ULL << 12) | (1ULL << 16) 2103 | (1ULL << 21) | (1ULL << 24)), 2104 DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1), 2105 DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState, 2106 pre_2_8_migration, false), 2107 DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState, 2108 pcie_ecs, true), 2109 DEFINE_PROP_BOOL("pre-5.1-associativity", SpaprPhbState, 2110 pre_5_1_assoc, false), 2111 DEFINE_PROP_END_OF_LIST(), 2112 }; 2113 2114 static const VMStateDescription vmstate_spapr_pci_lsi = { 2115 .name = "spapr_pci/lsi", 2116 .version_id = 1, 2117 .minimum_version_id = 1, 2118 .fields = (VMStateField[]) { 2119 VMSTATE_UINT32_EQUAL(irq, SpaprPciLsi, NULL), 2120 2121 VMSTATE_END_OF_LIST() 2122 }, 2123 }; 2124 2125 static const VMStateDescription vmstate_spapr_pci_msi = { 2126 .name = "spapr_pci/msi", 2127 .version_id = 1, 2128 .minimum_version_id = 1, 2129 .fields = (VMStateField []) { 2130 VMSTATE_UINT32(key, SpaprPciMsiMig), 2131 VMSTATE_UINT32(value.first_irq, SpaprPciMsiMig), 2132 VMSTATE_UINT32(value.num, SpaprPciMsiMig), 2133 VMSTATE_END_OF_LIST() 2134 }, 2135 }; 2136 2137 static int spapr_pci_pre_save(void *opaque) 2138 { 2139 SpaprPhbState *sphb = opaque; 2140 GHashTableIter iter; 2141 gpointer key, value; 2142 int i; 2143 2144 if (sphb->pre_2_8_migration) { 2145 sphb->mig_liobn = sphb->dma_liobn[0]; 2146 sphb->mig_mem_win_addr = sphb->mem_win_addr; 2147 sphb->mig_mem_win_size = sphb->mem_win_size; 2148 sphb->mig_io_win_addr = sphb->io_win_addr; 2149 sphb->mig_io_win_size = sphb->io_win_size; 2150 2151 if ((sphb->mem64_win_size != 0) 2152 && (sphb->mem64_win_addr 2153 == (sphb->mem_win_addr + sphb->mem_win_size))) { 2154 sphb->mig_mem_win_size += sphb->mem64_win_size; 2155 } 2156 } 2157 2158 g_free(sphb->msi_devs); 2159 sphb->msi_devs = NULL; 2160 sphb->msi_devs_num = g_hash_table_size(sphb->msi); 2161 if (!sphb->msi_devs_num) { 2162 return 0; 2163 } 2164 sphb->msi_devs = g_new(SpaprPciMsiMig, sphb->msi_devs_num); 2165 2166 g_hash_table_iter_init(&iter, sphb->msi); 2167 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { 2168 sphb->msi_devs[i].key = *(uint32_t *) key; 2169 sphb->msi_devs[i].value = *(SpaprPciMsi *) value; 2170 } 2171 2172 return 0; 2173 } 2174 2175 static int spapr_pci_post_save(void *opaque) 2176 { 2177 SpaprPhbState *sphb = opaque; 2178 2179 g_free(sphb->msi_devs); 2180 sphb->msi_devs = NULL; 2181 sphb->msi_devs_num = 0; 2182 return 0; 2183 } 2184 2185 static int spapr_pci_post_load(void *opaque, int version_id) 2186 { 2187 SpaprPhbState *sphb = opaque; 2188 gpointer key, value; 2189 int i; 2190 2191 for (i = 0; i < sphb->msi_devs_num; ++i) { 2192 key = g_memdup(&sphb->msi_devs[i].key, 2193 sizeof(sphb->msi_devs[i].key)); 2194 value = g_memdup(&sphb->msi_devs[i].value, 2195 sizeof(sphb->msi_devs[i].value)); 2196 g_hash_table_insert(sphb->msi, key, value); 2197 } 2198 g_free(sphb->msi_devs); 2199 sphb->msi_devs = NULL; 2200 sphb->msi_devs_num = 0; 2201 2202 return 0; 2203 } 2204 2205 static bool pre_2_8_migration(void *opaque, int version_id) 2206 { 2207 SpaprPhbState *sphb = opaque; 2208 2209 return sphb->pre_2_8_migration; 2210 } 2211 2212 static const VMStateDescription vmstate_spapr_pci = { 2213 .name = "spapr_pci", 2214 .version_id = 2, 2215 .minimum_version_id = 2, 2216 .pre_save = spapr_pci_pre_save, 2217 .post_save = spapr_pci_post_save, 2218 .post_load = spapr_pci_post_load, 2219 .fields = (VMStateField[]) { 2220 VMSTATE_UINT64_EQUAL(buid, SpaprPhbState, NULL), 2221 VMSTATE_UINT32_TEST(mig_liobn, SpaprPhbState, pre_2_8_migration), 2222 VMSTATE_UINT64_TEST(mig_mem_win_addr, SpaprPhbState, pre_2_8_migration), 2223 VMSTATE_UINT64_TEST(mig_mem_win_size, SpaprPhbState, pre_2_8_migration), 2224 VMSTATE_UINT64_TEST(mig_io_win_addr, SpaprPhbState, pre_2_8_migration), 2225 VMSTATE_UINT64_TEST(mig_io_win_size, SpaprPhbState, pre_2_8_migration), 2226 VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0, 2227 vmstate_spapr_pci_lsi, SpaprPciLsi), 2228 VMSTATE_INT32(msi_devs_num, SpaprPhbState), 2229 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, SpaprPhbState, msi_devs_num, 0, 2230 vmstate_spapr_pci_msi, SpaprPciMsiMig), 2231 VMSTATE_END_OF_LIST() 2232 }, 2233 }; 2234 2235 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, 2236 PCIBus *rootbus) 2237 { 2238 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); 2239 2240 return sphb->dtbusname; 2241 } 2242 2243 static void spapr_phb_class_init(ObjectClass *klass, void *data) 2244 { 2245 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 2246 DeviceClass *dc = DEVICE_CLASS(klass); 2247 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); 2248 2249 hc->root_bus_path = spapr_phb_root_bus_path; 2250 dc->realize = spapr_phb_realize; 2251 dc->unrealize = spapr_phb_unrealize; 2252 device_class_set_props(dc, spapr_phb_properties); 2253 dc->reset = spapr_phb_reset; 2254 dc->vmsd = &vmstate_spapr_pci; 2255 /* Supported by TYPE_SPAPR_MACHINE */ 2256 dc->user_creatable = true; 2257 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 2258 hp->pre_plug = spapr_pci_pre_plug; 2259 hp->plug = spapr_pci_plug; 2260 hp->unplug = spapr_pci_unplug; 2261 hp->unplug_request = spapr_pci_unplug_request; 2262 } 2263 2264 static const TypeInfo spapr_phb_info = { 2265 .name = TYPE_SPAPR_PCI_HOST_BRIDGE, 2266 .parent = TYPE_PCI_HOST_BRIDGE, 2267 .instance_size = sizeof(SpaprPhbState), 2268 .instance_finalize = spapr_phb_finalizefn, 2269 .class_init = spapr_phb_class_init, 2270 .interfaces = (InterfaceInfo[]) { 2271 { TYPE_HOTPLUG_HANDLER }, 2272 { } 2273 } 2274 }; 2275 2276 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, 2277 void *opaque) 2278 { 2279 unsigned int *bus_no = opaque; 2280 PCIBus *sec_bus = NULL; 2281 2282 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 2283 PCI_HEADER_TYPE_BRIDGE)) { 2284 return; 2285 } 2286 2287 (*bus_no)++; 2288 pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1); 2289 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); 2290 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 2291 2292 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 2293 if (!sec_bus) { 2294 return; 2295 } 2296 2297 pci_for_each_device_under_bus(sec_bus, spapr_phb_pci_enumerate_bridge, 2298 bus_no); 2299 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 2300 } 2301 2302 static void spapr_phb_pci_enumerate(SpaprPhbState *phb) 2303 { 2304 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 2305 unsigned int bus_no = 0; 2306 2307 pci_for_each_device_under_bus(bus, spapr_phb_pci_enumerate_bridge, 2308 &bus_no); 2309 2310 } 2311 2312 int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb, 2313 uint32_t intc_phandle, void *fdt, int *node_offset) 2314 { 2315 int bus_off, i, j, ret; 2316 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; 2317 struct { 2318 uint32_t hi; 2319 uint64_t child; 2320 uint64_t parent; 2321 uint64_t size; 2322 } QEMU_PACKED ranges[] = { 2323 { 2324 cpu_to_be32(b_ss(1)), cpu_to_be64(0), 2325 cpu_to_be64(phb->io_win_addr), 2326 cpu_to_be64(memory_region_size(&phb->iospace)), 2327 }, 2328 { 2329 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), 2330 cpu_to_be64(phb->mem_win_addr), 2331 cpu_to_be64(phb->mem_win_size), 2332 }, 2333 { 2334 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr), 2335 cpu_to_be64(phb->mem64_win_addr), 2336 cpu_to_be64(phb->mem64_win_size), 2337 }, 2338 }; 2339 const unsigned sizeof_ranges = 2340 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]); 2341 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; 2342 uint32_t interrupt_map_mask[] = { 2343 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; 2344 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; 2345 uint32_t ddw_applicable[] = { 2346 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW), 2347 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW), 2348 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW) 2349 }; 2350 uint32_t ddw_extensions[] = { 2351 cpu_to_be32(2), 2352 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW), 2353 cpu_to_be32(1), /* 1: ibm,query-pe-dma-window 6 outputs, PAPR 2.8 */ 2354 }; 2355 SpaprTceTable *tcet; 2356 SpaprDrc *drc; 2357 2358 /* Start populating the FDT */ 2359 _FDT(bus_off = fdt_add_subnode(fdt, 0, phb->dtbusname)); 2360 if (node_offset) { 2361 *node_offset = bus_off; 2362 } 2363 2364 /* Write PHB properties */ 2365 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); 2366 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); 2367 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); 2368 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); 2369 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); 2370 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); 2371 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); 2372 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); 2373 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", 2374 spapr_irq_nr_msis(spapr))); 2375 2376 /* Dynamic DMA window */ 2377 if (phb->ddw_enabled) { 2378 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable, 2379 sizeof(ddw_applicable))); 2380 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions", 2381 &ddw_extensions, sizeof(ddw_extensions))); 2382 } 2383 2384 /* Advertise NUMA via ibm,associativity */ 2385 if (phb->numa_node != -1) { 2386 spapr_numa_write_associativity_dt(spapr, fdt, bus_off, phb->numa_node); 2387 } 2388 2389 /* Build the interrupt-map, this must matches what is done 2390 * in pci_swizzle_map_irq_fn 2391 */ 2392 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", 2393 &interrupt_map_mask, sizeof(interrupt_map_mask))); 2394 for (i = 0; i < PCI_SLOT_MAX; i++) { 2395 for (j = 0; j < PCI_NUM_PINS; j++) { 2396 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; 2397 int lsi_num = pci_swizzle(i, j); 2398 2399 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); 2400 irqmap[1] = 0; 2401 irqmap[2] = 0; 2402 irqmap[3] = cpu_to_be32(j+1); 2403 irqmap[4] = cpu_to_be32(intc_phandle); 2404 spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true); 2405 } 2406 } 2407 /* Write interrupt map */ 2408 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, 2409 sizeof(interrupt_map))); 2410 2411 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]); 2412 if (!tcet) { 2413 return -1; 2414 } 2415 spapr_dma_dt(fdt, bus_off, "ibm,dma-window", 2416 tcet->liobn, tcet->bus_offset, 2417 tcet->nb_table << tcet->page_shift); 2418 2419 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, phb->index); 2420 if (drc) { 2421 uint32_t drc_index = cpu_to_be32(spapr_drc_index(drc)); 2422 2423 _FDT(fdt_setprop(fdt, bus_off, "ibm,my-drc-index", &drc_index, 2424 sizeof(drc_index))); 2425 } 2426 2427 /* Walk the bridges and program the bus numbers*/ 2428 spapr_phb_pci_enumerate(phb); 2429 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); 2430 2431 /* Walk the bridge and subordinate buses */ 2432 ret = spapr_dt_pci_bus(phb, PCI_HOST_BRIDGE(phb)->bus, fdt, bus_off); 2433 if (ret < 0) { 2434 return ret; 2435 } 2436 2437 return 0; 2438 } 2439 2440 void spapr_pci_rtas_init(void) 2441 { 2442 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", 2443 rtas_read_pci_config); 2444 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", 2445 rtas_write_pci_config); 2446 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", 2447 rtas_ibm_read_pci_config); 2448 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", 2449 rtas_ibm_write_pci_config); 2450 if (msi_nonbroken) { 2451 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, 2452 "ibm,query-interrupt-source-number", 2453 rtas_ibm_query_interrupt_source_number); 2454 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", 2455 rtas_ibm_change_msi); 2456 } 2457 2458 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, 2459 "ibm,set-eeh-option", 2460 rtas_ibm_set_eeh_option); 2461 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, 2462 "ibm,get-config-addr-info2", 2463 rtas_ibm_get_config_addr_info2); 2464 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, 2465 "ibm,read-slot-reset-state2", 2466 rtas_ibm_read_slot_reset_state2); 2467 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, 2468 "ibm,set-slot-reset", 2469 rtas_ibm_set_slot_reset); 2470 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, 2471 "ibm,configure-pe", 2472 rtas_ibm_configure_pe); 2473 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, 2474 "ibm,slot-error-detail", 2475 rtas_ibm_slot_error_detail); 2476 } 2477 2478 static void spapr_pci_register_types(void) 2479 { 2480 type_register_static(&spapr_phb_info); 2481 } 2482 2483 type_init(spapr_pci_register_types) 2484 2485 static int spapr_switch_one_vga(DeviceState *dev, void *opaque) 2486 { 2487 bool be = *(bool *)opaque; 2488 2489 if (object_dynamic_cast(OBJECT(dev), "VGA") 2490 || object_dynamic_cast(OBJECT(dev), "secondary-vga") 2491 || object_dynamic_cast(OBJECT(dev), "bochs-display") 2492 || object_dynamic_cast(OBJECT(dev), "virtio-vga")) { 2493 object_property_set_bool(OBJECT(dev), "big-endian-framebuffer", be, 2494 &error_abort); 2495 } 2496 return 0; 2497 } 2498 2499 void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian) 2500 { 2501 SpaprPhbState *sphb; 2502 2503 /* 2504 * For backward compatibility with existing guests, we switch 2505 * the endianness of the VGA controller when changing the guest 2506 * interrupt mode 2507 */ 2508 QLIST_FOREACH(sphb, &spapr->phbs, list) { 2509 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; 2510 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, 2511 &big_endian); 2512 } 2513 } 2514