xref: /openbmc/qemu/hw/ppc/spapr_pci.c (revision 9aa3397f)
1 /*
2  * QEMU sPAPR PCI host originated from Uninorth PCI host
3  *
4  * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5  * Copyright (C) 2011 David Gibson, IBM Corporation.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  */
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "qemu-common.h"
28 #include "cpu.h"
29 #include "hw/hw.h"
30 #include "hw/sysbus.h"
31 #include "hw/pci/pci.h"
32 #include "hw/pci/msi.h"
33 #include "hw/pci/msix.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/ppc/spapr.h"
36 #include "hw/pci-host/spapr.h"
37 #include "exec/address-spaces.h"
38 #include "exec/ram_addr.h"
39 #include <libfdt.h>
40 #include "trace.h"
41 #include "qemu/error-report.h"
42 #include "qapi/qmp/qerror.h"
43 
44 #include "hw/pci/pci_bridge.h"
45 #include "hw/pci/pci_bus.h"
46 #include "hw/pci/pci_ids.h"
47 #include "hw/ppc/spapr_drc.h"
48 #include "sysemu/device_tree.h"
49 #include "sysemu/kvm.h"
50 #include "sysemu/hostmem.h"
51 #include "sysemu/numa.h"
52 
53 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
54 #define RTAS_QUERY_FN           0
55 #define RTAS_CHANGE_FN          1
56 #define RTAS_RESET_FN           2
57 #define RTAS_CHANGE_MSI_FN      3
58 #define RTAS_CHANGE_MSIX_FN     4
59 
60 /* Interrupt types to return on RTAS_CHANGE_* */
61 #define RTAS_TYPE_MSI           1
62 #define RTAS_TYPE_MSIX          2
63 
64 #define FDT_NAME_MAX          128
65 
66 #define _FDT(exp) \
67     do { \
68         int ret = (exp);                                           \
69         if (ret < 0) {                                             \
70             return ret;                                            \
71         }                                                          \
72     } while (0)
73 
74 sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid)
75 {
76     sPAPRPHBState *sphb;
77 
78     QLIST_FOREACH(sphb, &spapr->phbs, list) {
79         if (sphb->buid != buid) {
80             continue;
81         }
82         return sphb;
83     }
84 
85     return NULL;
86 }
87 
88 PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
89                               uint32_t config_addr)
90 {
91     sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
92     PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
93     int bus_num = (config_addr >> 16) & 0xFF;
94     int devfn = (config_addr >> 8) & 0xFF;
95 
96     if (!phb) {
97         return NULL;
98     }
99 
100     return pci_find_device(phb->bus, bus_num, devfn);
101 }
102 
103 static uint32_t rtas_pci_cfgaddr(uint32_t arg)
104 {
105     /* This handles the encoding of extended config space addresses */
106     return ((arg >> 20) & 0xf00) | (arg & 0xff);
107 }
108 
109 static void finish_read_pci_config(sPAPRMachineState *spapr, uint64_t buid,
110                                    uint32_t addr, uint32_t size,
111                                    target_ulong rets)
112 {
113     PCIDevice *pci_dev;
114     uint32_t val;
115 
116     if ((size != 1) && (size != 2) && (size != 4)) {
117         /* access must be 1, 2 or 4 bytes */
118         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
119         return;
120     }
121 
122     pci_dev = spapr_pci_find_dev(spapr, buid, addr);
123     addr = rtas_pci_cfgaddr(addr);
124 
125     if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
126         /* Access must be to a valid device, within bounds and
127          * naturally aligned */
128         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
129         return;
130     }
131 
132     val = pci_host_config_read_common(pci_dev, addr,
133                                       pci_config_size(pci_dev), size);
134 
135     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
136     rtas_st(rets, 1, val);
137 }
138 
139 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
140                                      uint32_t token, uint32_t nargs,
141                                      target_ulong args,
142                                      uint32_t nret, target_ulong rets)
143 {
144     uint64_t buid;
145     uint32_t size, addr;
146 
147     if ((nargs != 4) || (nret != 2)) {
148         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
149         return;
150     }
151 
152     buid = rtas_ldq(args, 1);
153     size = rtas_ld(args, 3);
154     addr = rtas_ld(args, 0);
155 
156     finish_read_pci_config(spapr, buid, addr, size, rets);
157 }
158 
159 static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
160                                  uint32_t token, uint32_t nargs,
161                                  target_ulong args,
162                                  uint32_t nret, target_ulong rets)
163 {
164     uint32_t size, addr;
165 
166     if ((nargs != 2) || (nret != 2)) {
167         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
168         return;
169     }
170 
171     size = rtas_ld(args, 1);
172     addr = rtas_ld(args, 0);
173 
174     finish_read_pci_config(spapr, 0, addr, size, rets);
175 }
176 
177 static void finish_write_pci_config(sPAPRMachineState *spapr, uint64_t buid,
178                                     uint32_t addr, uint32_t size,
179                                     uint32_t val, target_ulong rets)
180 {
181     PCIDevice *pci_dev;
182 
183     if ((size != 1) && (size != 2) && (size != 4)) {
184         /* access must be 1, 2 or 4 bytes */
185         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
186         return;
187     }
188 
189     pci_dev = spapr_pci_find_dev(spapr, buid, addr);
190     addr = rtas_pci_cfgaddr(addr);
191 
192     if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
193         /* Access must be to a valid device, within bounds and
194          * naturally aligned */
195         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
196         return;
197     }
198 
199     pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
200                                  val, size);
201 
202     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
203 }
204 
205 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
206                                       uint32_t token, uint32_t nargs,
207                                       target_ulong args,
208                                       uint32_t nret, target_ulong rets)
209 {
210     uint64_t buid;
211     uint32_t val, size, addr;
212 
213     if ((nargs != 5) || (nret != 1)) {
214         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
215         return;
216     }
217 
218     buid = rtas_ldq(args, 1);
219     val = rtas_ld(args, 4);
220     size = rtas_ld(args, 3);
221     addr = rtas_ld(args, 0);
222 
223     finish_write_pci_config(spapr, buid, addr, size, val, rets);
224 }
225 
226 static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
227                                   uint32_t token, uint32_t nargs,
228                                   target_ulong args,
229                                   uint32_t nret, target_ulong rets)
230 {
231     uint32_t val, size, addr;
232 
233     if ((nargs != 3) || (nret != 1)) {
234         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
235         return;
236     }
237 
238 
239     val = rtas_ld(args, 2);
240     size = rtas_ld(args, 1);
241     addr = rtas_ld(args, 0);
242 
243     finish_write_pci_config(spapr, 0, addr, size, val, rets);
244 }
245 
246 /*
247  * Set MSI/MSIX message data.
248  * This is required for msi_notify()/msix_notify() which
249  * will write at the addresses via spapr_msi_write().
250  *
251  * If hwaddr == 0, all entries will have .data == first_irq i.e.
252  * table will be reset.
253  */
254 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix,
255                              unsigned first_irq, unsigned req_num)
256 {
257     unsigned i;
258     MSIMessage msg = { .address = addr, .data = first_irq };
259 
260     if (!msix) {
261         msi_set_message(pdev, msg);
262         trace_spapr_pci_msi_setup(pdev->name, 0, msg.address);
263         return;
264     }
265 
266     for (i = 0; i < req_num; ++i) {
267         msix_set_message(pdev, i, msg);
268         trace_spapr_pci_msi_setup(pdev->name, i, msg.address);
269         if (addr) {
270             ++msg.data;
271         }
272     }
273 }
274 
275 static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
276                                 uint32_t token, uint32_t nargs,
277                                 target_ulong args, uint32_t nret,
278                                 target_ulong rets)
279 {
280     uint32_t config_addr = rtas_ld(args, 0);
281     uint64_t buid = rtas_ldq(args, 1);
282     unsigned int func = rtas_ld(args, 3);
283     unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */
284     unsigned int seq_num = rtas_ld(args, 5);
285     unsigned int ret_intr_type;
286     unsigned int irq, max_irqs = 0;
287     sPAPRPHBState *phb = NULL;
288     PCIDevice *pdev = NULL;
289     spapr_pci_msi *msi;
290     int *config_addr_key;
291     Error *err = NULL;
292 
293     switch (func) {
294     case RTAS_CHANGE_MSI_FN:
295     case RTAS_CHANGE_FN:
296         ret_intr_type = RTAS_TYPE_MSI;
297         break;
298     case RTAS_CHANGE_MSIX_FN:
299         ret_intr_type = RTAS_TYPE_MSIX;
300         break;
301     default:
302         error_report("rtas_ibm_change_msi(%u) is not implemented", func);
303         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
304         return;
305     }
306 
307     /* Fins sPAPRPHBState */
308     phb = spapr_pci_find_phb(spapr, buid);
309     if (phb) {
310         pdev = spapr_pci_find_dev(spapr, buid, config_addr);
311     }
312     if (!phb || !pdev) {
313         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
314         return;
315     }
316 
317     msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
318 
319     /* Releasing MSIs */
320     if (!req_num) {
321         if (!msi) {
322             trace_spapr_pci_msi("Releasing wrong config", config_addr);
323             rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
324             return;
325         }
326 
327         spapr_ics_free(spapr->ics, msi->first_irq, msi->num);
328         if (msi_present(pdev)) {
329             spapr_msi_setmsg(pdev, 0, false, 0, 0);
330         }
331         if (msix_present(pdev)) {
332             spapr_msi_setmsg(pdev, 0, true, 0, 0);
333         }
334         g_hash_table_remove(phb->msi, &config_addr);
335 
336         trace_spapr_pci_msi("Released MSIs", config_addr);
337         rtas_st(rets, 0, RTAS_OUT_SUCCESS);
338         rtas_st(rets, 1, 0);
339         return;
340     }
341 
342     /* Enabling MSI */
343 
344     /* Check if the device supports as many IRQs as requested */
345     if (ret_intr_type == RTAS_TYPE_MSI) {
346         max_irqs = msi_nr_vectors_allocated(pdev);
347     } else if (ret_intr_type == RTAS_TYPE_MSIX) {
348         max_irqs = pdev->msix_entries_nr;
349     }
350     if (!max_irqs) {
351         error_report("Requested interrupt type %d is not enabled for device %x",
352                      ret_intr_type, config_addr);
353         rtas_st(rets, 0, -1); /* Hardware error */
354         return;
355     }
356     /* Correct the number if the guest asked for too many */
357     if (req_num > max_irqs) {
358         trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs);
359         req_num = max_irqs;
360         irq = 0; /* to avoid misleading trace */
361         goto out;
362     }
363 
364     /* Allocate MSIs */
365     irq = spapr_ics_alloc_block(spapr->ics, req_num, false,
366                            ret_intr_type == RTAS_TYPE_MSI, &err);
367     if (err) {
368         error_reportf_err(err, "Can't allocate MSIs for device %x: ",
369                           config_addr);
370         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
371         return;
372     }
373 
374     /* Release previous MSIs */
375     if (msi) {
376         spapr_ics_free(spapr->ics, msi->first_irq, msi->num);
377         g_hash_table_remove(phb->msi, &config_addr);
378     }
379 
380     /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
381     spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX,
382                      irq, req_num);
383 
384     /* Add MSI device to cache */
385     msi = g_new(spapr_pci_msi, 1);
386     msi->first_irq = irq;
387     msi->num = req_num;
388     config_addr_key = g_new(int, 1);
389     *config_addr_key = config_addr;
390     g_hash_table_insert(phb->msi, config_addr_key, msi);
391 
392 out:
393     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
394     rtas_st(rets, 1, req_num);
395     rtas_st(rets, 2, ++seq_num);
396     if (nret > 3) {
397         rtas_st(rets, 3, ret_intr_type);
398     }
399 
400     trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq);
401 }
402 
403 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
404                                                    sPAPRMachineState *spapr,
405                                                    uint32_t token,
406                                                    uint32_t nargs,
407                                                    target_ulong args,
408                                                    uint32_t nret,
409                                                    target_ulong rets)
410 {
411     uint32_t config_addr = rtas_ld(args, 0);
412     uint64_t buid = rtas_ldq(args, 1);
413     unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3);
414     sPAPRPHBState *phb = NULL;
415     PCIDevice *pdev = NULL;
416     spapr_pci_msi *msi;
417 
418     /* Find sPAPRPHBState */
419     phb = spapr_pci_find_phb(spapr, buid);
420     if (phb) {
421         pdev = spapr_pci_find_dev(spapr, buid, config_addr);
422     }
423     if (!phb || !pdev) {
424         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
425         return;
426     }
427 
428     /* Find device descriptor and start IRQ */
429     msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
430     if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) {
431         trace_spapr_pci_msi("Failed to return vector", config_addr);
432         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
433         return;
434     }
435     intr_src_num = msi->first_irq + ioa_intr_num;
436     trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num,
437                                                            intr_src_num);
438 
439     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
440     rtas_st(rets, 1, intr_src_num);
441     rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */
442 }
443 
444 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
445                                     sPAPRMachineState *spapr,
446                                     uint32_t token, uint32_t nargs,
447                                     target_ulong args, uint32_t nret,
448                                     target_ulong rets)
449 {
450     sPAPRPHBState *sphb;
451     uint32_t addr, option;
452     uint64_t buid;
453     int ret;
454 
455     if ((nargs != 4) || (nret != 1)) {
456         goto param_error_exit;
457     }
458 
459     buid = rtas_ldq(args, 1);
460     addr = rtas_ld(args, 0);
461     option = rtas_ld(args, 3);
462 
463     sphb = spapr_pci_find_phb(spapr, buid);
464     if (!sphb) {
465         goto param_error_exit;
466     }
467 
468     if (!spapr_phb_eeh_available(sphb)) {
469         goto param_error_exit;
470     }
471 
472     ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option);
473     rtas_st(rets, 0, ret);
474     return;
475 
476 param_error_exit:
477     rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
478 }
479 
480 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
481                                            sPAPRMachineState *spapr,
482                                            uint32_t token, uint32_t nargs,
483                                            target_ulong args, uint32_t nret,
484                                            target_ulong rets)
485 {
486     sPAPRPHBState *sphb;
487     PCIDevice *pdev;
488     uint32_t addr, option;
489     uint64_t buid;
490 
491     if ((nargs != 4) || (nret != 2)) {
492         goto param_error_exit;
493     }
494 
495     buid = rtas_ldq(args, 1);
496     sphb = spapr_pci_find_phb(spapr, buid);
497     if (!sphb) {
498         goto param_error_exit;
499     }
500 
501     if (!spapr_phb_eeh_available(sphb)) {
502         goto param_error_exit;
503     }
504 
505     /*
506      * We always have PE address of form "00BB0001". "BB"
507      * represents the bus number of PE's primary bus.
508      */
509     option = rtas_ld(args, 3);
510     switch (option) {
511     case RTAS_GET_PE_ADDR:
512         addr = rtas_ld(args, 0);
513         pdev = spapr_pci_find_dev(spapr, buid, addr);
514         if (!pdev) {
515             goto param_error_exit;
516         }
517 
518         rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1);
519         break;
520     case RTAS_GET_PE_MODE:
521         rtas_st(rets, 1, RTAS_PE_MODE_SHARED);
522         break;
523     default:
524         goto param_error_exit;
525     }
526 
527     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
528     return;
529 
530 param_error_exit:
531     rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
532 }
533 
534 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
535                                             sPAPRMachineState *spapr,
536                                             uint32_t token, uint32_t nargs,
537                                             target_ulong args, uint32_t nret,
538                                             target_ulong rets)
539 {
540     sPAPRPHBState *sphb;
541     uint64_t buid;
542     int state, ret;
543 
544     if ((nargs != 3) || (nret != 4 && nret != 5)) {
545         goto param_error_exit;
546     }
547 
548     buid = rtas_ldq(args, 1);
549     sphb = spapr_pci_find_phb(spapr, buid);
550     if (!sphb) {
551         goto param_error_exit;
552     }
553 
554     if (!spapr_phb_eeh_available(sphb)) {
555         goto param_error_exit;
556     }
557 
558     ret = spapr_phb_vfio_eeh_get_state(sphb, &state);
559     rtas_st(rets, 0, ret);
560     if (ret != RTAS_OUT_SUCCESS) {
561         return;
562     }
563 
564     rtas_st(rets, 1, state);
565     rtas_st(rets, 2, RTAS_EEH_SUPPORT);
566     rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO);
567     if (nret >= 5) {
568         rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO);
569     }
570     return;
571 
572 param_error_exit:
573     rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
574 }
575 
576 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
577                                     sPAPRMachineState *spapr,
578                                     uint32_t token, uint32_t nargs,
579                                     target_ulong args, uint32_t nret,
580                                     target_ulong rets)
581 {
582     sPAPRPHBState *sphb;
583     uint32_t option;
584     uint64_t buid;
585     int ret;
586 
587     if ((nargs != 4) || (nret != 1)) {
588         goto param_error_exit;
589     }
590 
591     buid = rtas_ldq(args, 1);
592     option = rtas_ld(args, 3);
593     sphb = spapr_pci_find_phb(spapr, buid);
594     if (!sphb) {
595         goto param_error_exit;
596     }
597 
598     if (!spapr_phb_eeh_available(sphb)) {
599         goto param_error_exit;
600     }
601 
602     ret = spapr_phb_vfio_eeh_reset(sphb, option);
603     rtas_st(rets, 0, ret);
604     return;
605 
606 param_error_exit:
607     rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
608 }
609 
610 static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
611                                   sPAPRMachineState *spapr,
612                                   uint32_t token, uint32_t nargs,
613                                   target_ulong args, uint32_t nret,
614                                   target_ulong rets)
615 {
616     sPAPRPHBState *sphb;
617     uint64_t buid;
618     int ret;
619 
620     if ((nargs != 3) || (nret != 1)) {
621         goto param_error_exit;
622     }
623 
624     buid = rtas_ldq(args, 1);
625     sphb = spapr_pci_find_phb(spapr, buid);
626     if (!sphb) {
627         goto param_error_exit;
628     }
629 
630     if (!spapr_phb_eeh_available(sphb)) {
631         goto param_error_exit;
632     }
633 
634     ret = spapr_phb_vfio_eeh_configure(sphb);
635     rtas_st(rets, 0, ret);
636     return;
637 
638 param_error_exit:
639     rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
640 }
641 
642 /* To support it later */
643 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
644                                        sPAPRMachineState *spapr,
645                                        uint32_t token, uint32_t nargs,
646                                        target_ulong args, uint32_t nret,
647                                        target_ulong rets)
648 {
649     sPAPRPHBState *sphb;
650     int option;
651     uint64_t buid;
652 
653     if ((nargs != 8) || (nret != 1)) {
654         goto param_error_exit;
655     }
656 
657     buid = rtas_ldq(args, 1);
658     sphb = spapr_pci_find_phb(spapr, buid);
659     if (!sphb) {
660         goto param_error_exit;
661     }
662 
663     if (!spapr_phb_eeh_available(sphb)) {
664         goto param_error_exit;
665     }
666 
667     option = rtas_ld(args, 7);
668     switch (option) {
669     case RTAS_SLOT_TEMP_ERR_LOG:
670     case RTAS_SLOT_PERM_ERR_LOG:
671         break;
672     default:
673         goto param_error_exit;
674     }
675 
676     /* We don't have error log yet */
677     rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
678     return;
679 
680 param_error_exit:
681     rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
682 }
683 
684 static int pci_spapr_swizzle(int slot, int pin)
685 {
686     return (slot + pin) % PCI_NUM_PINS;
687 }
688 
689 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
690 {
691     /*
692      * Here we need to convert pci_dev + irq_num to some unique value
693      * which is less than number of IRQs on the specific bus (4).  We
694      * use standard PCI swizzling, that is (slot number + pin number)
695      * % 4.
696      */
697     return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num);
698 }
699 
700 static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
701 {
702     /*
703      * Here we use the number returned by pci_spapr_map_irq to find a
704      * corresponding qemu_irq.
705      */
706     sPAPRPHBState *phb = opaque;
707 
708     trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq);
709     qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
710 }
711 
712 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin)
713 {
714     sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque);
715     PCIINTxRoute route;
716 
717     route.mode = PCI_INTX_ENABLED;
718     route.irq = sphb->lsi_table[pin].irq;
719 
720     return route;
721 }
722 
723 /*
724  * MSI/MSIX memory region implementation.
725  * The handler handles both MSI and MSIX.
726  * The vector number is encoded in least bits in data.
727  */
728 static void spapr_msi_write(void *opaque, hwaddr addr,
729                             uint64_t data, unsigned size)
730 {
731     sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
732     uint32_t irq = data;
733 
734     trace_spapr_pci_msi_write(addr, data, irq);
735 
736     qemu_irq_pulse(xics_get_qirq(XICS_FABRIC(spapr), irq));
737 }
738 
739 static const MemoryRegionOps spapr_msi_ops = {
740     /* There is no .read as the read result is undefined by PCI spec */
741     .read = NULL,
742     .write = spapr_msi_write,
743     .endianness = DEVICE_LITTLE_ENDIAN
744 };
745 
746 /*
747  * PHB PCI device
748  */
749 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
750 {
751     sPAPRPHBState *phb = opaque;
752 
753     return &phb->iommu_as;
754 }
755 
756 static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState *sphb,  PCIDevice *pdev)
757 {
758     char *path = NULL, *buf = NULL, *host = NULL;
759 
760     /* Get the PCI VFIO host id */
761     host = object_property_get_str(OBJECT(pdev), "host", NULL);
762     if (!host) {
763         goto err_out;
764     }
765 
766     /* Construct the path of the file that will give us the DT location */
767     path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host);
768     g_free(host);
769     if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) {
770         goto err_out;
771     }
772     g_free(path);
773 
774     /* Construct and read from host device tree the loc-code */
775     path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf);
776     g_free(buf);
777     if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) {
778         goto err_out;
779     }
780     return buf;
781 
782 err_out:
783     g_free(path);
784     return NULL;
785 }
786 
787 static char *spapr_phb_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev)
788 {
789     char *buf;
790     const char *devtype = "qemu";
791     uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
792 
793     if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
794         buf = spapr_phb_vfio_get_loc_code(sphb, pdev);
795         if (buf) {
796             return buf;
797         }
798         devtype = "vfio";
799     }
800     /*
801      * For emulated devices and VFIO-failure case, make up
802      * the loc-code.
803      */
804     buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
805                           devtype, pdev->name, sphb->index, busnr,
806                           PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
807     return buf;
808 }
809 
810 /* Macros to operate with address in OF binding to PCI */
811 #define b_x(x, p, l)    (((x) & ((1<<(l))-1)) << (p))
812 #define b_n(x)          b_x((x), 31, 1) /* 0 if relocatable */
813 #define b_p(x)          b_x((x), 30, 1) /* 1 if prefetchable */
814 #define b_t(x)          b_x((x), 29, 1) /* 1 if the address is aliased */
815 #define b_ss(x)         b_x((x), 24, 2) /* the space code */
816 #define b_bbbbbbbb(x)   b_x((x), 16, 8) /* bus number */
817 #define b_ddddd(x)      b_x((x), 11, 5) /* device number */
818 #define b_fff(x)        b_x((x), 8, 3)  /* function number */
819 #define b_rrrrrrrr(x)   b_x((x), 0, 8)  /* register number */
820 
821 /* for 'reg'/'assigned-addresses' OF properties */
822 #define RESOURCE_CELLS_SIZE 2
823 #define RESOURCE_CELLS_ADDRESS 3
824 
825 typedef struct ResourceFields {
826     uint32_t phys_hi;
827     uint32_t phys_mid;
828     uint32_t phys_lo;
829     uint32_t size_hi;
830     uint32_t size_lo;
831 } QEMU_PACKED ResourceFields;
832 
833 typedef struct ResourceProps {
834     ResourceFields reg[8];
835     ResourceFields assigned[7];
836     uint32_t reg_len;
837     uint32_t assigned_len;
838 } ResourceProps;
839 
840 /* fill in the 'reg'/'assigned-resources' OF properties for
841  * a PCI device. 'reg' describes resource requirements for a
842  * device's IO/MEM regions, 'assigned-addresses' describes the
843  * actual resource assignments.
844  *
845  * the properties are arrays of ('phys-addr', 'size') pairs describing
846  * the addressable regions of the PCI device, where 'phys-addr' is a
847  * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to
848  * (phys.hi, phys.mid, phys.lo), and 'size' is a
849  * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo).
850  *
851  * phys.hi = 0xYYXXXXZZ, where:
852  *   0xYY = npt000ss
853  *          |||   |
854  *          |||   +-- space code
855  *          |||               |
856  *          |||               +  00 if configuration space
857  *          |||               +  01 if IO region,
858  *          |||               +  10 if 32-bit MEM region
859  *          |||               +  11 if 64-bit MEM region
860  *          |||
861  *          ||+------ for non-relocatable IO: 1 if aliased
862  *          ||        for relocatable IO: 1 if below 64KB
863  *          ||        for MEM: 1 if below 1MB
864  *          |+------- 1 if region is prefetchable
865  *          +-------- 1 if region is non-relocatable
866  *   0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function
867  *            bits respectively
868  *   0xZZ = rrrrrrrr, the register number of the BAR corresponding
869  *          to the region
870  *
871  * phys.mid and phys.lo correspond respectively to the hi/lo portions
872  * of the actual address of the region.
873  *
874  * how the phys-addr/size values are used differ slightly between
875  * 'reg' and 'assigned-addresses' properties. namely, 'reg' has
876  * an additional description for the config space region of the
877  * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0
878  * to describe the region as relocatable, with an address-mapping
879  * that corresponds directly to the PHB's address space for the
880  * resource. 'assigned-addresses' always has n=1 set with an absolute
881  * address assigned for the resource. in general, 'assigned-addresses'
882  * won't be populated, since addresses for PCI devices are generally
883  * unmapped initially and left to the guest to assign.
884  *
885  * note also that addresses defined in these properties are, at least
886  * for PAPR guests, relative to the PHBs IO/MEM windows, and
887  * correspond directly to the addresses in the BARs.
888  *
889  * in accordance with PCI Bus Binding to Open Firmware,
890  * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7,
891  * Appendix C.
892  */
893 static void populate_resource_props(PCIDevice *d, ResourceProps *rp)
894 {
895     int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d))));
896     uint32_t dev_id = (b_bbbbbbbb(bus_num) |
897                        b_ddddd(PCI_SLOT(d->devfn)) |
898                        b_fff(PCI_FUNC(d->devfn)));
899     ResourceFields *reg, *assigned;
900     int i, reg_idx = 0, assigned_idx = 0;
901 
902     /* config space region */
903     reg = &rp->reg[reg_idx++];
904     reg->phys_hi = cpu_to_be32(dev_id);
905     reg->phys_mid = 0;
906     reg->phys_lo = 0;
907     reg->size_hi = 0;
908     reg->size_lo = 0;
909 
910     for (i = 0; i < PCI_NUM_REGIONS; i++) {
911         if (!d->io_regions[i].size) {
912             continue;
913         }
914 
915         reg = &rp->reg[reg_idx++];
916 
917         reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i)));
918         if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
919             reg->phys_hi |= cpu_to_be32(b_ss(1));
920         } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
921             reg->phys_hi |= cpu_to_be32(b_ss(3));
922         } else {
923             reg->phys_hi |= cpu_to_be32(b_ss(2));
924         }
925         reg->phys_mid = 0;
926         reg->phys_lo = 0;
927         reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32);
928         reg->size_lo = cpu_to_be32(d->io_regions[i].size);
929 
930         if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) {
931             continue;
932         }
933 
934         assigned = &rp->assigned[assigned_idx++];
935         assigned->phys_hi = cpu_to_be32(reg->phys_hi | b_n(1));
936         assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32);
937         assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr);
938         assigned->size_hi = reg->size_hi;
939         assigned->size_lo = reg->size_lo;
940     }
941 
942     rp->reg_len = reg_idx * sizeof(ResourceFields);
943     rp->assigned_len = assigned_idx * sizeof(ResourceFields);
944 }
945 
946 typedef struct PCIClass PCIClass;
947 typedef struct PCISubClass PCISubClass;
948 typedef struct PCIIFace PCIIFace;
949 
950 struct PCIIFace {
951     int iface;
952     const char *name;
953 };
954 
955 struct PCISubClass {
956     int subclass;
957     const char *name;
958     const PCIIFace *iface;
959 };
960 
961 struct PCIClass {
962     const char *name;
963     const PCISubClass *subc;
964 };
965 
966 static const PCISubClass undef_subclass[] = {
967     { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL },
968     { 0xFF, NULL, NULL },
969 };
970 
971 static const PCISubClass mass_subclass[] = {
972     { PCI_CLASS_STORAGE_SCSI, "scsi", NULL },
973     { PCI_CLASS_STORAGE_IDE, "ide", NULL },
974     { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL },
975     { PCI_CLASS_STORAGE_IPI, "ipi", NULL },
976     { PCI_CLASS_STORAGE_RAID, "raid", NULL },
977     { PCI_CLASS_STORAGE_ATA, "ata", NULL },
978     { PCI_CLASS_STORAGE_SATA, "sata", NULL },
979     { PCI_CLASS_STORAGE_SAS, "sas", NULL },
980     { 0xFF, NULL, NULL },
981 };
982 
983 static const PCISubClass net_subclass[] = {
984     { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL },
985     { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL },
986     { PCI_CLASS_NETWORK_FDDI, "fddi", NULL },
987     { PCI_CLASS_NETWORK_ATM, "atm", NULL },
988     { PCI_CLASS_NETWORK_ISDN, "isdn", NULL },
989     { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL },
990     { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL },
991     { 0xFF, NULL, NULL },
992 };
993 
994 static const PCISubClass displ_subclass[] = {
995     { PCI_CLASS_DISPLAY_VGA, "vga", NULL },
996     { PCI_CLASS_DISPLAY_XGA, "xga", NULL },
997     { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL },
998     { 0xFF, NULL, NULL },
999 };
1000 
1001 static const PCISubClass media_subclass[] = {
1002     { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL },
1003     { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL },
1004     { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL },
1005     { 0xFF, NULL, NULL },
1006 };
1007 
1008 static const PCISubClass mem_subclass[] = {
1009     { PCI_CLASS_MEMORY_RAM, "memory", NULL },
1010     { PCI_CLASS_MEMORY_FLASH, "flash", NULL },
1011     { 0xFF, NULL, NULL },
1012 };
1013 
1014 static const PCISubClass bridg_subclass[] = {
1015     { PCI_CLASS_BRIDGE_HOST, "host", NULL },
1016     { PCI_CLASS_BRIDGE_ISA, "isa", NULL },
1017     { PCI_CLASS_BRIDGE_EISA, "eisa", NULL },
1018     { PCI_CLASS_BRIDGE_MC, "mca", NULL },
1019     { PCI_CLASS_BRIDGE_PCI, "pci", NULL },
1020     { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL },
1021     { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL },
1022     { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL },
1023     { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL },
1024     { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL },
1025     { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL },
1026     { 0xFF, NULL, NULL },
1027 };
1028 
1029 static const PCISubClass comm_subclass[] = {
1030     { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL },
1031     { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL },
1032     { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL },
1033     { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL },
1034     { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL },
1035     { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL },
1036     { 0xFF, NULL, NULL, },
1037 };
1038 
1039 static const PCIIFace pic_iface[] = {
1040     { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" },
1041     { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" },
1042     { 0xFF, NULL },
1043 };
1044 
1045 static const PCISubClass sys_subclass[] = {
1046     { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface },
1047     { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL },
1048     { PCI_CLASS_SYSTEM_TIMER, "timer", NULL },
1049     { PCI_CLASS_SYSTEM_RTC, "rtc", NULL },
1050     { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL },
1051     { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL },
1052     { 0xFF, NULL, NULL },
1053 };
1054 
1055 static const PCISubClass inp_subclass[] = {
1056     { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL },
1057     { PCI_CLASS_INPUT_PEN, "pen", NULL },
1058     { PCI_CLASS_INPUT_MOUSE, "mouse", NULL },
1059     { PCI_CLASS_INPUT_SCANNER, "scanner", NULL },
1060     { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL },
1061     { 0xFF, NULL, NULL },
1062 };
1063 
1064 static const PCISubClass dock_subclass[] = {
1065     { PCI_CLASS_DOCKING_GENERIC, "dock", NULL },
1066     { 0xFF, NULL, NULL },
1067 };
1068 
1069 static const PCISubClass cpu_subclass[] = {
1070     { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL },
1071     { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL },
1072     { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL },
1073     { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL },
1074     { 0xFF, NULL, NULL },
1075 };
1076 
1077 static const PCIIFace usb_iface[] = {
1078     { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" },
1079     { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", },
1080     { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" },
1081     { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" },
1082     { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" },
1083     { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" },
1084     { 0xFF, NULL },
1085 };
1086 
1087 static const PCISubClass ser_subclass[] = {
1088     { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL },
1089     { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL },
1090     { PCI_CLASS_SERIAL_SSA, "ssa", NULL },
1091     { PCI_CLASS_SERIAL_USB, "usb", usb_iface },
1092     { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL },
1093     { PCI_CLASS_SERIAL_SMBUS, "smb", NULL },
1094     { PCI_CLASS_SERIAL_IB, "infiniband", NULL },
1095     { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL },
1096     { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL },
1097     { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL },
1098     { 0xFF, NULL, NULL },
1099 };
1100 
1101 static const PCISubClass wrl_subclass[] = {
1102     { PCI_CLASS_WIRELESS_IRDA, "irda", NULL },
1103     { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL },
1104     { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL },
1105     { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL },
1106     { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL },
1107     { 0xFF, NULL, NULL },
1108 };
1109 
1110 static const PCISubClass sat_subclass[] = {
1111     { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL },
1112     { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL },
1113     { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL },
1114     { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL },
1115     { 0xFF, NULL, NULL },
1116 };
1117 
1118 static const PCISubClass crypt_subclass[] = {
1119     { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL },
1120     { PCI_CLASS_CRYPT_ENTERTAINMENT,
1121       "entertainment-encryption", NULL },
1122     { 0xFF, NULL, NULL },
1123 };
1124 
1125 static const PCISubClass spc_subclass[] = {
1126     { PCI_CLASS_SP_DPIO, "dpio", NULL },
1127     { PCI_CLASS_SP_PERF, "counter", NULL },
1128     { PCI_CLASS_SP_SYNCH, "measurement", NULL },
1129     { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL },
1130     { 0xFF, NULL, NULL },
1131 };
1132 
1133 static const PCIClass pci_classes[] = {
1134     { "legacy-device", undef_subclass },
1135     { "mass-storage",  mass_subclass },
1136     { "network", net_subclass },
1137     { "display", displ_subclass, },
1138     { "multimedia-device", media_subclass },
1139     { "memory-controller", mem_subclass },
1140     { "unknown-bridge", bridg_subclass },
1141     { "communication-controller", comm_subclass},
1142     { "system-peripheral", sys_subclass },
1143     { "input-controller", inp_subclass },
1144     { "docking-station", dock_subclass },
1145     { "cpu", cpu_subclass },
1146     { "serial-bus", ser_subclass },
1147     { "wireless-controller", wrl_subclass },
1148     { "intelligent-io", NULL },
1149     { "satellite-device", sat_subclass },
1150     { "encryption", crypt_subclass },
1151     { "data-processing-controller", spc_subclass },
1152 };
1153 
1154 static const char *pci_find_device_name(uint8_t class, uint8_t subclass,
1155                                         uint8_t iface)
1156 {
1157     const PCIClass *pclass;
1158     const PCISubClass *psubclass;
1159     const PCIIFace *piface;
1160     const char *name;
1161 
1162     if (class >= ARRAY_SIZE(pci_classes)) {
1163         return "pci";
1164     }
1165 
1166     pclass = pci_classes + class;
1167     name = pclass->name;
1168 
1169     if (pclass->subc == NULL) {
1170         return name;
1171     }
1172 
1173     psubclass = pclass->subc;
1174     while ((psubclass->subclass & 0xff) != 0xff) {
1175         if ((psubclass->subclass & 0xff) == subclass) {
1176             name = psubclass->name;
1177             break;
1178         }
1179         psubclass++;
1180     }
1181 
1182     piface = psubclass->iface;
1183     if (piface == NULL) {
1184         return name;
1185     }
1186     while ((piface->iface & 0xff) != 0xff) {
1187         if ((piface->iface & 0xff) == iface) {
1188             name = piface->name;
1189             break;
1190         }
1191         piface++;
1192     }
1193 
1194     return name;
1195 }
1196 
1197 static void pci_get_node_name(char *nodename, int len, PCIDevice *dev)
1198 {
1199     int slot = PCI_SLOT(dev->devfn);
1200     int func = PCI_FUNC(dev->devfn);
1201     uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1202     const char *name;
1203 
1204     name = pci_find_device_name((ccode >> 16) & 0xff, (ccode >> 8) & 0xff,
1205                                 ccode & 0xff);
1206 
1207     if (func != 0) {
1208         snprintf(nodename, len, "%s@%x,%x", name, slot, func);
1209     } else {
1210         snprintf(nodename, len, "%s@%x", name, slot);
1211     }
1212 }
1213 
1214 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb,
1215                                             PCIDevice *pdev);
1216 
1217 static int spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset,
1218                                        sPAPRPHBState *sphb)
1219 {
1220     ResourceProps rp;
1221     bool is_bridge = false;
1222     int pci_status, err;
1223     char *buf = NULL;
1224     uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev);
1225     uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1226     uint32_t max_msi, max_msix;
1227 
1228     if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) ==
1229         PCI_HEADER_TYPE_BRIDGE) {
1230         is_bridge = true;
1231     }
1232 
1233     /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */
1234     _FDT(fdt_setprop_cell(fdt, offset, "vendor-id",
1235                           pci_default_read_config(dev, PCI_VENDOR_ID, 2)));
1236     _FDT(fdt_setprop_cell(fdt, offset, "device-id",
1237                           pci_default_read_config(dev, PCI_DEVICE_ID, 2)));
1238     _FDT(fdt_setprop_cell(fdt, offset, "revision-id",
1239                           pci_default_read_config(dev, PCI_REVISION_ID, 1)));
1240     _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode));
1241     if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) {
1242         _FDT(fdt_setprop_cell(fdt, offset, "interrupts",
1243                  pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)));
1244     }
1245 
1246     if (!is_bridge) {
1247         _FDT(fdt_setprop_cell(fdt, offset, "min-grant",
1248             pci_default_read_config(dev, PCI_MIN_GNT, 1)));
1249         _FDT(fdt_setprop_cell(fdt, offset, "max-latency",
1250             pci_default_read_config(dev, PCI_MAX_LAT, 1)));
1251     }
1252 
1253     if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) {
1254         _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id",
1255                  pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)));
1256     }
1257 
1258     if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) {
1259         _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id",
1260                  pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)));
1261     }
1262 
1263     _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size",
1264         pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1)));
1265 
1266     /* the following fdt cells are masked off the pci status register */
1267     pci_status = pci_default_read_config(dev, PCI_STATUS, 2);
1268     _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed",
1269                           PCI_STATUS_DEVSEL_MASK & pci_status));
1270 
1271     if (pci_status & PCI_STATUS_FAST_BACK) {
1272         _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0));
1273     }
1274     if (pci_status & PCI_STATUS_66MHZ) {
1275         _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0));
1276     }
1277     if (pci_status & PCI_STATUS_UDF) {
1278         _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0));
1279     }
1280 
1281     _FDT(fdt_setprop_string(fdt, offset, "name",
1282                             pci_find_device_name((ccode >> 16) & 0xff,
1283                                                  (ccode >> 8) & 0xff,
1284                                                  ccode & 0xff)));
1285     buf = spapr_phb_get_loc_code(sphb, dev);
1286     if (!buf) {
1287         error_report("Failed setting the ibm,loc-code");
1288         return -1;
1289     }
1290 
1291     err = fdt_setprop_string(fdt, offset, "ibm,loc-code", buf);
1292     g_free(buf);
1293     if (err < 0) {
1294         return err;
1295     }
1296 
1297     if (drc_index) {
1298         _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index));
1299     }
1300 
1301     _FDT(fdt_setprop_cell(fdt, offset, "#address-cells",
1302                           RESOURCE_CELLS_ADDRESS));
1303     _FDT(fdt_setprop_cell(fdt, offset, "#size-cells",
1304                           RESOURCE_CELLS_SIZE));
1305 
1306     max_msi = msi_nr_vectors_allocated(dev);
1307     if (max_msi) {
1308         _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi));
1309     }
1310     max_msix = dev->msix_entries_nr;
1311     if (max_msix) {
1312         _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix));
1313     }
1314 
1315     populate_resource_props(dev, &rp);
1316     _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len));
1317     _FDT(fdt_setprop(fdt, offset, "assigned-addresses",
1318                      (uint8_t *)rp.assigned, rp.assigned_len));
1319 
1320     if (sphb->pcie_ecs && pci_is_express(dev)) {
1321         _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1));
1322     }
1323 
1324     return 0;
1325 }
1326 
1327 /* create OF node for pci device and required OF DT properties */
1328 static int spapr_create_pci_child_dt(sPAPRPHBState *phb, PCIDevice *dev,
1329                                      void *fdt, int node_offset)
1330 {
1331     int offset, ret;
1332     char nodename[FDT_NAME_MAX];
1333 
1334     pci_get_node_name(nodename, FDT_NAME_MAX, dev);
1335     offset = fdt_add_subnode(fdt, node_offset, nodename);
1336     ret = spapr_populate_pci_child_dt(dev, fdt, offset, phb);
1337 
1338     g_assert(!ret);
1339     if (ret) {
1340         return 0;
1341     }
1342     return offset;
1343 }
1344 
1345 /* Callback to be called during DRC release. */
1346 void spapr_phb_remove_pci_device_cb(DeviceState *dev)
1347 {
1348     /* some version guests do not wait for completion of a device
1349      * cleanup (generally done asynchronously by the kernel) before
1350      * signaling to QEMU that the device is safe, but instead sleep
1351      * for some 'safe' period of time. unfortunately on a busy host
1352      * this sleep isn't guaranteed to be long enough, resulting in
1353      * bad things like IRQ lines being left asserted during final
1354      * device removal. to deal with this we call reset just prior
1355      * to finalizing the device, which will put the device back into
1356      * an 'idle' state, as the device cleanup code expects.
1357      */
1358     pci_device_reset(PCI_DEVICE(dev));
1359     object_unparent(OBJECT(dev));
1360 }
1361 
1362 static sPAPRDRConnector *spapr_phb_get_pci_func_drc(sPAPRPHBState *phb,
1363                                                     uint32_t busnr,
1364                                                     int32_t devfn)
1365 {
1366     return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI,
1367                            (phb->index << 16) | (busnr << 8) | devfn);
1368 }
1369 
1370 static sPAPRDRConnector *spapr_phb_get_pci_drc(sPAPRPHBState *phb,
1371                                                PCIDevice *pdev)
1372 {
1373     uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
1374     return spapr_phb_get_pci_func_drc(phb, busnr, pdev->devfn);
1375 }
1376 
1377 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb,
1378                                             PCIDevice *pdev)
1379 {
1380     sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev);
1381 
1382     if (!drc) {
1383         return 0;
1384     }
1385 
1386     return spapr_drc_index(drc);
1387 }
1388 
1389 static void spapr_pci_plug(HotplugHandler *plug_handler,
1390                            DeviceState *plugged_dev, Error **errp)
1391 {
1392     sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1393     PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1394     sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev);
1395     Error *local_err = NULL;
1396     PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1397     uint32_t slotnr = PCI_SLOT(pdev->devfn);
1398     void *fdt = NULL;
1399     int fdt_start_offset, fdt_size;
1400 
1401     /* if DR is disabled we don't need to do anything in the case of
1402      * hotplug or coldplug callbacks
1403      */
1404     if (!phb->dr_enabled) {
1405         /* if this is a hotplug operation initiated by the user
1406          * we need to let them know it's not enabled
1407          */
1408         if (plugged_dev->hotplugged) {
1409             error_setg(&local_err, QERR_BUS_NO_HOTPLUG,
1410                        object_get_typename(OBJECT(phb)));
1411         }
1412         goto out;
1413     }
1414 
1415     g_assert(drc);
1416 
1417     /* Following the QEMU convention used for PCIe multifunction
1418      * hotplug, we do not allow functions to be hotplugged to a
1419      * slot that already has function 0 present
1420      */
1421     if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] &&
1422         PCI_FUNC(pdev->devfn) != 0) {
1423         error_setg(&local_err, "PCI: slot %d function 0 already ocuppied by %s,"
1424                    " additional functions can no longer be exposed to guest.",
1425                    slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name);
1426         goto out;
1427     }
1428 
1429     fdt = create_device_tree(&fdt_size);
1430     fdt_start_offset = spapr_create_pci_child_dt(phb, pdev, fdt, 0);
1431     if (!fdt_start_offset) {
1432         error_setg(&local_err, "Failed to create pci child device tree node");
1433         goto out;
1434     }
1435 
1436     spapr_drc_attach(drc, DEVICE(pdev), fdt, fdt_start_offset, &local_err);
1437     if (local_err) {
1438         goto out;
1439     }
1440 
1441     /* If this is function 0, signal hotplug for all the device functions.
1442      * Otherwise defer sending the hotplug event.
1443      */
1444     if (!spapr_drc_hotplugged(plugged_dev)) {
1445         spapr_drc_reset(drc);
1446     } else if (PCI_FUNC(pdev->devfn) == 0) {
1447         int i;
1448 
1449         for (i = 0; i < 8; i++) {
1450             sPAPRDRConnector *func_drc;
1451             sPAPRDRConnectorClass *func_drck;
1452             sPAPRDREntitySense state;
1453 
1454             func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1455                                                   PCI_DEVFN(slotnr, i));
1456             func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1457             state = func_drck->dr_entity_sense(func_drc);
1458 
1459             if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1460                 spapr_hotplug_req_add_by_index(func_drc);
1461             }
1462         }
1463     }
1464 
1465 out:
1466     if (local_err) {
1467         error_propagate(errp, local_err);
1468         g_free(fdt);
1469     }
1470 }
1471 
1472 static void spapr_pci_unplug_request(HotplugHandler *plug_handler,
1473                                      DeviceState *plugged_dev, Error **errp)
1474 {
1475     sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1476     PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1477     sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev);
1478 
1479     if (!phb->dr_enabled) {
1480         error_setg(errp, QERR_BUS_NO_HOTPLUG,
1481                    object_get_typename(OBJECT(phb)));
1482         return;
1483     }
1484 
1485     g_assert(drc);
1486     g_assert(drc->dev == plugged_dev);
1487 
1488     if (!spapr_drc_unplug_requested(drc)) {
1489         PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1490         uint32_t slotnr = PCI_SLOT(pdev->devfn);
1491         sPAPRDRConnector *func_drc;
1492         sPAPRDRConnectorClass *func_drck;
1493         sPAPRDREntitySense state;
1494         int i;
1495 
1496         /* ensure any other present functions are pending unplug */
1497         if (PCI_FUNC(pdev->devfn) == 0) {
1498             for (i = 1; i < 8; i++) {
1499                 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1500                                                       PCI_DEVFN(slotnr, i));
1501                 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1502                 state = func_drck->dr_entity_sense(func_drc);
1503                 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT
1504                     && !spapr_drc_unplug_requested(func_drc)) {
1505                     error_setg(errp,
1506                                "PCI: slot %d, function %d still present. "
1507                                "Must unplug all non-0 functions first.",
1508                                slotnr, i);
1509                     return;
1510                 }
1511             }
1512         }
1513 
1514         spapr_drc_detach(drc);
1515 
1516         /* if this isn't func 0, defer unplug event. otherwise signal removal
1517          * for all present functions
1518          */
1519         if (PCI_FUNC(pdev->devfn) == 0) {
1520             for (i = 7; i >= 0; i--) {
1521                 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1522                                                       PCI_DEVFN(slotnr, i));
1523                 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1524                 state = func_drck->dr_entity_sense(func_drc);
1525                 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1526                     spapr_hotplug_req_remove_by_index(func_drc);
1527                 }
1528             }
1529         }
1530     }
1531 }
1532 
1533 static void spapr_phb_realize(DeviceState *dev, Error **errp)
1534 {
1535     sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1536     SysBusDevice *s = SYS_BUS_DEVICE(dev);
1537     sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
1538     PCIHostState *phb = PCI_HOST_BRIDGE(s);
1539     char *namebuf;
1540     int i;
1541     PCIBus *bus;
1542     uint64_t msi_window_size = 4096;
1543     sPAPRTCETable *tcet;
1544     const unsigned windows_supported =
1545         sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1;
1546 
1547     if (sphb->index != (uint32_t)-1) {
1548         sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
1549         Error *local_err = NULL;
1550 
1551         if ((sphb->buid != (uint64_t)-1) || (sphb->dma_liobn[0] != (uint32_t)-1)
1552             || (sphb->dma_liobn[1] != (uint32_t)-1 && windows_supported == 2)
1553             || (sphb->mem_win_addr != (hwaddr)-1)
1554             || (sphb->mem64_win_addr != (hwaddr)-1)
1555             || (sphb->io_win_addr != (hwaddr)-1)) {
1556             error_setg(errp, "Either \"index\" or other parameters must"
1557                        " be specified for PAPR PHB, not both");
1558             return;
1559         }
1560 
1561         smc->phb_placement(spapr, sphb->index,
1562                            &sphb->buid, &sphb->io_win_addr,
1563                            &sphb->mem_win_addr, &sphb->mem64_win_addr,
1564                            windows_supported, sphb->dma_liobn, &local_err);
1565         if (local_err) {
1566             error_propagate(errp, local_err);
1567             return;
1568         }
1569     }
1570 
1571     if (sphb->buid == (uint64_t)-1) {
1572         error_setg(errp, "BUID not specified for PHB");
1573         return;
1574     }
1575 
1576     if ((sphb->dma_liobn[0] == (uint32_t)-1) ||
1577         ((sphb->dma_liobn[1] == (uint32_t)-1) && (windows_supported > 1))) {
1578         error_setg(errp, "LIOBN(s) not specified for PHB");
1579         return;
1580     }
1581 
1582     if (sphb->mem_win_addr == (hwaddr)-1) {
1583         error_setg(errp, "Memory window address not specified for PHB");
1584         return;
1585     }
1586 
1587     if (sphb->io_win_addr == (hwaddr)-1) {
1588         error_setg(errp, "IO window address not specified for PHB");
1589         return;
1590     }
1591 
1592     if (sphb->mem64_win_size != 0) {
1593         if (sphb->mem64_win_addr == (hwaddr)-1) {
1594             error_setg(errp,
1595                        "64-bit memory window address not specified for PHB");
1596             return;
1597         }
1598 
1599         if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1600             error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx
1601                        " (max 2 GiB)", sphb->mem_win_size);
1602             return;
1603         }
1604 
1605         if (sphb->mem64_win_pciaddr == (hwaddr)-1) {
1606             /* 64-bit window defaults to identity mapping */
1607             sphb->mem64_win_pciaddr = sphb->mem64_win_addr;
1608         }
1609     } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1610         /*
1611          * For compatibility with old configuration, if no 64-bit MMIO
1612          * window is specified, but the ordinary (32-bit) memory
1613          * window is specified as > 2GiB, we treat it as a 2GiB 32-bit
1614          * window, with a 64-bit MMIO window following on immediately
1615          * afterwards
1616          */
1617         sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE;
1618         sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE;
1619         sphb->mem64_win_pciaddr =
1620             SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE;
1621         sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE;
1622     }
1623 
1624     if (spapr_pci_find_phb(spapr, sphb->buid)) {
1625         error_setg(errp, "PCI host bridges must have unique BUIDs");
1626         return;
1627     }
1628 
1629     if (sphb->numa_node != -1 &&
1630         (sphb->numa_node >= MAX_NODES || !numa_info[sphb->numa_node].present)) {
1631         error_setg(errp, "Invalid NUMA node ID for PCI host bridge");
1632         return;
1633     }
1634 
1635     sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
1636 
1637     namebuf = alloca(strlen(sphb->dtbusname) + 32);
1638 
1639     /* Initialize memory regions */
1640     sprintf(namebuf, "%s.mmio", sphb->dtbusname);
1641     memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX);
1642 
1643     sprintf(namebuf, "%s.mmio32-alias", sphb->dtbusname);
1644     memory_region_init_alias(&sphb->mem32window, OBJECT(sphb),
1645                              namebuf, &sphb->memspace,
1646                              SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
1647     memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
1648                                 &sphb->mem32window);
1649 
1650     sprintf(namebuf, "%s.mmio64-alias", sphb->dtbusname);
1651     memory_region_init_alias(&sphb->mem64window, OBJECT(sphb),
1652                              namebuf, &sphb->memspace,
1653                              sphb->mem64_win_pciaddr, sphb->mem64_win_size);
1654     memory_region_add_subregion(get_system_memory(), sphb->mem64_win_addr,
1655                                 &sphb->mem64window);
1656 
1657     /* Initialize IO regions */
1658     sprintf(namebuf, "%s.io", sphb->dtbusname);
1659     memory_region_init(&sphb->iospace, OBJECT(sphb),
1660                        namebuf, SPAPR_PCI_IO_WIN_SIZE);
1661 
1662     sprintf(namebuf, "%s.io-alias", sphb->dtbusname);
1663     memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf,
1664                              &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE);
1665     memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
1666                                 &sphb->iowindow);
1667 
1668     bus = pci_register_bus(dev, NULL,
1669                            pci_spapr_set_irq, pci_spapr_map_irq, sphb,
1670                            &sphb->memspace, &sphb->iospace,
1671                            PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS);
1672     phb->bus = bus;
1673     qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL);
1674 
1675     /*
1676      * Initialize PHB address space.
1677      * By default there will be at least one subregion for default
1678      * 32bit DMA window.
1679      * Later the guest might want to create another DMA window
1680      * which will become another memory subregion.
1681      */
1682     sprintf(namebuf, "%s.iommu-root", sphb->dtbusname);
1683 
1684     memory_region_init(&sphb->iommu_root, OBJECT(sphb),
1685                        namebuf, UINT64_MAX);
1686     address_space_init(&sphb->iommu_as, &sphb->iommu_root,
1687                        sphb->dtbusname);
1688 
1689     /*
1690      * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
1691      * we need to allocate some memory to catch those writes coming
1692      * from msi_notify()/msix_notify().
1693      * As MSIMessage:addr is going to be the same and MSIMessage:data
1694      * is going to be a VIRQ number, 4 bytes of the MSI MR will only
1695      * be used.
1696      *
1697      * For KVM we want to ensure that this memory is a full page so that
1698      * our memory slot is of page size granularity.
1699      */
1700 #ifdef CONFIG_KVM
1701     if (kvm_enabled()) {
1702         msi_window_size = getpagesize();
1703     }
1704 #endif
1705 
1706     memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr,
1707                           "msi", msi_window_size);
1708     memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW,
1709                                 &sphb->msiwindow);
1710 
1711     pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb);
1712 
1713     pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq);
1714 
1715     QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
1716 
1717     /* Initialize the LSI table */
1718     for (i = 0; i < PCI_NUM_PINS; i++) {
1719         uint32_t irq;
1720         Error *local_err = NULL;
1721 
1722         irq = spapr_ics_alloc_block(spapr->ics, 1, true, false, &local_err);
1723         if (local_err) {
1724             error_propagate(errp, local_err);
1725             error_prepend(errp, "can't allocate LSIs: ");
1726             return;
1727         }
1728 
1729         sphb->lsi_table[i].irq = irq;
1730     }
1731 
1732     /* allocate connectors for child PCI devices */
1733     if (sphb->dr_enabled) {
1734         for (i = 0; i < PCI_SLOT_MAX * 8; i++) {
1735             spapr_dr_connector_new(OBJECT(phb), TYPE_SPAPR_DRC_PCI,
1736                                    (sphb->index << 16) | i);
1737         }
1738     }
1739 
1740     /* DMA setup */
1741     if (((sphb->page_size_mask & qemu_getrampagesize()) == 0)
1742         && kvm_enabled()) {
1743         error_report("System page size 0x%lx is not enabled in page_size_mask "
1744                      "(0x%"PRIx64"). Performance may be slow",
1745                      qemu_getrampagesize(), sphb->page_size_mask);
1746     }
1747 
1748     for (i = 0; i < windows_supported; ++i) {
1749         tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]);
1750         if (!tcet) {
1751             error_setg(errp, "Creating window#%d failed for %s",
1752                        i, sphb->dtbusname);
1753             return;
1754         }
1755         memory_region_add_subregion(&sphb->iommu_root, 0,
1756                                     spapr_tce_get_iommu(tcet));
1757     }
1758 
1759     sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free);
1760 }
1761 
1762 static int spapr_phb_children_reset(Object *child, void *opaque)
1763 {
1764     DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
1765 
1766     if (dev) {
1767         device_reset(dev);
1768     }
1769 
1770     return 0;
1771 }
1772 
1773 void spapr_phb_dma_reset(sPAPRPHBState *sphb)
1774 {
1775     int i;
1776     sPAPRTCETable *tcet;
1777 
1778     for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) {
1779         tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
1780 
1781         if (tcet && tcet->nb_table) {
1782             spapr_tce_table_disable(tcet);
1783         }
1784     }
1785 
1786     /* Register default 32bit DMA window */
1787     tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]);
1788     spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr,
1789                            sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT);
1790 }
1791 
1792 static void spapr_phb_reset(DeviceState *qdev)
1793 {
1794     sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev);
1795 
1796     spapr_phb_dma_reset(sphb);
1797 
1798     /* Reset the IOMMU state */
1799     object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL);
1800 
1801     if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) {
1802         spapr_phb_vfio_reset(qdev);
1803     }
1804 }
1805 
1806 static Property spapr_phb_properties[] = {
1807     DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1),
1808     DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1),
1809     DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn[0], -1),
1810     DEFINE_PROP_UINT32("liobn64", sPAPRPHBState, dma_liobn[1], -1),
1811     DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1),
1812     DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size,
1813                        SPAPR_PCI_MEM32_WIN_SIZE),
1814     DEFINE_PROP_UINT64("mem64_win_addr", sPAPRPHBState, mem64_win_addr, -1),
1815     DEFINE_PROP_UINT64("mem64_win_size", sPAPRPHBState, mem64_win_size,
1816                        SPAPR_PCI_MEM64_WIN_SIZE),
1817     DEFINE_PROP_UINT64("mem64_win_pciaddr", sPAPRPHBState, mem64_win_pciaddr,
1818                        -1),
1819     DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1),
1820     DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size,
1821                        SPAPR_PCI_IO_WIN_SIZE),
1822     DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled,
1823                      true),
1824     /* Default DMA window is 0..1GB */
1825     DEFINE_PROP_UINT64("dma_win_addr", sPAPRPHBState, dma_win_addr, 0),
1826     DEFINE_PROP_UINT64("dma_win_size", sPAPRPHBState, dma_win_size, 0x40000000),
1827     DEFINE_PROP_UINT64("dma64_win_addr", sPAPRPHBState, dma64_win_addr,
1828                        0x800000000000000ULL),
1829     DEFINE_PROP_BOOL("ddw", sPAPRPHBState, ddw_enabled, true),
1830     DEFINE_PROP_UINT64("pgsz", sPAPRPHBState, page_size_mask,
1831                        (1ULL << 12) | (1ULL << 16)),
1832     DEFINE_PROP_UINT32("numa_node", sPAPRPHBState, numa_node, -1),
1833     DEFINE_PROP_BOOL("pre-2.8-migration", sPAPRPHBState,
1834                      pre_2_8_migration, false),
1835     DEFINE_PROP_BOOL("pcie-extended-configuration-space", sPAPRPHBState,
1836                      pcie_ecs, true),
1837     DEFINE_PROP_END_OF_LIST(),
1838 };
1839 
1840 static const VMStateDescription vmstate_spapr_pci_lsi = {
1841     .name = "spapr_pci/lsi",
1842     .version_id = 1,
1843     .minimum_version_id = 1,
1844     .fields = (VMStateField[]) {
1845         VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi, NULL),
1846 
1847         VMSTATE_END_OF_LIST()
1848     },
1849 };
1850 
1851 static const VMStateDescription vmstate_spapr_pci_msi = {
1852     .name = "spapr_pci/msi",
1853     .version_id = 1,
1854     .minimum_version_id = 1,
1855     .fields = (VMStateField []) {
1856         VMSTATE_UINT32(key, spapr_pci_msi_mig),
1857         VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig),
1858         VMSTATE_UINT32(value.num, spapr_pci_msi_mig),
1859         VMSTATE_END_OF_LIST()
1860     },
1861 };
1862 
1863 static void spapr_pci_pre_save(void *opaque)
1864 {
1865     sPAPRPHBState *sphb = opaque;
1866     GHashTableIter iter;
1867     gpointer key, value;
1868     int i;
1869 
1870     if (sphb->pre_2_8_migration) {
1871         sphb->mig_liobn = sphb->dma_liobn[0];
1872         sphb->mig_mem_win_addr = sphb->mem_win_addr;
1873         sphb->mig_mem_win_size = sphb->mem_win_size;
1874         sphb->mig_io_win_addr = sphb->io_win_addr;
1875         sphb->mig_io_win_size = sphb->io_win_size;
1876 
1877         if ((sphb->mem64_win_size != 0)
1878             && (sphb->mem64_win_addr
1879                 == (sphb->mem_win_addr + sphb->mem_win_size))) {
1880             sphb->mig_mem_win_size += sphb->mem64_win_size;
1881         }
1882     }
1883 
1884     g_free(sphb->msi_devs);
1885     sphb->msi_devs = NULL;
1886     sphb->msi_devs_num = g_hash_table_size(sphb->msi);
1887     if (!sphb->msi_devs_num) {
1888         return;
1889     }
1890     sphb->msi_devs = g_malloc(sphb->msi_devs_num * sizeof(spapr_pci_msi_mig));
1891 
1892     g_hash_table_iter_init(&iter, sphb->msi);
1893     for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) {
1894         sphb->msi_devs[i].key = *(uint32_t *) key;
1895         sphb->msi_devs[i].value = *(spapr_pci_msi *) value;
1896     }
1897 }
1898 
1899 static int spapr_pci_post_load(void *opaque, int version_id)
1900 {
1901     sPAPRPHBState *sphb = opaque;
1902     gpointer key, value;
1903     int i;
1904 
1905     for (i = 0; i < sphb->msi_devs_num; ++i) {
1906         key = g_memdup(&sphb->msi_devs[i].key,
1907                        sizeof(sphb->msi_devs[i].key));
1908         value = g_memdup(&sphb->msi_devs[i].value,
1909                          sizeof(sphb->msi_devs[i].value));
1910         g_hash_table_insert(sphb->msi, key, value);
1911     }
1912     g_free(sphb->msi_devs);
1913     sphb->msi_devs = NULL;
1914     sphb->msi_devs_num = 0;
1915 
1916     return 0;
1917 }
1918 
1919 static bool pre_2_8_migration(void *opaque, int version_id)
1920 {
1921     sPAPRPHBState *sphb = opaque;
1922 
1923     return sphb->pre_2_8_migration;
1924 }
1925 
1926 static const VMStateDescription vmstate_spapr_pci = {
1927     .name = "spapr_pci",
1928     .version_id = 2,
1929     .minimum_version_id = 2,
1930     .pre_save = spapr_pci_pre_save,
1931     .post_load = spapr_pci_post_load,
1932     .fields = (VMStateField[]) {
1933         VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState, NULL),
1934         VMSTATE_UINT32_TEST(mig_liobn, sPAPRPHBState, pre_2_8_migration),
1935         VMSTATE_UINT64_TEST(mig_mem_win_addr, sPAPRPHBState, pre_2_8_migration),
1936         VMSTATE_UINT64_TEST(mig_mem_win_size, sPAPRPHBState, pre_2_8_migration),
1937         VMSTATE_UINT64_TEST(mig_io_win_addr, sPAPRPHBState, pre_2_8_migration),
1938         VMSTATE_UINT64_TEST(mig_io_win_size, sPAPRPHBState, pre_2_8_migration),
1939         VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0,
1940                              vmstate_spapr_pci_lsi, struct spapr_pci_lsi),
1941         VMSTATE_INT32(msi_devs_num, sPAPRPHBState),
1942         VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0,
1943                                     vmstate_spapr_pci_msi, spapr_pci_msi_mig),
1944         VMSTATE_END_OF_LIST()
1945     },
1946 };
1947 
1948 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge,
1949                                            PCIBus *rootbus)
1950 {
1951     sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge);
1952 
1953     return sphb->dtbusname;
1954 }
1955 
1956 static void spapr_phb_class_init(ObjectClass *klass, void *data)
1957 {
1958     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
1959     DeviceClass *dc = DEVICE_CLASS(klass);
1960     HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass);
1961 
1962     hc->root_bus_path = spapr_phb_root_bus_path;
1963     dc->realize = spapr_phb_realize;
1964     dc->props = spapr_phb_properties;
1965     dc->reset = spapr_phb_reset;
1966     dc->vmsd = &vmstate_spapr_pci;
1967     /* Supported by TYPE_SPAPR_MACHINE */
1968     dc->user_creatable = true;
1969     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1970     hp->plug = spapr_pci_plug;
1971     hp->unplug_request = spapr_pci_unplug_request;
1972 }
1973 
1974 static const TypeInfo spapr_phb_info = {
1975     .name          = TYPE_SPAPR_PCI_HOST_BRIDGE,
1976     .parent        = TYPE_PCI_HOST_BRIDGE,
1977     .instance_size = sizeof(sPAPRPHBState),
1978     .class_init    = spapr_phb_class_init,
1979     .interfaces    = (InterfaceInfo[]) {
1980         { TYPE_HOTPLUG_HANDLER },
1981         { }
1982     }
1983 };
1984 
1985 PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index)
1986 {
1987     DeviceState *dev;
1988 
1989     dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
1990     qdev_prop_set_uint32(dev, "index", index);
1991     qdev_init_nofail(dev);
1992 
1993     return PCI_HOST_BRIDGE(dev);
1994 }
1995 
1996 typedef struct sPAPRFDT {
1997     void *fdt;
1998     int node_off;
1999     sPAPRPHBState *sphb;
2000 } sPAPRFDT;
2001 
2002 static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev,
2003                                           void *opaque)
2004 {
2005     PCIBus *sec_bus;
2006     sPAPRFDT *p = opaque;
2007     int offset;
2008     sPAPRFDT s_fdt;
2009 
2010     offset = spapr_create_pci_child_dt(p->sphb, pdev, p->fdt, p->node_off);
2011     if (!offset) {
2012         error_report("Failed to create pci child device tree node");
2013         return;
2014     }
2015 
2016     if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
2017          PCI_HEADER_TYPE_BRIDGE)) {
2018         return;
2019     }
2020 
2021     sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
2022     if (!sec_bus) {
2023         return;
2024     }
2025 
2026     s_fdt.fdt = p->fdt;
2027     s_fdt.node_off = offset;
2028     s_fdt.sphb = p->sphb;
2029     pci_for_each_device_reverse(sec_bus, pci_bus_num(sec_bus),
2030                                 spapr_populate_pci_devices_dt,
2031                                 &s_fdt);
2032 }
2033 
2034 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev,
2035                                            void *opaque)
2036 {
2037     unsigned int *bus_no = opaque;
2038     unsigned int primary = *bus_no;
2039     unsigned int subordinate = 0xff;
2040     PCIBus *sec_bus = NULL;
2041 
2042     if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
2043          PCI_HEADER_TYPE_BRIDGE)) {
2044         return;
2045     }
2046 
2047     (*bus_no)++;
2048     pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1);
2049     pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1);
2050     pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2051 
2052     sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
2053     if (!sec_bus) {
2054         return;
2055     }
2056 
2057     pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1);
2058     pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
2059                         spapr_phb_pci_enumerate_bridge, bus_no);
2060     pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2061 }
2062 
2063 static void spapr_phb_pci_enumerate(sPAPRPHBState *phb)
2064 {
2065     PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2066     unsigned int bus_no = 0;
2067 
2068     pci_for_each_device(bus, pci_bus_num(bus),
2069                         spapr_phb_pci_enumerate_bridge,
2070                         &bus_no);
2071 
2072 }
2073 
2074 int spapr_populate_pci_dt(sPAPRPHBState *phb,
2075                           uint32_t xics_phandle,
2076                           void *fdt)
2077 {
2078     int bus_off, i, j, ret;
2079     char nodename[FDT_NAME_MAX];
2080     uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
2081     struct {
2082         uint32_t hi;
2083         uint64_t child;
2084         uint64_t parent;
2085         uint64_t size;
2086     } QEMU_PACKED ranges[] = {
2087         {
2088             cpu_to_be32(b_ss(1)), cpu_to_be64(0),
2089             cpu_to_be64(phb->io_win_addr),
2090             cpu_to_be64(memory_region_size(&phb->iospace)),
2091         },
2092         {
2093             cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
2094             cpu_to_be64(phb->mem_win_addr),
2095             cpu_to_be64(phb->mem_win_size),
2096         },
2097         {
2098             cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr),
2099             cpu_to_be64(phb->mem64_win_addr),
2100             cpu_to_be64(phb->mem64_win_size),
2101         },
2102     };
2103     const unsigned sizeof_ranges =
2104         (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]);
2105     uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
2106     uint32_t interrupt_map_mask[] = {
2107         cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
2108     uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
2109     uint32_t ddw_applicable[] = {
2110         cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW),
2111         cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW),
2112         cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW)
2113     };
2114     uint32_t ddw_extensions[] = {
2115         cpu_to_be32(1),
2116         cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW)
2117     };
2118     uint32_t associativity[] = {cpu_to_be32(0x4),
2119                                 cpu_to_be32(0x0),
2120                                 cpu_to_be32(0x0),
2121                                 cpu_to_be32(0x0),
2122                                 cpu_to_be32(phb->numa_node)};
2123     sPAPRTCETable *tcet;
2124     PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2125     sPAPRFDT s_fdt;
2126 
2127     /* Start populating the FDT */
2128     snprintf(nodename, FDT_NAME_MAX, "pci@%" PRIx64, phb->buid);
2129     bus_off = fdt_add_subnode(fdt, 0, nodename);
2130     if (bus_off < 0) {
2131         return bus_off;
2132     }
2133 
2134     /* Write PHB properties */
2135     _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
2136     _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
2137     _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
2138     _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
2139     _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
2140     _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
2141     _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
2142     _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges));
2143     _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
2144     _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
2145     _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS_SPAPR));
2146 
2147     /* Dynamic DMA window */
2148     if (phb->ddw_enabled) {
2149         _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable,
2150                          sizeof(ddw_applicable)));
2151         _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions",
2152                          &ddw_extensions, sizeof(ddw_extensions)));
2153     }
2154 
2155     /* Advertise NUMA via ibm,associativity */
2156     if (phb->numa_node != -1) {
2157         _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity,
2158                          sizeof(associativity)));
2159     }
2160 
2161     /* Build the interrupt-map, this must matches what is done
2162      * in pci_spapr_map_irq
2163      */
2164     _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
2165                      &interrupt_map_mask, sizeof(interrupt_map_mask)));
2166     for (i = 0; i < PCI_SLOT_MAX; i++) {
2167         for (j = 0; j < PCI_NUM_PINS; j++) {
2168             uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
2169             int lsi_num = pci_spapr_swizzle(i, j);
2170 
2171             irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
2172             irqmap[1] = 0;
2173             irqmap[2] = 0;
2174             irqmap[3] = cpu_to_be32(j+1);
2175             irqmap[4] = cpu_to_be32(xics_phandle);
2176             irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq);
2177             irqmap[6] = cpu_to_be32(0x8);
2178         }
2179     }
2180     /* Write interrupt map */
2181     _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
2182                      sizeof(interrupt_map)));
2183 
2184     tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]);
2185     if (!tcet) {
2186         return -1;
2187     }
2188     spapr_dma_dt(fdt, bus_off, "ibm,dma-window",
2189                  tcet->liobn, tcet->bus_offset,
2190                  tcet->nb_table << tcet->page_shift);
2191 
2192     /* Walk the bridges and program the bus numbers*/
2193     spapr_phb_pci_enumerate(phb);
2194     _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1));
2195 
2196     /* Populate tree nodes with PCI devices attached */
2197     s_fdt.fdt = fdt;
2198     s_fdt.node_off = bus_off;
2199     s_fdt.sphb = phb;
2200     pci_for_each_device_reverse(bus, pci_bus_num(bus),
2201                                 spapr_populate_pci_devices_dt,
2202                                 &s_fdt);
2203 
2204     ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb),
2205                                 SPAPR_DR_CONNECTOR_TYPE_PCI);
2206     if (ret) {
2207         return ret;
2208     }
2209 
2210     return 0;
2211 }
2212 
2213 void spapr_pci_rtas_init(void)
2214 {
2215     spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config",
2216                         rtas_read_pci_config);
2217     spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config",
2218                         rtas_write_pci_config);
2219     spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config",
2220                         rtas_ibm_read_pci_config);
2221     spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config",
2222                         rtas_ibm_write_pci_config);
2223     if (msi_nonbroken) {
2224         spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER,
2225                             "ibm,query-interrupt-source-number",
2226                             rtas_ibm_query_interrupt_source_number);
2227         spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
2228                             rtas_ibm_change_msi);
2229     }
2230 
2231     spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION,
2232                         "ibm,set-eeh-option",
2233                         rtas_ibm_set_eeh_option);
2234     spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2,
2235                         "ibm,get-config-addr-info2",
2236                         rtas_ibm_get_config_addr_info2);
2237     spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2,
2238                         "ibm,read-slot-reset-state2",
2239                         rtas_ibm_read_slot_reset_state2);
2240     spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET,
2241                         "ibm,set-slot-reset",
2242                         rtas_ibm_set_slot_reset);
2243     spapr_rtas_register(RTAS_IBM_CONFIGURE_PE,
2244                         "ibm,configure-pe",
2245                         rtas_ibm_configure_pe);
2246     spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
2247                         "ibm,slot-error-detail",
2248                         rtas_ibm_slot_error_detail);
2249 }
2250 
2251 static void spapr_pci_register_types(void)
2252 {
2253     type_register_static(&spapr_phb_info);
2254 }
2255 
2256 type_init(spapr_pci_register_types)
2257 
2258 static int spapr_switch_one_vga(DeviceState *dev, void *opaque)
2259 {
2260     bool be = *(bool *)opaque;
2261 
2262     if (object_dynamic_cast(OBJECT(dev), "VGA")
2263         || object_dynamic_cast(OBJECT(dev), "secondary-vga")) {
2264         object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer",
2265                                  &error_abort);
2266     }
2267     return 0;
2268 }
2269 
2270 void spapr_pci_switch_vga(bool big_endian)
2271 {
2272     sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
2273     sPAPRPHBState *sphb;
2274 
2275     /*
2276      * For backward compatibility with existing guests, we switch
2277      * the endianness of the VGA controller when changing the guest
2278      * interrupt mode
2279      */
2280     QLIST_FOREACH(sphb, &spapr->phbs, list) {
2281         BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus;
2282         qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL,
2283                            &big_endian);
2284     }
2285 }
2286