1 /* 2 * QEMU sPAPR PCI host originated from Uninorth PCI host 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. 5 * Copyright (C) 2011 David Gibson, IBM Corporation. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/sysbus.h" 28 #include "hw/pci/pci.h" 29 #include "hw/pci/msi.h" 30 #include "hw/pci/msix.h" 31 #include "hw/pci/pci_host.h" 32 #include "hw/ppc/spapr.h" 33 #include "hw/pci-host/spapr.h" 34 #include "exec/address-spaces.h" 35 #include <libfdt.h> 36 #include "trace.h" 37 #include "qemu/error-report.h" 38 #include "qapi/qmp/qerror.h" 39 40 #include "hw/pci/pci_bridge.h" 41 #include "hw/pci/pci_bus.h" 42 #include "hw/ppc/spapr_drc.h" 43 #include "sysemu/device_tree.h" 44 45 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ 46 #define RTAS_QUERY_FN 0 47 #define RTAS_CHANGE_FN 1 48 #define RTAS_RESET_FN 2 49 #define RTAS_CHANGE_MSI_FN 3 50 #define RTAS_CHANGE_MSIX_FN 4 51 52 /* Interrupt types to return on RTAS_CHANGE_* */ 53 #define RTAS_TYPE_MSI 1 54 #define RTAS_TYPE_MSIX 2 55 56 #define FDT_NAME_MAX 128 57 58 #define _FDT(exp) \ 59 do { \ 60 int ret = (exp); \ 61 if (ret < 0) { \ 62 return ret; \ 63 } \ 64 } while (0) 65 66 sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid) 67 { 68 sPAPRPHBState *sphb; 69 70 QLIST_FOREACH(sphb, &spapr->phbs, list) { 71 if (sphb->buid != buid) { 72 continue; 73 } 74 return sphb; 75 } 76 77 return NULL; 78 } 79 80 PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid, 81 uint32_t config_addr) 82 { 83 sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid); 84 PCIHostState *phb = PCI_HOST_BRIDGE(sphb); 85 int bus_num = (config_addr >> 16) & 0xFF; 86 int devfn = (config_addr >> 8) & 0xFF; 87 88 if (!phb) { 89 return NULL; 90 } 91 92 return pci_find_device(phb->bus, bus_num, devfn); 93 } 94 95 static uint32_t rtas_pci_cfgaddr(uint32_t arg) 96 { 97 /* This handles the encoding of extended config space addresses */ 98 return ((arg >> 20) & 0xf00) | (arg & 0xff); 99 } 100 101 static void finish_read_pci_config(sPAPRMachineState *spapr, uint64_t buid, 102 uint32_t addr, uint32_t size, 103 target_ulong rets) 104 { 105 PCIDevice *pci_dev; 106 uint32_t val; 107 108 if ((size != 1) && (size != 2) && (size != 4)) { 109 /* access must be 1, 2 or 4 bytes */ 110 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 111 return; 112 } 113 114 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 115 addr = rtas_pci_cfgaddr(addr); 116 117 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 118 /* Access must be to a valid device, within bounds and 119 * naturally aligned */ 120 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 121 return; 122 } 123 124 val = pci_host_config_read_common(pci_dev, addr, 125 pci_config_size(pci_dev), size); 126 127 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 128 rtas_st(rets, 1, val); 129 } 130 131 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 132 uint32_t token, uint32_t nargs, 133 target_ulong args, 134 uint32_t nret, target_ulong rets) 135 { 136 uint64_t buid; 137 uint32_t size, addr; 138 139 if ((nargs != 4) || (nret != 2)) { 140 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 141 return; 142 } 143 144 buid = rtas_ldq(args, 1); 145 size = rtas_ld(args, 3); 146 addr = rtas_ld(args, 0); 147 148 finish_read_pci_config(spapr, buid, addr, size, rets); 149 } 150 151 static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 152 uint32_t token, uint32_t nargs, 153 target_ulong args, 154 uint32_t nret, target_ulong rets) 155 { 156 uint32_t size, addr; 157 158 if ((nargs != 2) || (nret != 2)) { 159 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 160 return; 161 } 162 163 size = rtas_ld(args, 1); 164 addr = rtas_ld(args, 0); 165 166 finish_read_pci_config(spapr, 0, addr, size, rets); 167 } 168 169 static void finish_write_pci_config(sPAPRMachineState *spapr, uint64_t buid, 170 uint32_t addr, uint32_t size, 171 uint32_t val, target_ulong rets) 172 { 173 PCIDevice *pci_dev; 174 175 if ((size != 1) && (size != 2) && (size != 4)) { 176 /* access must be 1, 2 or 4 bytes */ 177 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 178 return; 179 } 180 181 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 182 addr = rtas_pci_cfgaddr(addr); 183 184 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 185 /* Access must be to a valid device, within bounds and 186 * naturally aligned */ 187 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 188 return; 189 } 190 191 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), 192 val, size); 193 194 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 195 } 196 197 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 198 uint32_t token, uint32_t nargs, 199 target_ulong args, 200 uint32_t nret, target_ulong rets) 201 { 202 uint64_t buid; 203 uint32_t val, size, addr; 204 205 if ((nargs != 5) || (nret != 1)) { 206 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 207 return; 208 } 209 210 buid = rtas_ldq(args, 1); 211 val = rtas_ld(args, 4); 212 size = rtas_ld(args, 3); 213 addr = rtas_ld(args, 0); 214 215 finish_write_pci_config(spapr, buid, addr, size, val, rets); 216 } 217 218 static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 219 uint32_t token, uint32_t nargs, 220 target_ulong args, 221 uint32_t nret, target_ulong rets) 222 { 223 uint32_t val, size, addr; 224 225 if ((nargs != 3) || (nret != 1)) { 226 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 227 return; 228 } 229 230 231 val = rtas_ld(args, 2); 232 size = rtas_ld(args, 1); 233 addr = rtas_ld(args, 0); 234 235 finish_write_pci_config(spapr, 0, addr, size, val, rets); 236 } 237 238 /* 239 * Set MSI/MSIX message data. 240 * This is required for msi_notify()/msix_notify() which 241 * will write at the addresses via spapr_msi_write(). 242 * 243 * If hwaddr == 0, all entries will have .data == first_irq i.e. 244 * table will be reset. 245 */ 246 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, 247 unsigned first_irq, unsigned req_num) 248 { 249 unsigned i; 250 MSIMessage msg = { .address = addr, .data = first_irq }; 251 252 if (!msix) { 253 msi_set_message(pdev, msg); 254 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); 255 return; 256 } 257 258 for (i = 0; i < req_num; ++i) { 259 msix_set_message(pdev, i, msg); 260 trace_spapr_pci_msi_setup(pdev->name, i, msg.address); 261 if (addr) { 262 ++msg.data; 263 } 264 } 265 } 266 267 static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 268 uint32_t token, uint32_t nargs, 269 target_ulong args, uint32_t nret, 270 target_ulong rets) 271 { 272 uint32_t config_addr = rtas_ld(args, 0); 273 uint64_t buid = rtas_ldq(args, 1); 274 unsigned int func = rtas_ld(args, 3); 275 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ 276 unsigned int seq_num = rtas_ld(args, 5); 277 unsigned int ret_intr_type; 278 unsigned int irq, max_irqs = 0, num = 0; 279 sPAPRPHBState *phb = NULL; 280 PCIDevice *pdev = NULL; 281 spapr_pci_msi *msi; 282 int *config_addr_key; 283 284 switch (func) { 285 case RTAS_CHANGE_MSI_FN: 286 case RTAS_CHANGE_FN: 287 ret_intr_type = RTAS_TYPE_MSI; 288 break; 289 case RTAS_CHANGE_MSIX_FN: 290 ret_intr_type = RTAS_TYPE_MSIX; 291 break; 292 default: 293 error_report("rtas_ibm_change_msi(%u) is not implemented", func); 294 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 295 return; 296 } 297 298 /* Fins sPAPRPHBState */ 299 phb = spapr_pci_find_phb(spapr, buid); 300 if (phb) { 301 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 302 } 303 if (!phb || !pdev) { 304 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 305 return; 306 } 307 308 /* Releasing MSIs */ 309 if (!req_num) { 310 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); 311 if (!msi) { 312 trace_spapr_pci_msi("Releasing wrong config", config_addr); 313 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 314 return; 315 } 316 317 xics_free(spapr->icp, msi->first_irq, msi->num); 318 if (msi_present(pdev)) { 319 spapr_msi_setmsg(pdev, 0, false, 0, num); 320 } 321 if (msix_present(pdev)) { 322 spapr_msi_setmsg(pdev, 0, true, 0, num); 323 } 324 g_hash_table_remove(phb->msi, &config_addr); 325 326 trace_spapr_pci_msi("Released MSIs", config_addr); 327 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 328 rtas_st(rets, 1, 0); 329 return; 330 } 331 332 /* Enabling MSI */ 333 334 /* Check if the device supports as many IRQs as requested */ 335 if (ret_intr_type == RTAS_TYPE_MSI) { 336 max_irqs = msi_nr_vectors_allocated(pdev); 337 } else if (ret_intr_type == RTAS_TYPE_MSIX) { 338 max_irqs = pdev->msix_entries_nr; 339 } 340 if (!max_irqs) { 341 error_report("Requested interrupt type %d is not enabled for device %x", 342 ret_intr_type, config_addr); 343 rtas_st(rets, 0, -1); /* Hardware error */ 344 return; 345 } 346 /* Correct the number if the guest asked for too many */ 347 if (req_num > max_irqs) { 348 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); 349 req_num = max_irqs; 350 irq = 0; /* to avoid misleading trace */ 351 goto out; 352 } 353 354 /* Allocate MSIs */ 355 irq = xics_alloc_block(spapr->icp, 0, req_num, false, 356 ret_intr_type == RTAS_TYPE_MSI); 357 if (!irq) { 358 error_report("Cannot allocate MSIs for device %x", config_addr); 359 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 360 return; 361 } 362 363 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ 364 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, 365 irq, req_num); 366 367 /* Add MSI device to cache */ 368 msi = g_new(spapr_pci_msi, 1); 369 msi->first_irq = irq; 370 msi->num = req_num; 371 config_addr_key = g_new(int, 1); 372 *config_addr_key = config_addr; 373 g_hash_table_insert(phb->msi, config_addr_key, msi); 374 375 out: 376 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 377 rtas_st(rets, 1, req_num); 378 rtas_st(rets, 2, ++seq_num); 379 if (nret > 3) { 380 rtas_st(rets, 3, ret_intr_type); 381 } 382 383 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); 384 } 385 386 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, 387 sPAPRMachineState *spapr, 388 uint32_t token, 389 uint32_t nargs, 390 target_ulong args, 391 uint32_t nret, 392 target_ulong rets) 393 { 394 uint32_t config_addr = rtas_ld(args, 0); 395 uint64_t buid = rtas_ldq(args, 1); 396 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); 397 sPAPRPHBState *phb = NULL; 398 PCIDevice *pdev = NULL; 399 spapr_pci_msi *msi; 400 401 /* Find sPAPRPHBState */ 402 phb = spapr_pci_find_phb(spapr, buid); 403 if (phb) { 404 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 405 } 406 if (!phb || !pdev) { 407 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 408 return; 409 } 410 411 /* Find device descriptor and start IRQ */ 412 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); 413 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { 414 trace_spapr_pci_msi("Failed to return vector", config_addr); 415 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 416 return; 417 } 418 intr_src_num = msi->first_irq + ioa_intr_num; 419 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, 420 intr_src_num); 421 422 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 423 rtas_st(rets, 1, intr_src_num); 424 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ 425 } 426 427 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, 428 sPAPRMachineState *spapr, 429 uint32_t token, uint32_t nargs, 430 target_ulong args, uint32_t nret, 431 target_ulong rets) 432 { 433 sPAPRPHBState *sphb; 434 sPAPRPHBClass *spc; 435 uint32_t addr, option; 436 uint64_t buid; 437 int ret; 438 439 if ((nargs != 4) || (nret != 1)) { 440 goto param_error_exit; 441 } 442 443 buid = rtas_ldq(args, 1); 444 addr = rtas_ld(args, 0); 445 option = rtas_ld(args, 3); 446 447 sphb = spapr_pci_find_phb(spapr, buid); 448 if (!sphb) { 449 goto param_error_exit; 450 } 451 452 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 453 if (!spc->eeh_set_option) { 454 goto param_error_exit; 455 } 456 457 ret = spc->eeh_set_option(sphb, addr, option); 458 rtas_st(rets, 0, ret); 459 return; 460 461 param_error_exit: 462 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 463 } 464 465 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, 466 sPAPRMachineState *spapr, 467 uint32_t token, uint32_t nargs, 468 target_ulong args, uint32_t nret, 469 target_ulong rets) 470 { 471 sPAPRPHBState *sphb; 472 sPAPRPHBClass *spc; 473 PCIDevice *pdev; 474 uint32_t addr, option; 475 uint64_t buid; 476 477 if ((nargs != 4) || (nret != 2)) { 478 goto param_error_exit; 479 } 480 481 buid = rtas_ldq(args, 1); 482 sphb = spapr_pci_find_phb(spapr, buid); 483 if (!sphb) { 484 goto param_error_exit; 485 } 486 487 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 488 if (!spc->eeh_set_option) { 489 goto param_error_exit; 490 } 491 492 /* 493 * We always have PE address of form "00BB0001". "BB" 494 * represents the bus number of PE's primary bus. 495 */ 496 option = rtas_ld(args, 3); 497 switch (option) { 498 case RTAS_GET_PE_ADDR: 499 addr = rtas_ld(args, 0); 500 pdev = spapr_pci_find_dev(spapr, buid, addr); 501 if (!pdev) { 502 goto param_error_exit; 503 } 504 505 rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1); 506 break; 507 case RTAS_GET_PE_MODE: 508 rtas_st(rets, 1, RTAS_PE_MODE_SHARED); 509 break; 510 default: 511 goto param_error_exit; 512 } 513 514 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 515 return; 516 517 param_error_exit: 518 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 519 } 520 521 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, 522 sPAPRMachineState *spapr, 523 uint32_t token, uint32_t nargs, 524 target_ulong args, uint32_t nret, 525 target_ulong rets) 526 { 527 sPAPRPHBState *sphb; 528 sPAPRPHBClass *spc; 529 uint64_t buid; 530 int state, ret; 531 532 if ((nargs != 3) || (nret != 4 && nret != 5)) { 533 goto param_error_exit; 534 } 535 536 buid = rtas_ldq(args, 1); 537 sphb = spapr_pci_find_phb(spapr, buid); 538 if (!sphb) { 539 goto param_error_exit; 540 } 541 542 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 543 if (!spc->eeh_get_state) { 544 goto param_error_exit; 545 } 546 547 ret = spc->eeh_get_state(sphb, &state); 548 rtas_st(rets, 0, ret); 549 if (ret != RTAS_OUT_SUCCESS) { 550 return; 551 } 552 553 rtas_st(rets, 1, state); 554 rtas_st(rets, 2, RTAS_EEH_SUPPORT); 555 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); 556 if (nret >= 5) { 557 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); 558 } 559 return; 560 561 param_error_exit: 562 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 563 } 564 565 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, 566 sPAPRMachineState *spapr, 567 uint32_t token, uint32_t nargs, 568 target_ulong args, uint32_t nret, 569 target_ulong rets) 570 { 571 sPAPRPHBState *sphb; 572 sPAPRPHBClass *spc; 573 uint32_t option; 574 uint64_t buid; 575 int ret; 576 577 if ((nargs != 4) || (nret != 1)) { 578 goto param_error_exit; 579 } 580 581 buid = rtas_ldq(args, 1); 582 option = rtas_ld(args, 3); 583 sphb = spapr_pci_find_phb(spapr, buid); 584 if (!sphb) { 585 goto param_error_exit; 586 } 587 588 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 589 if (!spc->eeh_reset) { 590 goto param_error_exit; 591 } 592 593 ret = spc->eeh_reset(sphb, option); 594 rtas_st(rets, 0, ret); 595 return; 596 597 param_error_exit: 598 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 599 } 600 601 static void rtas_ibm_configure_pe(PowerPCCPU *cpu, 602 sPAPRMachineState *spapr, 603 uint32_t token, uint32_t nargs, 604 target_ulong args, uint32_t nret, 605 target_ulong rets) 606 { 607 sPAPRPHBState *sphb; 608 sPAPRPHBClass *spc; 609 uint64_t buid; 610 int ret; 611 612 if ((nargs != 3) || (nret != 1)) { 613 goto param_error_exit; 614 } 615 616 buid = rtas_ldq(args, 1); 617 sphb = spapr_pci_find_phb(spapr, buid); 618 if (!sphb) { 619 goto param_error_exit; 620 } 621 622 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 623 if (!spc->eeh_configure) { 624 goto param_error_exit; 625 } 626 627 ret = spc->eeh_configure(sphb); 628 rtas_st(rets, 0, ret); 629 return; 630 631 param_error_exit: 632 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 633 } 634 635 /* To support it later */ 636 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, 637 sPAPRMachineState *spapr, 638 uint32_t token, uint32_t nargs, 639 target_ulong args, uint32_t nret, 640 target_ulong rets) 641 { 642 sPAPRPHBState *sphb; 643 sPAPRPHBClass *spc; 644 int option; 645 uint64_t buid; 646 647 if ((nargs != 8) || (nret != 1)) { 648 goto param_error_exit; 649 } 650 651 buid = rtas_ldq(args, 1); 652 sphb = spapr_pci_find_phb(spapr, buid); 653 if (!sphb) { 654 goto param_error_exit; 655 } 656 657 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 658 if (!spc->eeh_set_option) { 659 goto param_error_exit; 660 } 661 662 option = rtas_ld(args, 7); 663 switch (option) { 664 case RTAS_SLOT_TEMP_ERR_LOG: 665 case RTAS_SLOT_PERM_ERR_LOG: 666 break; 667 default: 668 goto param_error_exit; 669 } 670 671 /* We don't have error log yet */ 672 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); 673 return; 674 675 param_error_exit: 676 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 677 } 678 679 static int pci_spapr_swizzle(int slot, int pin) 680 { 681 return (slot + pin) % PCI_NUM_PINS; 682 } 683 684 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) 685 { 686 /* 687 * Here we need to convert pci_dev + irq_num to some unique value 688 * which is less than number of IRQs on the specific bus (4). We 689 * use standard PCI swizzling, that is (slot number + pin number) 690 * % 4. 691 */ 692 return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num); 693 } 694 695 static void pci_spapr_set_irq(void *opaque, int irq_num, int level) 696 { 697 /* 698 * Here we use the number returned by pci_spapr_map_irq to find a 699 * corresponding qemu_irq. 700 */ 701 sPAPRPHBState *phb = opaque; 702 703 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); 704 qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); 705 } 706 707 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) 708 { 709 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); 710 PCIINTxRoute route; 711 712 route.mode = PCI_INTX_ENABLED; 713 route.irq = sphb->lsi_table[pin].irq; 714 715 return route; 716 } 717 718 /* 719 * MSI/MSIX memory region implementation. 720 * The handler handles both MSI and MSIX. 721 * For MSI-X, the vector number is encoded as a part of the address, 722 * data is set to 0. 723 * For MSI, the vector number is encoded in least bits in data. 724 */ 725 static void spapr_msi_write(void *opaque, hwaddr addr, 726 uint64_t data, unsigned size) 727 { 728 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 729 uint32_t irq = data; 730 731 trace_spapr_pci_msi_write(addr, data, irq); 732 733 qemu_irq_pulse(xics_get_qirq(spapr->icp, irq)); 734 } 735 736 static const MemoryRegionOps spapr_msi_ops = { 737 /* There is no .read as the read result is undefined by PCI spec */ 738 .read = NULL, 739 .write = spapr_msi_write, 740 .endianness = DEVICE_LITTLE_ENDIAN 741 }; 742 743 /* 744 * PHB PCI device 745 */ 746 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 747 { 748 sPAPRPHBState *phb = opaque; 749 750 return &phb->iommu_as; 751 } 752 753 static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) 754 { 755 char *path = NULL, *buf = NULL, *host = NULL; 756 757 /* Get the PCI VFIO host id */ 758 host = object_property_get_str(OBJECT(pdev), "host", NULL); 759 if (!host) { 760 goto err_out; 761 } 762 763 /* Construct the path of the file that will give us the DT location */ 764 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); 765 g_free(host); 766 if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { 767 goto err_out; 768 } 769 g_free(path); 770 771 /* Construct and read from host device tree the loc-code */ 772 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); 773 g_free(buf); 774 if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { 775 goto err_out; 776 } 777 return buf; 778 779 err_out: 780 g_free(path); 781 return NULL; 782 } 783 784 static char *spapr_phb_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) 785 { 786 char *buf; 787 const char *devtype = "qemu"; 788 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 789 790 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 791 buf = spapr_phb_vfio_get_loc_code(sphb, pdev); 792 if (buf) { 793 return buf; 794 } 795 devtype = "vfio"; 796 } 797 /* 798 * For emulated devices and VFIO-failure case, make up 799 * the loc-code. 800 */ 801 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", 802 devtype, pdev->name, sphb->index, busnr, 803 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 804 return buf; 805 } 806 807 /* Macros to operate with address in OF binding to PCI */ 808 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) 809 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ 810 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ 811 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ 812 #define b_ss(x) b_x((x), 24, 2) /* the space code */ 813 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ 814 #define b_ddddd(x) b_x((x), 11, 5) /* device number */ 815 #define b_fff(x) b_x((x), 8, 3) /* function number */ 816 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ 817 818 /* for 'reg'/'assigned-addresses' OF properties */ 819 #define RESOURCE_CELLS_SIZE 2 820 #define RESOURCE_CELLS_ADDRESS 3 821 822 typedef struct ResourceFields { 823 uint32_t phys_hi; 824 uint32_t phys_mid; 825 uint32_t phys_lo; 826 uint32_t size_hi; 827 uint32_t size_lo; 828 } QEMU_PACKED ResourceFields; 829 830 typedef struct ResourceProps { 831 ResourceFields reg[8]; 832 ResourceFields assigned[7]; 833 uint32_t reg_len; 834 uint32_t assigned_len; 835 } ResourceProps; 836 837 /* fill in the 'reg'/'assigned-resources' OF properties for 838 * a PCI device. 'reg' describes resource requirements for a 839 * device's IO/MEM regions, 'assigned-addresses' describes the 840 * actual resource assignments. 841 * 842 * the properties are arrays of ('phys-addr', 'size') pairs describing 843 * the addressable regions of the PCI device, where 'phys-addr' is a 844 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to 845 * (phys.hi, phys.mid, phys.lo), and 'size' is a 846 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). 847 * 848 * phys.hi = 0xYYXXXXZZ, where: 849 * 0xYY = npt000ss 850 * ||| | 851 * ||| +-- space code 852 * ||| | 853 * ||| + 00 if configuration space 854 * ||| + 01 if IO region, 855 * ||| + 10 if 32-bit MEM region 856 * ||| + 11 if 64-bit MEM region 857 * ||| 858 * ||+------ for non-relocatable IO: 1 if aliased 859 * || for relocatable IO: 1 if below 64KB 860 * || for MEM: 1 if below 1MB 861 * |+------- 1 if region is prefetchable 862 * +-------- 1 if region is non-relocatable 863 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function 864 * bits respectively 865 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding 866 * to the region 867 * 868 * phys.mid and phys.lo correspond respectively to the hi/lo portions 869 * of the actual address of the region. 870 * 871 * how the phys-addr/size values are used differ slightly between 872 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has 873 * an additional description for the config space region of the 874 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0 875 * to describe the region as relocatable, with an address-mapping 876 * that corresponds directly to the PHB's address space for the 877 * resource. 'assigned-addresses' always has n=1 set with an absolute 878 * address assigned for the resource. in general, 'assigned-addresses' 879 * won't be populated, since addresses for PCI devices are generally 880 * unmapped initially and left to the guest to assign. 881 * 882 * note also that addresses defined in these properties are, at least 883 * for PAPR guests, relative to the PHBs IO/MEM windows, and 884 * correspond directly to the addresses in the BARs. 885 * 886 * in accordance with PCI Bus Binding to Open Firmware, 887 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, 888 * Appendix C. 889 */ 890 static void populate_resource_props(PCIDevice *d, ResourceProps *rp) 891 { 892 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); 893 uint32_t dev_id = (b_bbbbbbbb(bus_num) | 894 b_ddddd(PCI_SLOT(d->devfn)) | 895 b_fff(PCI_FUNC(d->devfn))); 896 ResourceFields *reg, *assigned; 897 int i, reg_idx = 0, assigned_idx = 0; 898 899 /* config space region */ 900 reg = &rp->reg[reg_idx++]; 901 reg->phys_hi = cpu_to_be32(dev_id); 902 reg->phys_mid = 0; 903 reg->phys_lo = 0; 904 reg->size_hi = 0; 905 reg->size_lo = 0; 906 907 for (i = 0; i < PCI_NUM_REGIONS; i++) { 908 if (!d->io_regions[i].size) { 909 continue; 910 } 911 912 reg = &rp->reg[reg_idx++]; 913 914 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); 915 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 916 reg->phys_hi |= cpu_to_be32(b_ss(1)); 917 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 918 reg->phys_hi |= cpu_to_be32(b_ss(3)); 919 } else { 920 reg->phys_hi |= cpu_to_be32(b_ss(2)); 921 } 922 reg->phys_mid = 0; 923 reg->phys_lo = 0; 924 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); 925 reg->size_lo = cpu_to_be32(d->io_regions[i].size); 926 927 if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) { 928 continue; 929 } 930 931 assigned = &rp->assigned[assigned_idx++]; 932 assigned->phys_hi = cpu_to_be32(reg->phys_hi | b_n(1)); 933 assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32); 934 assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr); 935 assigned->size_hi = reg->size_hi; 936 assigned->size_lo = reg->size_lo; 937 } 938 939 rp->reg_len = reg_idx * sizeof(ResourceFields); 940 rp->assigned_len = assigned_idx * sizeof(ResourceFields); 941 } 942 943 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, 944 PCIDevice *pdev); 945 946 static int spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset, 947 sPAPRPHBState *sphb) 948 { 949 ResourceProps rp; 950 bool is_bridge = false; 951 int pci_status, err; 952 char *buf = NULL; 953 uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev); 954 uint32_t max_msi, max_msix; 955 956 if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) == 957 PCI_HEADER_TYPE_BRIDGE) { 958 is_bridge = true; 959 } 960 961 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ 962 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", 963 pci_default_read_config(dev, PCI_VENDOR_ID, 2))); 964 _FDT(fdt_setprop_cell(fdt, offset, "device-id", 965 pci_default_read_config(dev, PCI_DEVICE_ID, 2))); 966 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", 967 pci_default_read_config(dev, PCI_REVISION_ID, 1))); 968 _FDT(fdt_setprop_cell(fdt, offset, "class-code", 969 pci_default_read_config(dev, PCI_CLASS_PROG, 3))); 970 if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) { 971 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", 972 pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1))); 973 } 974 975 if (!is_bridge) { 976 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", 977 pci_default_read_config(dev, PCI_MIN_GNT, 1))); 978 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", 979 pci_default_read_config(dev, PCI_MAX_LAT, 1))); 980 } 981 982 if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) { 983 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", 984 pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2))); 985 } 986 987 if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) { 988 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", 989 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2))); 990 } 991 992 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", 993 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1))); 994 995 /* the following fdt cells are masked off the pci status register */ 996 pci_status = pci_default_read_config(dev, PCI_STATUS, 2); 997 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", 998 PCI_STATUS_DEVSEL_MASK & pci_status)); 999 1000 if (pci_status & PCI_STATUS_FAST_BACK) { 1001 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); 1002 } 1003 if (pci_status & PCI_STATUS_66MHZ) { 1004 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); 1005 } 1006 if (pci_status & PCI_STATUS_UDF) { 1007 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); 1008 } 1009 1010 /* NOTE: this is normally generated by firmware via path/unit name, 1011 * but in our case we must set it manually since it does not get 1012 * processed by OF beforehand 1013 */ 1014 _FDT(fdt_setprop_string(fdt, offset, "name", "pci")); 1015 buf = spapr_phb_get_loc_code(sphb, dev); 1016 if (!buf) { 1017 error_report("Failed setting the ibm,loc-code"); 1018 return -1; 1019 } 1020 1021 err = fdt_setprop_string(fdt, offset, "ibm,loc-code", buf); 1022 g_free(buf); 1023 if (err < 0) { 1024 return err; 1025 } 1026 1027 if (drc_index) { 1028 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)); 1029 } 1030 1031 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 1032 RESOURCE_CELLS_ADDRESS)); 1033 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1034 RESOURCE_CELLS_SIZE)); 1035 1036 max_msi = msi_nr_vectors_allocated(dev); 1037 if (max_msi) { 1038 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi)); 1039 } 1040 max_msix = dev->msix_entries_nr; 1041 if (max_msix) { 1042 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix)); 1043 } 1044 1045 populate_resource_props(dev, &rp); 1046 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); 1047 _FDT(fdt_setprop(fdt, offset, "assigned-addresses", 1048 (uint8_t *)rp.assigned, rp.assigned_len)); 1049 1050 return 0; 1051 } 1052 1053 /* create OF node for pci device and required OF DT properties */ 1054 static int spapr_create_pci_child_dt(sPAPRPHBState *phb, PCIDevice *dev, 1055 void *fdt, int node_offset) 1056 { 1057 int offset, ret; 1058 int slot = PCI_SLOT(dev->devfn); 1059 int func = PCI_FUNC(dev->devfn); 1060 char nodename[FDT_NAME_MAX]; 1061 1062 if (func != 0) { 1063 snprintf(nodename, FDT_NAME_MAX, "pci@%x,%x", slot, func); 1064 } else { 1065 snprintf(nodename, FDT_NAME_MAX, "pci@%x", slot); 1066 } 1067 offset = fdt_add_subnode(fdt, node_offset, nodename); 1068 ret = spapr_populate_pci_child_dt(dev, fdt, offset, phb); 1069 1070 g_assert(!ret); 1071 if (ret) { 1072 return 0; 1073 } 1074 return offset; 1075 } 1076 1077 static void spapr_phb_add_pci_device(sPAPRDRConnector *drc, 1078 sPAPRPHBState *phb, 1079 PCIDevice *pdev, 1080 Error **errp) 1081 { 1082 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1083 DeviceState *dev = DEVICE(pdev); 1084 void *fdt = NULL; 1085 int fdt_start_offset = 0, fdt_size; 1086 1087 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 1088 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(phb->dma_liobn); 1089 1090 spapr_tce_set_need_vfio(tcet, true); 1091 } 1092 1093 if (dev->hotplugged) { 1094 fdt = create_device_tree(&fdt_size); 1095 fdt_start_offset = spapr_create_pci_child_dt(phb, pdev, fdt, 0); 1096 if (!fdt_start_offset) { 1097 error_setg(errp, "Failed to create pci child device tree node"); 1098 goto out; 1099 } 1100 } 1101 1102 drck->attach(drc, DEVICE(pdev), 1103 fdt, fdt_start_offset, !dev->hotplugged, errp); 1104 out: 1105 if (*errp) { 1106 g_free(fdt); 1107 } 1108 } 1109 1110 static void spapr_phb_remove_pci_device_cb(DeviceState *dev, void *opaque) 1111 { 1112 /* some version guests do not wait for completion of a device 1113 * cleanup (generally done asynchronously by the kernel) before 1114 * signaling to QEMU that the device is safe, but instead sleep 1115 * for some 'safe' period of time. unfortunately on a busy host 1116 * this sleep isn't guaranteed to be long enough, resulting in 1117 * bad things like IRQ lines being left asserted during final 1118 * device removal. to deal with this we call reset just prior 1119 * to finalizing the device, which will put the device back into 1120 * an 'idle' state, as the device cleanup code expects. 1121 */ 1122 pci_device_reset(PCI_DEVICE(dev)); 1123 object_unparent(OBJECT(dev)); 1124 } 1125 1126 static void spapr_phb_remove_pci_device(sPAPRDRConnector *drc, 1127 sPAPRPHBState *phb, 1128 PCIDevice *pdev, 1129 Error **errp) 1130 { 1131 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1132 1133 drck->detach(drc, DEVICE(pdev), spapr_phb_remove_pci_device_cb, phb, errp); 1134 } 1135 1136 static sPAPRDRConnector *spapr_phb_get_pci_drc(sPAPRPHBState *phb, 1137 PCIDevice *pdev) 1138 { 1139 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 1140 return spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_PCI, 1141 (phb->index << 16) | 1142 (busnr << 8) | 1143 pdev->devfn); 1144 } 1145 1146 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, 1147 PCIDevice *pdev) 1148 { 1149 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1150 sPAPRDRConnectorClass *drck; 1151 1152 if (!drc) { 1153 return 0; 1154 } 1155 1156 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1157 return drck->get_index(drc); 1158 } 1159 1160 static void spapr_phb_hot_plug_child(HotplugHandler *plug_handler, 1161 DeviceState *plugged_dev, Error **errp) 1162 { 1163 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1164 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1165 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1166 Error *local_err = NULL; 1167 1168 /* if DR is disabled we don't need to do anything in the case of 1169 * hotplug or coldplug callbacks 1170 */ 1171 if (!phb->dr_enabled) { 1172 /* if this is a hotplug operation initiated by the user 1173 * we need to let them know it's not enabled 1174 */ 1175 if (plugged_dev->hotplugged) { 1176 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1177 object_get_typename(OBJECT(phb))); 1178 } 1179 return; 1180 } 1181 1182 g_assert(drc); 1183 1184 spapr_phb_add_pci_device(drc, phb, pdev, &local_err); 1185 if (local_err) { 1186 error_propagate(errp, local_err); 1187 return; 1188 } 1189 if (plugged_dev->hotplugged) { 1190 spapr_hotplug_req_add_by_index(drc); 1191 } 1192 } 1193 1194 static void spapr_phb_hot_unplug_child(HotplugHandler *plug_handler, 1195 DeviceState *plugged_dev, Error **errp) 1196 { 1197 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1198 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1199 sPAPRDRConnectorClass *drck; 1200 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1201 Error *local_err = NULL; 1202 1203 if (!phb->dr_enabled) { 1204 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1205 object_get_typename(OBJECT(phb))); 1206 return; 1207 } 1208 1209 g_assert(drc); 1210 1211 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1212 if (!drck->release_pending(drc)) { 1213 spapr_phb_remove_pci_device(drc, phb, pdev, &local_err); 1214 if (local_err) { 1215 error_propagate(errp, local_err); 1216 return; 1217 } 1218 spapr_hotplug_req_remove_by_index(drc); 1219 } 1220 } 1221 1222 static void spapr_phb_realize(DeviceState *dev, Error **errp) 1223 { 1224 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1225 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1226 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); 1227 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1228 sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(s); 1229 char *namebuf; 1230 int i; 1231 PCIBus *bus; 1232 uint64_t msi_window_size = 4096; 1233 1234 if (sphb->index != (uint32_t)-1) { 1235 hwaddr windows_base; 1236 1237 if ((sphb->buid != (uint64_t)-1) || (sphb->dma_liobn != (uint32_t)-1) 1238 || (sphb->mem_win_addr != (hwaddr)-1) 1239 || (sphb->io_win_addr != (hwaddr)-1)) { 1240 error_setg(errp, "Either \"index\" or other parameters must" 1241 " be specified for PAPR PHB, not both"); 1242 return; 1243 } 1244 1245 if (sphb->index > SPAPR_PCI_MAX_INDEX) { 1246 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 1247 SPAPR_PCI_MAX_INDEX); 1248 return; 1249 } 1250 1251 sphb->buid = SPAPR_PCI_BASE_BUID + sphb->index; 1252 sphb->dma_liobn = SPAPR_PCI_LIOBN(sphb->index, 0); 1253 1254 windows_base = SPAPR_PCI_WINDOW_BASE 1255 + sphb->index * SPAPR_PCI_WINDOW_SPACING; 1256 sphb->mem_win_addr = windows_base + SPAPR_PCI_MMIO_WIN_OFF; 1257 sphb->io_win_addr = windows_base + SPAPR_PCI_IO_WIN_OFF; 1258 } 1259 1260 if (sphb->buid == (uint64_t)-1) { 1261 error_setg(errp, "BUID not specified for PHB"); 1262 return; 1263 } 1264 1265 if (sphb->dma_liobn == (uint32_t)-1) { 1266 error_setg(errp, "LIOBN not specified for PHB"); 1267 return; 1268 } 1269 1270 if (sphb->mem_win_addr == (hwaddr)-1) { 1271 error_setg(errp, "Memory window address not specified for PHB"); 1272 return; 1273 } 1274 1275 if (sphb->io_win_addr == (hwaddr)-1) { 1276 error_setg(errp, "IO window address not specified for PHB"); 1277 return; 1278 } 1279 1280 if (spapr_pci_find_phb(spapr, sphb->buid)) { 1281 error_setg(errp, "PCI host bridges must have unique BUIDs"); 1282 return; 1283 } 1284 1285 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); 1286 1287 namebuf = alloca(strlen(sphb->dtbusname) + 32); 1288 1289 /* Initialize memory regions */ 1290 sprintf(namebuf, "%s.mmio", sphb->dtbusname); 1291 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); 1292 1293 sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname); 1294 memory_region_init_alias(&sphb->memwindow, OBJECT(sphb), 1295 namebuf, &sphb->memspace, 1296 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); 1297 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, 1298 &sphb->memwindow); 1299 1300 /* Initialize IO regions */ 1301 sprintf(namebuf, "%s.io", sphb->dtbusname); 1302 memory_region_init(&sphb->iospace, OBJECT(sphb), 1303 namebuf, SPAPR_PCI_IO_WIN_SIZE); 1304 1305 sprintf(namebuf, "%s.io-alias", sphb->dtbusname); 1306 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, 1307 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); 1308 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, 1309 &sphb->iowindow); 1310 1311 bus = pci_register_bus(dev, NULL, 1312 pci_spapr_set_irq, pci_spapr_map_irq, sphb, 1313 &sphb->memspace, &sphb->iospace, 1314 PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); 1315 phb->bus = bus; 1316 qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL); 1317 1318 /* 1319 * Initialize PHB address space. 1320 * By default there will be at least one subregion for default 1321 * 32bit DMA window. 1322 * Later the guest might want to create another DMA window 1323 * which will become another memory subregion. 1324 */ 1325 sprintf(namebuf, "%s.iommu-root", sphb->dtbusname); 1326 1327 memory_region_init(&sphb->iommu_root, OBJECT(sphb), 1328 namebuf, UINT64_MAX); 1329 address_space_init(&sphb->iommu_as, &sphb->iommu_root, 1330 sphb->dtbusname); 1331 1332 /* 1333 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, 1334 * we need to allocate some memory to catch those writes coming 1335 * from msi_notify()/msix_notify(). 1336 * As MSIMessage:addr is going to be the same and MSIMessage:data 1337 * is going to be a VIRQ number, 4 bytes of the MSI MR will only 1338 * be used. 1339 * 1340 * For KVM we want to ensure that this memory is a full page so that 1341 * our memory slot is of page size granularity. 1342 */ 1343 #ifdef CONFIG_KVM 1344 if (kvm_enabled()) { 1345 msi_window_size = getpagesize(); 1346 } 1347 #endif 1348 1349 memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr, 1350 "msi", msi_window_size); 1351 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, 1352 &sphb->msiwindow); 1353 1354 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); 1355 1356 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); 1357 1358 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); 1359 1360 /* Initialize the LSI table */ 1361 for (i = 0; i < PCI_NUM_PINS; i++) { 1362 uint32_t irq; 1363 1364 irq = xics_alloc_block(spapr->icp, 0, 1, true, false); 1365 if (!irq) { 1366 error_setg(errp, "spapr_allocate_lsi failed"); 1367 return; 1368 } 1369 1370 sphb->lsi_table[i].irq = irq; 1371 } 1372 1373 /* allocate connectors for child PCI devices */ 1374 if (sphb->dr_enabled) { 1375 for (i = 0; i < PCI_SLOT_MAX * 8; i++) { 1376 spapr_dr_connector_new(OBJECT(phb), 1377 SPAPR_DR_CONNECTOR_TYPE_PCI, 1378 (sphb->index << 16) | i); 1379 } 1380 } 1381 1382 if (!info->finish_realize) { 1383 error_setg(errp, "finish_realize not defined"); 1384 return; 1385 } 1386 1387 info->finish_realize(sphb, errp); 1388 1389 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); 1390 } 1391 1392 static void spapr_phb_finish_realize(sPAPRPHBState *sphb, Error **errp) 1393 { 1394 sPAPRTCETable *tcet; 1395 uint32_t nb_table; 1396 1397 nb_table = sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT; 1398 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn, 1399 0, SPAPR_TCE_PAGE_SHIFT, nb_table, false); 1400 if (!tcet) { 1401 error_setg(errp, "Unable to create TCE table for %s", 1402 sphb->dtbusname); 1403 return ; 1404 } 1405 1406 /* Register default 32bit DMA window */ 1407 memory_region_add_subregion(&sphb->iommu_root, sphb->dma_win_addr, 1408 spapr_tce_get_iommu(tcet)); 1409 } 1410 1411 static int spapr_phb_children_reset(Object *child, void *opaque) 1412 { 1413 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); 1414 1415 if (dev) { 1416 device_reset(dev); 1417 } 1418 1419 return 0; 1420 } 1421 1422 static void spapr_phb_reset(DeviceState *qdev) 1423 { 1424 /* Reset the IOMMU state */ 1425 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); 1426 } 1427 1428 static Property spapr_phb_properties[] = { 1429 DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1), 1430 DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1), 1431 DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn, -1), 1432 DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1), 1433 DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size, 1434 SPAPR_PCI_MMIO_WIN_SIZE), 1435 DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1), 1436 DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size, 1437 SPAPR_PCI_IO_WIN_SIZE), 1438 DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled, 1439 true), 1440 /* Default DMA window is 0..1GB */ 1441 DEFINE_PROP_UINT64("dma_win_addr", sPAPRPHBState, dma_win_addr, 0), 1442 DEFINE_PROP_UINT64("dma_win_size", sPAPRPHBState, dma_win_size, 0x40000000), 1443 DEFINE_PROP_END_OF_LIST(), 1444 }; 1445 1446 static const VMStateDescription vmstate_spapr_pci_lsi = { 1447 .name = "spapr_pci/lsi", 1448 .version_id = 1, 1449 .minimum_version_id = 1, 1450 .fields = (VMStateField[]) { 1451 VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi), 1452 1453 VMSTATE_END_OF_LIST() 1454 }, 1455 }; 1456 1457 static const VMStateDescription vmstate_spapr_pci_msi = { 1458 .name = "spapr_pci/msi", 1459 .version_id = 1, 1460 .minimum_version_id = 1, 1461 .fields = (VMStateField []) { 1462 VMSTATE_UINT32(key, spapr_pci_msi_mig), 1463 VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig), 1464 VMSTATE_UINT32(value.num, spapr_pci_msi_mig), 1465 VMSTATE_END_OF_LIST() 1466 }, 1467 }; 1468 1469 static void spapr_pci_pre_save(void *opaque) 1470 { 1471 sPAPRPHBState *sphb = opaque; 1472 GHashTableIter iter; 1473 gpointer key, value; 1474 int i; 1475 1476 g_free(sphb->msi_devs); 1477 sphb->msi_devs = NULL; 1478 sphb->msi_devs_num = g_hash_table_size(sphb->msi); 1479 if (!sphb->msi_devs_num) { 1480 return; 1481 } 1482 sphb->msi_devs = g_malloc(sphb->msi_devs_num * sizeof(spapr_pci_msi_mig)); 1483 1484 g_hash_table_iter_init(&iter, sphb->msi); 1485 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { 1486 sphb->msi_devs[i].key = *(uint32_t *) key; 1487 sphb->msi_devs[i].value = *(spapr_pci_msi *) value; 1488 } 1489 } 1490 1491 static int spapr_pci_post_load(void *opaque, int version_id) 1492 { 1493 sPAPRPHBState *sphb = opaque; 1494 gpointer key, value; 1495 int i; 1496 1497 for (i = 0; i < sphb->msi_devs_num; ++i) { 1498 key = g_memdup(&sphb->msi_devs[i].key, 1499 sizeof(sphb->msi_devs[i].key)); 1500 value = g_memdup(&sphb->msi_devs[i].value, 1501 sizeof(sphb->msi_devs[i].value)); 1502 g_hash_table_insert(sphb->msi, key, value); 1503 } 1504 g_free(sphb->msi_devs); 1505 sphb->msi_devs = NULL; 1506 sphb->msi_devs_num = 0; 1507 1508 return 0; 1509 } 1510 1511 static const VMStateDescription vmstate_spapr_pci = { 1512 .name = "spapr_pci", 1513 .version_id = 2, 1514 .minimum_version_id = 2, 1515 .pre_save = spapr_pci_pre_save, 1516 .post_load = spapr_pci_post_load, 1517 .fields = (VMStateField[]) { 1518 VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState), 1519 VMSTATE_UINT32_EQUAL(dma_liobn, sPAPRPHBState), 1520 VMSTATE_UINT64_EQUAL(mem_win_addr, sPAPRPHBState), 1521 VMSTATE_UINT64_EQUAL(mem_win_size, sPAPRPHBState), 1522 VMSTATE_UINT64_EQUAL(io_win_addr, sPAPRPHBState), 1523 VMSTATE_UINT64_EQUAL(io_win_size, sPAPRPHBState), 1524 VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0, 1525 vmstate_spapr_pci_lsi, struct spapr_pci_lsi), 1526 VMSTATE_INT32(msi_devs_num, sPAPRPHBState), 1527 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0, 1528 vmstate_spapr_pci_msi, spapr_pci_msi_mig), 1529 VMSTATE_END_OF_LIST() 1530 }, 1531 }; 1532 1533 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, 1534 PCIBus *rootbus) 1535 { 1536 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); 1537 1538 return sphb->dtbusname; 1539 } 1540 1541 static void spapr_phb_class_init(ObjectClass *klass, void *data) 1542 { 1543 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 1544 DeviceClass *dc = DEVICE_CLASS(klass); 1545 sPAPRPHBClass *spc = SPAPR_PCI_HOST_BRIDGE_CLASS(klass); 1546 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); 1547 1548 hc->root_bus_path = spapr_phb_root_bus_path; 1549 dc->realize = spapr_phb_realize; 1550 dc->props = spapr_phb_properties; 1551 dc->reset = spapr_phb_reset; 1552 dc->vmsd = &vmstate_spapr_pci; 1553 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 1554 dc->cannot_instantiate_with_device_add_yet = false; 1555 spc->finish_realize = spapr_phb_finish_realize; 1556 hp->plug = spapr_phb_hot_plug_child; 1557 hp->unplug = spapr_phb_hot_unplug_child; 1558 } 1559 1560 static const TypeInfo spapr_phb_info = { 1561 .name = TYPE_SPAPR_PCI_HOST_BRIDGE, 1562 .parent = TYPE_PCI_HOST_BRIDGE, 1563 .instance_size = sizeof(sPAPRPHBState), 1564 .class_init = spapr_phb_class_init, 1565 .class_size = sizeof(sPAPRPHBClass), 1566 .interfaces = (InterfaceInfo[]) { 1567 { TYPE_HOTPLUG_HANDLER }, 1568 { } 1569 } 1570 }; 1571 1572 PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index) 1573 { 1574 DeviceState *dev; 1575 1576 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 1577 qdev_prop_set_uint32(dev, "index", index); 1578 qdev_init_nofail(dev); 1579 1580 return PCI_HOST_BRIDGE(dev); 1581 } 1582 1583 typedef struct sPAPRFDT { 1584 void *fdt; 1585 int node_off; 1586 sPAPRPHBState *sphb; 1587 } sPAPRFDT; 1588 1589 static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev, 1590 void *opaque) 1591 { 1592 PCIBus *sec_bus; 1593 sPAPRFDT *p = opaque; 1594 int offset; 1595 sPAPRFDT s_fdt; 1596 1597 offset = spapr_create_pci_child_dt(p->sphb, pdev, p->fdt, p->node_off); 1598 if (!offset) { 1599 error_report("Failed to create pci child device tree node"); 1600 return; 1601 } 1602 1603 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 1604 PCI_HEADER_TYPE_BRIDGE)) { 1605 return; 1606 } 1607 1608 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 1609 if (!sec_bus) { 1610 return; 1611 } 1612 1613 s_fdt.fdt = p->fdt; 1614 s_fdt.node_off = offset; 1615 s_fdt.sphb = p->sphb; 1616 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 1617 spapr_populate_pci_devices_dt, 1618 &s_fdt); 1619 } 1620 1621 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, 1622 void *opaque) 1623 { 1624 unsigned int *bus_no = opaque; 1625 unsigned int primary = *bus_no; 1626 unsigned int subordinate = 0xff; 1627 PCIBus *sec_bus = NULL; 1628 1629 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 1630 PCI_HEADER_TYPE_BRIDGE)) { 1631 return; 1632 } 1633 1634 (*bus_no)++; 1635 pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1); 1636 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); 1637 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 1638 1639 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 1640 if (!sec_bus) { 1641 return; 1642 } 1643 1644 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1); 1645 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 1646 spapr_phb_pci_enumerate_bridge, bus_no); 1647 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 1648 } 1649 1650 static void spapr_phb_pci_enumerate(sPAPRPHBState *phb) 1651 { 1652 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 1653 unsigned int bus_no = 0; 1654 1655 pci_for_each_device(bus, pci_bus_num(bus), 1656 spapr_phb_pci_enumerate_bridge, 1657 &bus_no); 1658 1659 } 1660 1661 int spapr_populate_pci_dt(sPAPRPHBState *phb, 1662 uint32_t xics_phandle, 1663 void *fdt) 1664 { 1665 int bus_off, i, j, ret; 1666 char nodename[FDT_NAME_MAX]; 1667 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; 1668 const uint64_t mmiosize = memory_region_size(&phb->memwindow); 1669 const uint64_t w32max = (1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET; 1670 const uint64_t w32size = MIN(w32max, mmiosize); 1671 const uint64_t w64size = (mmiosize > w32size) ? (mmiosize - w32size) : 0; 1672 struct { 1673 uint32_t hi; 1674 uint64_t child; 1675 uint64_t parent; 1676 uint64_t size; 1677 } QEMU_PACKED ranges[] = { 1678 { 1679 cpu_to_be32(b_ss(1)), cpu_to_be64(0), 1680 cpu_to_be64(phb->io_win_addr), 1681 cpu_to_be64(memory_region_size(&phb->iospace)), 1682 }, 1683 { 1684 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), 1685 cpu_to_be64(phb->mem_win_addr), 1686 cpu_to_be64(w32size), 1687 }, 1688 { 1689 cpu_to_be32(b_ss(3)), cpu_to_be64(1ULL << 32), 1690 cpu_to_be64(phb->mem_win_addr + w32size), 1691 cpu_to_be64(w64size) 1692 }, 1693 }; 1694 const unsigned sizeof_ranges = (w64size ? 3 : 2) * sizeof(ranges[0]); 1695 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; 1696 uint32_t interrupt_map_mask[] = { 1697 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; 1698 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; 1699 sPAPRTCETable *tcet; 1700 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 1701 sPAPRFDT s_fdt; 1702 1703 /* Start populating the FDT */ 1704 snprintf(nodename, FDT_NAME_MAX, "pci@%" PRIx64, phb->buid); 1705 bus_off = fdt_add_subnode(fdt, 0, nodename); 1706 if (bus_off < 0) { 1707 return bus_off; 1708 } 1709 1710 /* Write PHB properties */ 1711 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); 1712 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); 1713 _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); 1714 _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); 1715 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); 1716 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); 1717 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); 1718 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); 1719 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); 1720 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); 1721 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS)); 1722 1723 /* Build the interrupt-map, this must matches what is done 1724 * in pci_spapr_map_irq 1725 */ 1726 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", 1727 &interrupt_map_mask, sizeof(interrupt_map_mask))); 1728 for (i = 0; i < PCI_SLOT_MAX; i++) { 1729 for (j = 0; j < PCI_NUM_PINS; j++) { 1730 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; 1731 int lsi_num = pci_spapr_swizzle(i, j); 1732 1733 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); 1734 irqmap[1] = 0; 1735 irqmap[2] = 0; 1736 irqmap[3] = cpu_to_be32(j+1); 1737 irqmap[4] = cpu_to_be32(xics_phandle); 1738 irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq); 1739 irqmap[6] = cpu_to_be32(0x8); 1740 } 1741 } 1742 /* Write interrupt map */ 1743 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, 1744 sizeof(interrupt_map))); 1745 1746 tcet = spapr_tce_find_by_liobn(SPAPR_PCI_LIOBN(phb->index, 0)); 1747 spapr_dma_dt(fdt, bus_off, "ibm,dma-window", 1748 tcet->liobn, tcet->bus_offset, 1749 tcet->nb_table << tcet->page_shift); 1750 1751 /* Walk the bridges and program the bus numbers*/ 1752 spapr_phb_pci_enumerate(phb); 1753 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); 1754 1755 /* Populate tree nodes with PCI devices attached */ 1756 s_fdt.fdt = fdt; 1757 s_fdt.node_off = bus_off; 1758 s_fdt.sphb = phb; 1759 pci_for_each_device(bus, pci_bus_num(bus), 1760 spapr_populate_pci_devices_dt, 1761 &s_fdt); 1762 1763 ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb), 1764 SPAPR_DR_CONNECTOR_TYPE_PCI); 1765 if (ret) { 1766 return ret; 1767 } 1768 1769 return 0; 1770 } 1771 1772 void spapr_pci_rtas_init(void) 1773 { 1774 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", 1775 rtas_read_pci_config); 1776 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", 1777 rtas_write_pci_config); 1778 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", 1779 rtas_ibm_read_pci_config); 1780 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", 1781 rtas_ibm_write_pci_config); 1782 if (msi_supported) { 1783 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, 1784 "ibm,query-interrupt-source-number", 1785 rtas_ibm_query_interrupt_source_number); 1786 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", 1787 rtas_ibm_change_msi); 1788 } 1789 1790 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, 1791 "ibm,set-eeh-option", 1792 rtas_ibm_set_eeh_option); 1793 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, 1794 "ibm,get-config-addr-info2", 1795 rtas_ibm_get_config_addr_info2); 1796 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, 1797 "ibm,read-slot-reset-state2", 1798 rtas_ibm_read_slot_reset_state2); 1799 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, 1800 "ibm,set-slot-reset", 1801 rtas_ibm_set_slot_reset); 1802 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, 1803 "ibm,configure-pe", 1804 rtas_ibm_configure_pe); 1805 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, 1806 "ibm,slot-error-detail", 1807 rtas_ibm_slot_error_detail); 1808 } 1809 1810 static void spapr_pci_register_types(void) 1811 { 1812 type_register_static(&spapr_phb_info); 1813 } 1814 1815 type_init(spapr_pci_register_types) 1816 1817 static int spapr_switch_one_vga(DeviceState *dev, void *opaque) 1818 { 1819 bool be = *(bool *)opaque; 1820 1821 if (object_dynamic_cast(OBJECT(dev), "VGA") 1822 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { 1823 object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", 1824 &error_abort); 1825 } 1826 return 0; 1827 } 1828 1829 void spapr_pci_switch_vga(bool big_endian) 1830 { 1831 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1832 sPAPRPHBState *sphb; 1833 1834 /* 1835 * For backward compatibility with existing guests, we switch 1836 * the endianness of the VGA controller when changing the guest 1837 * interrupt mode 1838 */ 1839 QLIST_FOREACH(sphb, &spapr->phbs, list) { 1840 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; 1841 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, 1842 &big_endian); 1843 } 1844 } 1845