1 /* 2 * QEMU sPAPR PCI host originated from Uninorth PCI host 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. 5 * Copyright (C) 2011 David Gibson, IBM Corporation. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "cpu.h" 29 #include "hw/irq.h" 30 #include "hw/sysbus.h" 31 #include "migration/vmstate.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/msi.h" 34 #include "hw/pci/msix.h" 35 #include "hw/pci/pci_host.h" 36 #include "hw/ppc/spapr.h" 37 #include "hw/pci-host/spapr.h" 38 #include "exec/address-spaces.h" 39 #include "exec/ram_addr.h" 40 #include <libfdt.h> 41 #include "trace.h" 42 #include "qemu/error-report.h" 43 #include "qemu/module.h" 44 #include "qapi/qmp/qerror.h" 45 #include "hw/ppc/fdt.h" 46 #include "hw/pci/pci_bridge.h" 47 #include "hw/pci/pci_bus.h" 48 #include "hw/pci/pci_ids.h" 49 #include "hw/ppc/spapr_drc.h" 50 #include "hw/qdev-properties.h" 51 #include "sysemu/device_tree.h" 52 #include "sysemu/kvm.h" 53 #include "sysemu/hostmem.h" 54 #include "sysemu/numa.h" 55 56 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ 57 #define RTAS_QUERY_FN 0 58 #define RTAS_CHANGE_FN 1 59 #define RTAS_RESET_FN 2 60 #define RTAS_CHANGE_MSI_FN 3 61 #define RTAS_CHANGE_MSIX_FN 4 62 63 /* Interrupt types to return on RTAS_CHANGE_* */ 64 #define RTAS_TYPE_MSI 1 65 #define RTAS_TYPE_MSIX 2 66 67 SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid) 68 { 69 SpaprPhbState *sphb; 70 71 QLIST_FOREACH(sphb, &spapr->phbs, list) { 72 if (sphb->buid != buid) { 73 continue; 74 } 75 return sphb; 76 } 77 78 return NULL; 79 } 80 81 PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid, 82 uint32_t config_addr) 83 { 84 SpaprPhbState *sphb = spapr_pci_find_phb(spapr, buid); 85 PCIHostState *phb = PCI_HOST_BRIDGE(sphb); 86 int bus_num = (config_addr >> 16) & 0xFF; 87 int devfn = (config_addr >> 8) & 0xFF; 88 89 if (!phb) { 90 return NULL; 91 } 92 93 return pci_find_device(phb->bus, bus_num, devfn); 94 } 95 96 static uint32_t rtas_pci_cfgaddr(uint32_t arg) 97 { 98 /* This handles the encoding of extended config space addresses */ 99 return ((arg >> 20) & 0xf00) | (arg & 0xff); 100 } 101 102 static void finish_read_pci_config(SpaprMachineState *spapr, uint64_t buid, 103 uint32_t addr, uint32_t size, 104 target_ulong rets) 105 { 106 PCIDevice *pci_dev; 107 uint32_t val; 108 109 if ((size != 1) && (size != 2) && (size != 4)) { 110 /* access must be 1, 2 or 4 bytes */ 111 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 112 return; 113 } 114 115 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 116 addr = rtas_pci_cfgaddr(addr); 117 118 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 119 /* Access must be to a valid device, within bounds and 120 * naturally aligned */ 121 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 122 return; 123 } 124 125 val = pci_host_config_read_common(pci_dev, addr, 126 pci_config_size(pci_dev), size); 127 128 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 129 rtas_st(rets, 1, val); 130 } 131 132 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 133 uint32_t token, uint32_t nargs, 134 target_ulong args, 135 uint32_t nret, target_ulong rets) 136 { 137 uint64_t buid; 138 uint32_t size, addr; 139 140 if ((nargs != 4) || (nret != 2)) { 141 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 142 return; 143 } 144 145 buid = rtas_ldq(args, 1); 146 size = rtas_ld(args, 3); 147 addr = rtas_ld(args, 0); 148 149 finish_read_pci_config(spapr, buid, addr, size, rets); 150 } 151 152 static void rtas_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 153 uint32_t token, uint32_t nargs, 154 target_ulong args, 155 uint32_t nret, target_ulong rets) 156 { 157 uint32_t size, addr; 158 159 if ((nargs != 2) || (nret != 2)) { 160 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 161 return; 162 } 163 164 size = rtas_ld(args, 1); 165 addr = rtas_ld(args, 0); 166 167 finish_read_pci_config(spapr, 0, addr, size, rets); 168 } 169 170 static void finish_write_pci_config(SpaprMachineState *spapr, uint64_t buid, 171 uint32_t addr, uint32_t size, 172 uint32_t val, target_ulong rets) 173 { 174 PCIDevice *pci_dev; 175 176 if ((size != 1) && (size != 2) && (size != 4)) { 177 /* access must be 1, 2 or 4 bytes */ 178 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 179 return; 180 } 181 182 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 183 addr = rtas_pci_cfgaddr(addr); 184 185 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 186 /* Access must be to a valid device, within bounds and 187 * naturally aligned */ 188 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 189 return; 190 } 191 192 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), 193 val, size); 194 195 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 196 } 197 198 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 199 uint32_t token, uint32_t nargs, 200 target_ulong args, 201 uint32_t nret, target_ulong rets) 202 { 203 uint64_t buid; 204 uint32_t val, size, addr; 205 206 if ((nargs != 5) || (nret != 1)) { 207 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 208 return; 209 } 210 211 buid = rtas_ldq(args, 1); 212 val = rtas_ld(args, 4); 213 size = rtas_ld(args, 3); 214 addr = rtas_ld(args, 0); 215 216 finish_write_pci_config(spapr, buid, addr, size, val, rets); 217 } 218 219 static void rtas_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 220 uint32_t token, uint32_t nargs, 221 target_ulong args, 222 uint32_t nret, target_ulong rets) 223 { 224 uint32_t val, size, addr; 225 226 if ((nargs != 3) || (nret != 1)) { 227 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 228 return; 229 } 230 231 232 val = rtas_ld(args, 2); 233 size = rtas_ld(args, 1); 234 addr = rtas_ld(args, 0); 235 236 finish_write_pci_config(spapr, 0, addr, size, val, rets); 237 } 238 239 /* 240 * Set MSI/MSIX message data. 241 * This is required for msi_notify()/msix_notify() which 242 * will write at the addresses via spapr_msi_write(). 243 * 244 * If hwaddr == 0, all entries will have .data == first_irq i.e. 245 * table will be reset. 246 */ 247 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, 248 unsigned first_irq, unsigned req_num) 249 { 250 unsigned i; 251 MSIMessage msg = { .address = addr, .data = first_irq }; 252 253 if (!msix) { 254 msi_set_message(pdev, msg); 255 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); 256 return; 257 } 258 259 for (i = 0; i < req_num; ++i) { 260 msix_set_message(pdev, i, msg); 261 trace_spapr_pci_msi_setup(pdev->name, i, msg.address); 262 if (addr) { 263 ++msg.data; 264 } 265 } 266 } 267 268 static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr, 269 uint32_t token, uint32_t nargs, 270 target_ulong args, uint32_t nret, 271 target_ulong rets) 272 { 273 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 274 uint32_t config_addr = rtas_ld(args, 0); 275 uint64_t buid = rtas_ldq(args, 1); 276 unsigned int func = rtas_ld(args, 3); 277 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ 278 unsigned int seq_num = rtas_ld(args, 5); 279 unsigned int ret_intr_type; 280 unsigned int irq, max_irqs = 0; 281 SpaprPhbState *phb = NULL; 282 PCIDevice *pdev = NULL; 283 SpaprPciMsi *msi; 284 int *config_addr_key; 285 Error *err = NULL; 286 int i; 287 288 /* Fins SpaprPhbState */ 289 phb = spapr_pci_find_phb(spapr, buid); 290 if (phb) { 291 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 292 } 293 if (!phb || !pdev) { 294 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 295 return; 296 } 297 298 switch (func) { 299 case RTAS_CHANGE_FN: 300 if (msi_present(pdev)) { 301 ret_intr_type = RTAS_TYPE_MSI; 302 } else if (msix_present(pdev)) { 303 ret_intr_type = RTAS_TYPE_MSIX; 304 } else { 305 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 306 return; 307 } 308 break; 309 case RTAS_CHANGE_MSI_FN: 310 if (msi_present(pdev)) { 311 ret_intr_type = RTAS_TYPE_MSI; 312 } else { 313 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 314 return; 315 } 316 break; 317 case RTAS_CHANGE_MSIX_FN: 318 if (msix_present(pdev)) { 319 ret_intr_type = RTAS_TYPE_MSIX; 320 } else { 321 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 322 return; 323 } 324 break; 325 default: 326 error_report("rtas_ibm_change_msi(%u) is not implemented", func); 327 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 328 return; 329 } 330 331 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr); 332 333 /* Releasing MSIs */ 334 if (!req_num) { 335 if (!msi) { 336 trace_spapr_pci_msi("Releasing wrong config", config_addr); 337 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 338 return; 339 } 340 341 if (msi_present(pdev)) { 342 spapr_msi_setmsg(pdev, 0, false, 0, 0); 343 } 344 if (msix_present(pdev)) { 345 spapr_msi_setmsg(pdev, 0, true, 0, 0); 346 } 347 g_hash_table_remove(phb->msi, &config_addr); 348 349 trace_spapr_pci_msi("Released MSIs", config_addr); 350 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 351 rtas_st(rets, 1, 0); 352 return; 353 } 354 355 /* Enabling MSI */ 356 357 /* Check if the device supports as many IRQs as requested */ 358 if (ret_intr_type == RTAS_TYPE_MSI) { 359 max_irqs = msi_nr_vectors_allocated(pdev); 360 } else if (ret_intr_type == RTAS_TYPE_MSIX) { 361 max_irqs = pdev->msix_entries_nr; 362 } 363 if (!max_irqs) { 364 error_report("Requested interrupt type %d is not enabled for device %x", 365 ret_intr_type, config_addr); 366 rtas_st(rets, 0, -1); /* Hardware error */ 367 return; 368 } 369 /* Correct the number if the guest asked for too many */ 370 if (req_num > max_irqs) { 371 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); 372 req_num = max_irqs; 373 irq = 0; /* to avoid misleading trace */ 374 goto out; 375 } 376 377 /* Allocate MSIs */ 378 if (smc->legacy_irq_allocation) { 379 irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI, 380 &err); 381 } else { 382 irq = spapr_irq_msi_alloc(spapr, req_num, 383 ret_intr_type == RTAS_TYPE_MSI, &err); 384 } 385 if (err) { 386 error_reportf_err(err, "Can't allocate MSIs for device %x: ", 387 config_addr); 388 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 389 return; 390 } 391 392 for (i = 0; i < req_num; i++) { 393 spapr_irq_claim(spapr, irq + i, false, &err); 394 if (err) { 395 if (i) { 396 spapr_irq_free(spapr, irq, i); 397 } 398 if (!smc->legacy_irq_allocation) { 399 spapr_irq_msi_free(spapr, irq, req_num); 400 } 401 error_reportf_err(err, "Can't allocate MSIs for device %x: ", 402 config_addr); 403 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 404 return; 405 } 406 } 407 408 /* Release previous MSIs */ 409 if (msi) { 410 g_hash_table_remove(phb->msi, &config_addr); 411 } 412 413 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ 414 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, 415 irq, req_num); 416 417 /* Add MSI device to cache */ 418 msi = g_new(SpaprPciMsi, 1); 419 msi->first_irq = irq; 420 msi->num = req_num; 421 config_addr_key = g_new(int, 1); 422 *config_addr_key = config_addr; 423 g_hash_table_insert(phb->msi, config_addr_key, msi); 424 425 out: 426 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 427 rtas_st(rets, 1, req_num); 428 rtas_st(rets, 2, ++seq_num); 429 if (nret > 3) { 430 rtas_st(rets, 3, ret_intr_type); 431 } 432 433 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); 434 } 435 436 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, 437 SpaprMachineState *spapr, 438 uint32_t token, 439 uint32_t nargs, 440 target_ulong args, 441 uint32_t nret, 442 target_ulong rets) 443 { 444 uint32_t config_addr = rtas_ld(args, 0); 445 uint64_t buid = rtas_ldq(args, 1); 446 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); 447 SpaprPhbState *phb = NULL; 448 PCIDevice *pdev = NULL; 449 SpaprPciMsi *msi; 450 451 /* Find SpaprPhbState */ 452 phb = spapr_pci_find_phb(spapr, buid); 453 if (phb) { 454 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 455 } 456 if (!phb || !pdev) { 457 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 458 return; 459 } 460 461 /* Find device descriptor and start IRQ */ 462 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr); 463 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { 464 trace_spapr_pci_msi("Failed to return vector", config_addr); 465 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 466 return; 467 } 468 intr_src_num = msi->first_irq + ioa_intr_num; 469 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, 470 intr_src_num); 471 472 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 473 rtas_st(rets, 1, intr_src_num); 474 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ 475 } 476 477 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, 478 SpaprMachineState *spapr, 479 uint32_t token, uint32_t nargs, 480 target_ulong args, uint32_t nret, 481 target_ulong rets) 482 { 483 SpaprPhbState *sphb; 484 uint32_t addr, option; 485 uint64_t buid; 486 int ret; 487 488 if ((nargs != 4) || (nret != 1)) { 489 goto param_error_exit; 490 } 491 492 buid = rtas_ldq(args, 1); 493 addr = rtas_ld(args, 0); 494 option = rtas_ld(args, 3); 495 496 sphb = spapr_pci_find_phb(spapr, buid); 497 if (!sphb) { 498 goto param_error_exit; 499 } 500 501 if (!spapr_phb_eeh_available(sphb)) { 502 goto param_error_exit; 503 } 504 505 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option); 506 rtas_st(rets, 0, ret); 507 return; 508 509 param_error_exit: 510 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 511 } 512 513 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, 514 SpaprMachineState *spapr, 515 uint32_t token, uint32_t nargs, 516 target_ulong args, uint32_t nret, 517 target_ulong rets) 518 { 519 SpaprPhbState *sphb; 520 PCIDevice *pdev; 521 uint32_t addr, option; 522 uint64_t buid; 523 524 if ((nargs != 4) || (nret != 2)) { 525 goto param_error_exit; 526 } 527 528 buid = rtas_ldq(args, 1); 529 sphb = spapr_pci_find_phb(spapr, buid); 530 if (!sphb) { 531 goto param_error_exit; 532 } 533 534 if (!spapr_phb_eeh_available(sphb)) { 535 goto param_error_exit; 536 } 537 538 /* 539 * We always have PE address of form "00BB0001". "BB" 540 * represents the bus number of PE's primary bus. 541 */ 542 option = rtas_ld(args, 3); 543 switch (option) { 544 case RTAS_GET_PE_ADDR: 545 addr = rtas_ld(args, 0); 546 pdev = spapr_pci_find_dev(spapr, buid, addr); 547 if (!pdev) { 548 goto param_error_exit; 549 } 550 551 rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1); 552 break; 553 case RTAS_GET_PE_MODE: 554 rtas_st(rets, 1, RTAS_PE_MODE_SHARED); 555 break; 556 default: 557 goto param_error_exit; 558 } 559 560 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 561 return; 562 563 param_error_exit: 564 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 565 } 566 567 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, 568 SpaprMachineState *spapr, 569 uint32_t token, uint32_t nargs, 570 target_ulong args, uint32_t nret, 571 target_ulong rets) 572 { 573 SpaprPhbState *sphb; 574 uint64_t buid; 575 int state, ret; 576 577 if ((nargs != 3) || (nret != 4 && nret != 5)) { 578 goto param_error_exit; 579 } 580 581 buid = rtas_ldq(args, 1); 582 sphb = spapr_pci_find_phb(spapr, buid); 583 if (!sphb) { 584 goto param_error_exit; 585 } 586 587 if (!spapr_phb_eeh_available(sphb)) { 588 goto param_error_exit; 589 } 590 591 ret = spapr_phb_vfio_eeh_get_state(sphb, &state); 592 rtas_st(rets, 0, ret); 593 if (ret != RTAS_OUT_SUCCESS) { 594 return; 595 } 596 597 rtas_st(rets, 1, state); 598 rtas_st(rets, 2, RTAS_EEH_SUPPORT); 599 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); 600 if (nret >= 5) { 601 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); 602 } 603 return; 604 605 param_error_exit: 606 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 607 } 608 609 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, 610 SpaprMachineState *spapr, 611 uint32_t token, uint32_t nargs, 612 target_ulong args, uint32_t nret, 613 target_ulong rets) 614 { 615 SpaprPhbState *sphb; 616 uint32_t option; 617 uint64_t buid; 618 int ret; 619 620 if ((nargs != 4) || (nret != 1)) { 621 goto param_error_exit; 622 } 623 624 buid = rtas_ldq(args, 1); 625 option = rtas_ld(args, 3); 626 sphb = spapr_pci_find_phb(spapr, buid); 627 if (!sphb) { 628 goto param_error_exit; 629 } 630 631 if (!spapr_phb_eeh_available(sphb)) { 632 goto param_error_exit; 633 } 634 635 ret = spapr_phb_vfio_eeh_reset(sphb, option); 636 rtas_st(rets, 0, ret); 637 return; 638 639 param_error_exit: 640 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 641 } 642 643 static void rtas_ibm_configure_pe(PowerPCCPU *cpu, 644 SpaprMachineState *spapr, 645 uint32_t token, uint32_t nargs, 646 target_ulong args, uint32_t nret, 647 target_ulong rets) 648 { 649 SpaprPhbState *sphb; 650 uint64_t buid; 651 int ret; 652 653 if ((nargs != 3) || (nret != 1)) { 654 goto param_error_exit; 655 } 656 657 buid = rtas_ldq(args, 1); 658 sphb = spapr_pci_find_phb(spapr, buid); 659 if (!sphb) { 660 goto param_error_exit; 661 } 662 663 if (!spapr_phb_eeh_available(sphb)) { 664 goto param_error_exit; 665 } 666 667 ret = spapr_phb_vfio_eeh_configure(sphb); 668 rtas_st(rets, 0, ret); 669 return; 670 671 param_error_exit: 672 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 673 } 674 675 /* To support it later */ 676 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, 677 SpaprMachineState *spapr, 678 uint32_t token, uint32_t nargs, 679 target_ulong args, uint32_t nret, 680 target_ulong rets) 681 { 682 SpaprPhbState *sphb; 683 int option; 684 uint64_t buid; 685 686 if ((nargs != 8) || (nret != 1)) { 687 goto param_error_exit; 688 } 689 690 buid = rtas_ldq(args, 1); 691 sphb = spapr_pci_find_phb(spapr, buid); 692 if (!sphb) { 693 goto param_error_exit; 694 } 695 696 if (!spapr_phb_eeh_available(sphb)) { 697 goto param_error_exit; 698 } 699 700 option = rtas_ld(args, 7); 701 switch (option) { 702 case RTAS_SLOT_TEMP_ERR_LOG: 703 case RTAS_SLOT_PERM_ERR_LOG: 704 break; 705 default: 706 goto param_error_exit; 707 } 708 709 /* We don't have error log yet */ 710 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); 711 return; 712 713 param_error_exit: 714 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 715 } 716 717 static void pci_spapr_set_irq(void *opaque, int irq_num, int level) 718 { 719 /* 720 * Here we use the number returned by pci_swizzle_map_irq_fn to find a 721 * corresponding qemu_irq. 722 */ 723 SpaprPhbState *phb = opaque; 724 725 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); 726 qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); 727 } 728 729 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) 730 { 731 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); 732 PCIINTxRoute route; 733 734 route.mode = PCI_INTX_ENABLED; 735 route.irq = sphb->lsi_table[pin].irq; 736 737 return route; 738 } 739 740 /* 741 * MSI/MSIX memory region implementation. 742 * The handler handles both MSI and MSIX. 743 * The vector number is encoded in least bits in data. 744 */ 745 static void spapr_msi_write(void *opaque, hwaddr addr, 746 uint64_t data, unsigned size) 747 { 748 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 749 uint32_t irq = data; 750 751 trace_spapr_pci_msi_write(addr, data, irq); 752 753 qemu_irq_pulse(spapr_qirq(spapr, irq)); 754 } 755 756 static const MemoryRegionOps spapr_msi_ops = { 757 /* There is no .read as the read result is undefined by PCI spec */ 758 .read = NULL, 759 .write = spapr_msi_write, 760 .endianness = DEVICE_LITTLE_ENDIAN 761 }; 762 763 /* 764 * PHB PCI device 765 */ 766 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 767 { 768 SpaprPhbState *phb = opaque; 769 770 return &phb->iommu_as; 771 } 772 773 static char *spapr_phb_vfio_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) 774 { 775 char *path = NULL, *buf = NULL, *host = NULL; 776 777 /* Get the PCI VFIO host id */ 778 host = object_property_get_str(OBJECT(pdev), "host", NULL); 779 if (!host) { 780 goto err_out; 781 } 782 783 /* Construct the path of the file that will give us the DT location */ 784 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); 785 g_free(host); 786 if (!g_file_get_contents(path, &buf, NULL, NULL)) { 787 goto err_out; 788 } 789 g_free(path); 790 791 /* Construct and read from host device tree the loc-code */ 792 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); 793 g_free(buf); 794 if (!g_file_get_contents(path, &buf, NULL, NULL)) { 795 goto err_out; 796 } 797 return buf; 798 799 err_out: 800 g_free(path); 801 return NULL; 802 } 803 804 static char *spapr_phb_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) 805 { 806 char *buf; 807 const char *devtype = "qemu"; 808 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 809 810 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 811 buf = spapr_phb_vfio_get_loc_code(sphb, pdev); 812 if (buf) { 813 return buf; 814 } 815 devtype = "vfio"; 816 } 817 /* 818 * For emulated devices and VFIO-failure case, make up 819 * the loc-code. 820 */ 821 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", 822 devtype, pdev->name, sphb->index, busnr, 823 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 824 return buf; 825 } 826 827 /* Macros to operate with address in OF binding to PCI */ 828 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) 829 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ 830 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ 831 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ 832 #define b_ss(x) b_x((x), 24, 2) /* the space code */ 833 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ 834 #define b_ddddd(x) b_x((x), 11, 5) /* device number */ 835 #define b_fff(x) b_x((x), 8, 3) /* function number */ 836 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ 837 838 /* for 'reg' OF properties */ 839 #define RESOURCE_CELLS_SIZE 2 840 #define RESOURCE_CELLS_ADDRESS 3 841 842 typedef struct ResourceFields { 843 uint32_t phys_hi; 844 uint32_t phys_mid; 845 uint32_t phys_lo; 846 uint32_t size_hi; 847 uint32_t size_lo; 848 } QEMU_PACKED ResourceFields; 849 850 typedef struct ResourceProps { 851 ResourceFields reg[8]; 852 uint32_t reg_len; 853 } ResourceProps; 854 855 /* fill in the 'reg' OF properties for 856 * a PCI device. 'reg' describes resource requirements for a 857 * device's IO/MEM regions. 858 * 859 * the property is an array of ('phys-addr', 'size') pairs describing 860 * the addressable regions of the PCI device, where 'phys-addr' is a 861 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to 862 * (phys.hi, phys.mid, phys.lo), and 'size' is a 863 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). 864 * 865 * phys.hi = 0xYYXXXXZZ, where: 866 * 0xYY = npt000ss 867 * ||| | 868 * ||| +-- space code 869 * ||| | 870 * ||| + 00 if configuration space 871 * ||| + 01 if IO region, 872 * ||| + 10 if 32-bit MEM region 873 * ||| + 11 if 64-bit MEM region 874 * ||| 875 * ||+------ for non-relocatable IO: 1 if aliased 876 * || for relocatable IO: 1 if below 64KB 877 * || for MEM: 1 if below 1MB 878 * |+------- 1 if region is prefetchable 879 * +-------- 1 if region is non-relocatable 880 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function 881 * bits respectively 882 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding 883 * to the region 884 * 885 * phys.mid and phys.lo correspond respectively to the hi/lo portions 886 * of the actual address of the region. 887 * 888 * note also that addresses defined in this property are, at least 889 * for PAPR guests, relative to the PHBs IO/MEM windows, and 890 * correspond directly to the addresses in the BARs. 891 * 892 * in accordance with PCI Bus Binding to Open Firmware, 893 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, 894 * Appendix C. 895 */ 896 static void populate_resource_props(PCIDevice *d, ResourceProps *rp) 897 { 898 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); 899 uint32_t dev_id = (b_bbbbbbbb(bus_num) | 900 b_ddddd(PCI_SLOT(d->devfn)) | 901 b_fff(PCI_FUNC(d->devfn))); 902 ResourceFields *reg; 903 int i, reg_idx = 0; 904 905 /* config space region */ 906 reg = &rp->reg[reg_idx++]; 907 reg->phys_hi = cpu_to_be32(dev_id); 908 reg->phys_mid = 0; 909 reg->phys_lo = 0; 910 reg->size_hi = 0; 911 reg->size_lo = 0; 912 913 for (i = 0; i < PCI_NUM_REGIONS; i++) { 914 if (!d->io_regions[i].size) { 915 continue; 916 } 917 918 reg = &rp->reg[reg_idx++]; 919 920 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); 921 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 922 reg->phys_hi |= cpu_to_be32(b_ss(1)); 923 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 924 reg->phys_hi |= cpu_to_be32(b_ss(3)); 925 } else { 926 reg->phys_hi |= cpu_to_be32(b_ss(2)); 927 } 928 reg->phys_mid = 0; 929 reg->phys_lo = 0; 930 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); 931 reg->size_lo = cpu_to_be32(d->io_regions[i].size); 932 } 933 934 rp->reg_len = reg_idx * sizeof(ResourceFields); 935 } 936 937 typedef struct PCIClass PCIClass; 938 typedef struct PCISubClass PCISubClass; 939 typedef struct PCIIFace PCIIFace; 940 941 struct PCIIFace { 942 int iface; 943 const char *name; 944 }; 945 946 struct PCISubClass { 947 int subclass; 948 const char *name; 949 const PCIIFace *iface; 950 }; 951 952 struct PCIClass { 953 const char *name; 954 const PCISubClass *subc; 955 }; 956 957 static const PCISubClass undef_subclass[] = { 958 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL }, 959 { 0xFF, NULL, NULL }, 960 }; 961 962 static const PCISubClass mass_subclass[] = { 963 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL }, 964 { PCI_CLASS_STORAGE_IDE, "ide", NULL }, 965 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL }, 966 { PCI_CLASS_STORAGE_IPI, "ipi", NULL }, 967 { PCI_CLASS_STORAGE_RAID, "raid", NULL }, 968 { PCI_CLASS_STORAGE_ATA, "ata", NULL }, 969 { PCI_CLASS_STORAGE_SATA, "sata", NULL }, 970 { PCI_CLASS_STORAGE_SAS, "sas", NULL }, 971 { 0xFF, NULL, NULL }, 972 }; 973 974 static const PCISubClass net_subclass[] = { 975 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL }, 976 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL }, 977 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL }, 978 { PCI_CLASS_NETWORK_ATM, "atm", NULL }, 979 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL }, 980 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL }, 981 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL }, 982 { 0xFF, NULL, NULL }, 983 }; 984 985 static const PCISubClass displ_subclass[] = { 986 { PCI_CLASS_DISPLAY_VGA, "vga", NULL }, 987 { PCI_CLASS_DISPLAY_XGA, "xga", NULL }, 988 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL }, 989 { 0xFF, NULL, NULL }, 990 }; 991 992 static const PCISubClass media_subclass[] = { 993 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL }, 994 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL }, 995 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL }, 996 { 0xFF, NULL, NULL }, 997 }; 998 999 static const PCISubClass mem_subclass[] = { 1000 { PCI_CLASS_MEMORY_RAM, "memory", NULL }, 1001 { PCI_CLASS_MEMORY_FLASH, "flash", NULL }, 1002 { 0xFF, NULL, NULL }, 1003 }; 1004 1005 static const PCISubClass bridg_subclass[] = { 1006 { PCI_CLASS_BRIDGE_HOST, "host", NULL }, 1007 { PCI_CLASS_BRIDGE_ISA, "isa", NULL }, 1008 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL }, 1009 { PCI_CLASS_BRIDGE_MC, "mca", NULL }, 1010 { PCI_CLASS_BRIDGE_PCI, "pci", NULL }, 1011 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL }, 1012 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL }, 1013 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL }, 1014 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL }, 1015 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL }, 1016 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL }, 1017 { 0xFF, NULL, NULL }, 1018 }; 1019 1020 static const PCISubClass comm_subclass[] = { 1021 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL }, 1022 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL }, 1023 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL }, 1024 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL }, 1025 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL }, 1026 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL }, 1027 { 0xFF, NULL, NULL, }, 1028 }; 1029 1030 static const PCIIFace pic_iface[] = { 1031 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" }, 1032 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" }, 1033 { 0xFF, NULL }, 1034 }; 1035 1036 static const PCISubClass sys_subclass[] = { 1037 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface }, 1038 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL }, 1039 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL }, 1040 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL }, 1041 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL }, 1042 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL }, 1043 { 0xFF, NULL, NULL }, 1044 }; 1045 1046 static const PCISubClass inp_subclass[] = { 1047 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL }, 1048 { PCI_CLASS_INPUT_PEN, "pen", NULL }, 1049 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL }, 1050 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL }, 1051 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL }, 1052 { 0xFF, NULL, NULL }, 1053 }; 1054 1055 static const PCISubClass dock_subclass[] = { 1056 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL }, 1057 { 0xFF, NULL, NULL }, 1058 }; 1059 1060 static const PCISubClass cpu_subclass[] = { 1061 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL }, 1062 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL }, 1063 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL }, 1064 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL }, 1065 { 0xFF, NULL, NULL }, 1066 }; 1067 1068 static const PCIIFace usb_iface[] = { 1069 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" }, 1070 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", }, 1071 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" }, 1072 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" }, 1073 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" }, 1074 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" }, 1075 { 0xFF, NULL }, 1076 }; 1077 1078 static const PCISubClass ser_subclass[] = { 1079 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL }, 1080 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL }, 1081 { PCI_CLASS_SERIAL_SSA, "ssa", NULL }, 1082 { PCI_CLASS_SERIAL_USB, "usb", usb_iface }, 1083 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL }, 1084 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL }, 1085 { PCI_CLASS_SERIAL_IB, "infiniband", NULL }, 1086 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL }, 1087 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL }, 1088 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL }, 1089 { 0xFF, NULL, NULL }, 1090 }; 1091 1092 static const PCISubClass wrl_subclass[] = { 1093 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL }, 1094 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL }, 1095 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL }, 1096 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL }, 1097 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL }, 1098 { 0xFF, NULL, NULL }, 1099 }; 1100 1101 static const PCISubClass sat_subclass[] = { 1102 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL }, 1103 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL }, 1104 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL }, 1105 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL }, 1106 { 0xFF, NULL, NULL }, 1107 }; 1108 1109 static const PCISubClass crypt_subclass[] = { 1110 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL }, 1111 { PCI_CLASS_CRYPT_ENTERTAINMENT, 1112 "entertainment-encryption", NULL }, 1113 { 0xFF, NULL, NULL }, 1114 }; 1115 1116 static const PCISubClass spc_subclass[] = { 1117 { PCI_CLASS_SP_DPIO, "dpio", NULL }, 1118 { PCI_CLASS_SP_PERF, "counter", NULL }, 1119 { PCI_CLASS_SP_SYNCH, "measurement", NULL }, 1120 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL }, 1121 { 0xFF, NULL, NULL }, 1122 }; 1123 1124 static const PCIClass pci_classes[] = { 1125 { "legacy-device", undef_subclass }, 1126 { "mass-storage", mass_subclass }, 1127 { "network", net_subclass }, 1128 { "display", displ_subclass, }, 1129 { "multimedia-device", media_subclass }, 1130 { "memory-controller", mem_subclass }, 1131 { "unknown-bridge", bridg_subclass }, 1132 { "communication-controller", comm_subclass}, 1133 { "system-peripheral", sys_subclass }, 1134 { "input-controller", inp_subclass }, 1135 { "docking-station", dock_subclass }, 1136 { "cpu", cpu_subclass }, 1137 { "serial-bus", ser_subclass }, 1138 { "wireless-controller", wrl_subclass }, 1139 { "intelligent-io", NULL }, 1140 { "satellite-device", sat_subclass }, 1141 { "encryption", crypt_subclass }, 1142 { "data-processing-controller", spc_subclass }, 1143 }; 1144 1145 static const char *dt_name_from_class(uint8_t class, uint8_t subclass, 1146 uint8_t iface) 1147 { 1148 const PCIClass *pclass; 1149 const PCISubClass *psubclass; 1150 const PCIIFace *piface; 1151 const char *name; 1152 1153 if (class >= ARRAY_SIZE(pci_classes)) { 1154 return "pci"; 1155 } 1156 1157 pclass = pci_classes + class; 1158 name = pclass->name; 1159 1160 if (pclass->subc == NULL) { 1161 return name; 1162 } 1163 1164 psubclass = pclass->subc; 1165 while ((psubclass->subclass & 0xff) != 0xff) { 1166 if ((psubclass->subclass & 0xff) == subclass) { 1167 name = psubclass->name; 1168 break; 1169 } 1170 psubclass++; 1171 } 1172 1173 piface = psubclass->iface; 1174 if (piface == NULL) { 1175 return name; 1176 } 1177 while ((piface->iface & 0xff) != 0xff) { 1178 if ((piface->iface & 0xff) == iface) { 1179 name = piface->name; 1180 break; 1181 } 1182 piface++; 1183 } 1184 1185 return name; 1186 } 1187 1188 /* 1189 * DRC helper functions 1190 */ 1191 1192 static uint32_t drc_id_from_devfn(SpaprPhbState *phb, 1193 uint8_t chassis, int32_t devfn) 1194 { 1195 return (phb->index << 16) | (chassis << 8) | devfn; 1196 } 1197 1198 static SpaprDrc *drc_from_devfn(SpaprPhbState *phb, 1199 uint8_t chassis, int32_t devfn) 1200 { 1201 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI, 1202 drc_id_from_devfn(phb, chassis, devfn)); 1203 } 1204 1205 static uint8_t chassis_from_bus(PCIBus *bus, Error **errp) 1206 { 1207 if (pci_bus_is_root(bus)) { 1208 return 0; 1209 } else { 1210 PCIDevice *bridge = pci_bridge_get_device(bus); 1211 1212 return object_property_get_uint(OBJECT(bridge), "chassis_nr", errp); 1213 } 1214 } 1215 1216 static SpaprDrc *drc_from_dev(SpaprPhbState *phb, PCIDevice *dev) 1217 { 1218 Error *local_err = NULL; 1219 uint8_t chassis = chassis_from_bus(pci_get_bus(dev), &local_err); 1220 1221 if (local_err) { 1222 error_report_err(local_err); 1223 return NULL; 1224 } 1225 1226 return drc_from_devfn(phb, chassis, dev->devfn); 1227 } 1228 1229 static void add_drcs(SpaprPhbState *phb, PCIBus *bus, Error **errp) 1230 { 1231 Object *owner; 1232 int i; 1233 uint8_t chassis; 1234 Error *local_err = NULL; 1235 1236 if (!phb->dr_enabled) { 1237 return; 1238 } 1239 1240 chassis = chassis_from_bus(bus, &local_err); 1241 if (local_err) { 1242 error_propagate(errp, local_err); 1243 return; 1244 } 1245 1246 if (pci_bus_is_root(bus)) { 1247 owner = OBJECT(phb); 1248 } else { 1249 owner = OBJECT(pci_bridge_get_device(bus)); 1250 } 1251 1252 for (i = 0; i < PCI_SLOT_MAX * PCI_FUNC_MAX; i++) { 1253 spapr_dr_connector_new(owner, TYPE_SPAPR_DRC_PCI, 1254 drc_id_from_devfn(phb, chassis, i)); 1255 } 1256 } 1257 1258 static void remove_drcs(SpaprPhbState *phb, PCIBus *bus, Error **errp) 1259 { 1260 int i; 1261 uint8_t chassis; 1262 Error *local_err = NULL; 1263 1264 if (!phb->dr_enabled) { 1265 return; 1266 } 1267 1268 chassis = chassis_from_bus(bus, &local_err); 1269 if (local_err) { 1270 error_propagate(errp, local_err); 1271 return; 1272 } 1273 1274 for (i = PCI_SLOT_MAX * PCI_FUNC_MAX - 1; i >= 0; i--) { 1275 SpaprDrc *drc = drc_from_devfn(phb, chassis, i); 1276 1277 if (drc) { 1278 object_unparent(OBJECT(drc)); 1279 } 1280 } 1281 } 1282 1283 typedef struct PciWalkFdt { 1284 void *fdt; 1285 int offset; 1286 SpaprPhbState *sphb; 1287 int err; 1288 } PciWalkFdt; 1289 1290 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev, 1291 void *fdt, int parent_offset); 1292 1293 static void spapr_dt_pci_device_cb(PCIBus *bus, PCIDevice *pdev, 1294 void *opaque) 1295 { 1296 PciWalkFdt *p = opaque; 1297 int err; 1298 1299 if (p->err) { 1300 /* Something's already broken, don't keep going */ 1301 return; 1302 } 1303 1304 err = spapr_dt_pci_device(p->sphb, pdev, p->fdt, p->offset); 1305 if (err < 0) { 1306 p->err = err; 1307 } 1308 } 1309 1310 /* Augment PCI device node with bridge specific information */ 1311 static int spapr_dt_pci_bus(SpaprPhbState *sphb, PCIBus *bus, 1312 void *fdt, int offset) 1313 { 1314 Object *owner; 1315 PciWalkFdt cbinfo = { 1316 .fdt = fdt, 1317 .offset = offset, 1318 .sphb = sphb, 1319 .err = 0, 1320 }; 1321 int ret; 1322 1323 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 1324 RESOURCE_CELLS_ADDRESS)); 1325 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1326 RESOURCE_CELLS_SIZE)); 1327 1328 assert(bus); 1329 pci_for_each_device_reverse(bus, pci_bus_num(bus), 1330 spapr_dt_pci_device_cb, &cbinfo); 1331 if (cbinfo.err) { 1332 return cbinfo.err; 1333 } 1334 1335 if (pci_bus_is_root(bus)) { 1336 owner = OBJECT(sphb); 1337 } else { 1338 owner = OBJECT(pci_bridge_get_device(bus)); 1339 } 1340 1341 ret = spapr_dt_drc(fdt, offset, owner, 1342 SPAPR_DR_CONNECTOR_TYPE_PCI); 1343 if (ret) { 1344 return ret; 1345 } 1346 1347 return offset; 1348 } 1349 1350 /* create OF node for pci device and required OF DT properties */ 1351 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev, 1352 void *fdt, int parent_offset) 1353 { 1354 int offset; 1355 const gchar *basename; 1356 gchar *nodename; 1357 int slot = PCI_SLOT(dev->devfn); 1358 int func = PCI_FUNC(dev->devfn); 1359 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1360 ResourceProps rp; 1361 SpaprDrc *drc = drc_from_dev(sphb, dev); 1362 uint32_t vendor_id = pci_default_read_config(dev, PCI_VENDOR_ID, 2); 1363 uint32_t device_id = pci_default_read_config(dev, PCI_DEVICE_ID, 2); 1364 uint32_t revision_id = pci_default_read_config(dev, PCI_REVISION_ID, 1); 1365 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); 1366 uint32_t irq_pin = pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1); 1367 uint32_t subsystem_id = pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2); 1368 uint32_t subsystem_vendor_id = 1369 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2); 1370 uint32_t cache_line_size = 1371 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1); 1372 uint32_t pci_status = pci_default_read_config(dev, PCI_STATUS, 2); 1373 gchar *loc_code; 1374 1375 basename = dt_name_from_class((ccode >> 16) & 0xff, (ccode >> 8) & 0xff, 1376 ccode & 0xff); 1377 1378 if (func != 0) { 1379 nodename = g_strdup_printf("%s@%x,%x", basename, slot, func); 1380 } else { 1381 nodename = g_strdup_printf("%s@%x", basename, slot); 1382 } 1383 1384 _FDT(offset = fdt_add_subnode(fdt, parent_offset, nodename)); 1385 1386 g_free(nodename); 1387 1388 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ 1389 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", vendor_id)); 1390 _FDT(fdt_setprop_cell(fdt, offset, "device-id", device_id)); 1391 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", revision_id)); 1392 1393 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode)); 1394 if (irq_pin) { 1395 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", irq_pin)); 1396 } 1397 1398 if (subsystem_id) { 1399 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", subsystem_id)); 1400 } 1401 1402 if (subsystem_vendor_id) { 1403 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", 1404 subsystem_vendor_id)); 1405 } 1406 1407 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", cache_line_size)); 1408 1409 1410 /* the following fdt cells are masked off the pci status register */ 1411 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", 1412 PCI_STATUS_DEVSEL_MASK & pci_status)); 1413 1414 if (pci_status & PCI_STATUS_FAST_BACK) { 1415 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); 1416 } 1417 if (pci_status & PCI_STATUS_66MHZ) { 1418 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); 1419 } 1420 if (pci_status & PCI_STATUS_UDF) { 1421 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); 1422 } 1423 1424 loc_code = spapr_phb_get_loc_code(sphb, dev); 1425 _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", loc_code)); 1426 g_free(loc_code); 1427 1428 if (drc) { 1429 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", 1430 spapr_drc_index(drc))); 1431 } 1432 1433 if (msi_present(dev)) { 1434 uint32_t max_msi = msi_nr_vectors_allocated(dev); 1435 if (max_msi) { 1436 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi)); 1437 } 1438 } 1439 if (msix_present(dev)) { 1440 uint32_t max_msix = dev->msix_entries_nr; 1441 if (max_msix) { 1442 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix)); 1443 } 1444 } 1445 1446 populate_resource_props(dev, &rp); 1447 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); 1448 1449 if (sphb->pcie_ecs && pci_is_express(dev)) { 1450 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1)); 1451 } 1452 1453 spapr_phb_nvgpu_populate_pcidev_dt(dev, fdt, offset, sphb); 1454 1455 if (!pc->is_bridge) { 1456 /* Properties only for non-bridges */ 1457 uint32_t min_grant = pci_default_read_config(dev, PCI_MIN_GNT, 1); 1458 uint32_t max_latency = pci_default_read_config(dev, PCI_MAX_LAT, 1); 1459 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", min_grant)); 1460 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", max_latency)); 1461 return offset; 1462 } else { 1463 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 1464 1465 return spapr_dt_pci_bus(sphb, sec_bus, fdt, offset); 1466 } 1467 } 1468 1469 /* Callback to be called during DRC release. */ 1470 void spapr_phb_remove_pci_device_cb(DeviceState *dev) 1471 { 1472 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 1473 1474 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 1475 object_unparent(OBJECT(dev)); 1476 } 1477 1478 int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 1479 void *fdt, int *fdt_start_offset, Error **errp) 1480 { 1481 HotplugHandler *plug_handler = qdev_get_hotplug_handler(drc->dev); 1482 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(plug_handler); 1483 PCIDevice *pdev = PCI_DEVICE(drc->dev); 1484 1485 *fdt_start_offset = spapr_dt_pci_device(sphb, pdev, fdt, 0); 1486 return 0; 1487 } 1488 1489 static void spapr_pci_bridge_plug(SpaprPhbState *phb, 1490 PCIBridge *bridge, 1491 Error **errp) 1492 { 1493 Error *local_err = NULL; 1494 PCIBus *bus = pci_bridge_get_sec_bus(bridge); 1495 1496 add_drcs(phb, bus, &local_err); 1497 if (local_err) { 1498 error_propagate(errp, local_err); 1499 return; 1500 } 1501 } 1502 1503 static void spapr_pci_plug(HotplugHandler *plug_handler, 1504 DeviceState *plugged_dev, Error **errp) 1505 { 1506 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1507 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1508 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1509 SpaprDrc *drc = drc_from_dev(phb, pdev); 1510 Error *local_err = NULL; 1511 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); 1512 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1513 1514 /* if DR is disabled we don't need to do anything in the case of 1515 * hotplug or coldplug callbacks 1516 */ 1517 if (!phb->dr_enabled) { 1518 /* if this is a hotplug operation initiated by the user 1519 * we need to let them know it's not enabled 1520 */ 1521 if (plugged_dev->hotplugged) { 1522 error_setg(&local_err, QERR_BUS_NO_HOTPLUG, 1523 object_get_typename(OBJECT(phb))); 1524 } 1525 goto out; 1526 } 1527 1528 g_assert(drc); 1529 1530 if (pc->is_bridge) { 1531 spapr_pci_bridge_plug(phb, PCI_BRIDGE(plugged_dev), &local_err); 1532 if (local_err) { 1533 error_propagate(errp, local_err); 1534 return; 1535 } 1536 } 1537 1538 /* Following the QEMU convention used for PCIe multifunction 1539 * hotplug, we do not allow functions to be hotplugged to a 1540 * slot that already has function 0 present 1541 */ 1542 if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] && 1543 PCI_FUNC(pdev->devfn) != 0) { 1544 error_setg(&local_err, "PCI: slot %d function 0 already ocuppied by %s," 1545 " additional functions can no longer be exposed to guest.", 1546 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name); 1547 goto out; 1548 } 1549 1550 spapr_drc_attach(drc, DEVICE(pdev), &local_err); 1551 if (local_err) { 1552 goto out; 1553 } 1554 1555 /* If this is function 0, signal hotplug for all the device functions. 1556 * Otherwise defer sending the hotplug event. 1557 */ 1558 if (!spapr_drc_hotplugged(plugged_dev)) { 1559 spapr_drc_reset(drc); 1560 } else if (PCI_FUNC(pdev->devfn) == 0) { 1561 int i; 1562 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev), &local_err); 1563 1564 if (local_err) { 1565 error_propagate(errp, local_err); 1566 return; 1567 } 1568 1569 for (i = 0; i < 8; i++) { 1570 SpaprDrc *func_drc; 1571 SpaprDrcClass *func_drck; 1572 SpaprDREntitySense state; 1573 1574 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1575 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1576 state = func_drck->dr_entity_sense(func_drc); 1577 1578 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { 1579 spapr_hotplug_req_add_by_index(func_drc); 1580 } 1581 } 1582 } 1583 1584 out: 1585 error_propagate(errp, local_err); 1586 } 1587 1588 static void spapr_pci_bridge_unplug(SpaprPhbState *phb, 1589 PCIBridge *bridge, 1590 Error **errp) 1591 { 1592 Error *local_err = NULL; 1593 PCIBus *bus = pci_bridge_get_sec_bus(bridge); 1594 1595 remove_drcs(phb, bus, &local_err); 1596 if (local_err) { 1597 error_propagate(errp, local_err); 1598 return; 1599 } 1600 } 1601 1602 static void spapr_pci_unplug(HotplugHandler *plug_handler, 1603 DeviceState *plugged_dev, Error **errp) 1604 { 1605 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1606 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1607 1608 /* some version guests do not wait for completion of a device 1609 * cleanup (generally done asynchronously by the kernel) before 1610 * signaling to QEMU that the device is safe, but instead sleep 1611 * for some 'safe' period of time. unfortunately on a busy host 1612 * this sleep isn't guaranteed to be long enough, resulting in 1613 * bad things like IRQ lines being left asserted during final 1614 * device removal. to deal with this we call reset just prior 1615 * to finalizing the device, which will put the device back into 1616 * an 'idle' state, as the device cleanup code expects. 1617 */ 1618 pci_device_reset(PCI_DEVICE(plugged_dev)); 1619 1620 if (pc->is_bridge) { 1621 Error *local_err = NULL; 1622 spapr_pci_bridge_unplug(phb, PCI_BRIDGE(plugged_dev), &local_err); 1623 if (local_err) { 1624 error_propagate(errp, local_err); 1625 } 1626 return; 1627 } 1628 1629 object_property_set_bool(OBJECT(plugged_dev), false, "realized", NULL); 1630 } 1631 1632 static void spapr_pci_unplug_request(HotplugHandler *plug_handler, 1633 DeviceState *plugged_dev, Error **errp) 1634 { 1635 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1636 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1637 SpaprDrc *drc = drc_from_dev(phb, pdev); 1638 1639 if (!phb->dr_enabled) { 1640 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1641 object_get_typename(OBJECT(phb))); 1642 return; 1643 } 1644 1645 g_assert(drc); 1646 g_assert(drc->dev == plugged_dev); 1647 1648 if (!spapr_drc_unplug_requested(drc)) { 1649 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1650 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1651 SpaprDrc *func_drc; 1652 SpaprDrcClass *func_drck; 1653 SpaprDREntitySense state; 1654 int i; 1655 Error *local_err = NULL; 1656 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev), &local_err); 1657 1658 if (local_err) { 1659 error_propagate(errp, local_err); 1660 return; 1661 } 1662 1663 if (pc->is_bridge) { 1664 error_setg(errp, "PCI: Hot unplug of PCI bridges not supported"); 1665 } 1666 1667 /* ensure any other present functions are pending unplug */ 1668 if (PCI_FUNC(pdev->devfn) == 0) { 1669 for (i = 1; i < 8; i++) { 1670 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1671 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1672 state = func_drck->dr_entity_sense(func_drc); 1673 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT 1674 && !spapr_drc_unplug_requested(func_drc)) { 1675 /* 1676 * Attempting to remove function 0 of a multifunction 1677 * device will will cascade into removing all child 1678 * functions, even if their unplug weren't requested 1679 * beforehand. 1680 */ 1681 spapr_drc_detach(func_drc); 1682 } 1683 } 1684 } 1685 1686 spapr_drc_detach(drc); 1687 1688 /* if this isn't func 0, defer unplug event. otherwise signal removal 1689 * for all present functions 1690 */ 1691 if (PCI_FUNC(pdev->devfn) == 0) { 1692 for (i = 7; i >= 0; i--) { 1693 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1694 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1695 state = func_drck->dr_entity_sense(func_drc); 1696 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { 1697 spapr_hotplug_req_remove_by_index(func_drc); 1698 } 1699 } 1700 } 1701 } 1702 } 1703 1704 static void spapr_phb_finalizefn(Object *obj) 1705 { 1706 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(obj); 1707 1708 g_free(sphb->dtbusname); 1709 sphb->dtbusname = NULL; 1710 } 1711 1712 static void spapr_phb_unrealize(DeviceState *dev, Error **errp) 1713 { 1714 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1715 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1716 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1717 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(phb); 1718 SpaprTceTable *tcet; 1719 int i; 1720 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 1721 Error *local_err = NULL; 1722 1723 spapr_phb_nvgpu_free(sphb); 1724 1725 if (sphb->msi) { 1726 g_hash_table_unref(sphb->msi); 1727 sphb->msi = NULL; 1728 } 1729 1730 /* 1731 * Remove IO/MMIO subregions and aliases, rest should get cleaned 1732 * via PHB's unrealize->object_finalize 1733 */ 1734 for (i = windows_supported - 1; i >= 0; i--) { 1735 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); 1736 if (tcet) { 1737 memory_region_del_subregion(&sphb->iommu_root, 1738 spapr_tce_get_iommu(tcet)); 1739 } 1740 } 1741 1742 remove_drcs(sphb, phb->bus, &local_err); 1743 if (local_err) { 1744 error_propagate(errp, local_err); 1745 return; 1746 } 1747 1748 for (i = PCI_NUM_PINS - 1; i >= 0; i--) { 1749 if (sphb->lsi_table[i].irq) { 1750 spapr_irq_free(spapr, sphb->lsi_table[i].irq, 1); 1751 sphb->lsi_table[i].irq = 0; 1752 } 1753 } 1754 1755 QLIST_REMOVE(sphb, list); 1756 1757 memory_region_del_subregion(&sphb->iommu_root, &sphb->msiwindow); 1758 1759 /* 1760 * An attached PCI device may have memory listeners, eg. VFIO PCI. We have 1761 * unmapped all sections. Remove the listeners now, before destroying the 1762 * address space. 1763 */ 1764 address_space_remove_listeners(&sphb->iommu_as); 1765 address_space_destroy(&sphb->iommu_as); 1766 1767 qbus_set_hotplug_handler(BUS(phb->bus), NULL, &error_abort); 1768 pci_unregister_root_bus(phb->bus); 1769 1770 memory_region_del_subregion(get_system_memory(), &sphb->iowindow); 1771 if (sphb->mem64_win_pciaddr != (hwaddr)-1) { 1772 memory_region_del_subregion(get_system_memory(), &sphb->mem64window); 1773 } 1774 memory_region_del_subregion(get_system_memory(), &sphb->mem32window); 1775 } 1776 1777 static void spapr_phb_destroy_msi(gpointer opaque) 1778 { 1779 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1780 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1781 SpaprPciMsi *msi = opaque; 1782 1783 if (!smc->legacy_irq_allocation) { 1784 spapr_irq_msi_free(spapr, msi->first_irq, msi->num); 1785 } 1786 spapr_irq_free(spapr, msi->first_irq, msi->num); 1787 g_free(msi); 1788 } 1789 1790 static void spapr_phb_realize(DeviceState *dev, Error **errp) 1791 { 1792 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 1793 * tries to add a sPAPR PHB to a non-pseries machine. 1794 */ 1795 SpaprMachineState *spapr = 1796 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), 1797 TYPE_SPAPR_MACHINE); 1798 SpaprMachineClass *smc = spapr ? SPAPR_MACHINE_GET_CLASS(spapr) : NULL; 1799 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1800 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(s); 1801 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1802 MachineState *ms = MACHINE(spapr); 1803 char *namebuf; 1804 int i; 1805 PCIBus *bus; 1806 uint64_t msi_window_size = 4096; 1807 SpaprTceTable *tcet; 1808 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 1809 Error *local_err = NULL; 1810 1811 if (!spapr) { 1812 error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine"); 1813 return; 1814 } 1815 1816 assert(sphb->index != (uint32_t)-1); /* checked in spapr_phb_pre_plug() */ 1817 1818 if (sphb->mem64_win_size != 0) { 1819 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { 1820 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx 1821 " (max 2 GiB)", sphb->mem_win_size); 1822 return; 1823 } 1824 1825 /* 64-bit window defaults to identity mapping */ 1826 sphb->mem64_win_pciaddr = sphb->mem64_win_addr; 1827 } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { 1828 /* 1829 * For compatibility with old configuration, if no 64-bit MMIO 1830 * window is specified, but the ordinary (32-bit) memory 1831 * window is specified as > 2GiB, we treat it as a 2GiB 32-bit 1832 * window, with a 64-bit MMIO window following on immediately 1833 * afterwards 1834 */ 1835 sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE; 1836 sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE; 1837 sphb->mem64_win_pciaddr = 1838 SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE; 1839 sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE; 1840 } 1841 1842 if (spapr_pci_find_phb(spapr, sphb->buid)) { 1843 SpaprPhbState *s; 1844 1845 error_setg(errp, "PCI host bridges must have unique indexes"); 1846 error_append_hint(errp, "The following indexes are already in use:"); 1847 QLIST_FOREACH(s, &spapr->phbs, list) { 1848 error_append_hint(errp, " %d", s->index); 1849 } 1850 error_append_hint(errp, "\nTry another value for the index property\n"); 1851 return; 1852 } 1853 1854 if (sphb->numa_node != -1 && 1855 (sphb->numa_node >= MAX_NODES || 1856 !ms->numa_state->nodes[sphb->numa_node].present)) { 1857 error_setg(errp, "Invalid NUMA node ID for PCI host bridge"); 1858 return; 1859 } 1860 1861 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); 1862 1863 /* Initialize memory regions */ 1864 namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname); 1865 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); 1866 g_free(namebuf); 1867 1868 namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname); 1869 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb), 1870 namebuf, &sphb->memspace, 1871 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); 1872 g_free(namebuf); 1873 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, 1874 &sphb->mem32window); 1875 1876 if (sphb->mem64_win_size != 0) { 1877 namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname); 1878 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb), 1879 namebuf, &sphb->memspace, 1880 sphb->mem64_win_pciaddr, sphb->mem64_win_size); 1881 g_free(namebuf); 1882 1883 memory_region_add_subregion(get_system_memory(), 1884 sphb->mem64_win_addr, 1885 &sphb->mem64window); 1886 } 1887 1888 /* Initialize IO regions */ 1889 namebuf = g_strdup_printf("%s.io", sphb->dtbusname); 1890 memory_region_init(&sphb->iospace, OBJECT(sphb), 1891 namebuf, SPAPR_PCI_IO_WIN_SIZE); 1892 g_free(namebuf); 1893 1894 namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname); 1895 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, 1896 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); 1897 g_free(namebuf); 1898 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, 1899 &sphb->iowindow); 1900 1901 bus = pci_register_root_bus(dev, NULL, 1902 pci_spapr_set_irq, pci_swizzle_map_irq_fn, sphb, 1903 &sphb->memspace, &sphb->iospace, 1904 PCI_DEVFN(0, 0), PCI_NUM_PINS, 1905 TYPE_PCI_BUS); 1906 1907 /* 1908 * Despite resembling a vanilla PCI bus in most ways, the PAPR 1909 * para-virtualized PCI bus *does* permit PCI-E extended config 1910 * space access 1911 */ 1912 if (sphb->pcie_ecs) { 1913 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 1914 } 1915 phb->bus = bus; 1916 qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb), NULL); 1917 1918 /* 1919 * Initialize PHB address space. 1920 * By default there will be at least one subregion for default 1921 * 32bit DMA window. 1922 * Later the guest might want to create another DMA window 1923 * which will become another memory subregion. 1924 */ 1925 namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname); 1926 memory_region_init(&sphb->iommu_root, OBJECT(sphb), 1927 namebuf, UINT64_MAX); 1928 g_free(namebuf); 1929 address_space_init(&sphb->iommu_as, &sphb->iommu_root, 1930 sphb->dtbusname); 1931 1932 /* 1933 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, 1934 * we need to allocate some memory to catch those writes coming 1935 * from msi_notify()/msix_notify(). 1936 * As MSIMessage:addr is going to be the same and MSIMessage:data 1937 * is going to be a VIRQ number, 4 bytes of the MSI MR will only 1938 * be used. 1939 * 1940 * For KVM we want to ensure that this memory is a full page so that 1941 * our memory slot is of page size granularity. 1942 */ 1943 if (kvm_enabled()) { 1944 msi_window_size = getpagesize(); 1945 } 1946 1947 memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr, 1948 "msi", msi_window_size); 1949 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, 1950 &sphb->msiwindow); 1951 1952 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); 1953 1954 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); 1955 1956 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); 1957 1958 /* Initialize the LSI table */ 1959 for (i = 0; i < PCI_NUM_PINS; i++) { 1960 uint32_t irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i; 1961 1962 if (smc->legacy_irq_allocation) { 1963 irq = spapr_irq_findone(spapr, &local_err); 1964 if (local_err) { 1965 error_propagate_prepend(errp, local_err, 1966 "can't allocate LSIs: "); 1967 /* 1968 * Older machines will never support PHB hotplug, ie, this is an 1969 * init only path and QEMU will terminate. No need to rollback. 1970 */ 1971 return; 1972 } 1973 } 1974 1975 spapr_irq_claim(spapr, irq, true, &local_err); 1976 if (local_err) { 1977 error_propagate_prepend(errp, local_err, "can't allocate LSIs: "); 1978 goto unrealize; 1979 } 1980 1981 sphb->lsi_table[i].irq = irq; 1982 } 1983 1984 /* allocate connectors for child PCI devices */ 1985 add_drcs(sphb, phb->bus, &local_err); 1986 if (local_err) { 1987 error_propagate(errp, local_err); 1988 goto unrealize; 1989 } 1990 1991 /* DMA setup */ 1992 for (i = 0; i < windows_supported; ++i) { 1993 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]); 1994 if (!tcet) { 1995 error_setg(errp, "Creating window#%d failed for %s", 1996 i, sphb->dtbusname); 1997 goto unrealize; 1998 } 1999 memory_region_add_subregion(&sphb->iommu_root, 0, 2000 spapr_tce_get_iommu(tcet)); 2001 } 2002 2003 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, 2004 spapr_phb_destroy_msi); 2005 return; 2006 2007 unrealize: 2008 spapr_phb_unrealize(dev, NULL); 2009 } 2010 2011 static int spapr_phb_children_reset(Object *child, void *opaque) 2012 { 2013 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); 2014 2015 if (dev) { 2016 device_reset(dev); 2017 } 2018 2019 return 0; 2020 } 2021 2022 void spapr_phb_dma_reset(SpaprPhbState *sphb) 2023 { 2024 int i; 2025 SpaprTceTable *tcet; 2026 2027 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) { 2028 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); 2029 2030 if (tcet && tcet->nb_table) { 2031 spapr_tce_table_disable(tcet); 2032 } 2033 } 2034 2035 /* Register default 32bit DMA window */ 2036 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]); 2037 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr, 2038 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT); 2039 } 2040 2041 static void spapr_phb_reset(DeviceState *qdev) 2042 { 2043 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev); 2044 Error *errp = NULL; 2045 2046 spapr_phb_dma_reset(sphb); 2047 spapr_phb_nvgpu_free(sphb); 2048 spapr_phb_nvgpu_setup(sphb, &errp); 2049 if (errp) { 2050 error_report_err(errp); 2051 } 2052 2053 /* Reset the IOMMU state */ 2054 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); 2055 2056 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) { 2057 spapr_phb_vfio_reset(qdev); 2058 } 2059 2060 g_hash_table_remove_all(sphb->msi); 2061 } 2062 2063 static Property spapr_phb_properties[] = { 2064 DEFINE_PROP_UINT32("index", SpaprPhbState, index, -1), 2065 DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState, mem_win_size, 2066 SPAPR_PCI_MEM32_WIN_SIZE), 2067 DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState, mem64_win_size, 2068 SPAPR_PCI_MEM64_WIN_SIZE), 2069 DEFINE_PROP_UINT64("io_win_size", SpaprPhbState, io_win_size, 2070 SPAPR_PCI_IO_WIN_SIZE), 2071 DEFINE_PROP_BOOL("dynamic-reconfiguration", SpaprPhbState, dr_enabled, 2072 true), 2073 /* Default DMA window is 0..1GB */ 2074 DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState, dma_win_addr, 0), 2075 DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState, dma_win_size, 0x40000000), 2076 DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState, dma64_win_addr, 2077 0x800000000000000ULL), 2078 DEFINE_PROP_BOOL("ddw", SpaprPhbState, ddw_enabled, true), 2079 DEFINE_PROP_UINT64("pgsz", SpaprPhbState, page_size_mask, 2080 (1ULL << 12) | (1ULL << 16) 2081 | (1ULL << 21) | (1ULL << 24)), 2082 DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1), 2083 DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState, 2084 pre_2_8_migration, false), 2085 DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState, 2086 pcie_ecs, true), 2087 DEFINE_PROP_UINT64("gpa", SpaprPhbState, nv2_gpa_win_addr, 0), 2088 DEFINE_PROP_UINT64("atsd", SpaprPhbState, nv2_atsd_win_addr, 0), 2089 DEFINE_PROP_END_OF_LIST(), 2090 }; 2091 2092 static const VMStateDescription vmstate_spapr_pci_lsi = { 2093 .name = "spapr_pci/lsi", 2094 .version_id = 1, 2095 .minimum_version_id = 1, 2096 .fields = (VMStateField[]) { 2097 VMSTATE_UINT32_EQUAL(irq, SpaprPciLsi, NULL), 2098 2099 VMSTATE_END_OF_LIST() 2100 }, 2101 }; 2102 2103 static const VMStateDescription vmstate_spapr_pci_msi = { 2104 .name = "spapr_pci/msi", 2105 .version_id = 1, 2106 .minimum_version_id = 1, 2107 .fields = (VMStateField []) { 2108 VMSTATE_UINT32(key, SpaprPciMsiMig), 2109 VMSTATE_UINT32(value.first_irq, SpaprPciMsiMig), 2110 VMSTATE_UINT32(value.num, SpaprPciMsiMig), 2111 VMSTATE_END_OF_LIST() 2112 }, 2113 }; 2114 2115 static int spapr_pci_pre_save(void *opaque) 2116 { 2117 SpaprPhbState *sphb = opaque; 2118 GHashTableIter iter; 2119 gpointer key, value; 2120 int i; 2121 2122 if (sphb->pre_2_8_migration) { 2123 sphb->mig_liobn = sphb->dma_liobn[0]; 2124 sphb->mig_mem_win_addr = sphb->mem_win_addr; 2125 sphb->mig_mem_win_size = sphb->mem_win_size; 2126 sphb->mig_io_win_addr = sphb->io_win_addr; 2127 sphb->mig_io_win_size = sphb->io_win_size; 2128 2129 if ((sphb->mem64_win_size != 0) 2130 && (sphb->mem64_win_addr 2131 == (sphb->mem_win_addr + sphb->mem_win_size))) { 2132 sphb->mig_mem_win_size += sphb->mem64_win_size; 2133 } 2134 } 2135 2136 g_free(sphb->msi_devs); 2137 sphb->msi_devs = NULL; 2138 sphb->msi_devs_num = g_hash_table_size(sphb->msi); 2139 if (!sphb->msi_devs_num) { 2140 return 0; 2141 } 2142 sphb->msi_devs = g_new(SpaprPciMsiMig, sphb->msi_devs_num); 2143 2144 g_hash_table_iter_init(&iter, sphb->msi); 2145 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { 2146 sphb->msi_devs[i].key = *(uint32_t *) key; 2147 sphb->msi_devs[i].value = *(SpaprPciMsi *) value; 2148 } 2149 2150 return 0; 2151 } 2152 2153 static int spapr_pci_post_load(void *opaque, int version_id) 2154 { 2155 SpaprPhbState *sphb = opaque; 2156 gpointer key, value; 2157 int i; 2158 2159 for (i = 0; i < sphb->msi_devs_num; ++i) { 2160 key = g_memdup(&sphb->msi_devs[i].key, 2161 sizeof(sphb->msi_devs[i].key)); 2162 value = g_memdup(&sphb->msi_devs[i].value, 2163 sizeof(sphb->msi_devs[i].value)); 2164 g_hash_table_insert(sphb->msi, key, value); 2165 } 2166 g_free(sphb->msi_devs); 2167 sphb->msi_devs = NULL; 2168 sphb->msi_devs_num = 0; 2169 2170 return 0; 2171 } 2172 2173 static bool pre_2_8_migration(void *opaque, int version_id) 2174 { 2175 SpaprPhbState *sphb = opaque; 2176 2177 return sphb->pre_2_8_migration; 2178 } 2179 2180 static const VMStateDescription vmstate_spapr_pci = { 2181 .name = "spapr_pci", 2182 .version_id = 2, 2183 .minimum_version_id = 2, 2184 .pre_save = spapr_pci_pre_save, 2185 .post_load = spapr_pci_post_load, 2186 .fields = (VMStateField[]) { 2187 VMSTATE_UINT64_EQUAL(buid, SpaprPhbState, NULL), 2188 VMSTATE_UINT32_TEST(mig_liobn, SpaprPhbState, pre_2_8_migration), 2189 VMSTATE_UINT64_TEST(mig_mem_win_addr, SpaprPhbState, pre_2_8_migration), 2190 VMSTATE_UINT64_TEST(mig_mem_win_size, SpaprPhbState, pre_2_8_migration), 2191 VMSTATE_UINT64_TEST(mig_io_win_addr, SpaprPhbState, pre_2_8_migration), 2192 VMSTATE_UINT64_TEST(mig_io_win_size, SpaprPhbState, pre_2_8_migration), 2193 VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0, 2194 vmstate_spapr_pci_lsi, SpaprPciLsi), 2195 VMSTATE_INT32(msi_devs_num, SpaprPhbState), 2196 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, SpaprPhbState, msi_devs_num, 0, 2197 vmstate_spapr_pci_msi, SpaprPciMsiMig), 2198 VMSTATE_END_OF_LIST() 2199 }, 2200 }; 2201 2202 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, 2203 PCIBus *rootbus) 2204 { 2205 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); 2206 2207 return sphb->dtbusname; 2208 } 2209 2210 static void spapr_phb_class_init(ObjectClass *klass, void *data) 2211 { 2212 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 2213 DeviceClass *dc = DEVICE_CLASS(klass); 2214 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); 2215 2216 hc->root_bus_path = spapr_phb_root_bus_path; 2217 dc->realize = spapr_phb_realize; 2218 dc->unrealize = spapr_phb_unrealize; 2219 dc->props = spapr_phb_properties; 2220 dc->reset = spapr_phb_reset; 2221 dc->vmsd = &vmstate_spapr_pci; 2222 /* Supported by TYPE_SPAPR_MACHINE */ 2223 dc->user_creatable = true; 2224 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 2225 hp->plug = spapr_pci_plug; 2226 hp->unplug = spapr_pci_unplug; 2227 hp->unplug_request = spapr_pci_unplug_request; 2228 } 2229 2230 static const TypeInfo spapr_phb_info = { 2231 .name = TYPE_SPAPR_PCI_HOST_BRIDGE, 2232 .parent = TYPE_PCI_HOST_BRIDGE, 2233 .instance_size = sizeof(SpaprPhbState), 2234 .instance_finalize = spapr_phb_finalizefn, 2235 .class_init = spapr_phb_class_init, 2236 .interfaces = (InterfaceInfo[]) { 2237 { TYPE_HOTPLUG_HANDLER }, 2238 { } 2239 } 2240 }; 2241 2242 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, 2243 void *opaque) 2244 { 2245 unsigned int *bus_no = opaque; 2246 PCIBus *sec_bus = NULL; 2247 2248 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 2249 PCI_HEADER_TYPE_BRIDGE)) { 2250 return; 2251 } 2252 2253 (*bus_no)++; 2254 pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1); 2255 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); 2256 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 2257 2258 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 2259 if (!sec_bus) { 2260 return; 2261 } 2262 2263 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 2264 spapr_phb_pci_enumerate_bridge, bus_no); 2265 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 2266 } 2267 2268 static void spapr_phb_pci_enumerate(SpaprPhbState *phb) 2269 { 2270 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 2271 unsigned int bus_no = 0; 2272 2273 pci_for_each_device(bus, pci_bus_num(bus), 2274 spapr_phb_pci_enumerate_bridge, 2275 &bus_no); 2276 2277 } 2278 2279 int spapr_dt_phb(SpaprPhbState *phb, uint32_t intc_phandle, void *fdt, 2280 uint32_t nr_msis, int *node_offset) 2281 { 2282 int bus_off, i, j, ret; 2283 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; 2284 struct { 2285 uint32_t hi; 2286 uint64_t child; 2287 uint64_t parent; 2288 uint64_t size; 2289 } QEMU_PACKED ranges[] = { 2290 { 2291 cpu_to_be32(b_ss(1)), cpu_to_be64(0), 2292 cpu_to_be64(phb->io_win_addr), 2293 cpu_to_be64(memory_region_size(&phb->iospace)), 2294 }, 2295 { 2296 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), 2297 cpu_to_be64(phb->mem_win_addr), 2298 cpu_to_be64(phb->mem_win_size), 2299 }, 2300 { 2301 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr), 2302 cpu_to_be64(phb->mem64_win_addr), 2303 cpu_to_be64(phb->mem64_win_size), 2304 }, 2305 }; 2306 const unsigned sizeof_ranges = 2307 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]); 2308 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; 2309 uint32_t interrupt_map_mask[] = { 2310 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; 2311 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; 2312 uint32_t ddw_applicable[] = { 2313 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW), 2314 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW), 2315 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW) 2316 }; 2317 uint32_t ddw_extensions[] = { 2318 cpu_to_be32(1), 2319 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW) 2320 }; 2321 uint32_t associativity[] = {cpu_to_be32(0x4), 2322 cpu_to_be32(0x0), 2323 cpu_to_be32(0x0), 2324 cpu_to_be32(0x0), 2325 cpu_to_be32(phb->numa_node)}; 2326 SpaprTceTable *tcet; 2327 SpaprDrc *drc; 2328 Error *errp = NULL; 2329 2330 /* Start populating the FDT */ 2331 _FDT(bus_off = fdt_add_subnode(fdt, 0, phb->dtbusname)); 2332 if (node_offset) { 2333 *node_offset = bus_off; 2334 } 2335 2336 /* Write PHB properties */ 2337 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); 2338 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); 2339 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); 2340 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); 2341 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); 2342 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); 2343 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); 2344 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); 2345 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", nr_msis)); 2346 2347 /* Dynamic DMA window */ 2348 if (phb->ddw_enabled) { 2349 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable, 2350 sizeof(ddw_applicable))); 2351 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions", 2352 &ddw_extensions, sizeof(ddw_extensions))); 2353 } 2354 2355 /* Advertise NUMA via ibm,associativity */ 2356 if (phb->numa_node != -1) { 2357 _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity, 2358 sizeof(associativity))); 2359 } 2360 2361 /* Build the interrupt-map, this must matches what is done 2362 * in pci_swizzle_map_irq_fn 2363 */ 2364 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", 2365 &interrupt_map_mask, sizeof(interrupt_map_mask))); 2366 for (i = 0; i < PCI_SLOT_MAX; i++) { 2367 for (j = 0; j < PCI_NUM_PINS; j++) { 2368 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; 2369 int lsi_num = pci_swizzle(i, j); 2370 2371 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); 2372 irqmap[1] = 0; 2373 irqmap[2] = 0; 2374 irqmap[3] = cpu_to_be32(j+1); 2375 irqmap[4] = cpu_to_be32(intc_phandle); 2376 spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true); 2377 } 2378 } 2379 /* Write interrupt map */ 2380 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, 2381 sizeof(interrupt_map))); 2382 2383 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]); 2384 if (!tcet) { 2385 return -1; 2386 } 2387 spapr_dma_dt(fdt, bus_off, "ibm,dma-window", 2388 tcet->liobn, tcet->bus_offset, 2389 tcet->nb_table << tcet->page_shift); 2390 2391 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, phb->index); 2392 if (drc) { 2393 uint32_t drc_index = cpu_to_be32(spapr_drc_index(drc)); 2394 2395 _FDT(fdt_setprop(fdt, bus_off, "ibm,my-drc-index", &drc_index, 2396 sizeof(drc_index))); 2397 } 2398 2399 /* Walk the bridges and program the bus numbers*/ 2400 spapr_phb_pci_enumerate(phb); 2401 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); 2402 2403 /* Walk the bridge and subordinate buses */ 2404 ret = spapr_dt_pci_bus(phb, PCI_HOST_BRIDGE(phb)->bus, fdt, bus_off); 2405 if (ret < 0) { 2406 return ret; 2407 } 2408 2409 spapr_phb_nvgpu_populate_dt(phb, fdt, bus_off, &errp); 2410 if (errp) { 2411 error_report_err(errp); 2412 } 2413 spapr_phb_nvgpu_ram_populate_dt(phb, fdt); 2414 2415 return 0; 2416 } 2417 2418 void spapr_pci_rtas_init(void) 2419 { 2420 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", 2421 rtas_read_pci_config); 2422 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", 2423 rtas_write_pci_config); 2424 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", 2425 rtas_ibm_read_pci_config); 2426 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", 2427 rtas_ibm_write_pci_config); 2428 if (msi_nonbroken) { 2429 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, 2430 "ibm,query-interrupt-source-number", 2431 rtas_ibm_query_interrupt_source_number); 2432 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", 2433 rtas_ibm_change_msi); 2434 } 2435 2436 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, 2437 "ibm,set-eeh-option", 2438 rtas_ibm_set_eeh_option); 2439 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, 2440 "ibm,get-config-addr-info2", 2441 rtas_ibm_get_config_addr_info2); 2442 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, 2443 "ibm,read-slot-reset-state2", 2444 rtas_ibm_read_slot_reset_state2); 2445 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, 2446 "ibm,set-slot-reset", 2447 rtas_ibm_set_slot_reset); 2448 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, 2449 "ibm,configure-pe", 2450 rtas_ibm_configure_pe); 2451 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, 2452 "ibm,slot-error-detail", 2453 rtas_ibm_slot_error_detail); 2454 } 2455 2456 static void spapr_pci_register_types(void) 2457 { 2458 type_register_static(&spapr_phb_info); 2459 } 2460 2461 type_init(spapr_pci_register_types) 2462 2463 static int spapr_switch_one_vga(DeviceState *dev, void *opaque) 2464 { 2465 bool be = *(bool *)opaque; 2466 2467 if (object_dynamic_cast(OBJECT(dev), "VGA") 2468 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { 2469 object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", 2470 &error_abort); 2471 } 2472 return 0; 2473 } 2474 2475 void spapr_pci_switch_vga(bool big_endian) 2476 { 2477 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 2478 SpaprPhbState *sphb; 2479 2480 /* 2481 * For backward compatibility with existing guests, we switch 2482 * the endianness of the VGA controller when changing the guest 2483 * interrupt mode 2484 */ 2485 QLIST_FOREACH(sphb, &spapr->phbs, list) { 2486 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; 2487 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, 2488 &big_endian); 2489 } 2490 } 2491