1 /* 2 * QEMU sPAPR PCI host originated from Uninorth PCI host 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. 5 * Copyright (C) 2011 David Gibson, IBM Corporation. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "hw/hw.h" 26 #include "hw/sysbus.h" 27 #include "hw/pci/pci.h" 28 #include "hw/pci/msi.h" 29 #include "hw/pci/msix.h" 30 #include "hw/pci/pci_host.h" 31 #include "hw/ppc/spapr.h" 32 #include "hw/pci-host/spapr.h" 33 #include "exec/address-spaces.h" 34 #include <libfdt.h> 35 #include "trace.h" 36 #include "qemu/error-report.h" 37 #include "qapi/qmp/qerror.h" 38 39 #include "hw/pci/pci_bridge.h" 40 #include "hw/pci/pci_bus.h" 41 #include "hw/ppc/spapr_drc.h" 42 #include "sysemu/device_tree.h" 43 44 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ 45 #define RTAS_QUERY_FN 0 46 #define RTAS_CHANGE_FN 1 47 #define RTAS_RESET_FN 2 48 #define RTAS_CHANGE_MSI_FN 3 49 #define RTAS_CHANGE_MSIX_FN 4 50 51 /* Interrupt types to return on RTAS_CHANGE_* */ 52 #define RTAS_TYPE_MSI 1 53 #define RTAS_TYPE_MSIX 2 54 55 #define FDT_NAME_MAX 128 56 57 #define _FDT(exp) \ 58 do { \ 59 int ret = (exp); \ 60 if (ret < 0) { \ 61 return ret; \ 62 } \ 63 } while (0) 64 65 sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid) 66 { 67 sPAPRPHBState *sphb; 68 69 QLIST_FOREACH(sphb, &spapr->phbs, list) { 70 if (sphb->buid != buid) { 71 continue; 72 } 73 return sphb; 74 } 75 76 return NULL; 77 } 78 79 PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid, 80 uint32_t config_addr) 81 { 82 sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid); 83 PCIHostState *phb = PCI_HOST_BRIDGE(sphb); 84 int bus_num = (config_addr >> 16) & 0xFF; 85 int devfn = (config_addr >> 8) & 0xFF; 86 87 if (!phb) { 88 return NULL; 89 } 90 91 return pci_find_device(phb->bus, bus_num, devfn); 92 } 93 94 static uint32_t rtas_pci_cfgaddr(uint32_t arg) 95 { 96 /* This handles the encoding of extended config space addresses */ 97 return ((arg >> 20) & 0xf00) | (arg & 0xff); 98 } 99 100 static void finish_read_pci_config(sPAPRMachineState *spapr, uint64_t buid, 101 uint32_t addr, uint32_t size, 102 target_ulong rets) 103 { 104 PCIDevice *pci_dev; 105 uint32_t val; 106 107 if ((size != 1) && (size != 2) && (size != 4)) { 108 /* access must be 1, 2 or 4 bytes */ 109 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 110 return; 111 } 112 113 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 114 addr = rtas_pci_cfgaddr(addr); 115 116 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 117 /* Access must be to a valid device, within bounds and 118 * naturally aligned */ 119 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 120 return; 121 } 122 123 val = pci_host_config_read_common(pci_dev, addr, 124 pci_config_size(pci_dev), size); 125 126 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 127 rtas_st(rets, 1, val); 128 } 129 130 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 131 uint32_t token, uint32_t nargs, 132 target_ulong args, 133 uint32_t nret, target_ulong rets) 134 { 135 uint64_t buid; 136 uint32_t size, addr; 137 138 if ((nargs != 4) || (nret != 2)) { 139 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 140 return; 141 } 142 143 buid = rtas_ldq(args, 1); 144 size = rtas_ld(args, 3); 145 addr = rtas_ld(args, 0); 146 147 finish_read_pci_config(spapr, buid, addr, size, rets); 148 } 149 150 static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 151 uint32_t token, uint32_t nargs, 152 target_ulong args, 153 uint32_t nret, target_ulong rets) 154 { 155 uint32_t size, addr; 156 157 if ((nargs != 2) || (nret != 2)) { 158 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 159 return; 160 } 161 162 size = rtas_ld(args, 1); 163 addr = rtas_ld(args, 0); 164 165 finish_read_pci_config(spapr, 0, addr, size, rets); 166 } 167 168 static void finish_write_pci_config(sPAPRMachineState *spapr, uint64_t buid, 169 uint32_t addr, uint32_t size, 170 uint32_t val, target_ulong rets) 171 { 172 PCIDevice *pci_dev; 173 174 if ((size != 1) && (size != 2) && (size != 4)) { 175 /* access must be 1, 2 or 4 bytes */ 176 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 177 return; 178 } 179 180 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 181 addr = rtas_pci_cfgaddr(addr); 182 183 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 184 /* Access must be to a valid device, within bounds and 185 * naturally aligned */ 186 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 187 return; 188 } 189 190 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), 191 val, size); 192 193 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 194 } 195 196 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 197 uint32_t token, uint32_t nargs, 198 target_ulong args, 199 uint32_t nret, target_ulong rets) 200 { 201 uint64_t buid; 202 uint32_t val, size, addr; 203 204 if ((nargs != 5) || (nret != 1)) { 205 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 206 return; 207 } 208 209 buid = rtas_ldq(args, 1); 210 val = rtas_ld(args, 4); 211 size = rtas_ld(args, 3); 212 addr = rtas_ld(args, 0); 213 214 finish_write_pci_config(spapr, buid, addr, size, val, rets); 215 } 216 217 static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 218 uint32_t token, uint32_t nargs, 219 target_ulong args, 220 uint32_t nret, target_ulong rets) 221 { 222 uint32_t val, size, addr; 223 224 if ((nargs != 3) || (nret != 1)) { 225 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 226 return; 227 } 228 229 230 val = rtas_ld(args, 2); 231 size = rtas_ld(args, 1); 232 addr = rtas_ld(args, 0); 233 234 finish_write_pci_config(spapr, 0, addr, size, val, rets); 235 } 236 237 /* 238 * Set MSI/MSIX message data. 239 * This is required for msi_notify()/msix_notify() which 240 * will write at the addresses via spapr_msi_write(). 241 * 242 * If hwaddr == 0, all entries will have .data == first_irq i.e. 243 * table will be reset. 244 */ 245 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, 246 unsigned first_irq, unsigned req_num) 247 { 248 unsigned i; 249 MSIMessage msg = { .address = addr, .data = first_irq }; 250 251 if (!msix) { 252 msi_set_message(pdev, msg); 253 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); 254 return; 255 } 256 257 for (i = 0; i < req_num; ++i) { 258 msix_set_message(pdev, i, msg); 259 trace_spapr_pci_msi_setup(pdev->name, i, msg.address); 260 if (addr) { 261 ++msg.data; 262 } 263 } 264 } 265 266 static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 267 uint32_t token, uint32_t nargs, 268 target_ulong args, uint32_t nret, 269 target_ulong rets) 270 { 271 uint32_t config_addr = rtas_ld(args, 0); 272 uint64_t buid = rtas_ldq(args, 1); 273 unsigned int func = rtas_ld(args, 3); 274 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ 275 unsigned int seq_num = rtas_ld(args, 5); 276 unsigned int ret_intr_type; 277 unsigned int irq, max_irqs = 0, num = 0; 278 sPAPRPHBState *phb = NULL; 279 PCIDevice *pdev = NULL; 280 spapr_pci_msi *msi; 281 int *config_addr_key; 282 283 switch (func) { 284 case RTAS_CHANGE_MSI_FN: 285 case RTAS_CHANGE_FN: 286 ret_intr_type = RTAS_TYPE_MSI; 287 break; 288 case RTAS_CHANGE_MSIX_FN: 289 ret_intr_type = RTAS_TYPE_MSIX; 290 break; 291 default: 292 error_report("rtas_ibm_change_msi(%u) is not implemented", func); 293 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 294 return; 295 } 296 297 /* Fins sPAPRPHBState */ 298 phb = spapr_pci_find_phb(spapr, buid); 299 if (phb) { 300 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 301 } 302 if (!phb || !pdev) { 303 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 304 return; 305 } 306 307 /* Releasing MSIs */ 308 if (!req_num) { 309 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); 310 if (!msi) { 311 trace_spapr_pci_msi("Releasing wrong config", config_addr); 312 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 313 return; 314 } 315 316 xics_free(spapr->icp, msi->first_irq, msi->num); 317 if (msi_present(pdev)) { 318 spapr_msi_setmsg(pdev, 0, false, 0, num); 319 } 320 if (msix_present(pdev)) { 321 spapr_msi_setmsg(pdev, 0, true, 0, num); 322 } 323 g_hash_table_remove(phb->msi, &config_addr); 324 325 trace_spapr_pci_msi("Released MSIs", config_addr); 326 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 327 rtas_st(rets, 1, 0); 328 return; 329 } 330 331 /* Enabling MSI */ 332 333 /* Check if the device supports as many IRQs as requested */ 334 if (ret_intr_type == RTAS_TYPE_MSI) { 335 max_irqs = msi_nr_vectors_allocated(pdev); 336 } else if (ret_intr_type == RTAS_TYPE_MSIX) { 337 max_irqs = pdev->msix_entries_nr; 338 } 339 if (!max_irqs) { 340 error_report("Requested interrupt type %d is not enabled for device %x", 341 ret_intr_type, config_addr); 342 rtas_st(rets, 0, -1); /* Hardware error */ 343 return; 344 } 345 /* Correct the number if the guest asked for too many */ 346 if (req_num > max_irqs) { 347 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); 348 req_num = max_irqs; 349 irq = 0; /* to avoid misleading trace */ 350 goto out; 351 } 352 353 /* Allocate MSIs */ 354 irq = xics_alloc_block(spapr->icp, 0, req_num, false, 355 ret_intr_type == RTAS_TYPE_MSI); 356 if (!irq) { 357 error_report("Cannot allocate MSIs for device %x", config_addr); 358 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 359 return; 360 } 361 362 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ 363 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, 364 irq, req_num); 365 366 /* Add MSI device to cache */ 367 msi = g_new(spapr_pci_msi, 1); 368 msi->first_irq = irq; 369 msi->num = req_num; 370 config_addr_key = g_new(int, 1); 371 *config_addr_key = config_addr; 372 g_hash_table_insert(phb->msi, config_addr_key, msi); 373 374 out: 375 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 376 rtas_st(rets, 1, req_num); 377 rtas_st(rets, 2, ++seq_num); 378 if (nret > 3) { 379 rtas_st(rets, 3, ret_intr_type); 380 } 381 382 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); 383 } 384 385 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, 386 sPAPRMachineState *spapr, 387 uint32_t token, 388 uint32_t nargs, 389 target_ulong args, 390 uint32_t nret, 391 target_ulong rets) 392 { 393 uint32_t config_addr = rtas_ld(args, 0); 394 uint64_t buid = rtas_ldq(args, 1); 395 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); 396 sPAPRPHBState *phb = NULL; 397 PCIDevice *pdev = NULL; 398 spapr_pci_msi *msi; 399 400 /* Find sPAPRPHBState */ 401 phb = spapr_pci_find_phb(spapr, buid); 402 if (phb) { 403 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 404 } 405 if (!phb || !pdev) { 406 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 407 return; 408 } 409 410 /* Find device descriptor and start IRQ */ 411 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); 412 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { 413 trace_spapr_pci_msi("Failed to return vector", config_addr); 414 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 415 return; 416 } 417 intr_src_num = msi->first_irq + ioa_intr_num; 418 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, 419 intr_src_num); 420 421 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 422 rtas_st(rets, 1, intr_src_num); 423 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ 424 } 425 426 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, 427 sPAPRMachineState *spapr, 428 uint32_t token, uint32_t nargs, 429 target_ulong args, uint32_t nret, 430 target_ulong rets) 431 { 432 sPAPRPHBState *sphb; 433 sPAPRPHBClass *spc; 434 uint32_t addr, option; 435 uint64_t buid; 436 int ret; 437 438 if ((nargs != 4) || (nret != 1)) { 439 goto param_error_exit; 440 } 441 442 buid = rtas_ldq(args, 1); 443 addr = rtas_ld(args, 0); 444 option = rtas_ld(args, 3); 445 446 sphb = spapr_pci_find_phb(spapr, buid); 447 if (!sphb) { 448 goto param_error_exit; 449 } 450 451 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 452 if (!spc->eeh_set_option) { 453 goto param_error_exit; 454 } 455 456 ret = spc->eeh_set_option(sphb, addr, option); 457 rtas_st(rets, 0, ret); 458 return; 459 460 param_error_exit: 461 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 462 } 463 464 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, 465 sPAPRMachineState *spapr, 466 uint32_t token, uint32_t nargs, 467 target_ulong args, uint32_t nret, 468 target_ulong rets) 469 { 470 sPAPRPHBState *sphb; 471 sPAPRPHBClass *spc; 472 PCIDevice *pdev; 473 uint32_t addr, option; 474 uint64_t buid; 475 476 if ((nargs != 4) || (nret != 2)) { 477 goto param_error_exit; 478 } 479 480 buid = rtas_ldq(args, 1); 481 sphb = spapr_pci_find_phb(spapr, buid); 482 if (!sphb) { 483 goto param_error_exit; 484 } 485 486 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 487 if (!spc->eeh_set_option) { 488 goto param_error_exit; 489 } 490 491 /* 492 * We always have PE address of form "00BB0001". "BB" 493 * represents the bus number of PE's primary bus. 494 */ 495 option = rtas_ld(args, 3); 496 switch (option) { 497 case RTAS_GET_PE_ADDR: 498 addr = rtas_ld(args, 0); 499 pdev = spapr_pci_find_dev(spapr, buid, addr); 500 if (!pdev) { 501 goto param_error_exit; 502 } 503 504 rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1); 505 break; 506 case RTAS_GET_PE_MODE: 507 rtas_st(rets, 1, RTAS_PE_MODE_SHARED); 508 break; 509 default: 510 goto param_error_exit; 511 } 512 513 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 514 return; 515 516 param_error_exit: 517 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 518 } 519 520 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, 521 sPAPRMachineState *spapr, 522 uint32_t token, uint32_t nargs, 523 target_ulong args, uint32_t nret, 524 target_ulong rets) 525 { 526 sPAPRPHBState *sphb; 527 sPAPRPHBClass *spc; 528 uint64_t buid; 529 int state, ret; 530 531 if ((nargs != 3) || (nret != 4 && nret != 5)) { 532 goto param_error_exit; 533 } 534 535 buid = rtas_ldq(args, 1); 536 sphb = spapr_pci_find_phb(spapr, buid); 537 if (!sphb) { 538 goto param_error_exit; 539 } 540 541 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 542 if (!spc->eeh_get_state) { 543 goto param_error_exit; 544 } 545 546 ret = spc->eeh_get_state(sphb, &state); 547 rtas_st(rets, 0, ret); 548 if (ret != RTAS_OUT_SUCCESS) { 549 return; 550 } 551 552 rtas_st(rets, 1, state); 553 rtas_st(rets, 2, RTAS_EEH_SUPPORT); 554 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); 555 if (nret >= 5) { 556 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); 557 } 558 return; 559 560 param_error_exit: 561 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 562 } 563 564 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, 565 sPAPRMachineState *spapr, 566 uint32_t token, uint32_t nargs, 567 target_ulong args, uint32_t nret, 568 target_ulong rets) 569 { 570 sPAPRPHBState *sphb; 571 sPAPRPHBClass *spc; 572 uint32_t option; 573 uint64_t buid; 574 int ret; 575 576 if ((nargs != 4) || (nret != 1)) { 577 goto param_error_exit; 578 } 579 580 buid = rtas_ldq(args, 1); 581 option = rtas_ld(args, 3); 582 sphb = spapr_pci_find_phb(spapr, buid); 583 if (!sphb) { 584 goto param_error_exit; 585 } 586 587 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 588 if (!spc->eeh_reset) { 589 goto param_error_exit; 590 } 591 592 ret = spc->eeh_reset(sphb, option); 593 rtas_st(rets, 0, ret); 594 return; 595 596 param_error_exit: 597 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 598 } 599 600 static void rtas_ibm_configure_pe(PowerPCCPU *cpu, 601 sPAPRMachineState *spapr, 602 uint32_t token, uint32_t nargs, 603 target_ulong args, uint32_t nret, 604 target_ulong rets) 605 { 606 sPAPRPHBState *sphb; 607 sPAPRPHBClass *spc; 608 uint64_t buid; 609 int ret; 610 611 if ((nargs != 3) || (nret != 1)) { 612 goto param_error_exit; 613 } 614 615 buid = rtas_ldq(args, 1); 616 sphb = spapr_pci_find_phb(spapr, buid); 617 if (!sphb) { 618 goto param_error_exit; 619 } 620 621 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 622 if (!spc->eeh_configure) { 623 goto param_error_exit; 624 } 625 626 ret = spc->eeh_configure(sphb); 627 rtas_st(rets, 0, ret); 628 return; 629 630 param_error_exit: 631 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 632 } 633 634 /* To support it later */ 635 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, 636 sPAPRMachineState *spapr, 637 uint32_t token, uint32_t nargs, 638 target_ulong args, uint32_t nret, 639 target_ulong rets) 640 { 641 sPAPRPHBState *sphb; 642 sPAPRPHBClass *spc; 643 int option; 644 uint64_t buid; 645 646 if ((nargs != 8) || (nret != 1)) { 647 goto param_error_exit; 648 } 649 650 buid = rtas_ldq(args, 1); 651 sphb = spapr_pci_find_phb(spapr, buid); 652 if (!sphb) { 653 goto param_error_exit; 654 } 655 656 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 657 if (!spc->eeh_set_option) { 658 goto param_error_exit; 659 } 660 661 option = rtas_ld(args, 7); 662 switch (option) { 663 case RTAS_SLOT_TEMP_ERR_LOG: 664 case RTAS_SLOT_PERM_ERR_LOG: 665 break; 666 default: 667 goto param_error_exit; 668 } 669 670 /* We don't have error log yet */ 671 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); 672 return; 673 674 param_error_exit: 675 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 676 } 677 678 static int pci_spapr_swizzle(int slot, int pin) 679 { 680 return (slot + pin) % PCI_NUM_PINS; 681 } 682 683 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) 684 { 685 /* 686 * Here we need to convert pci_dev + irq_num to some unique value 687 * which is less than number of IRQs on the specific bus (4). We 688 * use standard PCI swizzling, that is (slot number + pin number) 689 * % 4. 690 */ 691 return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num); 692 } 693 694 static void pci_spapr_set_irq(void *opaque, int irq_num, int level) 695 { 696 /* 697 * Here we use the number returned by pci_spapr_map_irq to find a 698 * corresponding qemu_irq. 699 */ 700 sPAPRPHBState *phb = opaque; 701 702 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); 703 qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); 704 } 705 706 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) 707 { 708 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); 709 PCIINTxRoute route; 710 711 route.mode = PCI_INTX_ENABLED; 712 route.irq = sphb->lsi_table[pin].irq; 713 714 return route; 715 } 716 717 /* 718 * MSI/MSIX memory region implementation. 719 * The handler handles both MSI and MSIX. 720 * For MSI-X, the vector number is encoded as a part of the address, 721 * data is set to 0. 722 * For MSI, the vector number is encoded in least bits in data. 723 */ 724 static void spapr_msi_write(void *opaque, hwaddr addr, 725 uint64_t data, unsigned size) 726 { 727 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 728 uint32_t irq = data; 729 730 trace_spapr_pci_msi_write(addr, data, irq); 731 732 qemu_irq_pulse(xics_get_qirq(spapr->icp, irq)); 733 } 734 735 static const MemoryRegionOps spapr_msi_ops = { 736 /* There is no .read as the read result is undefined by PCI spec */ 737 .read = NULL, 738 .write = spapr_msi_write, 739 .endianness = DEVICE_LITTLE_ENDIAN 740 }; 741 742 /* 743 * PHB PCI device 744 */ 745 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 746 { 747 sPAPRPHBState *phb = opaque; 748 749 return &phb->iommu_as; 750 } 751 752 static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) 753 { 754 char *path = NULL, *buf = NULL, *host = NULL; 755 756 /* Get the PCI VFIO host id */ 757 host = object_property_get_str(OBJECT(pdev), "host", NULL); 758 if (!host) { 759 goto err_out; 760 } 761 762 /* Construct the path of the file that will give us the DT location */ 763 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); 764 g_free(host); 765 if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { 766 goto err_out; 767 } 768 g_free(path); 769 770 /* Construct and read from host device tree the loc-code */ 771 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); 772 g_free(buf); 773 if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { 774 goto err_out; 775 } 776 return buf; 777 778 err_out: 779 g_free(path); 780 return NULL; 781 } 782 783 static char *spapr_phb_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) 784 { 785 char *buf; 786 const char *devtype = "qemu"; 787 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 788 789 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 790 buf = spapr_phb_vfio_get_loc_code(sphb, pdev); 791 if (buf) { 792 return buf; 793 } 794 devtype = "vfio"; 795 } 796 /* 797 * For emulated devices and VFIO-failure case, make up 798 * the loc-code. 799 */ 800 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", 801 devtype, pdev->name, sphb->index, busnr, 802 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 803 return buf; 804 } 805 806 /* Macros to operate with address in OF binding to PCI */ 807 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) 808 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ 809 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ 810 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ 811 #define b_ss(x) b_x((x), 24, 2) /* the space code */ 812 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ 813 #define b_ddddd(x) b_x((x), 11, 5) /* device number */ 814 #define b_fff(x) b_x((x), 8, 3) /* function number */ 815 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ 816 817 /* for 'reg'/'assigned-addresses' OF properties */ 818 #define RESOURCE_CELLS_SIZE 2 819 #define RESOURCE_CELLS_ADDRESS 3 820 821 typedef struct ResourceFields { 822 uint32_t phys_hi; 823 uint32_t phys_mid; 824 uint32_t phys_lo; 825 uint32_t size_hi; 826 uint32_t size_lo; 827 } QEMU_PACKED ResourceFields; 828 829 typedef struct ResourceProps { 830 ResourceFields reg[8]; 831 ResourceFields assigned[7]; 832 uint32_t reg_len; 833 uint32_t assigned_len; 834 } ResourceProps; 835 836 /* fill in the 'reg'/'assigned-resources' OF properties for 837 * a PCI device. 'reg' describes resource requirements for a 838 * device's IO/MEM regions, 'assigned-addresses' describes the 839 * actual resource assignments. 840 * 841 * the properties are arrays of ('phys-addr', 'size') pairs describing 842 * the addressable regions of the PCI device, where 'phys-addr' is a 843 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to 844 * (phys.hi, phys.mid, phys.lo), and 'size' is a 845 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). 846 * 847 * phys.hi = 0xYYXXXXZZ, where: 848 * 0xYY = npt000ss 849 * ||| | 850 * ||| +-- space code 851 * ||| | 852 * ||| + 00 if configuration space 853 * ||| + 01 if IO region, 854 * ||| + 10 if 32-bit MEM region 855 * ||| + 11 if 64-bit MEM region 856 * ||| 857 * ||+------ for non-relocatable IO: 1 if aliased 858 * || for relocatable IO: 1 if below 64KB 859 * || for MEM: 1 if below 1MB 860 * |+------- 1 if region is prefetchable 861 * +-------- 1 if region is non-relocatable 862 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function 863 * bits respectively 864 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding 865 * to the region 866 * 867 * phys.mid and phys.lo correspond respectively to the hi/lo portions 868 * of the actual address of the region. 869 * 870 * how the phys-addr/size values are used differ slightly between 871 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has 872 * an additional description for the config space region of the 873 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0 874 * to describe the region as relocatable, with an address-mapping 875 * that corresponds directly to the PHB's address space for the 876 * resource. 'assigned-addresses' always has n=1 set with an absolute 877 * address assigned for the resource. in general, 'assigned-addresses' 878 * won't be populated, since addresses for PCI devices are generally 879 * unmapped initially and left to the guest to assign. 880 * 881 * note also that addresses defined in these properties are, at least 882 * for PAPR guests, relative to the PHBs IO/MEM windows, and 883 * correspond directly to the addresses in the BARs. 884 * 885 * in accordance with PCI Bus Binding to Open Firmware, 886 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, 887 * Appendix C. 888 */ 889 static void populate_resource_props(PCIDevice *d, ResourceProps *rp) 890 { 891 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); 892 uint32_t dev_id = (b_bbbbbbbb(bus_num) | 893 b_ddddd(PCI_SLOT(d->devfn)) | 894 b_fff(PCI_FUNC(d->devfn))); 895 ResourceFields *reg, *assigned; 896 int i, reg_idx = 0, assigned_idx = 0; 897 898 /* config space region */ 899 reg = &rp->reg[reg_idx++]; 900 reg->phys_hi = cpu_to_be32(dev_id); 901 reg->phys_mid = 0; 902 reg->phys_lo = 0; 903 reg->size_hi = 0; 904 reg->size_lo = 0; 905 906 for (i = 0; i < PCI_NUM_REGIONS; i++) { 907 if (!d->io_regions[i].size) { 908 continue; 909 } 910 911 reg = &rp->reg[reg_idx++]; 912 913 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); 914 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 915 reg->phys_hi |= cpu_to_be32(b_ss(1)); 916 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 917 reg->phys_hi |= cpu_to_be32(b_ss(3)); 918 } else { 919 reg->phys_hi |= cpu_to_be32(b_ss(2)); 920 } 921 reg->phys_mid = 0; 922 reg->phys_lo = 0; 923 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); 924 reg->size_lo = cpu_to_be32(d->io_regions[i].size); 925 926 if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) { 927 continue; 928 } 929 930 assigned = &rp->assigned[assigned_idx++]; 931 assigned->phys_hi = cpu_to_be32(reg->phys_hi | b_n(1)); 932 assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32); 933 assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr); 934 assigned->size_hi = reg->size_hi; 935 assigned->size_lo = reg->size_lo; 936 } 937 938 rp->reg_len = reg_idx * sizeof(ResourceFields); 939 rp->assigned_len = assigned_idx * sizeof(ResourceFields); 940 } 941 942 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, 943 PCIDevice *pdev); 944 945 static int spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset, 946 sPAPRPHBState *sphb) 947 { 948 ResourceProps rp; 949 bool is_bridge = false; 950 int pci_status, err; 951 char *buf = NULL; 952 uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev); 953 uint32_t max_msi, max_msix; 954 955 if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) == 956 PCI_HEADER_TYPE_BRIDGE) { 957 is_bridge = true; 958 } 959 960 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ 961 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", 962 pci_default_read_config(dev, PCI_VENDOR_ID, 2))); 963 _FDT(fdt_setprop_cell(fdt, offset, "device-id", 964 pci_default_read_config(dev, PCI_DEVICE_ID, 2))); 965 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", 966 pci_default_read_config(dev, PCI_REVISION_ID, 1))); 967 _FDT(fdt_setprop_cell(fdt, offset, "class-code", 968 pci_default_read_config(dev, PCI_CLASS_PROG, 3))); 969 if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) { 970 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", 971 pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1))); 972 } 973 974 if (!is_bridge) { 975 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", 976 pci_default_read_config(dev, PCI_MIN_GNT, 1))); 977 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", 978 pci_default_read_config(dev, PCI_MAX_LAT, 1))); 979 } 980 981 if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) { 982 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", 983 pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2))); 984 } 985 986 if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) { 987 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", 988 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2))); 989 } 990 991 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", 992 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1))); 993 994 /* the following fdt cells are masked off the pci status register */ 995 pci_status = pci_default_read_config(dev, PCI_STATUS, 2); 996 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", 997 PCI_STATUS_DEVSEL_MASK & pci_status)); 998 999 if (pci_status & PCI_STATUS_FAST_BACK) { 1000 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); 1001 } 1002 if (pci_status & PCI_STATUS_66MHZ) { 1003 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); 1004 } 1005 if (pci_status & PCI_STATUS_UDF) { 1006 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); 1007 } 1008 1009 /* NOTE: this is normally generated by firmware via path/unit name, 1010 * but in our case we must set it manually since it does not get 1011 * processed by OF beforehand 1012 */ 1013 _FDT(fdt_setprop_string(fdt, offset, "name", "pci")); 1014 buf = spapr_phb_get_loc_code(sphb, dev); 1015 if (!buf) { 1016 error_report("Failed setting the ibm,loc-code"); 1017 return -1; 1018 } 1019 1020 err = fdt_setprop_string(fdt, offset, "ibm,loc-code", buf); 1021 g_free(buf); 1022 if (err < 0) { 1023 return err; 1024 } 1025 1026 if (drc_index) { 1027 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)); 1028 } 1029 1030 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 1031 RESOURCE_CELLS_ADDRESS)); 1032 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1033 RESOURCE_CELLS_SIZE)); 1034 1035 max_msi = msi_nr_vectors_allocated(dev); 1036 if (max_msi) { 1037 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi)); 1038 } 1039 max_msix = dev->msix_entries_nr; 1040 if (max_msix) { 1041 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix)); 1042 } 1043 1044 populate_resource_props(dev, &rp); 1045 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); 1046 _FDT(fdt_setprop(fdt, offset, "assigned-addresses", 1047 (uint8_t *)rp.assigned, rp.assigned_len)); 1048 1049 return 0; 1050 } 1051 1052 /* create OF node for pci device and required OF DT properties */ 1053 static int spapr_create_pci_child_dt(sPAPRPHBState *phb, PCIDevice *dev, 1054 void *fdt, int node_offset) 1055 { 1056 int offset, ret; 1057 int slot = PCI_SLOT(dev->devfn); 1058 int func = PCI_FUNC(dev->devfn); 1059 char nodename[FDT_NAME_MAX]; 1060 1061 if (func != 0) { 1062 snprintf(nodename, FDT_NAME_MAX, "pci@%x,%x", slot, func); 1063 } else { 1064 snprintf(nodename, FDT_NAME_MAX, "pci@%x", slot); 1065 } 1066 offset = fdt_add_subnode(fdt, node_offset, nodename); 1067 ret = spapr_populate_pci_child_dt(dev, fdt, offset, phb); 1068 1069 g_assert(!ret); 1070 if (ret) { 1071 return 0; 1072 } 1073 return offset; 1074 } 1075 1076 static void spapr_phb_add_pci_device(sPAPRDRConnector *drc, 1077 sPAPRPHBState *phb, 1078 PCIDevice *pdev, 1079 Error **errp) 1080 { 1081 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1082 DeviceState *dev = DEVICE(pdev); 1083 void *fdt = NULL; 1084 int fdt_start_offset = 0, fdt_size; 1085 1086 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 1087 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(phb->dma_liobn); 1088 1089 spapr_tce_set_need_vfio(tcet, true); 1090 } 1091 1092 if (dev->hotplugged) { 1093 fdt = create_device_tree(&fdt_size); 1094 fdt_start_offset = spapr_create_pci_child_dt(phb, pdev, fdt, 0); 1095 if (!fdt_start_offset) { 1096 error_setg(errp, "Failed to create pci child device tree node"); 1097 goto out; 1098 } 1099 } 1100 1101 drck->attach(drc, DEVICE(pdev), 1102 fdt, fdt_start_offset, !dev->hotplugged, errp); 1103 out: 1104 if (*errp) { 1105 g_free(fdt); 1106 } 1107 } 1108 1109 static void spapr_phb_remove_pci_device_cb(DeviceState *dev, void *opaque) 1110 { 1111 /* some version guests do not wait for completion of a device 1112 * cleanup (generally done asynchronously by the kernel) before 1113 * signaling to QEMU that the device is safe, but instead sleep 1114 * for some 'safe' period of time. unfortunately on a busy host 1115 * this sleep isn't guaranteed to be long enough, resulting in 1116 * bad things like IRQ lines being left asserted during final 1117 * device removal. to deal with this we call reset just prior 1118 * to finalizing the device, which will put the device back into 1119 * an 'idle' state, as the device cleanup code expects. 1120 */ 1121 pci_device_reset(PCI_DEVICE(dev)); 1122 object_unparent(OBJECT(dev)); 1123 } 1124 1125 static void spapr_phb_remove_pci_device(sPAPRDRConnector *drc, 1126 sPAPRPHBState *phb, 1127 PCIDevice *pdev, 1128 Error **errp) 1129 { 1130 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1131 1132 drck->detach(drc, DEVICE(pdev), spapr_phb_remove_pci_device_cb, phb, errp); 1133 } 1134 1135 static sPAPRDRConnector *spapr_phb_get_pci_drc(sPAPRPHBState *phb, 1136 PCIDevice *pdev) 1137 { 1138 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 1139 return spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_PCI, 1140 (phb->index << 16) | 1141 (busnr << 8) | 1142 pdev->devfn); 1143 } 1144 1145 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, 1146 PCIDevice *pdev) 1147 { 1148 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1149 sPAPRDRConnectorClass *drck; 1150 1151 if (!drc) { 1152 return 0; 1153 } 1154 1155 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1156 return drck->get_index(drc); 1157 } 1158 1159 static void spapr_phb_hot_plug_child(HotplugHandler *plug_handler, 1160 DeviceState *plugged_dev, Error **errp) 1161 { 1162 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1163 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1164 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1165 Error *local_err = NULL; 1166 1167 /* if DR is disabled we don't need to do anything in the case of 1168 * hotplug or coldplug callbacks 1169 */ 1170 if (!phb->dr_enabled) { 1171 /* if this is a hotplug operation initiated by the user 1172 * we need to let them know it's not enabled 1173 */ 1174 if (plugged_dev->hotplugged) { 1175 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1176 object_get_typename(OBJECT(phb))); 1177 } 1178 return; 1179 } 1180 1181 g_assert(drc); 1182 1183 spapr_phb_add_pci_device(drc, phb, pdev, &local_err); 1184 if (local_err) { 1185 error_propagate(errp, local_err); 1186 return; 1187 } 1188 if (plugged_dev->hotplugged) { 1189 spapr_hotplug_req_add_by_index(drc); 1190 } 1191 } 1192 1193 static void spapr_phb_hot_unplug_child(HotplugHandler *plug_handler, 1194 DeviceState *plugged_dev, Error **errp) 1195 { 1196 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1197 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1198 sPAPRDRConnectorClass *drck; 1199 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1200 Error *local_err = NULL; 1201 1202 if (!phb->dr_enabled) { 1203 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1204 object_get_typename(OBJECT(phb))); 1205 return; 1206 } 1207 1208 g_assert(drc); 1209 1210 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1211 if (!drck->release_pending(drc)) { 1212 spapr_phb_remove_pci_device(drc, phb, pdev, &local_err); 1213 if (local_err) { 1214 error_propagate(errp, local_err); 1215 return; 1216 } 1217 spapr_hotplug_req_remove_by_index(drc); 1218 } 1219 } 1220 1221 static void spapr_phb_realize(DeviceState *dev, Error **errp) 1222 { 1223 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1224 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1225 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); 1226 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1227 sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(s); 1228 char *namebuf; 1229 int i; 1230 PCIBus *bus; 1231 uint64_t msi_window_size = 4096; 1232 1233 if (sphb->index != (uint32_t)-1) { 1234 hwaddr windows_base; 1235 1236 if ((sphb->buid != (uint64_t)-1) || (sphb->dma_liobn != (uint32_t)-1) 1237 || (sphb->mem_win_addr != (hwaddr)-1) 1238 || (sphb->io_win_addr != (hwaddr)-1)) { 1239 error_setg(errp, "Either \"index\" or other parameters must" 1240 " be specified for PAPR PHB, not both"); 1241 return; 1242 } 1243 1244 if (sphb->index > SPAPR_PCI_MAX_INDEX) { 1245 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 1246 SPAPR_PCI_MAX_INDEX); 1247 return; 1248 } 1249 1250 sphb->buid = SPAPR_PCI_BASE_BUID + sphb->index; 1251 sphb->dma_liobn = SPAPR_PCI_LIOBN(sphb->index, 0); 1252 1253 windows_base = SPAPR_PCI_WINDOW_BASE 1254 + sphb->index * SPAPR_PCI_WINDOW_SPACING; 1255 sphb->mem_win_addr = windows_base + SPAPR_PCI_MMIO_WIN_OFF; 1256 sphb->io_win_addr = windows_base + SPAPR_PCI_IO_WIN_OFF; 1257 } 1258 1259 if (sphb->buid == (uint64_t)-1) { 1260 error_setg(errp, "BUID not specified for PHB"); 1261 return; 1262 } 1263 1264 if (sphb->dma_liobn == (uint32_t)-1) { 1265 error_setg(errp, "LIOBN not specified for PHB"); 1266 return; 1267 } 1268 1269 if (sphb->mem_win_addr == (hwaddr)-1) { 1270 error_setg(errp, "Memory window address not specified for PHB"); 1271 return; 1272 } 1273 1274 if (sphb->io_win_addr == (hwaddr)-1) { 1275 error_setg(errp, "IO window address not specified for PHB"); 1276 return; 1277 } 1278 1279 if (spapr_pci_find_phb(spapr, sphb->buid)) { 1280 error_setg(errp, "PCI host bridges must have unique BUIDs"); 1281 return; 1282 } 1283 1284 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); 1285 1286 namebuf = alloca(strlen(sphb->dtbusname) + 32); 1287 1288 /* Initialize memory regions */ 1289 sprintf(namebuf, "%s.mmio", sphb->dtbusname); 1290 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); 1291 1292 sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname); 1293 memory_region_init_alias(&sphb->memwindow, OBJECT(sphb), 1294 namebuf, &sphb->memspace, 1295 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); 1296 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, 1297 &sphb->memwindow); 1298 1299 /* Initialize IO regions */ 1300 sprintf(namebuf, "%s.io", sphb->dtbusname); 1301 memory_region_init(&sphb->iospace, OBJECT(sphb), 1302 namebuf, SPAPR_PCI_IO_WIN_SIZE); 1303 1304 sprintf(namebuf, "%s.io-alias", sphb->dtbusname); 1305 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, 1306 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); 1307 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, 1308 &sphb->iowindow); 1309 1310 bus = pci_register_bus(dev, NULL, 1311 pci_spapr_set_irq, pci_spapr_map_irq, sphb, 1312 &sphb->memspace, &sphb->iospace, 1313 PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); 1314 phb->bus = bus; 1315 qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL); 1316 1317 /* 1318 * Initialize PHB address space. 1319 * By default there will be at least one subregion for default 1320 * 32bit DMA window. 1321 * Later the guest might want to create another DMA window 1322 * which will become another memory subregion. 1323 */ 1324 sprintf(namebuf, "%s.iommu-root", sphb->dtbusname); 1325 1326 memory_region_init(&sphb->iommu_root, OBJECT(sphb), 1327 namebuf, UINT64_MAX); 1328 address_space_init(&sphb->iommu_as, &sphb->iommu_root, 1329 sphb->dtbusname); 1330 1331 /* 1332 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, 1333 * we need to allocate some memory to catch those writes coming 1334 * from msi_notify()/msix_notify(). 1335 * As MSIMessage:addr is going to be the same and MSIMessage:data 1336 * is going to be a VIRQ number, 4 bytes of the MSI MR will only 1337 * be used. 1338 * 1339 * For KVM we want to ensure that this memory is a full page so that 1340 * our memory slot is of page size granularity. 1341 */ 1342 #ifdef CONFIG_KVM 1343 if (kvm_enabled()) { 1344 msi_window_size = getpagesize(); 1345 } 1346 #endif 1347 1348 memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr, 1349 "msi", msi_window_size); 1350 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, 1351 &sphb->msiwindow); 1352 1353 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); 1354 1355 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); 1356 1357 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); 1358 1359 /* Initialize the LSI table */ 1360 for (i = 0; i < PCI_NUM_PINS; i++) { 1361 uint32_t irq; 1362 1363 irq = xics_alloc_block(spapr->icp, 0, 1, true, false); 1364 if (!irq) { 1365 error_setg(errp, "spapr_allocate_lsi failed"); 1366 return; 1367 } 1368 1369 sphb->lsi_table[i].irq = irq; 1370 } 1371 1372 /* allocate connectors for child PCI devices */ 1373 if (sphb->dr_enabled) { 1374 for (i = 0; i < PCI_SLOT_MAX * 8; i++) { 1375 spapr_dr_connector_new(OBJECT(phb), 1376 SPAPR_DR_CONNECTOR_TYPE_PCI, 1377 (sphb->index << 16) | i); 1378 } 1379 } 1380 1381 if (!info->finish_realize) { 1382 error_setg(errp, "finish_realize not defined"); 1383 return; 1384 } 1385 1386 info->finish_realize(sphb, errp); 1387 1388 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); 1389 } 1390 1391 static void spapr_phb_finish_realize(sPAPRPHBState *sphb, Error **errp) 1392 { 1393 sPAPRTCETable *tcet; 1394 uint32_t nb_table; 1395 1396 nb_table = sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT; 1397 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn, 1398 0, SPAPR_TCE_PAGE_SHIFT, nb_table, false); 1399 if (!tcet) { 1400 error_setg(errp, "Unable to create TCE table for %s", 1401 sphb->dtbusname); 1402 return ; 1403 } 1404 1405 /* Register default 32bit DMA window */ 1406 memory_region_add_subregion(&sphb->iommu_root, sphb->dma_win_addr, 1407 spapr_tce_get_iommu(tcet)); 1408 } 1409 1410 static int spapr_phb_children_reset(Object *child, void *opaque) 1411 { 1412 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); 1413 1414 if (dev) { 1415 device_reset(dev); 1416 } 1417 1418 return 0; 1419 } 1420 1421 static void spapr_phb_reset(DeviceState *qdev) 1422 { 1423 /* Reset the IOMMU state */ 1424 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); 1425 } 1426 1427 static Property spapr_phb_properties[] = { 1428 DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1), 1429 DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1), 1430 DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn, -1), 1431 DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1), 1432 DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size, 1433 SPAPR_PCI_MMIO_WIN_SIZE), 1434 DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1), 1435 DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size, 1436 SPAPR_PCI_IO_WIN_SIZE), 1437 DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled, 1438 true), 1439 /* Default DMA window is 0..1GB */ 1440 DEFINE_PROP_UINT64("dma_win_addr", sPAPRPHBState, dma_win_addr, 0), 1441 DEFINE_PROP_UINT64("dma_win_size", sPAPRPHBState, dma_win_size, 0x40000000), 1442 DEFINE_PROP_END_OF_LIST(), 1443 }; 1444 1445 static const VMStateDescription vmstate_spapr_pci_lsi = { 1446 .name = "spapr_pci/lsi", 1447 .version_id = 1, 1448 .minimum_version_id = 1, 1449 .fields = (VMStateField[]) { 1450 VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi), 1451 1452 VMSTATE_END_OF_LIST() 1453 }, 1454 }; 1455 1456 static const VMStateDescription vmstate_spapr_pci_msi = { 1457 .name = "spapr_pci/msi", 1458 .version_id = 1, 1459 .minimum_version_id = 1, 1460 .fields = (VMStateField []) { 1461 VMSTATE_UINT32(key, spapr_pci_msi_mig), 1462 VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig), 1463 VMSTATE_UINT32(value.num, spapr_pci_msi_mig), 1464 VMSTATE_END_OF_LIST() 1465 }, 1466 }; 1467 1468 static void spapr_pci_pre_save(void *opaque) 1469 { 1470 sPAPRPHBState *sphb = opaque; 1471 GHashTableIter iter; 1472 gpointer key, value; 1473 int i; 1474 1475 g_free(sphb->msi_devs); 1476 sphb->msi_devs = NULL; 1477 sphb->msi_devs_num = g_hash_table_size(sphb->msi); 1478 if (!sphb->msi_devs_num) { 1479 return; 1480 } 1481 sphb->msi_devs = g_malloc(sphb->msi_devs_num * sizeof(spapr_pci_msi_mig)); 1482 1483 g_hash_table_iter_init(&iter, sphb->msi); 1484 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { 1485 sphb->msi_devs[i].key = *(uint32_t *) key; 1486 sphb->msi_devs[i].value = *(spapr_pci_msi *) value; 1487 } 1488 } 1489 1490 static int spapr_pci_post_load(void *opaque, int version_id) 1491 { 1492 sPAPRPHBState *sphb = opaque; 1493 gpointer key, value; 1494 int i; 1495 1496 for (i = 0; i < sphb->msi_devs_num; ++i) { 1497 key = g_memdup(&sphb->msi_devs[i].key, 1498 sizeof(sphb->msi_devs[i].key)); 1499 value = g_memdup(&sphb->msi_devs[i].value, 1500 sizeof(sphb->msi_devs[i].value)); 1501 g_hash_table_insert(sphb->msi, key, value); 1502 } 1503 g_free(sphb->msi_devs); 1504 sphb->msi_devs = NULL; 1505 sphb->msi_devs_num = 0; 1506 1507 return 0; 1508 } 1509 1510 static const VMStateDescription vmstate_spapr_pci = { 1511 .name = "spapr_pci", 1512 .version_id = 2, 1513 .minimum_version_id = 2, 1514 .pre_save = spapr_pci_pre_save, 1515 .post_load = spapr_pci_post_load, 1516 .fields = (VMStateField[]) { 1517 VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState), 1518 VMSTATE_UINT32_EQUAL(dma_liobn, sPAPRPHBState), 1519 VMSTATE_UINT64_EQUAL(mem_win_addr, sPAPRPHBState), 1520 VMSTATE_UINT64_EQUAL(mem_win_size, sPAPRPHBState), 1521 VMSTATE_UINT64_EQUAL(io_win_addr, sPAPRPHBState), 1522 VMSTATE_UINT64_EQUAL(io_win_size, sPAPRPHBState), 1523 VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0, 1524 vmstate_spapr_pci_lsi, struct spapr_pci_lsi), 1525 VMSTATE_INT32(msi_devs_num, sPAPRPHBState), 1526 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0, 1527 vmstate_spapr_pci_msi, spapr_pci_msi_mig), 1528 VMSTATE_END_OF_LIST() 1529 }, 1530 }; 1531 1532 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, 1533 PCIBus *rootbus) 1534 { 1535 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); 1536 1537 return sphb->dtbusname; 1538 } 1539 1540 static void spapr_phb_class_init(ObjectClass *klass, void *data) 1541 { 1542 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 1543 DeviceClass *dc = DEVICE_CLASS(klass); 1544 sPAPRPHBClass *spc = SPAPR_PCI_HOST_BRIDGE_CLASS(klass); 1545 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); 1546 1547 hc->root_bus_path = spapr_phb_root_bus_path; 1548 dc->realize = spapr_phb_realize; 1549 dc->props = spapr_phb_properties; 1550 dc->reset = spapr_phb_reset; 1551 dc->vmsd = &vmstate_spapr_pci; 1552 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 1553 dc->cannot_instantiate_with_device_add_yet = false; 1554 spc->finish_realize = spapr_phb_finish_realize; 1555 hp->plug = spapr_phb_hot_plug_child; 1556 hp->unplug = spapr_phb_hot_unplug_child; 1557 } 1558 1559 static const TypeInfo spapr_phb_info = { 1560 .name = TYPE_SPAPR_PCI_HOST_BRIDGE, 1561 .parent = TYPE_PCI_HOST_BRIDGE, 1562 .instance_size = sizeof(sPAPRPHBState), 1563 .class_init = spapr_phb_class_init, 1564 .class_size = sizeof(sPAPRPHBClass), 1565 .interfaces = (InterfaceInfo[]) { 1566 { TYPE_HOTPLUG_HANDLER }, 1567 { } 1568 } 1569 }; 1570 1571 PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index) 1572 { 1573 DeviceState *dev; 1574 1575 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 1576 qdev_prop_set_uint32(dev, "index", index); 1577 qdev_init_nofail(dev); 1578 1579 return PCI_HOST_BRIDGE(dev); 1580 } 1581 1582 typedef struct sPAPRFDT { 1583 void *fdt; 1584 int node_off; 1585 sPAPRPHBState *sphb; 1586 } sPAPRFDT; 1587 1588 static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev, 1589 void *opaque) 1590 { 1591 PCIBus *sec_bus; 1592 sPAPRFDT *p = opaque; 1593 int offset; 1594 sPAPRFDT s_fdt; 1595 1596 offset = spapr_create_pci_child_dt(p->sphb, pdev, p->fdt, p->node_off); 1597 if (!offset) { 1598 error_report("Failed to create pci child device tree node"); 1599 return; 1600 } 1601 1602 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 1603 PCI_HEADER_TYPE_BRIDGE)) { 1604 return; 1605 } 1606 1607 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 1608 if (!sec_bus) { 1609 return; 1610 } 1611 1612 s_fdt.fdt = p->fdt; 1613 s_fdt.node_off = offset; 1614 s_fdt.sphb = p->sphb; 1615 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 1616 spapr_populate_pci_devices_dt, 1617 &s_fdt); 1618 } 1619 1620 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, 1621 void *opaque) 1622 { 1623 unsigned int *bus_no = opaque; 1624 unsigned int primary = *bus_no; 1625 unsigned int subordinate = 0xff; 1626 PCIBus *sec_bus = NULL; 1627 1628 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 1629 PCI_HEADER_TYPE_BRIDGE)) { 1630 return; 1631 } 1632 1633 (*bus_no)++; 1634 pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1); 1635 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); 1636 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 1637 1638 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 1639 if (!sec_bus) { 1640 return; 1641 } 1642 1643 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1); 1644 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 1645 spapr_phb_pci_enumerate_bridge, bus_no); 1646 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 1647 } 1648 1649 static void spapr_phb_pci_enumerate(sPAPRPHBState *phb) 1650 { 1651 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 1652 unsigned int bus_no = 0; 1653 1654 pci_for_each_device(bus, pci_bus_num(bus), 1655 spapr_phb_pci_enumerate_bridge, 1656 &bus_no); 1657 1658 } 1659 1660 int spapr_populate_pci_dt(sPAPRPHBState *phb, 1661 uint32_t xics_phandle, 1662 void *fdt) 1663 { 1664 int bus_off, i, j, ret; 1665 char nodename[FDT_NAME_MAX]; 1666 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; 1667 const uint64_t mmiosize = memory_region_size(&phb->memwindow); 1668 const uint64_t w32max = (1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET; 1669 const uint64_t w32size = MIN(w32max, mmiosize); 1670 const uint64_t w64size = (mmiosize > w32size) ? (mmiosize - w32size) : 0; 1671 struct { 1672 uint32_t hi; 1673 uint64_t child; 1674 uint64_t parent; 1675 uint64_t size; 1676 } QEMU_PACKED ranges[] = { 1677 { 1678 cpu_to_be32(b_ss(1)), cpu_to_be64(0), 1679 cpu_to_be64(phb->io_win_addr), 1680 cpu_to_be64(memory_region_size(&phb->iospace)), 1681 }, 1682 { 1683 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), 1684 cpu_to_be64(phb->mem_win_addr), 1685 cpu_to_be64(w32size), 1686 }, 1687 { 1688 cpu_to_be32(b_ss(3)), cpu_to_be64(1ULL << 32), 1689 cpu_to_be64(phb->mem_win_addr + w32size), 1690 cpu_to_be64(w64size) 1691 }, 1692 }; 1693 const unsigned sizeof_ranges = (w64size ? 3 : 2) * sizeof(ranges[0]); 1694 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; 1695 uint32_t interrupt_map_mask[] = { 1696 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; 1697 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; 1698 sPAPRTCETable *tcet; 1699 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 1700 sPAPRFDT s_fdt; 1701 1702 /* Start populating the FDT */ 1703 snprintf(nodename, FDT_NAME_MAX, "pci@%" PRIx64, phb->buid); 1704 bus_off = fdt_add_subnode(fdt, 0, nodename); 1705 if (bus_off < 0) { 1706 return bus_off; 1707 } 1708 1709 /* Write PHB properties */ 1710 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); 1711 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); 1712 _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); 1713 _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); 1714 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); 1715 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); 1716 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); 1717 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); 1718 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); 1719 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); 1720 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS)); 1721 1722 /* Build the interrupt-map, this must matches what is done 1723 * in pci_spapr_map_irq 1724 */ 1725 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", 1726 &interrupt_map_mask, sizeof(interrupt_map_mask))); 1727 for (i = 0; i < PCI_SLOT_MAX; i++) { 1728 for (j = 0; j < PCI_NUM_PINS; j++) { 1729 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; 1730 int lsi_num = pci_spapr_swizzle(i, j); 1731 1732 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); 1733 irqmap[1] = 0; 1734 irqmap[2] = 0; 1735 irqmap[3] = cpu_to_be32(j+1); 1736 irqmap[4] = cpu_to_be32(xics_phandle); 1737 irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq); 1738 irqmap[6] = cpu_to_be32(0x8); 1739 } 1740 } 1741 /* Write interrupt map */ 1742 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, 1743 sizeof(interrupt_map))); 1744 1745 tcet = spapr_tce_find_by_liobn(SPAPR_PCI_LIOBN(phb->index, 0)); 1746 spapr_dma_dt(fdt, bus_off, "ibm,dma-window", 1747 tcet->liobn, tcet->bus_offset, 1748 tcet->nb_table << tcet->page_shift); 1749 1750 /* Walk the bridges and program the bus numbers*/ 1751 spapr_phb_pci_enumerate(phb); 1752 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); 1753 1754 /* Populate tree nodes with PCI devices attached */ 1755 s_fdt.fdt = fdt; 1756 s_fdt.node_off = bus_off; 1757 s_fdt.sphb = phb; 1758 pci_for_each_device(bus, pci_bus_num(bus), 1759 spapr_populate_pci_devices_dt, 1760 &s_fdt); 1761 1762 ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb), 1763 SPAPR_DR_CONNECTOR_TYPE_PCI); 1764 if (ret) { 1765 return ret; 1766 } 1767 1768 return 0; 1769 } 1770 1771 void spapr_pci_rtas_init(void) 1772 { 1773 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", 1774 rtas_read_pci_config); 1775 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", 1776 rtas_write_pci_config); 1777 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", 1778 rtas_ibm_read_pci_config); 1779 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", 1780 rtas_ibm_write_pci_config); 1781 if (msi_supported) { 1782 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, 1783 "ibm,query-interrupt-source-number", 1784 rtas_ibm_query_interrupt_source_number); 1785 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", 1786 rtas_ibm_change_msi); 1787 } 1788 1789 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, 1790 "ibm,set-eeh-option", 1791 rtas_ibm_set_eeh_option); 1792 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, 1793 "ibm,get-config-addr-info2", 1794 rtas_ibm_get_config_addr_info2); 1795 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, 1796 "ibm,read-slot-reset-state2", 1797 rtas_ibm_read_slot_reset_state2); 1798 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, 1799 "ibm,set-slot-reset", 1800 rtas_ibm_set_slot_reset); 1801 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, 1802 "ibm,configure-pe", 1803 rtas_ibm_configure_pe); 1804 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, 1805 "ibm,slot-error-detail", 1806 rtas_ibm_slot_error_detail); 1807 } 1808 1809 static void spapr_pci_register_types(void) 1810 { 1811 type_register_static(&spapr_phb_info); 1812 } 1813 1814 type_init(spapr_pci_register_types) 1815 1816 static int spapr_switch_one_vga(DeviceState *dev, void *opaque) 1817 { 1818 bool be = *(bool *)opaque; 1819 1820 if (object_dynamic_cast(OBJECT(dev), "VGA") 1821 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { 1822 object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", 1823 &error_abort); 1824 } 1825 return 0; 1826 } 1827 1828 void spapr_pci_switch_vga(bool big_endian) 1829 { 1830 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1831 sPAPRPHBState *sphb; 1832 1833 /* 1834 * For backward compatibility with existing guests, we switch 1835 * the endianness of the VGA controller when changing the guest 1836 * interrupt mode 1837 */ 1838 QLIST_FOREACH(sphb, &spapr->phbs, list) { 1839 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; 1840 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, 1841 &big_endian); 1842 } 1843 } 1844