1 /* 2 * QEMU sPAPR PCI host originated from Uninorth PCI host 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. 5 * Copyright (C) 2011 David Gibson, IBM Corporation. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "hw/hw.h" 26 #include "hw/sysbus.h" 27 #include "hw/pci/pci.h" 28 #include "hw/pci/msi.h" 29 #include "hw/pci/msix.h" 30 #include "hw/pci/pci_host.h" 31 #include "hw/ppc/spapr.h" 32 #include "hw/pci-host/spapr.h" 33 #include "exec/address-spaces.h" 34 #include <libfdt.h> 35 #include "trace.h" 36 #include "qemu/error-report.h" 37 #include "qapi/qmp/qerror.h" 38 39 #include "hw/pci/pci_bridge.h" 40 #include "hw/pci/pci_bus.h" 41 #include "hw/ppc/spapr_drc.h" 42 #include "sysemu/device_tree.h" 43 44 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ 45 #define RTAS_QUERY_FN 0 46 #define RTAS_CHANGE_FN 1 47 #define RTAS_RESET_FN 2 48 #define RTAS_CHANGE_MSI_FN 3 49 #define RTAS_CHANGE_MSIX_FN 4 50 51 /* Interrupt types to return on RTAS_CHANGE_* */ 52 #define RTAS_TYPE_MSI 1 53 #define RTAS_TYPE_MSIX 2 54 55 #define FDT_NAME_MAX 128 56 57 #define _FDT(exp) \ 58 do { \ 59 int ret = (exp); \ 60 if (ret < 0) { \ 61 return ret; \ 62 } \ 63 } while (0) 64 65 sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid) 66 { 67 sPAPRPHBState *sphb; 68 69 QLIST_FOREACH(sphb, &spapr->phbs, list) { 70 if (sphb->buid != buid) { 71 continue; 72 } 73 return sphb; 74 } 75 76 return NULL; 77 } 78 79 PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid, 80 uint32_t config_addr) 81 { 82 sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid); 83 PCIHostState *phb = PCI_HOST_BRIDGE(sphb); 84 int bus_num = (config_addr >> 16) & 0xFF; 85 int devfn = (config_addr >> 8) & 0xFF; 86 87 if (!phb) { 88 return NULL; 89 } 90 91 return pci_find_device(phb->bus, bus_num, devfn); 92 } 93 94 static uint32_t rtas_pci_cfgaddr(uint32_t arg) 95 { 96 /* This handles the encoding of extended config space addresses */ 97 return ((arg >> 20) & 0xf00) | (arg & 0xff); 98 } 99 100 static void finish_read_pci_config(sPAPRMachineState *spapr, uint64_t buid, 101 uint32_t addr, uint32_t size, 102 target_ulong rets) 103 { 104 PCIDevice *pci_dev; 105 uint32_t val; 106 107 if ((size != 1) && (size != 2) && (size != 4)) { 108 /* access must be 1, 2 or 4 bytes */ 109 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 110 return; 111 } 112 113 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 114 addr = rtas_pci_cfgaddr(addr); 115 116 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 117 /* Access must be to a valid device, within bounds and 118 * naturally aligned */ 119 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 120 return; 121 } 122 123 val = pci_host_config_read_common(pci_dev, addr, 124 pci_config_size(pci_dev), size); 125 126 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 127 rtas_st(rets, 1, val); 128 } 129 130 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 131 uint32_t token, uint32_t nargs, 132 target_ulong args, 133 uint32_t nret, target_ulong rets) 134 { 135 uint64_t buid; 136 uint32_t size, addr; 137 138 if ((nargs != 4) || (nret != 2)) { 139 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 140 return; 141 } 142 143 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 144 size = rtas_ld(args, 3); 145 addr = rtas_ld(args, 0); 146 147 finish_read_pci_config(spapr, buid, addr, size, rets); 148 } 149 150 static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 151 uint32_t token, uint32_t nargs, 152 target_ulong args, 153 uint32_t nret, target_ulong rets) 154 { 155 uint32_t size, addr; 156 157 if ((nargs != 2) || (nret != 2)) { 158 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 159 return; 160 } 161 162 size = rtas_ld(args, 1); 163 addr = rtas_ld(args, 0); 164 165 finish_read_pci_config(spapr, 0, addr, size, rets); 166 } 167 168 static void finish_write_pci_config(sPAPRMachineState *spapr, uint64_t buid, 169 uint32_t addr, uint32_t size, 170 uint32_t val, target_ulong rets) 171 { 172 PCIDevice *pci_dev; 173 174 if ((size != 1) && (size != 2) && (size != 4)) { 175 /* access must be 1, 2 or 4 bytes */ 176 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 177 return; 178 } 179 180 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 181 addr = rtas_pci_cfgaddr(addr); 182 183 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 184 /* Access must be to a valid device, within bounds and 185 * naturally aligned */ 186 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 187 return; 188 } 189 190 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), 191 val, size); 192 193 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 194 } 195 196 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 197 uint32_t token, uint32_t nargs, 198 target_ulong args, 199 uint32_t nret, target_ulong rets) 200 { 201 uint64_t buid; 202 uint32_t val, size, addr; 203 204 if ((nargs != 5) || (nret != 1)) { 205 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 206 return; 207 } 208 209 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 210 val = rtas_ld(args, 4); 211 size = rtas_ld(args, 3); 212 addr = rtas_ld(args, 0); 213 214 finish_write_pci_config(spapr, buid, addr, size, val, rets); 215 } 216 217 static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr, 218 uint32_t token, uint32_t nargs, 219 target_ulong args, 220 uint32_t nret, target_ulong rets) 221 { 222 uint32_t val, size, addr; 223 224 if ((nargs != 3) || (nret != 1)) { 225 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 226 return; 227 } 228 229 230 val = rtas_ld(args, 2); 231 size = rtas_ld(args, 1); 232 addr = rtas_ld(args, 0); 233 234 finish_write_pci_config(spapr, 0, addr, size, val, rets); 235 } 236 237 /* 238 * Set MSI/MSIX message data. 239 * This is required for msi_notify()/msix_notify() which 240 * will write at the addresses via spapr_msi_write(). 241 * 242 * If hwaddr == 0, all entries will have .data == first_irq i.e. 243 * table will be reset. 244 */ 245 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, 246 unsigned first_irq, unsigned req_num) 247 { 248 unsigned i; 249 MSIMessage msg = { .address = addr, .data = first_irq }; 250 251 if (!msix) { 252 msi_set_message(pdev, msg); 253 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); 254 return; 255 } 256 257 for (i = 0; i < req_num; ++i) { 258 msix_set_message(pdev, i, msg); 259 trace_spapr_pci_msi_setup(pdev->name, i, msg.address); 260 if (addr) { 261 ++msg.data; 262 } 263 } 264 } 265 266 static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 267 uint32_t token, uint32_t nargs, 268 target_ulong args, uint32_t nret, 269 target_ulong rets) 270 { 271 uint32_t config_addr = rtas_ld(args, 0); 272 uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 273 unsigned int func = rtas_ld(args, 3); 274 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ 275 unsigned int seq_num = rtas_ld(args, 5); 276 unsigned int ret_intr_type; 277 unsigned int irq, max_irqs = 0, num = 0; 278 sPAPRPHBState *phb = NULL; 279 PCIDevice *pdev = NULL; 280 spapr_pci_msi *msi; 281 int *config_addr_key; 282 283 switch (func) { 284 case RTAS_CHANGE_MSI_FN: 285 case RTAS_CHANGE_FN: 286 ret_intr_type = RTAS_TYPE_MSI; 287 break; 288 case RTAS_CHANGE_MSIX_FN: 289 ret_intr_type = RTAS_TYPE_MSIX; 290 break; 291 default: 292 error_report("rtas_ibm_change_msi(%u) is not implemented", func); 293 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 294 return; 295 } 296 297 /* Fins sPAPRPHBState */ 298 phb = spapr_pci_find_phb(spapr, buid); 299 if (phb) { 300 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 301 } 302 if (!phb || !pdev) { 303 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 304 return; 305 } 306 307 /* Releasing MSIs */ 308 if (!req_num) { 309 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); 310 if (!msi) { 311 trace_spapr_pci_msi("Releasing wrong config", config_addr); 312 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 313 return; 314 } 315 316 xics_free(spapr->icp, msi->first_irq, msi->num); 317 if (msi_present(pdev)) { 318 spapr_msi_setmsg(pdev, 0, false, 0, num); 319 } 320 if (msix_present(pdev)) { 321 spapr_msi_setmsg(pdev, 0, true, 0, num); 322 } 323 g_hash_table_remove(phb->msi, &config_addr); 324 325 trace_spapr_pci_msi("Released MSIs", config_addr); 326 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 327 rtas_st(rets, 1, 0); 328 return; 329 } 330 331 /* Enabling MSI */ 332 333 /* Check if the device supports as many IRQs as requested */ 334 if (ret_intr_type == RTAS_TYPE_MSI) { 335 max_irqs = msi_nr_vectors_allocated(pdev); 336 } else if (ret_intr_type == RTAS_TYPE_MSIX) { 337 max_irqs = pdev->msix_entries_nr; 338 } 339 if (!max_irqs) { 340 error_report("Requested interrupt type %d is not enabled for device %x", 341 ret_intr_type, config_addr); 342 rtas_st(rets, 0, -1); /* Hardware error */ 343 return; 344 } 345 /* Correct the number if the guest asked for too many */ 346 if (req_num > max_irqs) { 347 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); 348 req_num = max_irqs; 349 irq = 0; /* to avoid misleading trace */ 350 goto out; 351 } 352 353 /* Allocate MSIs */ 354 irq = xics_alloc_block(spapr->icp, 0, req_num, false, 355 ret_intr_type == RTAS_TYPE_MSI); 356 if (!irq) { 357 error_report("Cannot allocate MSIs for device %x", config_addr); 358 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 359 return; 360 } 361 362 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ 363 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, 364 irq, req_num); 365 366 /* Add MSI device to cache */ 367 msi = g_new(spapr_pci_msi, 1); 368 msi->first_irq = irq; 369 msi->num = req_num; 370 config_addr_key = g_new(int, 1); 371 *config_addr_key = config_addr; 372 g_hash_table_insert(phb->msi, config_addr_key, msi); 373 374 out: 375 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 376 rtas_st(rets, 1, req_num); 377 rtas_st(rets, 2, ++seq_num); 378 rtas_st(rets, 3, ret_intr_type); 379 380 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); 381 } 382 383 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, 384 sPAPRMachineState *spapr, 385 uint32_t token, 386 uint32_t nargs, 387 target_ulong args, 388 uint32_t nret, 389 target_ulong rets) 390 { 391 uint32_t config_addr = rtas_ld(args, 0); 392 uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 393 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); 394 sPAPRPHBState *phb = NULL; 395 PCIDevice *pdev = NULL; 396 spapr_pci_msi *msi; 397 398 /* Find sPAPRPHBState */ 399 phb = spapr_pci_find_phb(spapr, buid); 400 if (phb) { 401 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 402 } 403 if (!phb || !pdev) { 404 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 405 return; 406 } 407 408 /* Find device descriptor and start IRQ */ 409 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); 410 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { 411 trace_spapr_pci_msi("Failed to return vector", config_addr); 412 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 413 return; 414 } 415 intr_src_num = msi->first_irq + ioa_intr_num; 416 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, 417 intr_src_num); 418 419 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 420 rtas_st(rets, 1, intr_src_num); 421 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ 422 } 423 424 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, 425 sPAPRMachineState *spapr, 426 uint32_t token, uint32_t nargs, 427 target_ulong args, uint32_t nret, 428 target_ulong rets) 429 { 430 sPAPRPHBState *sphb; 431 sPAPRPHBClass *spc; 432 PCIDevice *pdev; 433 uint32_t addr, option; 434 uint64_t buid; 435 int ret; 436 437 if ((nargs != 4) || (nret != 1)) { 438 goto param_error_exit; 439 } 440 441 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 442 addr = rtas_ld(args, 0); 443 option = rtas_ld(args, 3); 444 445 sphb = spapr_pci_find_phb(spapr, buid); 446 if (!sphb) { 447 goto param_error_exit; 448 } 449 450 pdev = pci_find_device(PCI_HOST_BRIDGE(sphb)->bus, 451 (addr >> 16) & 0xFF, (addr >> 8) & 0xFF); 452 if (!pdev || !object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 453 goto param_error_exit; 454 } 455 456 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 457 if (!spc->eeh_set_option) { 458 goto param_error_exit; 459 } 460 461 ret = spc->eeh_set_option(sphb, addr, option); 462 rtas_st(rets, 0, ret); 463 return; 464 465 param_error_exit: 466 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 467 } 468 469 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, 470 sPAPRMachineState *spapr, 471 uint32_t token, uint32_t nargs, 472 target_ulong args, uint32_t nret, 473 target_ulong rets) 474 { 475 sPAPRPHBState *sphb; 476 sPAPRPHBClass *spc; 477 PCIDevice *pdev; 478 uint32_t addr, option; 479 uint64_t buid; 480 481 if ((nargs != 4) || (nret != 2)) { 482 goto param_error_exit; 483 } 484 485 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 486 sphb = spapr_pci_find_phb(spapr, buid); 487 if (!sphb) { 488 goto param_error_exit; 489 } 490 491 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 492 if (!spc->eeh_set_option) { 493 goto param_error_exit; 494 } 495 496 /* 497 * We always have PE address of form "00BB0001". "BB" 498 * represents the bus number of PE's primary bus. 499 */ 500 option = rtas_ld(args, 3); 501 switch (option) { 502 case RTAS_GET_PE_ADDR: 503 addr = rtas_ld(args, 0); 504 pdev = spapr_pci_find_dev(spapr, buid, addr); 505 if (!pdev) { 506 goto param_error_exit; 507 } 508 509 rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1); 510 break; 511 case RTAS_GET_PE_MODE: 512 rtas_st(rets, 1, RTAS_PE_MODE_SHARED); 513 break; 514 default: 515 goto param_error_exit; 516 } 517 518 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 519 return; 520 521 param_error_exit: 522 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 523 } 524 525 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, 526 sPAPRMachineState *spapr, 527 uint32_t token, uint32_t nargs, 528 target_ulong args, uint32_t nret, 529 target_ulong rets) 530 { 531 sPAPRPHBState *sphb; 532 sPAPRPHBClass *spc; 533 uint64_t buid; 534 int state, ret; 535 536 if ((nargs != 3) || (nret != 4 && nret != 5)) { 537 goto param_error_exit; 538 } 539 540 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 541 sphb = spapr_pci_find_phb(spapr, buid); 542 if (!sphb) { 543 goto param_error_exit; 544 } 545 546 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 547 if (!spc->eeh_get_state) { 548 goto param_error_exit; 549 } 550 551 ret = spc->eeh_get_state(sphb, &state); 552 rtas_st(rets, 0, ret); 553 if (ret != RTAS_OUT_SUCCESS) { 554 return; 555 } 556 557 rtas_st(rets, 1, state); 558 rtas_st(rets, 2, RTAS_EEH_SUPPORT); 559 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); 560 if (nret >= 5) { 561 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); 562 } 563 return; 564 565 param_error_exit: 566 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 567 } 568 569 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, 570 sPAPRMachineState *spapr, 571 uint32_t token, uint32_t nargs, 572 target_ulong args, uint32_t nret, 573 target_ulong rets) 574 { 575 sPAPRPHBState *sphb; 576 sPAPRPHBClass *spc; 577 uint32_t option; 578 uint64_t buid; 579 int ret; 580 581 if ((nargs != 4) || (nret != 1)) { 582 goto param_error_exit; 583 } 584 585 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 586 option = rtas_ld(args, 3); 587 sphb = spapr_pci_find_phb(spapr, buid); 588 if (!sphb) { 589 goto param_error_exit; 590 } 591 592 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 593 if (!spc->eeh_reset) { 594 goto param_error_exit; 595 } 596 597 ret = spc->eeh_reset(sphb, option); 598 rtas_st(rets, 0, ret); 599 return; 600 601 param_error_exit: 602 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 603 } 604 605 static void rtas_ibm_configure_pe(PowerPCCPU *cpu, 606 sPAPRMachineState *spapr, 607 uint32_t token, uint32_t nargs, 608 target_ulong args, uint32_t nret, 609 target_ulong rets) 610 { 611 sPAPRPHBState *sphb; 612 sPAPRPHBClass *spc; 613 uint64_t buid; 614 int ret; 615 616 if ((nargs != 3) || (nret != 1)) { 617 goto param_error_exit; 618 } 619 620 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 621 sphb = spapr_pci_find_phb(spapr, buid); 622 if (!sphb) { 623 goto param_error_exit; 624 } 625 626 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 627 if (!spc->eeh_configure) { 628 goto param_error_exit; 629 } 630 631 ret = spc->eeh_configure(sphb); 632 rtas_st(rets, 0, ret); 633 return; 634 635 param_error_exit: 636 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 637 } 638 639 /* To support it later */ 640 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, 641 sPAPRMachineState *spapr, 642 uint32_t token, uint32_t nargs, 643 target_ulong args, uint32_t nret, 644 target_ulong rets) 645 { 646 sPAPRPHBState *sphb; 647 sPAPRPHBClass *spc; 648 int option; 649 uint64_t buid; 650 651 if ((nargs != 8) || (nret != 1)) { 652 goto param_error_exit; 653 } 654 655 buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); 656 sphb = spapr_pci_find_phb(spapr, buid); 657 if (!sphb) { 658 goto param_error_exit; 659 } 660 661 spc = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(sphb); 662 if (!spc->eeh_set_option) { 663 goto param_error_exit; 664 } 665 666 option = rtas_ld(args, 7); 667 switch (option) { 668 case RTAS_SLOT_TEMP_ERR_LOG: 669 case RTAS_SLOT_PERM_ERR_LOG: 670 break; 671 default: 672 goto param_error_exit; 673 } 674 675 /* We don't have error log yet */ 676 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); 677 return; 678 679 param_error_exit: 680 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 681 } 682 683 static int pci_spapr_swizzle(int slot, int pin) 684 { 685 return (slot + pin) % PCI_NUM_PINS; 686 } 687 688 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) 689 { 690 /* 691 * Here we need to convert pci_dev + irq_num to some unique value 692 * which is less than number of IRQs on the specific bus (4). We 693 * use standard PCI swizzling, that is (slot number + pin number) 694 * % 4. 695 */ 696 return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num); 697 } 698 699 static void pci_spapr_set_irq(void *opaque, int irq_num, int level) 700 { 701 /* 702 * Here we use the number returned by pci_spapr_map_irq to find a 703 * corresponding qemu_irq. 704 */ 705 sPAPRPHBState *phb = opaque; 706 707 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); 708 qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); 709 } 710 711 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) 712 { 713 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); 714 PCIINTxRoute route; 715 716 route.mode = PCI_INTX_ENABLED; 717 route.irq = sphb->lsi_table[pin].irq; 718 719 return route; 720 } 721 722 /* 723 * MSI/MSIX memory region implementation. 724 * The handler handles both MSI and MSIX. 725 * For MSI-X, the vector number is encoded as a part of the address, 726 * data is set to 0. 727 * For MSI, the vector number is encoded in least bits in data. 728 */ 729 static void spapr_msi_write(void *opaque, hwaddr addr, 730 uint64_t data, unsigned size) 731 { 732 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 733 uint32_t irq = data; 734 735 trace_spapr_pci_msi_write(addr, data, irq); 736 737 qemu_irq_pulse(xics_get_qirq(spapr->icp, irq)); 738 } 739 740 static const MemoryRegionOps spapr_msi_ops = { 741 /* There is no .read as the read result is undefined by PCI spec */ 742 .read = NULL, 743 .write = spapr_msi_write, 744 .endianness = DEVICE_LITTLE_ENDIAN 745 }; 746 747 /* 748 * PHB PCI device 749 */ 750 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 751 { 752 sPAPRPHBState *phb = opaque; 753 754 return &phb->iommu_as; 755 } 756 757 static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) 758 { 759 char *path = NULL, *buf = NULL, *host = NULL; 760 761 /* Get the PCI VFIO host id */ 762 host = object_property_get_str(OBJECT(pdev), "host", NULL); 763 if (!host) { 764 goto err_out; 765 } 766 767 /* Construct the path of the file that will give us the DT location */ 768 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); 769 g_free(host); 770 if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { 771 goto err_out; 772 } 773 g_free(path); 774 775 /* Construct and read from host device tree the loc-code */ 776 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); 777 g_free(buf); 778 if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) { 779 goto err_out; 780 } 781 return buf; 782 783 err_out: 784 g_free(path); 785 return NULL; 786 } 787 788 static char *spapr_phb_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev) 789 { 790 char *buf; 791 const char *devtype = "qemu"; 792 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 793 794 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 795 buf = spapr_phb_vfio_get_loc_code(sphb, pdev); 796 if (buf) { 797 return buf; 798 } 799 devtype = "vfio"; 800 } 801 /* 802 * For emulated devices and VFIO-failure case, make up 803 * the loc-code. 804 */ 805 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", 806 devtype, pdev->name, sphb->index, busnr, 807 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 808 return buf; 809 } 810 811 /* Macros to operate with address in OF binding to PCI */ 812 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) 813 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ 814 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ 815 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ 816 #define b_ss(x) b_x((x), 24, 2) /* the space code */ 817 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ 818 #define b_ddddd(x) b_x((x), 11, 5) /* device number */ 819 #define b_fff(x) b_x((x), 8, 3) /* function number */ 820 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ 821 822 /* for 'reg'/'assigned-addresses' OF properties */ 823 #define RESOURCE_CELLS_SIZE 2 824 #define RESOURCE_CELLS_ADDRESS 3 825 826 typedef struct ResourceFields { 827 uint32_t phys_hi; 828 uint32_t phys_mid; 829 uint32_t phys_lo; 830 uint32_t size_hi; 831 uint32_t size_lo; 832 } QEMU_PACKED ResourceFields; 833 834 typedef struct ResourceProps { 835 ResourceFields reg[8]; 836 ResourceFields assigned[7]; 837 uint32_t reg_len; 838 uint32_t assigned_len; 839 } ResourceProps; 840 841 /* fill in the 'reg'/'assigned-resources' OF properties for 842 * a PCI device. 'reg' describes resource requirements for a 843 * device's IO/MEM regions, 'assigned-addresses' describes the 844 * actual resource assignments. 845 * 846 * the properties are arrays of ('phys-addr', 'size') pairs describing 847 * the addressable regions of the PCI device, where 'phys-addr' is a 848 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to 849 * (phys.hi, phys.mid, phys.lo), and 'size' is a 850 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). 851 * 852 * phys.hi = 0xYYXXXXZZ, where: 853 * 0xYY = npt000ss 854 * ||| | 855 * ||| +-- space code 856 * ||| | 857 * ||| + 00 if configuration space 858 * ||| + 01 if IO region, 859 * ||| + 10 if 32-bit MEM region 860 * ||| + 11 if 64-bit MEM region 861 * ||| 862 * ||+------ for non-relocatable IO: 1 if aliased 863 * || for relocatable IO: 1 if below 64KB 864 * || for MEM: 1 if below 1MB 865 * |+------- 1 if region is prefetchable 866 * +-------- 1 if region is non-relocatable 867 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function 868 * bits respectively 869 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding 870 * to the region 871 * 872 * phys.mid and phys.lo correspond respectively to the hi/lo portions 873 * of the actual address of the region. 874 * 875 * how the phys-addr/size values are used differ slightly between 876 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has 877 * an additional description for the config space region of the 878 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0 879 * to describe the region as relocatable, with an address-mapping 880 * that corresponds directly to the PHB's address space for the 881 * resource. 'assigned-addresses' always has n=1 set with an absolute 882 * address assigned for the resource. in general, 'assigned-addresses' 883 * won't be populated, since addresses for PCI devices are generally 884 * unmapped initially and left to the guest to assign. 885 * 886 * note also that addresses defined in these properties are, at least 887 * for PAPR guests, relative to the PHBs IO/MEM windows, and 888 * correspond directly to the addresses in the BARs. 889 * 890 * in accordance with PCI Bus Binding to Open Firmware, 891 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, 892 * Appendix C. 893 */ 894 static void populate_resource_props(PCIDevice *d, ResourceProps *rp) 895 { 896 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); 897 uint32_t dev_id = (b_bbbbbbbb(bus_num) | 898 b_ddddd(PCI_SLOT(d->devfn)) | 899 b_fff(PCI_FUNC(d->devfn))); 900 ResourceFields *reg, *assigned; 901 int i, reg_idx = 0, assigned_idx = 0; 902 903 /* config space region */ 904 reg = &rp->reg[reg_idx++]; 905 reg->phys_hi = cpu_to_be32(dev_id); 906 reg->phys_mid = 0; 907 reg->phys_lo = 0; 908 reg->size_hi = 0; 909 reg->size_lo = 0; 910 911 for (i = 0; i < PCI_NUM_REGIONS; i++) { 912 if (!d->io_regions[i].size) { 913 continue; 914 } 915 916 reg = &rp->reg[reg_idx++]; 917 918 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); 919 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 920 reg->phys_hi |= cpu_to_be32(b_ss(1)); 921 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 922 reg->phys_hi |= cpu_to_be32(b_ss(3)); 923 } else { 924 reg->phys_hi |= cpu_to_be32(b_ss(2)); 925 } 926 reg->phys_mid = 0; 927 reg->phys_lo = 0; 928 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); 929 reg->size_lo = cpu_to_be32(d->io_regions[i].size); 930 931 if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) { 932 continue; 933 } 934 935 assigned = &rp->assigned[assigned_idx++]; 936 assigned->phys_hi = cpu_to_be32(reg->phys_hi | b_n(1)); 937 assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32); 938 assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr); 939 assigned->size_hi = reg->size_hi; 940 assigned->size_lo = reg->size_lo; 941 } 942 943 rp->reg_len = reg_idx * sizeof(ResourceFields); 944 rp->assigned_len = assigned_idx * sizeof(ResourceFields); 945 } 946 947 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, 948 PCIDevice *pdev); 949 950 static int spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset, 951 sPAPRPHBState *sphb) 952 { 953 ResourceProps rp; 954 bool is_bridge = false; 955 int pci_status, err; 956 char *buf = NULL; 957 uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev); 958 959 if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) == 960 PCI_HEADER_TYPE_BRIDGE) { 961 is_bridge = true; 962 } 963 964 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ 965 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", 966 pci_default_read_config(dev, PCI_VENDOR_ID, 2))); 967 _FDT(fdt_setprop_cell(fdt, offset, "device-id", 968 pci_default_read_config(dev, PCI_DEVICE_ID, 2))); 969 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", 970 pci_default_read_config(dev, PCI_REVISION_ID, 1))); 971 _FDT(fdt_setprop_cell(fdt, offset, "class-code", 972 pci_default_read_config(dev, PCI_CLASS_PROG, 3))); 973 if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) { 974 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", 975 pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1))); 976 } 977 978 if (!is_bridge) { 979 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", 980 pci_default_read_config(dev, PCI_MIN_GNT, 1))); 981 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", 982 pci_default_read_config(dev, PCI_MAX_LAT, 1))); 983 } 984 985 if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) { 986 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", 987 pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2))); 988 } 989 990 if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) { 991 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", 992 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2))); 993 } 994 995 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", 996 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1))); 997 998 /* the following fdt cells are masked off the pci status register */ 999 pci_status = pci_default_read_config(dev, PCI_STATUS, 2); 1000 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", 1001 PCI_STATUS_DEVSEL_MASK & pci_status)); 1002 1003 if (pci_status & PCI_STATUS_FAST_BACK) { 1004 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); 1005 } 1006 if (pci_status & PCI_STATUS_66MHZ) { 1007 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); 1008 } 1009 if (pci_status & PCI_STATUS_UDF) { 1010 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); 1011 } 1012 1013 /* NOTE: this is normally generated by firmware via path/unit name, 1014 * but in our case we must set it manually since it does not get 1015 * processed by OF beforehand 1016 */ 1017 _FDT(fdt_setprop_string(fdt, offset, "name", "pci")); 1018 buf = spapr_phb_get_loc_code(sphb, dev); 1019 if (!buf) { 1020 error_report("Failed setting the ibm,loc-code"); 1021 return -1; 1022 } 1023 1024 err = fdt_setprop_string(fdt, offset, "ibm,loc-code", buf); 1025 g_free(buf); 1026 if (err < 0) { 1027 return err; 1028 } 1029 1030 if (drc_index) { 1031 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)); 1032 } 1033 1034 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 1035 RESOURCE_CELLS_ADDRESS)); 1036 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1037 RESOURCE_CELLS_SIZE)); 1038 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", 1039 RESOURCE_CELLS_SIZE)); 1040 1041 populate_resource_props(dev, &rp); 1042 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); 1043 _FDT(fdt_setprop(fdt, offset, "assigned-addresses", 1044 (uint8_t *)rp.assigned, rp.assigned_len)); 1045 1046 return 0; 1047 } 1048 1049 /* create OF node for pci device and required OF DT properties */ 1050 static int spapr_create_pci_child_dt(sPAPRPHBState *phb, PCIDevice *dev, 1051 void *fdt, int node_offset) 1052 { 1053 int offset, ret; 1054 int slot = PCI_SLOT(dev->devfn); 1055 int func = PCI_FUNC(dev->devfn); 1056 char nodename[FDT_NAME_MAX]; 1057 1058 if (func != 0) { 1059 snprintf(nodename, FDT_NAME_MAX, "pci@%x,%x", slot, func); 1060 } else { 1061 snprintf(nodename, FDT_NAME_MAX, "pci@%x", slot); 1062 } 1063 offset = fdt_add_subnode(fdt, node_offset, nodename); 1064 ret = spapr_populate_pci_child_dt(dev, fdt, offset, phb); 1065 1066 g_assert(!ret); 1067 if (ret) { 1068 return 0; 1069 } 1070 return offset; 1071 } 1072 1073 static void spapr_phb_add_pci_device(sPAPRDRConnector *drc, 1074 sPAPRPHBState *phb, 1075 PCIDevice *pdev, 1076 Error **errp) 1077 { 1078 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1079 DeviceState *dev = DEVICE(pdev); 1080 void *fdt = NULL; 1081 int fdt_start_offset = 0, fdt_size; 1082 1083 if (dev->hotplugged) { 1084 fdt = create_device_tree(&fdt_size); 1085 fdt_start_offset = spapr_create_pci_child_dt(phb, pdev, fdt, 0); 1086 if (!fdt_start_offset) { 1087 error_setg(errp, "Failed to create pci child device tree node"); 1088 goto out; 1089 } 1090 } 1091 1092 drck->attach(drc, DEVICE(pdev), 1093 fdt, fdt_start_offset, !dev->hotplugged, errp); 1094 out: 1095 if (*errp) { 1096 g_free(fdt); 1097 } 1098 } 1099 1100 static void spapr_phb_remove_pci_device_cb(DeviceState *dev, void *opaque) 1101 { 1102 /* some version guests do not wait for completion of a device 1103 * cleanup (generally done asynchronously by the kernel) before 1104 * signaling to QEMU that the device is safe, but instead sleep 1105 * for some 'safe' period of time. unfortunately on a busy host 1106 * this sleep isn't guaranteed to be long enough, resulting in 1107 * bad things like IRQ lines being left asserted during final 1108 * device removal. to deal with this we call reset just prior 1109 * to finalizing the device, which will put the device back into 1110 * an 'idle' state, as the device cleanup code expects. 1111 */ 1112 pci_device_reset(PCI_DEVICE(dev)); 1113 object_unparent(OBJECT(dev)); 1114 } 1115 1116 static void spapr_phb_remove_pci_device(sPAPRDRConnector *drc, 1117 sPAPRPHBState *phb, 1118 PCIDevice *pdev, 1119 Error **errp) 1120 { 1121 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1122 1123 drck->detach(drc, DEVICE(pdev), spapr_phb_remove_pci_device_cb, phb, errp); 1124 } 1125 1126 static sPAPRDRConnector *spapr_phb_get_pci_drc(sPAPRPHBState *phb, 1127 PCIDevice *pdev) 1128 { 1129 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 1130 return spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_PCI, 1131 (phb->index << 16) | 1132 (busnr << 8) | 1133 pdev->devfn); 1134 } 1135 1136 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb, 1137 PCIDevice *pdev) 1138 { 1139 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1140 sPAPRDRConnectorClass *drck; 1141 1142 if (!drc) { 1143 return 0; 1144 } 1145 1146 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1147 return drck->get_index(drc); 1148 } 1149 1150 static void spapr_phb_hot_plug_child(HotplugHandler *plug_handler, 1151 DeviceState *plugged_dev, Error **errp) 1152 { 1153 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1154 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1155 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1156 Error *local_err = NULL; 1157 1158 /* if DR is disabled we don't need to do anything in the case of 1159 * hotplug or coldplug callbacks 1160 */ 1161 if (!phb->dr_enabled) { 1162 /* if this is a hotplug operation initiated by the user 1163 * we need to let them know it's not enabled 1164 */ 1165 if (plugged_dev->hotplugged) { 1166 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1167 object_get_typename(OBJECT(phb))); 1168 } 1169 return; 1170 } 1171 1172 g_assert(drc); 1173 1174 spapr_phb_add_pci_device(drc, phb, pdev, &local_err); 1175 if (local_err) { 1176 error_propagate(errp, local_err); 1177 return; 1178 } 1179 if (plugged_dev->hotplugged) { 1180 spapr_hotplug_req_add_event(drc); 1181 } 1182 } 1183 1184 static void spapr_phb_hot_unplug_child(HotplugHandler *plug_handler, 1185 DeviceState *plugged_dev, Error **errp) 1186 { 1187 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1188 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1189 sPAPRDRConnectorClass *drck; 1190 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev); 1191 Error *local_err = NULL; 1192 1193 if (!phb->dr_enabled) { 1194 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1195 object_get_typename(OBJECT(phb))); 1196 return; 1197 } 1198 1199 g_assert(drc); 1200 1201 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 1202 if (!drck->release_pending(drc)) { 1203 spapr_phb_remove_pci_device(drc, phb, pdev, &local_err); 1204 if (local_err) { 1205 error_propagate(errp, local_err); 1206 return; 1207 } 1208 spapr_hotplug_req_remove_event(drc); 1209 } 1210 } 1211 1212 static void spapr_phb_realize(DeviceState *dev, Error **errp) 1213 { 1214 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1215 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1216 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s); 1217 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1218 sPAPRPHBClass *info = SPAPR_PCI_HOST_BRIDGE_GET_CLASS(s); 1219 char *namebuf; 1220 int i; 1221 PCIBus *bus; 1222 uint64_t msi_window_size = 4096; 1223 1224 if (sphb->index != (uint32_t)-1) { 1225 hwaddr windows_base; 1226 1227 if ((sphb->buid != (uint64_t)-1) || (sphb->dma_liobn != (uint32_t)-1) 1228 || (sphb->mem_win_addr != (hwaddr)-1) 1229 || (sphb->io_win_addr != (hwaddr)-1)) { 1230 error_setg(errp, "Either \"index\" or other parameters must" 1231 " be specified for PAPR PHB, not both"); 1232 return; 1233 } 1234 1235 if (sphb->index > SPAPR_PCI_MAX_INDEX) { 1236 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 1237 SPAPR_PCI_MAX_INDEX); 1238 return; 1239 } 1240 1241 sphb->buid = SPAPR_PCI_BASE_BUID + sphb->index; 1242 sphb->dma_liobn = SPAPR_PCI_LIOBN(sphb->index, 0); 1243 1244 windows_base = SPAPR_PCI_WINDOW_BASE 1245 + sphb->index * SPAPR_PCI_WINDOW_SPACING; 1246 sphb->mem_win_addr = windows_base + SPAPR_PCI_MMIO_WIN_OFF; 1247 sphb->io_win_addr = windows_base + SPAPR_PCI_IO_WIN_OFF; 1248 } 1249 1250 if (sphb->buid == (uint64_t)-1) { 1251 error_setg(errp, "BUID not specified for PHB"); 1252 return; 1253 } 1254 1255 if (sphb->dma_liobn == (uint32_t)-1) { 1256 error_setg(errp, "LIOBN not specified for PHB"); 1257 return; 1258 } 1259 1260 if (sphb->mem_win_addr == (hwaddr)-1) { 1261 error_setg(errp, "Memory window address not specified for PHB"); 1262 return; 1263 } 1264 1265 if (sphb->io_win_addr == (hwaddr)-1) { 1266 error_setg(errp, "IO window address not specified for PHB"); 1267 return; 1268 } 1269 1270 if (spapr_pci_find_phb(spapr, sphb->buid)) { 1271 error_setg(errp, "PCI host bridges must have unique BUIDs"); 1272 return; 1273 } 1274 1275 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); 1276 1277 namebuf = alloca(strlen(sphb->dtbusname) + 32); 1278 1279 /* Initialize memory regions */ 1280 sprintf(namebuf, "%s.mmio", sphb->dtbusname); 1281 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); 1282 1283 sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname); 1284 memory_region_init_alias(&sphb->memwindow, OBJECT(sphb), 1285 namebuf, &sphb->memspace, 1286 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); 1287 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, 1288 &sphb->memwindow); 1289 1290 /* Initialize IO regions */ 1291 sprintf(namebuf, "%s.io", sphb->dtbusname); 1292 memory_region_init(&sphb->iospace, OBJECT(sphb), 1293 namebuf, SPAPR_PCI_IO_WIN_SIZE); 1294 1295 sprintf(namebuf, "%s.io-alias", sphb->dtbusname); 1296 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, 1297 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); 1298 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, 1299 &sphb->iowindow); 1300 1301 bus = pci_register_bus(dev, NULL, 1302 pci_spapr_set_irq, pci_spapr_map_irq, sphb, 1303 &sphb->memspace, &sphb->iospace, 1304 PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); 1305 phb->bus = bus; 1306 qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL); 1307 1308 /* 1309 * Initialize PHB address space. 1310 * By default there will be at least one subregion for default 1311 * 32bit DMA window. 1312 * Later the guest might want to create another DMA window 1313 * which will become another memory subregion. 1314 */ 1315 sprintf(namebuf, "%s.iommu-root", sphb->dtbusname); 1316 1317 memory_region_init(&sphb->iommu_root, OBJECT(sphb), 1318 namebuf, UINT64_MAX); 1319 address_space_init(&sphb->iommu_as, &sphb->iommu_root, 1320 sphb->dtbusname); 1321 1322 /* 1323 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, 1324 * we need to allocate some memory to catch those writes coming 1325 * from msi_notify()/msix_notify(). 1326 * As MSIMessage:addr is going to be the same and MSIMessage:data 1327 * is going to be a VIRQ number, 4 bytes of the MSI MR will only 1328 * be used. 1329 * 1330 * For KVM we want to ensure that this memory is a full page so that 1331 * our memory slot is of page size granularity. 1332 */ 1333 #ifdef CONFIG_KVM 1334 if (kvm_enabled()) { 1335 msi_window_size = getpagesize(); 1336 } 1337 #endif 1338 1339 memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr, 1340 "msi", msi_window_size); 1341 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, 1342 &sphb->msiwindow); 1343 1344 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); 1345 1346 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); 1347 1348 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); 1349 1350 /* Initialize the LSI table */ 1351 for (i = 0; i < PCI_NUM_PINS; i++) { 1352 uint32_t irq; 1353 1354 irq = xics_alloc_block(spapr->icp, 0, 1, true, false); 1355 if (!irq) { 1356 error_setg(errp, "spapr_allocate_lsi failed"); 1357 return; 1358 } 1359 1360 sphb->lsi_table[i].irq = irq; 1361 } 1362 1363 /* allocate connectors for child PCI devices */ 1364 if (sphb->dr_enabled) { 1365 for (i = 0; i < PCI_SLOT_MAX * 8; i++) { 1366 spapr_dr_connector_new(OBJECT(phb), 1367 SPAPR_DR_CONNECTOR_TYPE_PCI, 1368 (sphb->index << 16) | i); 1369 } 1370 } 1371 1372 if (!info->finish_realize) { 1373 error_setg(errp, "finish_realize not defined"); 1374 return; 1375 } 1376 1377 info->finish_realize(sphb, errp); 1378 1379 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); 1380 } 1381 1382 static void spapr_phb_finish_realize(sPAPRPHBState *sphb, Error **errp) 1383 { 1384 sPAPRTCETable *tcet; 1385 uint32_t nb_table; 1386 1387 nb_table = SPAPR_PCI_DMA32_SIZE >> SPAPR_TCE_PAGE_SHIFT; 1388 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn, 1389 0, SPAPR_TCE_PAGE_SHIFT, nb_table, false); 1390 if (!tcet) { 1391 error_setg(errp, "Unable to create TCE table for %s", 1392 sphb->dtbusname); 1393 return ; 1394 } 1395 1396 /* Register default 32bit DMA window */ 1397 memory_region_add_subregion(&sphb->iommu_root, 0, 1398 spapr_tce_get_iommu(tcet)); 1399 } 1400 1401 static int spapr_phb_children_reset(Object *child, void *opaque) 1402 { 1403 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); 1404 1405 if (dev) { 1406 device_reset(dev); 1407 } 1408 1409 return 0; 1410 } 1411 1412 static void spapr_phb_reset(DeviceState *qdev) 1413 { 1414 /* Reset the IOMMU state */ 1415 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); 1416 } 1417 1418 static Property spapr_phb_properties[] = { 1419 DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1), 1420 DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1), 1421 DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn, -1), 1422 DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1), 1423 DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size, 1424 SPAPR_PCI_MMIO_WIN_SIZE), 1425 DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1), 1426 DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size, 1427 SPAPR_PCI_IO_WIN_SIZE), 1428 DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled, 1429 true), 1430 DEFINE_PROP_END_OF_LIST(), 1431 }; 1432 1433 static const VMStateDescription vmstate_spapr_pci_lsi = { 1434 .name = "spapr_pci/lsi", 1435 .version_id = 1, 1436 .minimum_version_id = 1, 1437 .fields = (VMStateField[]) { 1438 VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi), 1439 1440 VMSTATE_END_OF_LIST() 1441 }, 1442 }; 1443 1444 static const VMStateDescription vmstate_spapr_pci_msi = { 1445 .name = "spapr_pci/msi", 1446 .version_id = 1, 1447 .minimum_version_id = 1, 1448 .fields = (VMStateField []) { 1449 VMSTATE_UINT32(key, spapr_pci_msi_mig), 1450 VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig), 1451 VMSTATE_UINT32(value.num, spapr_pci_msi_mig), 1452 VMSTATE_END_OF_LIST() 1453 }, 1454 }; 1455 1456 static void spapr_pci_pre_save(void *opaque) 1457 { 1458 sPAPRPHBState *sphb = opaque; 1459 GHashTableIter iter; 1460 gpointer key, value; 1461 int i; 1462 1463 if (sphb->msi_devs) { 1464 g_free(sphb->msi_devs); 1465 sphb->msi_devs = NULL; 1466 } 1467 sphb->msi_devs_num = g_hash_table_size(sphb->msi); 1468 if (!sphb->msi_devs_num) { 1469 return; 1470 } 1471 sphb->msi_devs = g_malloc(sphb->msi_devs_num * sizeof(spapr_pci_msi_mig)); 1472 1473 g_hash_table_iter_init(&iter, sphb->msi); 1474 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { 1475 sphb->msi_devs[i].key = *(uint32_t *) key; 1476 sphb->msi_devs[i].value = *(spapr_pci_msi *) value; 1477 } 1478 } 1479 1480 static int spapr_pci_post_load(void *opaque, int version_id) 1481 { 1482 sPAPRPHBState *sphb = opaque; 1483 gpointer key, value; 1484 int i; 1485 1486 for (i = 0; i < sphb->msi_devs_num; ++i) { 1487 key = g_memdup(&sphb->msi_devs[i].key, 1488 sizeof(sphb->msi_devs[i].key)); 1489 value = g_memdup(&sphb->msi_devs[i].value, 1490 sizeof(sphb->msi_devs[i].value)); 1491 g_hash_table_insert(sphb->msi, key, value); 1492 } 1493 if (sphb->msi_devs) { 1494 g_free(sphb->msi_devs); 1495 sphb->msi_devs = NULL; 1496 } 1497 sphb->msi_devs_num = 0; 1498 1499 return 0; 1500 } 1501 1502 static const VMStateDescription vmstate_spapr_pci = { 1503 .name = "spapr_pci", 1504 .version_id = 2, 1505 .minimum_version_id = 2, 1506 .pre_save = spapr_pci_pre_save, 1507 .post_load = spapr_pci_post_load, 1508 .fields = (VMStateField[]) { 1509 VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState), 1510 VMSTATE_UINT32_EQUAL(dma_liobn, sPAPRPHBState), 1511 VMSTATE_UINT64_EQUAL(mem_win_addr, sPAPRPHBState), 1512 VMSTATE_UINT64_EQUAL(mem_win_size, sPAPRPHBState), 1513 VMSTATE_UINT64_EQUAL(io_win_addr, sPAPRPHBState), 1514 VMSTATE_UINT64_EQUAL(io_win_size, sPAPRPHBState), 1515 VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0, 1516 vmstate_spapr_pci_lsi, struct spapr_pci_lsi), 1517 VMSTATE_INT32(msi_devs_num, sPAPRPHBState), 1518 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0, 1519 vmstate_spapr_pci_msi, spapr_pci_msi_mig), 1520 VMSTATE_END_OF_LIST() 1521 }, 1522 }; 1523 1524 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, 1525 PCIBus *rootbus) 1526 { 1527 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); 1528 1529 return sphb->dtbusname; 1530 } 1531 1532 static void spapr_phb_class_init(ObjectClass *klass, void *data) 1533 { 1534 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 1535 DeviceClass *dc = DEVICE_CLASS(klass); 1536 sPAPRPHBClass *spc = SPAPR_PCI_HOST_BRIDGE_CLASS(klass); 1537 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); 1538 1539 hc->root_bus_path = spapr_phb_root_bus_path; 1540 dc->realize = spapr_phb_realize; 1541 dc->props = spapr_phb_properties; 1542 dc->reset = spapr_phb_reset; 1543 dc->vmsd = &vmstate_spapr_pci; 1544 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 1545 dc->cannot_instantiate_with_device_add_yet = false; 1546 spc->finish_realize = spapr_phb_finish_realize; 1547 hp->plug = spapr_phb_hot_plug_child; 1548 hp->unplug = spapr_phb_hot_unplug_child; 1549 } 1550 1551 static const TypeInfo spapr_phb_info = { 1552 .name = TYPE_SPAPR_PCI_HOST_BRIDGE, 1553 .parent = TYPE_PCI_HOST_BRIDGE, 1554 .instance_size = sizeof(sPAPRPHBState), 1555 .class_init = spapr_phb_class_init, 1556 .class_size = sizeof(sPAPRPHBClass), 1557 .interfaces = (InterfaceInfo[]) { 1558 { TYPE_HOTPLUG_HANDLER }, 1559 { } 1560 } 1561 }; 1562 1563 PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index) 1564 { 1565 DeviceState *dev; 1566 1567 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 1568 qdev_prop_set_uint32(dev, "index", index); 1569 qdev_init_nofail(dev); 1570 1571 return PCI_HOST_BRIDGE(dev); 1572 } 1573 1574 typedef struct sPAPRFDT { 1575 void *fdt; 1576 int node_off; 1577 sPAPRPHBState *sphb; 1578 } sPAPRFDT; 1579 1580 static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev, 1581 void *opaque) 1582 { 1583 PCIBus *sec_bus; 1584 sPAPRFDT *p = opaque; 1585 int offset; 1586 sPAPRFDT s_fdt; 1587 1588 offset = spapr_create_pci_child_dt(p->sphb, pdev, p->fdt, p->node_off); 1589 if (!offset) { 1590 error_report("Failed to create pci child device tree node"); 1591 return; 1592 } 1593 1594 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 1595 PCI_HEADER_TYPE_BRIDGE)) { 1596 return; 1597 } 1598 1599 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 1600 if (!sec_bus) { 1601 return; 1602 } 1603 1604 s_fdt.fdt = p->fdt; 1605 s_fdt.node_off = offset; 1606 s_fdt.sphb = p->sphb; 1607 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 1608 spapr_populate_pci_devices_dt, 1609 &s_fdt); 1610 } 1611 1612 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, 1613 void *opaque) 1614 { 1615 unsigned int *bus_no = opaque; 1616 unsigned int primary = *bus_no; 1617 unsigned int subordinate = 0xff; 1618 PCIBus *sec_bus = NULL; 1619 1620 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 1621 PCI_HEADER_TYPE_BRIDGE)) { 1622 return; 1623 } 1624 1625 (*bus_no)++; 1626 pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1); 1627 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); 1628 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 1629 1630 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 1631 if (!sec_bus) { 1632 return; 1633 } 1634 1635 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1); 1636 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 1637 spapr_phb_pci_enumerate_bridge, bus_no); 1638 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 1639 } 1640 1641 static void spapr_phb_pci_enumerate(sPAPRPHBState *phb) 1642 { 1643 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 1644 unsigned int bus_no = 0; 1645 1646 pci_for_each_device(bus, pci_bus_num(bus), 1647 spapr_phb_pci_enumerate_bridge, 1648 &bus_no); 1649 1650 } 1651 1652 int spapr_populate_pci_dt(sPAPRPHBState *phb, 1653 uint32_t xics_phandle, 1654 void *fdt) 1655 { 1656 int bus_off, i, j, ret; 1657 char nodename[FDT_NAME_MAX]; 1658 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; 1659 const uint64_t mmiosize = memory_region_size(&phb->memwindow); 1660 const uint64_t w32max = (1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET; 1661 const uint64_t w32size = MIN(w32max, mmiosize); 1662 const uint64_t w64size = (mmiosize > w32size) ? (mmiosize - w32size) : 0; 1663 struct { 1664 uint32_t hi; 1665 uint64_t child; 1666 uint64_t parent; 1667 uint64_t size; 1668 } QEMU_PACKED ranges[] = { 1669 { 1670 cpu_to_be32(b_ss(1)), cpu_to_be64(0), 1671 cpu_to_be64(phb->io_win_addr), 1672 cpu_to_be64(memory_region_size(&phb->iospace)), 1673 }, 1674 { 1675 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), 1676 cpu_to_be64(phb->mem_win_addr), 1677 cpu_to_be64(w32size), 1678 }, 1679 { 1680 cpu_to_be32(b_ss(3)), cpu_to_be64(1ULL << 32), 1681 cpu_to_be64(phb->mem_win_addr + w32size), 1682 cpu_to_be64(w64size) 1683 }, 1684 }; 1685 const unsigned sizeof_ranges = (w64size ? 3 : 2) * sizeof(ranges[0]); 1686 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; 1687 uint32_t interrupt_map_mask[] = { 1688 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; 1689 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; 1690 sPAPRTCETable *tcet; 1691 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 1692 sPAPRFDT s_fdt; 1693 1694 /* Start populating the FDT */ 1695 snprintf(nodename, FDT_NAME_MAX, "pci@%" PRIx64, phb->buid); 1696 bus_off = fdt_add_subnode(fdt, 0, nodename); 1697 if (bus_off < 0) { 1698 return bus_off; 1699 } 1700 1701 /* Write PHB properties */ 1702 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); 1703 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); 1704 _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); 1705 _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); 1706 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); 1707 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); 1708 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); 1709 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); 1710 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); 1711 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); 1712 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS)); 1713 1714 /* Build the interrupt-map, this must matches what is done 1715 * in pci_spapr_map_irq 1716 */ 1717 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", 1718 &interrupt_map_mask, sizeof(interrupt_map_mask))); 1719 for (i = 0; i < PCI_SLOT_MAX; i++) { 1720 for (j = 0; j < PCI_NUM_PINS; j++) { 1721 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; 1722 int lsi_num = pci_spapr_swizzle(i, j); 1723 1724 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); 1725 irqmap[1] = 0; 1726 irqmap[2] = 0; 1727 irqmap[3] = cpu_to_be32(j+1); 1728 irqmap[4] = cpu_to_be32(xics_phandle); 1729 irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq); 1730 irqmap[6] = cpu_to_be32(0x8); 1731 } 1732 } 1733 /* Write interrupt map */ 1734 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, 1735 sizeof(interrupt_map))); 1736 1737 tcet = spapr_tce_find_by_liobn(SPAPR_PCI_LIOBN(phb->index, 0)); 1738 spapr_dma_dt(fdt, bus_off, "ibm,dma-window", 1739 tcet->liobn, tcet->bus_offset, 1740 tcet->nb_table << tcet->page_shift); 1741 1742 /* Walk the bridges and program the bus numbers*/ 1743 spapr_phb_pci_enumerate(phb); 1744 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); 1745 1746 /* Populate tree nodes with PCI devices attached */ 1747 s_fdt.fdt = fdt; 1748 s_fdt.node_off = bus_off; 1749 s_fdt.sphb = phb; 1750 pci_for_each_device(bus, pci_bus_num(bus), 1751 spapr_populate_pci_devices_dt, 1752 &s_fdt); 1753 1754 ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb), 1755 SPAPR_DR_CONNECTOR_TYPE_PCI); 1756 if (ret) { 1757 return ret; 1758 } 1759 1760 return 0; 1761 } 1762 1763 void spapr_pci_rtas_init(void) 1764 { 1765 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", 1766 rtas_read_pci_config); 1767 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", 1768 rtas_write_pci_config); 1769 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", 1770 rtas_ibm_read_pci_config); 1771 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", 1772 rtas_ibm_write_pci_config); 1773 if (msi_supported) { 1774 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, 1775 "ibm,query-interrupt-source-number", 1776 rtas_ibm_query_interrupt_source_number); 1777 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", 1778 rtas_ibm_change_msi); 1779 } 1780 1781 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, 1782 "ibm,set-eeh-option", 1783 rtas_ibm_set_eeh_option); 1784 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, 1785 "ibm,get-config-addr-info2", 1786 rtas_ibm_get_config_addr_info2); 1787 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, 1788 "ibm,read-slot-reset-state2", 1789 rtas_ibm_read_slot_reset_state2); 1790 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, 1791 "ibm,set-slot-reset", 1792 rtas_ibm_set_slot_reset); 1793 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, 1794 "ibm,configure-pe", 1795 rtas_ibm_configure_pe); 1796 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, 1797 "ibm,slot-error-detail", 1798 rtas_ibm_slot_error_detail); 1799 } 1800 1801 static void spapr_pci_register_types(void) 1802 { 1803 type_register_static(&spapr_phb_info); 1804 } 1805 1806 type_init(spapr_pci_register_types) 1807 1808 static int spapr_switch_one_vga(DeviceState *dev, void *opaque) 1809 { 1810 bool be = *(bool *)opaque; 1811 1812 if (object_dynamic_cast(OBJECT(dev), "VGA") 1813 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { 1814 object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", 1815 &error_abort); 1816 } 1817 return 0; 1818 } 1819 1820 void spapr_pci_switch_vga(bool big_endian) 1821 { 1822 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1823 sPAPRPHBState *sphb; 1824 1825 /* 1826 * For backward compatibility with existing guests, we switch 1827 * the endianness of the VGA controller when changing the guest 1828 * interrupt mode 1829 */ 1830 QLIST_FOREACH(sphb, &spapr->phbs, list) { 1831 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; 1832 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, 1833 &big_endian); 1834 } 1835 } 1836