xref: /openbmc/qemu/hw/ppc/spapr_pci.c (revision 3f53bc61)
1 /*
2  * QEMU sPAPR PCI host originated from Uninorth PCI host
3  *
4  * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5  * Copyright (C) 2011 David Gibson, IBM Corporation.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  */
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "qemu-common.h"
28 #include "cpu.h"
29 #include "hw/hw.h"
30 #include "hw/sysbus.h"
31 #include "hw/pci/pci.h"
32 #include "hw/pci/msi.h"
33 #include "hw/pci/msix.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/ppc/spapr.h"
36 #include "hw/pci-host/spapr.h"
37 #include "exec/address-spaces.h"
38 #include "exec/ram_addr.h"
39 #include <libfdt.h>
40 #include "trace.h"
41 #include "qemu/error-report.h"
42 #include "qapi/qmp/qerror.h"
43 
44 #include "hw/pci/pci_bridge.h"
45 #include "hw/pci/pci_bus.h"
46 #include "hw/pci/pci_ids.h"
47 #include "hw/ppc/spapr_drc.h"
48 #include "sysemu/device_tree.h"
49 #include "sysemu/kvm.h"
50 #include "sysemu/hostmem.h"
51 #include "sysemu/numa.h"
52 
53 #include "hw/vfio/vfio.h"
54 
55 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
56 #define RTAS_QUERY_FN           0
57 #define RTAS_CHANGE_FN          1
58 #define RTAS_RESET_FN           2
59 #define RTAS_CHANGE_MSI_FN      3
60 #define RTAS_CHANGE_MSIX_FN     4
61 
62 /* Interrupt types to return on RTAS_CHANGE_* */
63 #define RTAS_TYPE_MSI           1
64 #define RTAS_TYPE_MSIX          2
65 
66 #define FDT_NAME_MAX          128
67 
68 #define _FDT(exp) \
69     do { \
70         int ret = (exp);                                           \
71         if (ret < 0) {                                             \
72             return ret;                                            \
73         }                                                          \
74     } while (0)
75 
76 sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid)
77 {
78     sPAPRPHBState *sphb;
79 
80     QLIST_FOREACH(sphb, &spapr->phbs, list) {
81         if (sphb->buid != buid) {
82             continue;
83         }
84         return sphb;
85     }
86 
87     return NULL;
88 }
89 
90 PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
91                               uint32_t config_addr)
92 {
93     sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
94     PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
95     int bus_num = (config_addr >> 16) & 0xFF;
96     int devfn = (config_addr >> 8) & 0xFF;
97 
98     if (!phb) {
99         return NULL;
100     }
101 
102     return pci_find_device(phb->bus, bus_num, devfn);
103 }
104 
105 static uint32_t rtas_pci_cfgaddr(uint32_t arg)
106 {
107     /* This handles the encoding of extended config space addresses */
108     return ((arg >> 20) & 0xf00) | (arg & 0xff);
109 }
110 
111 static void finish_read_pci_config(sPAPRMachineState *spapr, uint64_t buid,
112                                    uint32_t addr, uint32_t size,
113                                    target_ulong rets)
114 {
115     PCIDevice *pci_dev;
116     uint32_t val;
117 
118     if ((size != 1) && (size != 2) && (size != 4)) {
119         /* access must be 1, 2 or 4 bytes */
120         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
121         return;
122     }
123 
124     pci_dev = spapr_pci_find_dev(spapr, buid, addr);
125     addr = rtas_pci_cfgaddr(addr);
126 
127     if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
128         /* Access must be to a valid device, within bounds and
129          * naturally aligned */
130         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
131         return;
132     }
133 
134     val = pci_host_config_read_common(pci_dev, addr,
135                                       pci_config_size(pci_dev), size);
136 
137     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
138     rtas_st(rets, 1, val);
139 }
140 
141 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
142                                      uint32_t token, uint32_t nargs,
143                                      target_ulong args,
144                                      uint32_t nret, target_ulong rets)
145 {
146     uint64_t buid;
147     uint32_t size, addr;
148 
149     if ((nargs != 4) || (nret != 2)) {
150         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
151         return;
152     }
153 
154     buid = rtas_ldq(args, 1);
155     size = rtas_ld(args, 3);
156     addr = rtas_ld(args, 0);
157 
158     finish_read_pci_config(spapr, buid, addr, size, rets);
159 }
160 
161 static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
162                                  uint32_t token, uint32_t nargs,
163                                  target_ulong args,
164                                  uint32_t nret, target_ulong rets)
165 {
166     uint32_t size, addr;
167 
168     if ((nargs != 2) || (nret != 2)) {
169         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
170         return;
171     }
172 
173     size = rtas_ld(args, 1);
174     addr = rtas_ld(args, 0);
175 
176     finish_read_pci_config(spapr, 0, addr, size, rets);
177 }
178 
179 static void finish_write_pci_config(sPAPRMachineState *spapr, uint64_t buid,
180                                     uint32_t addr, uint32_t size,
181                                     uint32_t val, target_ulong rets)
182 {
183     PCIDevice *pci_dev;
184 
185     if ((size != 1) && (size != 2) && (size != 4)) {
186         /* access must be 1, 2 or 4 bytes */
187         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
188         return;
189     }
190 
191     pci_dev = spapr_pci_find_dev(spapr, buid, addr);
192     addr = rtas_pci_cfgaddr(addr);
193 
194     if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
195         /* Access must be to a valid device, within bounds and
196          * naturally aligned */
197         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
198         return;
199     }
200 
201     pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
202                                  val, size);
203 
204     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
205 }
206 
207 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
208                                       uint32_t token, uint32_t nargs,
209                                       target_ulong args,
210                                       uint32_t nret, target_ulong rets)
211 {
212     uint64_t buid;
213     uint32_t val, size, addr;
214 
215     if ((nargs != 5) || (nret != 1)) {
216         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
217         return;
218     }
219 
220     buid = rtas_ldq(args, 1);
221     val = rtas_ld(args, 4);
222     size = rtas_ld(args, 3);
223     addr = rtas_ld(args, 0);
224 
225     finish_write_pci_config(spapr, buid, addr, size, val, rets);
226 }
227 
228 static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
229                                   uint32_t token, uint32_t nargs,
230                                   target_ulong args,
231                                   uint32_t nret, target_ulong rets)
232 {
233     uint32_t val, size, addr;
234 
235     if ((nargs != 3) || (nret != 1)) {
236         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
237         return;
238     }
239 
240 
241     val = rtas_ld(args, 2);
242     size = rtas_ld(args, 1);
243     addr = rtas_ld(args, 0);
244 
245     finish_write_pci_config(spapr, 0, addr, size, val, rets);
246 }
247 
248 /*
249  * Set MSI/MSIX message data.
250  * This is required for msi_notify()/msix_notify() which
251  * will write at the addresses via spapr_msi_write().
252  *
253  * If hwaddr == 0, all entries will have .data == first_irq i.e.
254  * table will be reset.
255  */
256 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix,
257                              unsigned first_irq, unsigned req_num)
258 {
259     unsigned i;
260     MSIMessage msg = { .address = addr, .data = first_irq };
261 
262     if (!msix) {
263         msi_set_message(pdev, msg);
264         trace_spapr_pci_msi_setup(pdev->name, 0, msg.address);
265         return;
266     }
267 
268     for (i = 0; i < req_num; ++i) {
269         msix_set_message(pdev, i, msg);
270         trace_spapr_pci_msi_setup(pdev->name, i, msg.address);
271         if (addr) {
272             ++msg.data;
273         }
274     }
275 }
276 
277 static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
278                                 uint32_t token, uint32_t nargs,
279                                 target_ulong args, uint32_t nret,
280                                 target_ulong rets)
281 {
282     uint32_t config_addr = rtas_ld(args, 0);
283     uint64_t buid = rtas_ldq(args, 1);
284     unsigned int func = rtas_ld(args, 3);
285     unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */
286     unsigned int seq_num = rtas_ld(args, 5);
287     unsigned int ret_intr_type;
288     unsigned int irq, max_irqs = 0;
289     sPAPRPHBState *phb = NULL;
290     PCIDevice *pdev = NULL;
291     spapr_pci_msi *msi;
292     int *config_addr_key;
293     Error *err = NULL;
294 
295     switch (func) {
296     case RTAS_CHANGE_MSI_FN:
297     case RTAS_CHANGE_FN:
298         ret_intr_type = RTAS_TYPE_MSI;
299         break;
300     case RTAS_CHANGE_MSIX_FN:
301         ret_intr_type = RTAS_TYPE_MSIX;
302         break;
303     default:
304         error_report("rtas_ibm_change_msi(%u) is not implemented", func);
305         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
306         return;
307     }
308 
309     /* Fins sPAPRPHBState */
310     phb = spapr_pci_find_phb(spapr, buid);
311     if (phb) {
312         pdev = spapr_pci_find_dev(spapr, buid, config_addr);
313     }
314     if (!phb || !pdev) {
315         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
316         return;
317     }
318 
319     msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
320 
321     /* Releasing MSIs */
322     if (!req_num) {
323         if (!msi) {
324             trace_spapr_pci_msi("Releasing wrong config", config_addr);
325             rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
326             return;
327         }
328 
329         spapr_ics_free(spapr->ics, msi->first_irq, msi->num);
330         if (msi_present(pdev)) {
331             spapr_msi_setmsg(pdev, 0, false, 0, 0);
332         }
333         if (msix_present(pdev)) {
334             spapr_msi_setmsg(pdev, 0, true, 0, 0);
335         }
336         g_hash_table_remove(phb->msi, &config_addr);
337 
338         trace_spapr_pci_msi("Released MSIs", config_addr);
339         rtas_st(rets, 0, RTAS_OUT_SUCCESS);
340         rtas_st(rets, 1, 0);
341         return;
342     }
343 
344     /* Enabling MSI */
345 
346     /* Check if the device supports as many IRQs as requested */
347     if (ret_intr_type == RTAS_TYPE_MSI) {
348         max_irqs = msi_nr_vectors_allocated(pdev);
349     } else if (ret_intr_type == RTAS_TYPE_MSIX) {
350         max_irqs = pdev->msix_entries_nr;
351     }
352     if (!max_irqs) {
353         error_report("Requested interrupt type %d is not enabled for device %x",
354                      ret_intr_type, config_addr);
355         rtas_st(rets, 0, -1); /* Hardware error */
356         return;
357     }
358     /* Correct the number if the guest asked for too many */
359     if (req_num > max_irqs) {
360         trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs);
361         req_num = max_irqs;
362         irq = 0; /* to avoid misleading trace */
363         goto out;
364     }
365 
366     /* Allocate MSIs */
367     irq = spapr_ics_alloc_block(spapr->ics, req_num, false,
368                            ret_intr_type == RTAS_TYPE_MSI, &err);
369     if (err) {
370         error_reportf_err(err, "Can't allocate MSIs for device %x: ",
371                           config_addr);
372         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
373         return;
374     }
375 
376     /* Release previous MSIs */
377     if (msi) {
378         spapr_ics_free(spapr->ics, msi->first_irq, msi->num);
379         g_hash_table_remove(phb->msi, &config_addr);
380     }
381 
382     /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
383     spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX,
384                      irq, req_num);
385 
386     /* Add MSI device to cache */
387     msi = g_new(spapr_pci_msi, 1);
388     msi->first_irq = irq;
389     msi->num = req_num;
390     config_addr_key = g_new(int, 1);
391     *config_addr_key = config_addr;
392     g_hash_table_insert(phb->msi, config_addr_key, msi);
393 
394 out:
395     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
396     rtas_st(rets, 1, req_num);
397     rtas_st(rets, 2, ++seq_num);
398     if (nret > 3) {
399         rtas_st(rets, 3, ret_intr_type);
400     }
401 
402     trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq);
403 }
404 
405 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
406                                                    sPAPRMachineState *spapr,
407                                                    uint32_t token,
408                                                    uint32_t nargs,
409                                                    target_ulong args,
410                                                    uint32_t nret,
411                                                    target_ulong rets)
412 {
413     uint32_t config_addr = rtas_ld(args, 0);
414     uint64_t buid = rtas_ldq(args, 1);
415     unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3);
416     sPAPRPHBState *phb = NULL;
417     PCIDevice *pdev = NULL;
418     spapr_pci_msi *msi;
419 
420     /* Find sPAPRPHBState */
421     phb = spapr_pci_find_phb(spapr, buid);
422     if (phb) {
423         pdev = spapr_pci_find_dev(spapr, buid, config_addr);
424     }
425     if (!phb || !pdev) {
426         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
427         return;
428     }
429 
430     /* Find device descriptor and start IRQ */
431     msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
432     if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) {
433         trace_spapr_pci_msi("Failed to return vector", config_addr);
434         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
435         return;
436     }
437     intr_src_num = msi->first_irq + ioa_intr_num;
438     trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num,
439                                                            intr_src_num);
440 
441     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
442     rtas_st(rets, 1, intr_src_num);
443     rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */
444 }
445 
446 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
447                                     sPAPRMachineState *spapr,
448                                     uint32_t token, uint32_t nargs,
449                                     target_ulong args, uint32_t nret,
450                                     target_ulong rets)
451 {
452     sPAPRPHBState *sphb;
453     uint32_t addr, option;
454     uint64_t buid;
455     int ret;
456 
457     if ((nargs != 4) || (nret != 1)) {
458         goto param_error_exit;
459     }
460 
461     buid = rtas_ldq(args, 1);
462     addr = rtas_ld(args, 0);
463     option = rtas_ld(args, 3);
464 
465     sphb = spapr_pci_find_phb(spapr, buid);
466     if (!sphb) {
467         goto param_error_exit;
468     }
469 
470     if (!spapr_phb_eeh_available(sphb)) {
471         goto param_error_exit;
472     }
473 
474     ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option);
475     rtas_st(rets, 0, ret);
476     return;
477 
478 param_error_exit:
479     rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
480 }
481 
482 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
483                                            sPAPRMachineState *spapr,
484                                            uint32_t token, uint32_t nargs,
485                                            target_ulong args, uint32_t nret,
486                                            target_ulong rets)
487 {
488     sPAPRPHBState *sphb;
489     PCIDevice *pdev;
490     uint32_t addr, option;
491     uint64_t buid;
492 
493     if ((nargs != 4) || (nret != 2)) {
494         goto param_error_exit;
495     }
496 
497     buid = rtas_ldq(args, 1);
498     sphb = spapr_pci_find_phb(spapr, buid);
499     if (!sphb) {
500         goto param_error_exit;
501     }
502 
503     if (!spapr_phb_eeh_available(sphb)) {
504         goto param_error_exit;
505     }
506 
507     /*
508      * We always have PE address of form "00BB0001". "BB"
509      * represents the bus number of PE's primary bus.
510      */
511     option = rtas_ld(args, 3);
512     switch (option) {
513     case RTAS_GET_PE_ADDR:
514         addr = rtas_ld(args, 0);
515         pdev = spapr_pci_find_dev(spapr, buid, addr);
516         if (!pdev) {
517             goto param_error_exit;
518         }
519 
520         rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1);
521         break;
522     case RTAS_GET_PE_MODE:
523         rtas_st(rets, 1, RTAS_PE_MODE_SHARED);
524         break;
525     default:
526         goto param_error_exit;
527     }
528 
529     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
530     return;
531 
532 param_error_exit:
533     rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
534 }
535 
536 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
537                                             sPAPRMachineState *spapr,
538                                             uint32_t token, uint32_t nargs,
539                                             target_ulong args, uint32_t nret,
540                                             target_ulong rets)
541 {
542     sPAPRPHBState *sphb;
543     uint64_t buid;
544     int state, ret;
545 
546     if ((nargs != 3) || (nret != 4 && nret != 5)) {
547         goto param_error_exit;
548     }
549 
550     buid = rtas_ldq(args, 1);
551     sphb = spapr_pci_find_phb(spapr, buid);
552     if (!sphb) {
553         goto param_error_exit;
554     }
555 
556     if (!spapr_phb_eeh_available(sphb)) {
557         goto param_error_exit;
558     }
559 
560     ret = spapr_phb_vfio_eeh_get_state(sphb, &state);
561     rtas_st(rets, 0, ret);
562     if (ret != RTAS_OUT_SUCCESS) {
563         return;
564     }
565 
566     rtas_st(rets, 1, state);
567     rtas_st(rets, 2, RTAS_EEH_SUPPORT);
568     rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO);
569     if (nret >= 5) {
570         rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO);
571     }
572     return;
573 
574 param_error_exit:
575     rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
576 }
577 
578 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
579                                     sPAPRMachineState *spapr,
580                                     uint32_t token, uint32_t nargs,
581                                     target_ulong args, uint32_t nret,
582                                     target_ulong rets)
583 {
584     sPAPRPHBState *sphb;
585     uint32_t option;
586     uint64_t buid;
587     int ret;
588 
589     if ((nargs != 4) || (nret != 1)) {
590         goto param_error_exit;
591     }
592 
593     buid = rtas_ldq(args, 1);
594     option = rtas_ld(args, 3);
595     sphb = spapr_pci_find_phb(spapr, buid);
596     if (!sphb) {
597         goto param_error_exit;
598     }
599 
600     if (!spapr_phb_eeh_available(sphb)) {
601         goto param_error_exit;
602     }
603 
604     ret = spapr_phb_vfio_eeh_reset(sphb, option);
605     rtas_st(rets, 0, ret);
606     return;
607 
608 param_error_exit:
609     rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
610 }
611 
612 static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
613                                   sPAPRMachineState *spapr,
614                                   uint32_t token, uint32_t nargs,
615                                   target_ulong args, uint32_t nret,
616                                   target_ulong rets)
617 {
618     sPAPRPHBState *sphb;
619     uint64_t buid;
620     int ret;
621 
622     if ((nargs != 3) || (nret != 1)) {
623         goto param_error_exit;
624     }
625 
626     buid = rtas_ldq(args, 1);
627     sphb = spapr_pci_find_phb(spapr, buid);
628     if (!sphb) {
629         goto param_error_exit;
630     }
631 
632     if (!spapr_phb_eeh_available(sphb)) {
633         goto param_error_exit;
634     }
635 
636     ret = spapr_phb_vfio_eeh_configure(sphb);
637     rtas_st(rets, 0, ret);
638     return;
639 
640 param_error_exit:
641     rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
642 }
643 
644 /* To support it later */
645 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
646                                        sPAPRMachineState *spapr,
647                                        uint32_t token, uint32_t nargs,
648                                        target_ulong args, uint32_t nret,
649                                        target_ulong rets)
650 {
651     sPAPRPHBState *sphb;
652     int option;
653     uint64_t buid;
654 
655     if ((nargs != 8) || (nret != 1)) {
656         goto param_error_exit;
657     }
658 
659     buid = rtas_ldq(args, 1);
660     sphb = spapr_pci_find_phb(spapr, buid);
661     if (!sphb) {
662         goto param_error_exit;
663     }
664 
665     if (!spapr_phb_eeh_available(sphb)) {
666         goto param_error_exit;
667     }
668 
669     option = rtas_ld(args, 7);
670     switch (option) {
671     case RTAS_SLOT_TEMP_ERR_LOG:
672     case RTAS_SLOT_PERM_ERR_LOG:
673         break;
674     default:
675         goto param_error_exit;
676     }
677 
678     /* We don't have error log yet */
679     rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
680     return;
681 
682 param_error_exit:
683     rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
684 }
685 
686 static int pci_spapr_swizzle(int slot, int pin)
687 {
688     return (slot + pin) % PCI_NUM_PINS;
689 }
690 
691 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
692 {
693     /*
694      * Here we need to convert pci_dev + irq_num to some unique value
695      * which is less than number of IRQs on the specific bus (4).  We
696      * use standard PCI swizzling, that is (slot number + pin number)
697      * % 4.
698      */
699     return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num);
700 }
701 
702 static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
703 {
704     /*
705      * Here we use the number returned by pci_spapr_map_irq to find a
706      * corresponding qemu_irq.
707      */
708     sPAPRPHBState *phb = opaque;
709 
710     trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq);
711     qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
712 }
713 
714 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin)
715 {
716     sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque);
717     PCIINTxRoute route;
718 
719     route.mode = PCI_INTX_ENABLED;
720     route.irq = sphb->lsi_table[pin].irq;
721 
722     return route;
723 }
724 
725 /*
726  * MSI/MSIX memory region implementation.
727  * The handler handles both MSI and MSIX.
728  * For MSI-X, the vector number is encoded as a part of the address,
729  * data is set to 0.
730  * For MSI, the vector number is encoded in least bits in data.
731  */
732 static void spapr_msi_write(void *opaque, hwaddr addr,
733                             uint64_t data, unsigned size)
734 {
735     sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
736     uint32_t irq = data;
737 
738     trace_spapr_pci_msi_write(addr, data, irq);
739 
740     qemu_irq_pulse(xics_get_qirq(XICS_FABRIC(spapr), irq));
741 }
742 
743 static const MemoryRegionOps spapr_msi_ops = {
744     /* There is no .read as the read result is undefined by PCI spec */
745     .read = NULL,
746     .write = spapr_msi_write,
747     .endianness = DEVICE_LITTLE_ENDIAN
748 };
749 
750 /*
751  * PHB PCI device
752  */
753 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
754 {
755     sPAPRPHBState *phb = opaque;
756 
757     return &phb->iommu_as;
758 }
759 
760 static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState *sphb,  PCIDevice *pdev)
761 {
762     char *path = NULL, *buf = NULL, *host = NULL;
763 
764     /* Get the PCI VFIO host id */
765     host = object_property_get_str(OBJECT(pdev), "host", NULL);
766     if (!host) {
767         goto err_out;
768     }
769 
770     /* Construct the path of the file that will give us the DT location */
771     path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host);
772     g_free(host);
773     if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) {
774         goto err_out;
775     }
776     g_free(path);
777 
778     /* Construct and read from host device tree the loc-code */
779     path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf);
780     g_free(buf);
781     if (!path || !g_file_get_contents(path, &buf, NULL, NULL)) {
782         goto err_out;
783     }
784     return buf;
785 
786 err_out:
787     g_free(path);
788     return NULL;
789 }
790 
791 static char *spapr_phb_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev)
792 {
793     char *buf;
794     const char *devtype = "qemu";
795     uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
796 
797     if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
798         buf = spapr_phb_vfio_get_loc_code(sphb, pdev);
799         if (buf) {
800             return buf;
801         }
802         devtype = "vfio";
803     }
804     /*
805      * For emulated devices and VFIO-failure case, make up
806      * the loc-code.
807      */
808     buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
809                           devtype, pdev->name, sphb->index, busnr,
810                           PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
811     return buf;
812 }
813 
814 /* Macros to operate with address in OF binding to PCI */
815 #define b_x(x, p, l)    (((x) & ((1<<(l))-1)) << (p))
816 #define b_n(x)          b_x((x), 31, 1) /* 0 if relocatable */
817 #define b_p(x)          b_x((x), 30, 1) /* 1 if prefetchable */
818 #define b_t(x)          b_x((x), 29, 1) /* 1 if the address is aliased */
819 #define b_ss(x)         b_x((x), 24, 2) /* the space code */
820 #define b_bbbbbbbb(x)   b_x((x), 16, 8) /* bus number */
821 #define b_ddddd(x)      b_x((x), 11, 5) /* device number */
822 #define b_fff(x)        b_x((x), 8, 3)  /* function number */
823 #define b_rrrrrrrr(x)   b_x((x), 0, 8)  /* register number */
824 
825 /* for 'reg'/'assigned-addresses' OF properties */
826 #define RESOURCE_CELLS_SIZE 2
827 #define RESOURCE_CELLS_ADDRESS 3
828 
829 typedef struct ResourceFields {
830     uint32_t phys_hi;
831     uint32_t phys_mid;
832     uint32_t phys_lo;
833     uint32_t size_hi;
834     uint32_t size_lo;
835 } QEMU_PACKED ResourceFields;
836 
837 typedef struct ResourceProps {
838     ResourceFields reg[8];
839     ResourceFields assigned[7];
840     uint32_t reg_len;
841     uint32_t assigned_len;
842 } ResourceProps;
843 
844 /* fill in the 'reg'/'assigned-resources' OF properties for
845  * a PCI device. 'reg' describes resource requirements for a
846  * device's IO/MEM regions, 'assigned-addresses' describes the
847  * actual resource assignments.
848  *
849  * the properties are arrays of ('phys-addr', 'size') pairs describing
850  * the addressable regions of the PCI device, where 'phys-addr' is a
851  * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to
852  * (phys.hi, phys.mid, phys.lo), and 'size' is a
853  * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo).
854  *
855  * phys.hi = 0xYYXXXXZZ, where:
856  *   0xYY = npt000ss
857  *          |||   |
858  *          |||   +-- space code
859  *          |||               |
860  *          |||               +  00 if configuration space
861  *          |||               +  01 if IO region,
862  *          |||               +  10 if 32-bit MEM region
863  *          |||               +  11 if 64-bit MEM region
864  *          |||
865  *          ||+------ for non-relocatable IO: 1 if aliased
866  *          ||        for relocatable IO: 1 if below 64KB
867  *          ||        for MEM: 1 if below 1MB
868  *          |+------- 1 if region is prefetchable
869  *          +-------- 1 if region is non-relocatable
870  *   0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function
871  *            bits respectively
872  *   0xZZ = rrrrrrrr, the register number of the BAR corresponding
873  *          to the region
874  *
875  * phys.mid and phys.lo correspond respectively to the hi/lo portions
876  * of the actual address of the region.
877  *
878  * how the phys-addr/size values are used differ slightly between
879  * 'reg' and 'assigned-addresses' properties. namely, 'reg' has
880  * an additional description for the config space region of the
881  * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0
882  * to describe the region as relocatable, with an address-mapping
883  * that corresponds directly to the PHB's address space for the
884  * resource. 'assigned-addresses' always has n=1 set with an absolute
885  * address assigned for the resource. in general, 'assigned-addresses'
886  * won't be populated, since addresses for PCI devices are generally
887  * unmapped initially and left to the guest to assign.
888  *
889  * note also that addresses defined in these properties are, at least
890  * for PAPR guests, relative to the PHBs IO/MEM windows, and
891  * correspond directly to the addresses in the BARs.
892  *
893  * in accordance with PCI Bus Binding to Open Firmware,
894  * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7,
895  * Appendix C.
896  */
897 static void populate_resource_props(PCIDevice *d, ResourceProps *rp)
898 {
899     int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d))));
900     uint32_t dev_id = (b_bbbbbbbb(bus_num) |
901                        b_ddddd(PCI_SLOT(d->devfn)) |
902                        b_fff(PCI_FUNC(d->devfn)));
903     ResourceFields *reg, *assigned;
904     int i, reg_idx = 0, assigned_idx = 0;
905 
906     /* config space region */
907     reg = &rp->reg[reg_idx++];
908     reg->phys_hi = cpu_to_be32(dev_id);
909     reg->phys_mid = 0;
910     reg->phys_lo = 0;
911     reg->size_hi = 0;
912     reg->size_lo = 0;
913 
914     for (i = 0; i < PCI_NUM_REGIONS; i++) {
915         if (!d->io_regions[i].size) {
916             continue;
917         }
918 
919         reg = &rp->reg[reg_idx++];
920 
921         reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i)));
922         if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
923             reg->phys_hi |= cpu_to_be32(b_ss(1));
924         } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
925             reg->phys_hi |= cpu_to_be32(b_ss(3));
926         } else {
927             reg->phys_hi |= cpu_to_be32(b_ss(2));
928         }
929         reg->phys_mid = 0;
930         reg->phys_lo = 0;
931         reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32);
932         reg->size_lo = cpu_to_be32(d->io_regions[i].size);
933 
934         if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) {
935             continue;
936         }
937 
938         assigned = &rp->assigned[assigned_idx++];
939         assigned->phys_hi = cpu_to_be32(reg->phys_hi | b_n(1));
940         assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32);
941         assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr);
942         assigned->size_hi = reg->size_hi;
943         assigned->size_lo = reg->size_lo;
944     }
945 
946     rp->reg_len = reg_idx * sizeof(ResourceFields);
947     rp->assigned_len = assigned_idx * sizeof(ResourceFields);
948 }
949 
950 typedef struct PCIClass PCIClass;
951 typedef struct PCISubClass PCISubClass;
952 typedef struct PCIIFace PCIIFace;
953 
954 struct PCIIFace {
955     int iface;
956     const char *name;
957 };
958 
959 struct PCISubClass {
960     int subclass;
961     const char *name;
962     const PCIIFace *iface;
963 };
964 
965 struct PCIClass {
966     const char *name;
967     const PCISubClass *subc;
968 };
969 
970 static const PCISubClass undef_subclass[] = {
971     { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL },
972     { 0xFF, NULL, NULL },
973 };
974 
975 static const PCISubClass mass_subclass[] = {
976     { PCI_CLASS_STORAGE_SCSI, "scsi", NULL },
977     { PCI_CLASS_STORAGE_IDE, "ide", NULL },
978     { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL },
979     { PCI_CLASS_STORAGE_IPI, "ipi", NULL },
980     { PCI_CLASS_STORAGE_RAID, "raid", NULL },
981     { PCI_CLASS_STORAGE_ATA, "ata", NULL },
982     { PCI_CLASS_STORAGE_SATA, "sata", NULL },
983     { PCI_CLASS_STORAGE_SAS, "sas", NULL },
984     { 0xFF, NULL, NULL },
985 };
986 
987 static const PCISubClass net_subclass[] = {
988     { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL },
989     { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL },
990     { PCI_CLASS_NETWORK_FDDI, "fddi", NULL },
991     { PCI_CLASS_NETWORK_ATM, "atm", NULL },
992     { PCI_CLASS_NETWORK_ISDN, "isdn", NULL },
993     { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL },
994     { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL },
995     { 0xFF, NULL, NULL },
996 };
997 
998 static const PCISubClass displ_subclass[] = {
999     { PCI_CLASS_DISPLAY_VGA, "vga", NULL },
1000     { PCI_CLASS_DISPLAY_XGA, "xga", NULL },
1001     { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL },
1002     { 0xFF, NULL, NULL },
1003 };
1004 
1005 static const PCISubClass media_subclass[] = {
1006     { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL },
1007     { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL },
1008     { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL },
1009     { 0xFF, NULL, NULL },
1010 };
1011 
1012 static const PCISubClass mem_subclass[] = {
1013     { PCI_CLASS_MEMORY_RAM, "memory", NULL },
1014     { PCI_CLASS_MEMORY_FLASH, "flash", NULL },
1015     { 0xFF, NULL, NULL },
1016 };
1017 
1018 static const PCISubClass bridg_subclass[] = {
1019     { PCI_CLASS_BRIDGE_HOST, "host", NULL },
1020     { PCI_CLASS_BRIDGE_ISA, "isa", NULL },
1021     { PCI_CLASS_BRIDGE_EISA, "eisa", NULL },
1022     { PCI_CLASS_BRIDGE_MC, "mca", NULL },
1023     { PCI_CLASS_BRIDGE_PCI, "pci", NULL },
1024     { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL },
1025     { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL },
1026     { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL },
1027     { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL },
1028     { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL },
1029     { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL },
1030     { 0xFF, NULL, NULL },
1031 };
1032 
1033 static const PCISubClass comm_subclass[] = {
1034     { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL },
1035     { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL },
1036     { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL },
1037     { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL },
1038     { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL },
1039     { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL },
1040     { 0xFF, NULL, NULL, },
1041 };
1042 
1043 static const PCIIFace pic_iface[] = {
1044     { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" },
1045     { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" },
1046     { 0xFF, NULL },
1047 };
1048 
1049 static const PCISubClass sys_subclass[] = {
1050     { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface },
1051     { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL },
1052     { PCI_CLASS_SYSTEM_TIMER, "timer", NULL },
1053     { PCI_CLASS_SYSTEM_RTC, "rtc", NULL },
1054     { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL },
1055     { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL },
1056     { 0xFF, NULL, NULL },
1057 };
1058 
1059 static const PCISubClass inp_subclass[] = {
1060     { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL },
1061     { PCI_CLASS_INPUT_PEN, "pen", NULL },
1062     { PCI_CLASS_INPUT_MOUSE, "mouse", NULL },
1063     { PCI_CLASS_INPUT_SCANNER, "scanner", NULL },
1064     { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL },
1065     { 0xFF, NULL, NULL },
1066 };
1067 
1068 static const PCISubClass dock_subclass[] = {
1069     { PCI_CLASS_DOCKING_GENERIC, "dock", NULL },
1070     { 0xFF, NULL, NULL },
1071 };
1072 
1073 static const PCISubClass cpu_subclass[] = {
1074     { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL },
1075     { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL },
1076     { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL },
1077     { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL },
1078     { 0xFF, NULL, NULL },
1079 };
1080 
1081 static const PCIIFace usb_iface[] = {
1082     { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" },
1083     { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", },
1084     { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" },
1085     { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" },
1086     { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" },
1087     { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" },
1088     { 0xFF, NULL },
1089 };
1090 
1091 static const PCISubClass ser_subclass[] = {
1092     { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL },
1093     { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL },
1094     { PCI_CLASS_SERIAL_SSA, "ssa", NULL },
1095     { PCI_CLASS_SERIAL_USB, "usb", usb_iface },
1096     { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL },
1097     { PCI_CLASS_SERIAL_SMBUS, "smb", NULL },
1098     { PCI_CLASS_SERIAL_IB, "infiniband", NULL },
1099     { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL },
1100     { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL },
1101     { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL },
1102     { 0xFF, NULL, NULL },
1103 };
1104 
1105 static const PCISubClass wrl_subclass[] = {
1106     { PCI_CLASS_WIRELESS_IRDA, "irda", NULL },
1107     { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL },
1108     { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL },
1109     { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL },
1110     { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL },
1111     { 0xFF, NULL, NULL },
1112 };
1113 
1114 static const PCISubClass sat_subclass[] = {
1115     { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL },
1116     { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL },
1117     { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL },
1118     { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL },
1119     { 0xFF, NULL, NULL },
1120 };
1121 
1122 static const PCISubClass crypt_subclass[] = {
1123     { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL },
1124     { PCI_CLASS_CRYPT_ENTERTAINMENT,
1125       "entertainment-encryption", NULL },
1126     { 0xFF, NULL, NULL },
1127 };
1128 
1129 static const PCISubClass spc_subclass[] = {
1130     { PCI_CLASS_SP_DPIO, "dpio", NULL },
1131     { PCI_CLASS_SP_PERF, "counter", NULL },
1132     { PCI_CLASS_SP_SYNCH, "measurement", NULL },
1133     { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL },
1134     { 0xFF, NULL, NULL },
1135 };
1136 
1137 static const PCIClass pci_classes[] = {
1138     { "legacy-device", undef_subclass },
1139     { "mass-storage",  mass_subclass },
1140     { "network", net_subclass },
1141     { "display", displ_subclass, },
1142     { "multimedia-device", media_subclass },
1143     { "memory-controller", mem_subclass },
1144     { "unknown-bridge", bridg_subclass },
1145     { "communication-controller", comm_subclass},
1146     { "system-peripheral", sys_subclass },
1147     { "input-controller", inp_subclass },
1148     { "docking-station", dock_subclass },
1149     { "cpu", cpu_subclass },
1150     { "serial-bus", ser_subclass },
1151     { "wireless-controller", wrl_subclass },
1152     { "intelligent-io", NULL },
1153     { "satellite-device", sat_subclass },
1154     { "encryption", crypt_subclass },
1155     { "data-processing-controller", spc_subclass },
1156 };
1157 
1158 static const char *pci_find_device_name(uint8_t class, uint8_t subclass,
1159                                         uint8_t iface)
1160 {
1161     const PCIClass *pclass;
1162     const PCISubClass *psubclass;
1163     const PCIIFace *piface;
1164     const char *name;
1165 
1166     if (class >= ARRAY_SIZE(pci_classes)) {
1167         return "pci";
1168     }
1169 
1170     pclass = pci_classes + class;
1171     name = pclass->name;
1172 
1173     if (pclass->subc == NULL) {
1174         return name;
1175     }
1176 
1177     psubclass = pclass->subc;
1178     while ((psubclass->subclass & 0xff) != 0xff) {
1179         if ((psubclass->subclass & 0xff) == subclass) {
1180             name = psubclass->name;
1181             break;
1182         }
1183         psubclass++;
1184     }
1185 
1186     piface = psubclass->iface;
1187     if (piface == NULL) {
1188         return name;
1189     }
1190     while ((piface->iface & 0xff) != 0xff) {
1191         if ((piface->iface & 0xff) == iface) {
1192             name = piface->name;
1193             break;
1194         }
1195         piface++;
1196     }
1197 
1198     return name;
1199 }
1200 
1201 static void pci_get_node_name(char *nodename, int len, PCIDevice *dev)
1202 {
1203     int slot = PCI_SLOT(dev->devfn);
1204     int func = PCI_FUNC(dev->devfn);
1205     uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1206     const char *name;
1207 
1208     name = pci_find_device_name((ccode >> 16) & 0xff, (ccode >> 8) & 0xff,
1209                                 ccode & 0xff);
1210 
1211     if (func != 0) {
1212         snprintf(nodename, len, "%s@%x,%x", name, slot, func);
1213     } else {
1214         snprintf(nodename, len, "%s@%x", name, slot);
1215     }
1216 }
1217 
1218 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb,
1219                                             PCIDevice *pdev);
1220 
1221 static int spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset,
1222                                        sPAPRPHBState *sphb)
1223 {
1224     ResourceProps rp;
1225     bool is_bridge = false;
1226     int pci_status, err;
1227     char *buf = NULL;
1228     uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev);
1229     uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1230     uint32_t max_msi, max_msix;
1231 
1232     if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) ==
1233         PCI_HEADER_TYPE_BRIDGE) {
1234         is_bridge = true;
1235     }
1236 
1237     /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */
1238     _FDT(fdt_setprop_cell(fdt, offset, "vendor-id",
1239                           pci_default_read_config(dev, PCI_VENDOR_ID, 2)));
1240     _FDT(fdt_setprop_cell(fdt, offset, "device-id",
1241                           pci_default_read_config(dev, PCI_DEVICE_ID, 2)));
1242     _FDT(fdt_setprop_cell(fdt, offset, "revision-id",
1243                           pci_default_read_config(dev, PCI_REVISION_ID, 1)));
1244     _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode));
1245     if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) {
1246         _FDT(fdt_setprop_cell(fdt, offset, "interrupts",
1247                  pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)));
1248     }
1249 
1250     if (!is_bridge) {
1251         _FDT(fdt_setprop_cell(fdt, offset, "min-grant",
1252             pci_default_read_config(dev, PCI_MIN_GNT, 1)));
1253         _FDT(fdt_setprop_cell(fdt, offset, "max-latency",
1254             pci_default_read_config(dev, PCI_MAX_LAT, 1)));
1255     }
1256 
1257     if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) {
1258         _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id",
1259                  pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)));
1260     }
1261 
1262     if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) {
1263         _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id",
1264                  pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)));
1265     }
1266 
1267     _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size",
1268         pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1)));
1269 
1270     /* the following fdt cells are masked off the pci status register */
1271     pci_status = pci_default_read_config(dev, PCI_STATUS, 2);
1272     _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed",
1273                           PCI_STATUS_DEVSEL_MASK & pci_status));
1274 
1275     if (pci_status & PCI_STATUS_FAST_BACK) {
1276         _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0));
1277     }
1278     if (pci_status & PCI_STATUS_66MHZ) {
1279         _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0));
1280     }
1281     if (pci_status & PCI_STATUS_UDF) {
1282         _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0));
1283     }
1284 
1285     _FDT(fdt_setprop_string(fdt, offset, "name",
1286                             pci_find_device_name((ccode >> 16) & 0xff,
1287                                                  (ccode >> 8) & 0xff,
1288                                                  ccode & 0xff)));
1289     buf = spapr_phb_get_loc_code(sphb, dev);
1290     if (!buf) {
1291         error_report("Failed setting the ibm,loc-code");
1292         return -1;
1293     }
1294 
1295     err = fdt_setprop_string(fdt, offset, "ibm,loc-code", buf);
1296     g_free(buf);
1297     if (err < 0) {
1298         return err;
1299     }
1300 
1301     if (drc_index) {
1302         _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index));
1303     }
1304 
1305     _FDT(fdt_setprop_cell(fdt, offset, "#address-cells",
1306                           RESOURCE_CELLS_ADDRESS));
1307     _FDT(fdt_setprop_cell(fdt, offset, "#size-cells",
1308                           RESOURCE_CELLS_SIZE));
1309 
1310     max_msi = msi_nr_vectors_allocated(dev);
1311     if (max_msi) {
1312         _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi));
1313     }
1314     max_msix = dev->msix_entries_nr;
1315     if (max_msix) {
1316         _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix));
1317     }
1318 
1319     populate_resource_props(dev, &rp);
1320     _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len));
1321     _FDT(fdt_setprop(fdt, offset, "assigned-addresses",
1322                      (uint8_t *)rp.assigned, rp.assigned_len));
1323 
1324     if (sphb->pcie_ecs && pci_is_express(dev)) {
1325         _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1));
1326     }
1327 
1328     return 0;
1329 }
1330 
1331 /* create OF node for pci device and required OF DT properties */
1332 static int spapr_create_pci_child_dt(sPAPRPHBState *phb, PCIDevice *dev,
1333                                      void *fdt, int node_offset)
1334 {
1335     int offset, ret;
1336     char nodename[FDT_NAME_MAX];
1337 
1338     pci_get_node_name(nodename, FDT_NAME_MAX, dev);
1339     offset = fdt_add_subnode(fdt, node_offset, nodename);
1340     ret = spapr_populate_pci_child_dt(dev, fdt, offset, phb);
1341 
1342     g_assert(!ret);
1343     if (ret) {
1344         return 0;
1345     }
1346     return offset;
1347 }
1348 
1349 static void spapr_phb_add_pci_device(sPAPRDRConnector *drc,
1350                                      sPAPRPHBState *phb,
1351                                      PCIDevice *pdev,
1352                                      Error **errp)
1353 {
1354     sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
1355     DeviceState *dev = DEVICE(pdev);
1356     void *fdt = NULL;
1357     int fdt_start_offset = 0, fdt_size;
1358 
1359     fdt = create_device_tree(&fdt_size);
1360     fdt_start_offset = spapr_create_pci_child_dt(phb, pdev, fdt, 0);
1361     if (!fdt_start_offset) {
1362         error_setg(errp, "Failed to create pci child device tree node");
1363         goto out;
1364     }
1365 
1366     drck->attach(drc, DEVICE(pdev),
1367                  fdt, fdt_start_offset, !dev->hotplugged, errp);
1368 out:
1369     if (*errp) {
1370         g_free(fdt);
1371     }
1372 }
1373 
1374 static void spapr_phb_remove_pci_device_cb(DeviceState *dev, void *opaque)
1375 {
1376     /* some version guests do not wait for completion of a device
1377      * cleanup (generally done asynchronously by the kernel) before
1378      * signaling to QEMU that the device is safe, but instead sleep
1379      * for some 'safe' period of time. unfortunately on a busy host
1380      * this sleep isn't guaranteed to be long enough, resulting in
1381      * bad things like IRQ lines being left asserted during final
1382      * device removal. to deal with this we call reset just prior
1383      * to finalizing the device, which will put the device back into
1384      * an 'idle' state, as the device cleanup code expects.
1385      */
1386     pci_device_reset(PCI_DEVICE(dev));
1387     object_unparent(OBJECT(dev));
1388 }
1389 
1390 static void spapr_phb_remove_pci_device(sPAPRDRConnector *drc,
1391                                         sPAPRPHBState *phb,
1392                                         PCIDevice *pdev,
1393                                         Error **errp)
1394 {
1395     sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
1396 
1397     drck->detach(drc, DEVICE(pdev), spapr_phb_remove_pci_device_cb, phb, errp);
1398 }
1399 
1400 static sPAPRDRConnector *spapr_phb_get_pci_func_drc(sPAPRPHBState *phb,
1401                                                     uint32_t busnr,
1402                                                     int32_t devfn)
1403 {
1404     return spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_PCI,
1405                                     (phb->index << 16) |
1406                                     (busnr << 8) |
1407                                     devfn);
1408 }
1409 
1410 static sPAPRDRConnector *spapr_phb_get_pci_drc(sPAPRPHBState *phb,
1411                                                PCIDevice *pdev)
1412 {
1413     uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
1414     return spapr_phb_get_pci_func_drc(phb, busnr, pdev->devfn);
1415 }
1416 
1417 static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb,
1418                                             PCIDevice *pdev)
1419 {
1420     sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev);
1421     sPAPRDRConnectorClass *drck;
1422 
1423     if (!drc) {
1424         return 0;
1425     }
1426 
1427     drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
1428     return drck->get_index(drc);
1429 }
1430 
1431 static void spapr_phb_hot_plug_child(HotplugHandler *plug_handler,
1432                                      DeviceState *plugged_dev, Error **errp)
1433 {
1434     sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1435     PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1436     sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev);
1437     Error *local_err = NULL;
1438     PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1439     uint32_t slotnr = PCI_SLOT(pdev->devfn);
1440 
1441     /* if DR is disabled we don't need to do anything in the case of
1442      * hotplug or coldplug callbacks
1443      */
1444     if (!phb->dr_enabled) {
1445         /* if this is a hotplug operation initiated by the user
1446          * we need to let them know it's not enabled
1447          */
1448         if (plugged_dev->hotplugged) {
1449             error_setg(errp, QERR_BUS_NO_HOTPLUG,
1450                        object_get_typename(OBJECT(phb)));
1451         }
1452         return;
1453     }
1454 
1455     g_assert(drc);
1456 
1457     /* Following the QEMU convention used for PCIe multifunction
1458      * hotplug, we do not allow functions to be hotplugged to a
1459      * slot that already has function 0 present
1460      */
1461     if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] &&
1462         PCI_FUNC(pdev->devfn) != 0) {
1463         error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s,"
1464                    " additional functions can no longer be exposed to guest.",
1465                    slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name);
1466         return;
1467     }
1468 
1469     spapr_phb_add_pci_device(drc, phb, pdev, &local_err);
1470     if (local_err) {
1471         error_propagate(errp, local_err);
1472         return;
1473     }
1474 
1475     /* If this is function 0, signal hotplug for all the device functions.
1476      * Otherwise defer sending the hotplug event.
1477      */
1478     if (plugged_dev->hotplugged && PCI_FUNC(pdev->devfn) == 0) {
1479         int i;
1480 
1481         for (i = 0; i < 8; i++) {
1482             sPAPRDRConnector *func_drc;
1483             sPAPRDRConnectorClass *func_drck;
1484             sPAPRDREntitySense state;
1485 
1486             func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1487                                                   PCI_DEVFN(slotnr, i));
1488             func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1489             func_drck->entity_sense(func_drc, &state);
1490 
1491             if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1492                 spapr_hotplug_req_add_by_index(func_drc);
1493             }
1494         }
1495     }
1496 }
1497 
1498 static void spapr_phb_hot_unplug_child(HotplugHandler *plug_handler,
1499                                        DeviceState *plugged_dev, Error **errp)
1500 {
1501     sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1502     PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1503     sPAPRDRConnectorClass *drck;
1504     sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev);
1505     Error *local_err = NULL;
1506 
1507     if (!phb->dr_enabled) {
1508         error_setg(errp, QERR_BUS_NO_HOTPLUG,
1509                    object_get_typename(OBJECT(phb)));
1510         return;
1511     }
1512 
1513     g_assert(drc);
1514 
1515     drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
1516     if (!drck->release_pending(drc)) {
1517         PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1518         uint32_t slotnr = PCI_SLOT(pdev->devfn);
1519         sPAPRDRConnector *func_drc;
1520         sPAPRDRConnectorClass *func_drck;
1521         sPAPRDREntitySense state;
1522         int i;
1523 
1524         /* ensure any other present functions are pending unplug */
1525         if (PCI_FUNC(pdev->devfn) == 0) {
1526             for (i = 1; i < 8; i++) {
1527                 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1528                                                       PCI_DEVFN(slotnr, i));
1529                 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1530                 func_drck->entity_sense(func_drc, &state);
1531                 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT
1532                     && !func_drck->release_pending(func_drc)) {
1533                     error_setg(errp,
1534                                "PCI: slot %d, function %d still present. "
1535                                "Must unplug all non-0 functions first.",
1536                                slotnr, i);
1537                     return;
1538                 }
1539             }
1540         }
1541 
1542         spapr_phb_remove_pci_device(drc, phb, pdev, &local_err);
1543         if (local_err) {
1544             error_propagate(errp, local_err);
1545             return;
1546         }
1547 
1548         /* if this isn't func 0, defer unplug event. otherwise signal removal
1549          * for all present functions
1550          */
1551         if (PCI_FUNC(pdev->devfn) == 0) {
1552             for (i = 7; i >= 0; i--) {
1553                 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1554                                                       PCI_DEVFN(slotnr, i));
1555                 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1556                 func_drck->entity_sense(func_drc, &state);
1557                 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1558                     spapr_hotplug_req_remove_by_index(func_drc);
1559                 }
1560             }
1561         }
1562     }
1563 }
1564 
1565 static void spapr_phb_realize(DeviceState *dev, Error **errp)
1566 {
1567     sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1568     SysBusDevice *s = SYS_BUS_DEVICE(dev);
1569     sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
1570     PCIHostState *phb = PCI_HOST_BRIDGE(s);
1571     char *namebuf;
1572     int i;
1573     PCIBus *bus;
1574     uint64_t msi_window_size = 4096;
1575     sPAPRTCETable *tcet;
1576     const unsigned windows_supported =
1577         sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1;
1578 
1579     if (sphb->index != (uint32_t)-1) {
1580         sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
1581         Error *local_err = NULL;
1582 
1583         if ((sphb->buid != (uint64_t)-1) || (sphb->dma_liobn[0] != (uint32_t)-1)
1584             || (sphb->dma_liobn[1] != (uint32_t)-1 && windows_supported == 2)
1585             || (sphb->mem_win_addr != (hwaddr)-1)
1586             || (sphb->mem64_win_addr != (hwaddr)-1)
1587             || (sphb->io_win_addr != (hwaddr)-1)) {
1588             error_setg(errp, "Either \"index\" or other parameters must"
1589                        " be specified for PAPR PHB, not both");
1590             return;
1591         }
1592 
1593         smc->phb_placement(spapr, sphb->index,
1594                            &sphb->buid, &sphb->io_win_addr,
1595                            &sphb->mem_win_addr, &sphb->mem64_win_addr,
1596                            windows_supported, sphb->dma_liobn, &local_err);
1597         if (local_err) {
1598             error_propagate(errp, local_err);
1599             return;
1600         }
1601     }
1602 
1603     if (sphb->buid == (uint64_t)-1) {
1604         error_setg(errp, "BUID not specified for PHB");
1605         return;
1606     }
1607 
1608     if ((sphb->dma_liobn[0] == (uint32_t)-1) ||
1609         ((sphb->dma_liobn[1] == (uint32_t)-1) && (windows_supported > 1))) {
1610         error_setg(errp, "LIOBN(s) not specified for PHB");
1611         return;
1612     }
1613 
1614     if (sphb->mem_win_addr == (hwaddr)-1) {
1615         error_setg(errp, "Memory window address not specified for PHB");
1616         return;
1617     }
1618 
1619     if (sphb->io_win_addr == (hwaddr)-1) {
1620         error_setg(errp, "IO window address not specified for PHB");
1621         return;
1622     }
1623 
1624     if (sphb->mem64_win_size != 0) {
1625         if (sphb->mem64_win_addr == (hwaddr)-1) {
1626             error_setg(errp,
1627                        "64-bit memory window address not specified for PHB");
1628             return;
1629         }
1630 
1631         if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1632             error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx
1633                        " (max 2 GiB)", sphb->mem_win_size);
1634             return;
1635         }
1636 
1637         if (sphb->mem64_win_pciaddr == (hwaddr)-1) {
1638             /* 64-bit window defaults to identity mapping */
1639             sphb->mem64_win_pciaddr = sphb->mem64_win_addr;
1640         }
1641     } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1642         /*
1643          * For compatibility with old configuration, if no 64-bit MMIO
1644          * window is specified, but the ordinary (32-bit) memory
1645          * window is specified as > 2GiB, we treat it as a 2GiB 32-bit
1646          * window, with a 64-bit MMIO window following on immediately
1647          * afterwards
1648          */
1649         sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE;
1650         sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE;
1651         sphb->mem64_win_pciaddr =
1652             SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE;
1653         sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE;
1654     }
1655 
1656     if (spapr_pci_find_phb(spapr, sphb->buid)) {
1657         error_setg(errp, "PCI host bridges must have unique BUIDs");
1658         return;
1659     }
1660 
1661     if (sphb->numa_node != -1 &&
1662         (sphb->numa_node >= MAX_NODES || !numa_info[sphb->numa_node].present)) {
1663         error_setg(errp, "Invalid NUMA node ID for PCI host bridge");
1664         return;
1665     }
1666 
1667     sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
1668 
1669     namebuf = alloca(strlen(sphb->dtbusname) + 32);
1670 
1671     /* Initialize memory regions */
1672     sprintf(namebuf, "%s.mmio", sphb->dtbusname);
1673     memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX);
1674 
1675     sprintf(namebuf, "%s.mmio32-alias", sphb->dtbusname);
1676     memory_region_init_alias(&sphb->mem32window, OBJECT(sphb),
1677                              namebuf, &sphb->memspace,
1678                              SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
1679     memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
1680                                 &sphb->mem32window);
1681 
1682     sprintf(namebuf, "%s.mmio64-alias", sphb->dtbusname);
1683     memory_region_init_alias(&sphb->mem64window, OBJECT(sphb),
1684                              namebuf, &sphb->memspace,
1685                              sphb->mem64_win_pciaddr, sphb->mem64_win_size);
1686     memory_region_add_subregion(get_system_memory(), sphb->mem64_win_addr,
1687                                 &sphb->mem64window);
1688 
1689     /* Initialize IO regions */
1690     sprintf(namebuf, "%s.io", sphb->dtbusname);
1691     memory_region_init(&sphb->iospace, OBJECT(sphb),
1692                        namebuf, SPAPR_PCI_IO_WIN_SIZE);
1693 
1694     sprintf(namebuf, "%s.io-alias", sphb->dtbusname);
1695     memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf,
1696                              &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE);
1697     memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
1698                                 &sphb->iowindow);
1699 
1700     bus = pci_register_bus(dev, NULL,
1701                            pci_spapr_set_irq, pci_spapr_map_irq, sphb,
1702                            &sphb->memspace, &sphb->iospace,
1703                            PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS);
1704     phb->bus = bus;
1705     qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL);
1706 
1707     /*
1708      * Initialize PHB address space.
1709      * By default there will be at least one subregion for default
1710      * 32bit DMA window.
1711      * Later the guest might want to create another DMA window
1712      * which will become another memory subregion.
1713      */
1714     sprintf(namebuf, "%s.iommu-root", sphb->dtbusname);
1715 
1716     memory_region_init(&sphb->iommu_root, OBJECT(sphb),
1717                        namebuf, UINT64_MAX);
1718     address_space_init(&sphb->iommu_as, &sphb->iommu_root,
1719                        sphb->dtbusname);
1720 
1721     /*
1722      * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
1723      * we need to allocate some memory to catch those writes coming
1724      * from msi_notify()/msix_notify().
1725      * As MSIMessage:addr is going to be the same and MSIMessage:data
1726      * is going to be a VIRQ number, 4 bytes of the MSI MR will only
1727      * be used.
1728      *
1729      * For KVM we want to ensure that this memory is a full page so that
1730      * our memory slot is of page size granularity.
1731      */
1732 #ifdef CONFIG_KVM
1733     if (kvm_enabled()) {
1734         msi_window_size = getpagesize();
1735     }
1736 #endif
1737 
1738     memory_region_init_io(&sphb->msiwindow, NULL, &spapr_msi_ops, spapr,
1739                           "msi", msi_window_size);
1740     memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW,
1741                                 &sphb->msiwindow);
1742 
1743     pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb);
1744 
1745     pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq);
1746 
1747     QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
1748 
1749     /* Initialize the LSI table */
1750     for (i = 0; i < PCI_NUM_PINS; i++) {
1751         uint32_t irq;
1752         Error *local_err = NULL;
1753 
1754         irq = spapr_ics_alloc_block(spapr->ics, 1, true, false, &local_err);
1755         if (local_err) {
1756             error_propagate(errp, local_err);
1757             error_prepend(errp, "can't allocate LSIs: ");
1758             return;
1759         }
1760 
1761         sphb->lsi_table[i].irq = irq;
1762     }
1763 
1764     /* allocate connectors for child PCI devices */
1765     if (sphb->dr_enabled) {
1766         for (i = 0; i < PCI_SLOT_MAX * 8; i++) {
1767             spapr_dr_connector_new(OBJECT(phb),
1768                                    SPAPR_DR_CONNECTOR_TYPE_PCI,
1769                                    (sphb->index << 16) | i);
1770         }
1771     }
1772 
1773     /* DMA setup */
1774     for (i = 0; i < windows_supported; ++i) {
1775         tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]);
1776         if (!tcet) {
1777             error_setg(errp, "Creating window#%d failed for %s",
1778                        i, sphb->dtbusname);
1779             return;
1780         }
1781         memory_region_add_subregion_overlap(&sphb->iommu_root, 0,
1782                                             spapr_tce_get_iommu(tcet), 0);
1783     }
1784 
1785     sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free);
1786 }
1787 
1788 static int spapr_phb_children_reset(Object *child, void *opaque)
1789 {
1790     DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
1791 
1792     if (dev) {
1793         device_reset(dev);
1794     }
1795 
1796     return 0;
1797 }
1798 
1799 void spapr_phb_dma_reset(sPAPRPHBState *sphb)
1800 {
1801     int i;
1802     sPAPRTCETable *tcet;
1803 
1804     for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) {
1805         tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
1806 
1807         if (tcet && tcet->nb_table) {
1808             spapr_tce_table_disable(tcet);
1809         }
1810     }
1811 
1812     /* Register default 32bit DMA window */
1813     tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]);
1814     spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr,
1815                            sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT);
1816 }
1817 
1818 static void spapr_phb_reset(DeviceState *qdev)
1819 {
1820     sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev);
1821 
1822     spapr_phb_dma_reset(sphb);
1823 
1824     /* Reset the IOMMU state */
1825     object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL);
1826 
1827     if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) {
1828         spapr_phb_vfio_reset(qdev);
1829     }
1830 }
1831 
1832 static Property spapr_phb_properties[] = {
1833     DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1),
1834     DEFINE_PROP_UINT64("buid", sPAPRPHBState, buid, -1),
1835     DEFINE_PROP_UINT32("liobn", sPAPRPHBState, dma_liobn[0], -1),
1836     DEFINE_PROP_UINT32("liobn64", sPAPRPHBState, dma_liobn[1], -1),
1837     DEFINE_PROP_UINT64("mem_win_addr", sPAPRPHBState, mem_win_addr, -1),
1838     DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size,
1839                        SPAPR_PCI_MEM32_WIN_SIZE),
1840     DEFINE_PROP_UINT64("mem64_win_addr", sPAPRPHBState, mem64_win_addr, -1),
1841     DEFINE_PROP_UINT64("mem64_win_size", sPAPRPHBState, mem64_win_size,
1842                        SPAPR_PCI_MEM64_WIN_SIZE),
1843     DEFINE_PROP_UINT64("mem64_win_pciaddr", sPAPRPHBState, mem64_win_pciaddr,
1844                        -1),
1845     DEFINE_PROP_UINT64("io_win_addr", sPAPRPHBState, io_win_addr, -1),
1846     DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size,
1847                        SPAPR_PCI_IO_WIN_SIZE),
1848     DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled,
1849                      true),
1850     /* Default DMA window is 0..1GB */
1851     DEFINE_PROP_UINT64("dma_win_addr", sPAPRPHBState, dma_win_addr, 0),
1852     DEFINE_PROP_UINT64("dma_win_size", sPAPRPHBState, dma_win_size, 0x40000000),
1853     DEFINE_PROP_UINT64("dma64_win_addr", sPAPRPHBState, dma64_win_addr,
1854                        0x800000000000000ULL),
1855     DEFINE_PROP_BOOL("ddw", sPAPRPHBState, ddw_enabled, true),
1856     DEFINE_PROP_UINT64("pgsz", sPAPRPHBState, page_size_mask,
1857                        (1ULL << 12) | (1ULL << 16)),
1858     DEFINE_PROP_UINT32("numa_node", sPAPRPHBState, numa_node, -1),
1859     DEFINE_PROP_BOOL("pre-2.8-migration", sPAPRPHBState,
1860                      pre_2_8_migration, false),
1861     DEFINE_PROP_BOOL("pcie-extended-configuration-space", sPAPRPHBState,
1862                      pcie_ecs, true),
1863     DEFINE_PROP_END_OF_LIST(),
1864 };
1865 
1866 static const VMStateDescription vmstate_spapr_pci_lsi = {
1867     .name = "spapr_pci/lsi",
1868     .version_id = 1,
1869     .minimum_version_id = 1,
1870     .fields = (VMStateField[]) {
1871         VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi),
1872 
1873         VMSTATE_END_OF_LIST()
1874     },
1875 };
1876 
1877 static const VMStateDescription vmstate_spapr_pci_msi = {
1878     .name = "spapr_pci/msi",
1879     .version_id = 1,
1880     .minimum_version_id = 1,
1881     .fields = (VMStateField []) {
1882         VMSTATE_UINT32(key, spapr_pci_msi_mig),
1883         VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig),
1884         VMSTATE_UINT32(value.num, spapr_pci_msi_mig),
1885         VMSTATE_END_OF_LIST()
1886     },
1887 };
1888 
1889 static void spapr_pci_pre_save(void *opaque)
1890 {
1891     sPAPRPHBState *sphb = opaque;
1892     GHashTableIter iter;
1893     gpointer key, value;
1894     int i;
1895 
1896     g_free(sphb->msi_devs);
1897     sphb->msi_devs = NULL;
1898     sphb->msi_devs_num = g_hash_table_size(sphb->msi);
1899     if (!sphb->msi_devs_num) {
1900         return;
1901     }
1902     sphb->msi_devs = g_malloc(sphb->msi_devs_num * sizeof(spapr_pci_msi_mig));
1903 
1904     g_hash_table_iter_init(&iter, sphb->msi);
1905     for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) {
1906         sphb->msi_devs[i].key = *(uint32_t *) key;
1907         sphb->msi_devs[i].value = *(spapr_pci_msi *) value;
1908     }
1909 
1910     if (sphb->pre_2_8_migration) {
1911         sphb->mig_liobn = sphb->dma_liobn[0];
1912         sphb->mig_mem_win_addr = sphb->mem_win_addr;
1913         sphb->mig_mem_win_size = sphb->mem_win_size;
1914         sphb->mig_io_win_addr = sphb->io_win_addr;
1915         sphb->mig_io_win_size = sphb->io_win_size;
1916 
1917         if ((sphb->mem64_win_size != 0)
1918             && (sphb->mem64_win_addr
1919                 == (sphb->mem_win_addr + sphb->mem_win_size))) {
1920             sphb->mig_mem_win_size += sphb->mem64_win_size;
1921         }
1922     }
1923 }
1924 
1925 static int spapr_pci_post_load(void *opaque, int version_id)
1926 {
1927     sPAPRPHBState *sphb = opaque;
1928     gpointer key, value;
1929     int i;
1930 
1931     for (i = 0; i < sphb->msi_devs_num; ++i) {
1932         key = g_memdup(&sphb->msi_devs[i].key,
1933                        sizeof(sphb->msi_devs[i].key));
1934         value = g_memdup(&sphb->msi_devs[i].value,
1935                          sizeof(sphb->msi_devs[i].value));
1936         g_hash_table_insert(sphb->msi, key, value);
1937     }
1938     g_free(sphb->msi_devs);
1939     sphb->msi_devs = NULL;
1940     sphb->msi_devs_num = 0;
1941 
1942     return 0;
1943 }
1944 
1945 static bool pre_2_8_migration(void *opaque, int version_id)
1946 {
1947     sPAPRPHBState *sphb = opaque;
1948 
1949     return sphb->pre_2_8_migration;
1950 }
1951 
1952 static const VMStateDescription vmstate_spapr_pci = {
1953     .name = "spapr_pci",
1954     .version_id = 2,
1955     .minimum_version_id = 2,
1956     .pre_save = spapr_pci_pre_save,
1957     .post_load = spapr_pci_post_load,
1958     .fields = (VMStateField[]) {
1959         VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState),
1960         VMSTATE_UINT32_TEST(mig_liobn, sPAPRPHBState, pre_2_8_migration),
1961         VMSTATE_UINT64_TEST(mig_mem_win_addr, sPAPRPHBState, pre_2_8_migration),
1962         VMSTATE_UINT64_TEST(mig_mem_win_size, sPAPRPHBState, pre_2_8_migration),
1963         VMSTATE_UINT64_TEST(mig_io_win_addr, sPAPRPHBState, pre_2_8_migration),
1964         VMSTATE_UINT64_TEST(mig_io_win_size, sPAPRPHBState, pre_2_8_migration),
1965         VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0,
1966                              vmstate_spapr_pci_lsi, struct spapr_pci_lsi),
1967         VMSTATE_INT32(msi_devs_num, sPAPRPHBState),
1968         VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0,
1969                                     vmstate_spapr_pci_msi, spapr_pci_msi_mig),
1970         VMSTATE_END_OF_LIST()
1971     },
1972 };
1973 
1974 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge,
1975                                            PCIBus *rootbus)
1976 {
1977     sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge);
1978 
1979     return sphb->dtbusname;
1980 }
1981 
1982 static void spapr_phb_class_init(ObjectClass *klass, void *data)
1983 {
1984     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
1985     DeviceClass *dc = DEVICE_CLASS(klass);
1986     HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass);
1987 
1988     hc->root_bus_path = spapr_phb_root_bus_path;
1989     dc->realize = spapr_phb_realize;
1990     dc->props = spapr_phb_properties;
1991     dc->reset = spapr_phb_reset;
1992     dc->vmsd = &vmstate_spapr_pci;
1993     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1994     hp->plug = spapr_phb_hot_plug_child;
1995     hp->unplug = spapr_phb_hot_unplug_child;
1996 }
1997 
1998 static const TypeInfo spapr_phb_info = {
1999     .name          = TYPE_SPAPR_PCI_HOST_BRIDGE,
2000     .parent        = TYPE_PCI_HOST_BRIDGE,
2001     .instance_size = sizeof(sPAPRPHBState),
2002     .class_init    = spapr_phb_class_init,
2003     .interfaces    = (InterfaceInfo[]) {
2004         { TYPE_HOTPLUG_HANDLER },
2005         { }
2006     }
2007 };
2008 
2009 PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index)
2010 {
2011     DeviceState *dev;
2012 
2013     dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
2014     qdev_prop_set_uint32(dev, "index", index);
2015     qdev_init_nofail(dev);
2016 
2017     return PCI_HOST_BRIDGE(dev);
2018 }
2019 
2020 typedef struct sPAPRFDT {
2021     void *fdt;
2022     int node_off;
2023     sPAPRPHBState *sphb;
2024 } sPAPRFDT;
2025 
2026 static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev,
2027                                           void *opaque)
2028 {
2029     PCIBus *sec_bus;
2030     sPAPRFDT *p = opaque;
2031     int offset;
2032     sPAPRFDT s_fdt;
2033 
2034     offset = spapr_create_pci_child_dt(p->sphb, pdev, p->fdt, p->node_off);
2035     if (!offset) {
2036         error_report("Failed to create pci child device tree node");
2037         return;
2038     }
2039 
2040     if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
2041          PCI_HEADER_TYPE_BRIDGE)) {
2042         return;
2043     }
2044 
2045     sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
2046     if (!sec_bus) {
2047         return;
2048     }
2049 
2050     s_fdt.fdt = p->fdt;
2051     s_fdt.node_off = offset;
2052     s_fdt.sphb = p->sphb;
2053     pci_for_each_device_reverse(sec_bus, pci_bus_num(sec_bus),
2054                                 spapr_populate_pci_devices_dt,
2055                                 &s_fdt);
2056 }
2057 
2058 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev,
2059                                            void *opaque)
2060 {
2061     unsigned int *bus_no = opaque;
2062     unsigned int primary = *bus_no;
2063     unsigned int subordinate = 0xff;
2064     PCIBus *sec_bus = NULL;
2065 
2066     if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
2067          PCI_HEADER_TYPE_BRIDGE)) {
2068         return;
2069     }
2070 
2071     (*bus_no)++;
2072     pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1);
2073     pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1);
2074     pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2075 
2076     sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
2077     if (!sec_bus) {
2078         return;
2079     }
2080 
2081     pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1);
2082     pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
2083                         spapr_phb_pci_enumerate_bridge, bus_no);
2084     pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2085 }
2086 
2087 static void spapr_phb_pci_enumerate(sPAPRPHBState *phb)
2088 {
2089     PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2090     unsigned int bus_no = 0;
2091 
2092     pci_for_each_device(bus, pci_bus_num(bus),
2093                         spapr_phb_pci_enumerate_bridge,
2094                         &bus_no);
2095 
2096 }
2097 
2098 int spapr_populate_pci_dt(sPAPRPHBState *phb,
2099                           uint32_t xics_phandle,
2100                           void *fdt)
2101 {
2102     int bus_off, i, j, ret;
2103     char nodename[FDT_NAME_MAX];
2104     uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
2105     struct {
2106         uint32_t hi;
2107         uint64_t child;
2108         uint64_t parent;
2109         uint64_t size;
2110     } QEMU_PACKED ranges[] = {
2111         {
2112             cpu_to_be32(b_ss(1)), cpu_to_be64(0),
2113             cpu_to_be64(phb->io_win_addr),
2114             cpu_to_be64(memory_region_size(&phb->iospace)),
2115         },
2116         {
2117             cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
2118             cpu_to_be64(phb->mem_win_addr),
2119             cpu_to_be64(phb->mem_win_size),
2120         },
2121         {
2122             cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr),
2123             cpu_to_be64(phb->mem64_win_addr),
2124             cpu_to_be64(phb->mem64_win_size),
2125         },
2126     };
2127     const unsigned sizeof_ranges =
2128         (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]);
2129     uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
2130     uint32_t interrupt_map_mask[] = {
2131         cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
2132     uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
2133     uint32_t ddw_applicable[] = {
2134         cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW),
2135         cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW),
2136         cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW)
2137     };
2138     uint32_t ddw_extensions[] = {
2139         cpu_to_be32(1),
2140         cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW)
2141     };
2142     uint32_t associativity[] = {cpu_to_be32(0x4),
2143                                 cpu_to_be32(0x0),
2144                                 cpu_to_be32(0x0),
2145                                 cpu_to_be32(0x0),
2146                                 cpu_to_be32(phb->numa_node)};
2147     sPAPRTCETable *tcet;
2148     PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2149     sPAPRFDT s_fdt;
2150 
2151     /* Start populating the FDT */
2152     snprintf(nodename, FDT_NAME_MAX, "pci@%" PRIx64, phb->buid);
2153     bus_off = fdt_add_subnode(fdt, 0, nodename);
2154     if (bus_off < 0) {
2155         return bus_off;
2156     }
2157 
2158     /* Write PHB properties */
2159     _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
2160     _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
2161     _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
2162     _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
2163     _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
2164     _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
2165     _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
2166     _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges));
2167     _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
2168     _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
2169     _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS_SPAPR));
2170 
2171     /* Dynamic DMA window */
2172     if (phb->ddw_enabled) {
2173         _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable,
2174                          sizeof(ddw_applicable)));
2175         _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions",
2176                          &ddw_extensions, sizeof(ddw_extensions)));
2177     }
2178 
2179     /* Advertise NUMA via ibm,associativity */
2180     if (phb->numa_node != -1) {
2181         _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity,
2182                          sizeof(associativity)));
2183     }
2184 
2185     /* Build the interrupt-map, this must matches what is done
2186      * in pci_spapr_map_irq
2187      */
2188     _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
2189                      &interrupt_map_mask, sizeof(interrupt_map_mask)));
2190     for (i = 0; i < PCI_SLOT_MAX; i++) {
2191         for (j = 0; j < PCI_NUM_PINS; j++) {
2192             uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
2193             int lsi_num = pci_spapr_swizzle(i, j);
2194 
2195             irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
2196             irqmap[1] = 0;
2197             irqmap[2] = 0;
2198             irqmap[3] = cpu_to_be32(j+1);
2199             irqmap[4] = cpu_to_be32(xics_phandle);
2200             irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq);
2201             irqmap[6] = cpu_to_be32(0x8);
2202         }
2203     }
2204     /* Write interrupt map */
2205     _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
2206                      sizeof(interrupt_map)));
2207 
2208     tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]);
2209     if (!tcet) {
2210         return -1;
2211     }
2212     spapr_dma_dt(fdt, bus_off, "ibm,dma-window",
2213                  tcet->liobn, tcet->bus_offset,
2214                  tcet->nb_table << tcet->page_shift);
2215 
2216     /* Walk the bridges and program the bus numbers*/
2217     spapr_phb_pci_enumerate(phb);
2218     _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1));
2219 
2220     /* Populate tree nodes with PCI devices attached */
2221     s_fdt.fdt = fdt;
2222     s_fdt.node_off = bus_off;
2223     s_fdt.sphb = phb;
2224     pci_for_each_device_reverse(bus, pci_bus_num(bus),
2225                                 spapr_populate_pci_devices_dt,
2226                                 &s_fdt);
2227 
2228     ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb),
2229                                 SPAPR_DR_CONNECTOR_TYPE_PCI);
2230     if (ret) {
2231         return ret;
2232     }
2233 
2234     return 0;
2235 }
2236 
2237 void spapr_pci_rtas_init(void)
2238 {
2239     spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config",
2240                         rtas_read_pci_config);
2241     spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config",
2242                         rtas_write_pci_config);
2243     spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config",
2244                         rtas_ibm_read_pci_config);
2245     spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config",
2246                         rtas_ibm_write_pci_config);
2247     if (msi_nonbroken) {
2248         spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER,
2249                             "ibm,query-interrupt-source-number",
2250                             rtas_ibm_query_interrupt_source_number);
2251         spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
2252                             rtas_ibm_change_msi);
2253     }
2254 
2255     spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION,
2256                         "ibm,set-eeh-option",
2257                         rtas_ibm_set_eeh_option);
2258     spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2,
2259                         "ibm,get-config-addr-info2",
2260                         rtas_ibm_get_config_addr_info2);
2261     spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2,
2262                         "ibm,read-slot-reset-state2",
2263                         rtas_ibm_read_slot_reset_state2);
2264     spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET,
2265                         "ibm,set-slot-reset",
2266                         rtas_ibm_set_slot_reset);
2267     spapr_rtas_register(RTAS_IBM_CONFIGURE_PE,
2268                         "ibm,configure-pe",
2269                         rtas_ibm_configure_pe);
2270     spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
2271                         "ibm,slot-error-detail",
2272                         rtas_ibm_slot_error_detail);
2273 }
2274 
2275 static void spapr_pci_register_types(void)
2276 {
2277     type_register_static(&spapr_phb_info);
2278 }
2279 
2280 type_init(spapr_pci_register_types)
2281 
2282 static int spapr_switch_one_vga(DeviceState *dev, void *opaque)
2283 {
2284     bool be = *(bool *)opaque;
2285 
2286     if (object_dynamic_cast(OBJECT(dev), "VGA")
2287         || object_dynamic_cast(OBJECT(dev), "secondary-vga")) {
2288         object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer",
2289                                  &error_abort);
2290     }
2291     return 0;
2292 }
2293 
2294 void spapr_pci_switch_vga(bool big_endian)
2295 {
2296     sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
2297     sPAPRPHBState *sphb;
2298 
2299     /*
2300      * For backward compatibility with existing guests, we switch
2301      * the endianness of the VGA controller when changing the guest
2302      * interrupt mode
2303      */
2304     QLIST_FOREACH(sphb, &spapr->phbs, list) {
2305         BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus;
2306         qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL,
2307                            &big_endian);
2308     }
2309 }
2310