1 /* 2 * QEMU sPAPR PCI host originated from Uninorth PCI host 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. 5 * Copyright (C) 2011 David Gibson, IBM Corporation. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "cpu.h" 29 #include "hw/irq.h" 30 #include "hw/sysbus.h" 31 #include "migration/vmstate.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/msi.h" 34 #include "hw/pci/msix.h" 35 #include "hw/pci/pci_host.h" 36 #include "hw/ppc/spapr.h" 37 #include "hw/pci-host/spapr.h" 38 #include "exec/address-spaces.h" 39 #include "exec/ram_addr.h" 40 #include <libfdt.h> 41 #include "trace.h" 42 #include "qemu/error-report.h" 43 #include "qemu/module.h" 44 #include "qapi/qmp/qerror.h" 45 #include "hw/ppc/fdt.h" 46 #include "hw/pci/pci_bridge.h" 47 #include "hw/pci/pci_bus.h" 48 #include "hw/pci/pci_ids.h" 49 #include "hw/ppc/spapr_drc.h" 50 #include "hw/qdev-properties.h" 51 #include "sysemu/device_tree.h" 52 #include "sysemu/kvm.h" 53 #include "sysemu/hostmem.h" 54 #include "sysemu/numa.h" 55 56 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ 57 #define RTAS_QUERY_FN 0 58 #define RTAS_CHANGE_FN 1 59 #define RTAS_RESET_FN 2 60 #define RTAS_CHANGE_MSI_FN 3 61 #define RTAS_CHANGE_MSIX_FN 4 62 63 /* Interrupt types to return on RTAS_CHANGE_* */ 64 #define RTAS_TYPE_MSI 1 65 #define RTAS_TYPE_MSIX 2 66 67 SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid) 68 { 69 SpaprPhbState *sphb; 70 71 QLIST_FOREACH(sphb, &spapr->phbs, list) { 72 if (sphb->buid != buid) { 73 continue; 74 } 75 return sphb; 76 } 77 78 return NULL; 79 } 80 81 PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid, 82 uint32_t config_addr) 83 { 84 SpaprPhbState *sphb = spapr_pci_find_phb(spapr, buid); 85 PCIHostState *phb = PCI_HOST_BRIDGE(sphb); 86 int bus_num = (config_addr >> 16) & 0xFF; 87 int devfn = (config_addr >> 8) & 0xFF; 88 89 if (!phb) { 90 return NULL; 91 } 92 93 return pci_find_device(phb->bus, bus_num, devfn); 94 } 95 96 static uint32_t rtas_pci_cfgaddr(uint32_t arg) 97 { 98 /* This handles the encoding of extended config space addresses */ 99 return ((arg >> 20) & 0xf00) | (arg & 0xff); 100 } 101 102 static void finish_read_pci_config(SpaprMachineState *spapr, uint64_t buid, 103 uint32_t addr, uint32_t size, 104 target_ulong rets) 105 { 106 PCIDevice *pci_dev; 107 uint32_t val; 108 109 if ((size != 1) && (size != 2) && (size != 4)) { 110 /* access must be 1, 2 or 4 bytes */ 111 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 112 return; 113 } 114 115 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 116 addr = rtas_pci_cfgaddr(addr); 117 118 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 119 /* Access must be to a valid device, within bounds and 120 * naturally aligned */ 121 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 122 return; 123 } 124 125 val = pci_host_config_read_common(pci_dev, addr, 126 pci_config_size(pci_dev), size); 127 128 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 129 rtas_st(rets, 1, val); 130 } 131 132 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 133 uint32_t token, uint32_t nargs, 134 target_ulong args, 135 uint32_t nret, target_ulong rets) 136 { 137 uint64_t buid; 138 uint32_t size, addr; 139 140 if ((nargs != 4) || (nret != 2)) { 141 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 142 return; 143 } 144 145 buid = rtas_ldq(args, 1); 146 size = rtas_ld(args, 3); 147 addr = rtas_ld(args, 0); 148 149 finish_read_pci_config(spapr, buid, addr, size, rets); 150 } 151 152 static void rtas_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 153 uint32_t token, uint32_t nargs, 154 target_ulong args, 155 uint32_t nret, target_ulong rets) 156 { 157 uint32_t size, addr; 158 159 if ((nargs != 2) || (nret != 2)) { 160 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 161 return; 162 } 163 164 size = rtas_ld(args, 1); 165 addr = rtas_ld(args, 0); 166 167 finish_read_pci_config(spapr, 0, addr, size, rets); 168 } 169 170 static void finish_write_pci_config(SpaprMachineState *spapr, uint64_t buid, 171 uint32_t addr, uint32_t size, 172 uint32_t val, target_ulong rets) 173 { 174 PCIDevice *pci_dev; 175 176 if ((size != 1) && (size != 2) && (size != 4)) { 177 /* access must be 1, 2 or 4 bytes */ 178 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 179 return; 180 } 181 182 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 183 addr = rtas_pci_cfgaddr(addr); 184 185 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 186 /* Access must be to a valid device, within bounds and 187 * naturally aligned */ 188 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 189 return; 190 } 191 192 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), 193 val, size); 194 195 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 196 } 197 198 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 199 uint32_t token, uint32_t nargs, 200 target_ulong args, 201 uint32_t nret, target_ulong rets) 202 { 203 uint64_t buid; 204 uint32_t val, size, addr; 205 206 if ((nargs != 5) || (nret != 1)) { 207 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 208 return; 209 } 210 211 buid = rtas_ldq(args, 1); 212 val = rtas_ld(args, 4); 213 size = rtas_ld(args, 3); 214 addr = rtas_ld(args, 0); 215 216 finish_write_pci_config(spapr, buid, addr, size, val, rets); 217 } 218 219 static void rtas_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 220 uint32_t token, uint32_t nargs, 221 target_ulong args, 222 uint32_t nret, target_ulong rets) 223 { 224 uint32_t val, size, addr; 225 226 if ((nargs != 3) || (nret != 1)) { 227 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 228 return; 229 } 230 231 232 val = rtas_ld(args, 2); 233 size = rtas_ld(args, 1); 234 addr = rtas_ld(args, 0); 235 236 finish_write_pci_config(spapr, 0, addr, size, val, rets); 237 } 238 239 /* 240 * Set MSI/MSIX message data. 241 * This is required for msi_notify()/msix_notify() which 242 * will write at the addresses via spapr_msi_write(). 243 * 244 * If hwaddr == 0, all entries will have .data == first_irq i.e. 245 * table will be reset. 246 */ 247 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, 248 unsigned first_irq, unsigned req_num) 249 { 250 unsigned i; 251 MSIMessage msg = { .address = addr, .data = first_irq }; 252 253 if (!msix) { 254 msi_set_message(pdev, msg); 255 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); 256 return; 257 } 258 259 for (i = 0; i < req_num; ++i) { 260 msix_set_message(pdev, i, msg); 261 trace_spapr_pci_msi_setup(pdev->name, i, msg.address); 262 if (addr) { 263 ++msg.data; 264 } 265 } 266 } 267 268 static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr, 269 uint32_t token, uint32_t nargs, 270 target_ulong args, uint32_t nret, 271 target_ulong rets) 272 { 273 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 274 uint32_t config_addr = rtas_ld(args, 0); 275 uint64_t buid = rtas_ldq(args, 1); 276 unsigned int func = rtas_ld(args, 3); 277 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ 278 unsigned int seq_num = rtas_ld(args, 5); 279 unsigned int ret_intr_type; 280 unsigned int irq, max_irqs = 0; 281 SpaprPhbState *phb = NULL; 282 PCIDevice *pdev = NULL; 283 spapr_pci_msi *msi; 284 int *config_addr_key; 285 Error *err = NULL; 286 int i; 287 288 /* Fins SpaprPhbState */ 289 phb = spapr_pci_find_phb(spapr, buid); 290 if (phb) { 291 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 292 } 293 if (!phb || !pdev) { 294 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 295 return; 296 } 297 298 switch (func) { 299 case RTAS_CHANGE_FN: 300 if (msi_present(pdev)) { 301 ret_intr_type = RTAS_TYPE_MSI; 302 } else if (msix_present(pdev)) { 303 ret_intr_type = RTAS_TYPE_MSIX; 304 } else { 305 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 306 return; 307 } 308 break; 309 case RTAS_CHANGE_MSI_FN: 310 if (msi_present(pdev)) { 311 ret_intr_type = RTAS_TYPE_MSI; 312 } else { 313 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 314 return; 315 } 316 break; 317 case RTAS_CHANGE_MSIX_FN: 318 if (msix_present(pdev)) { 319 ret_intr_type = RTAS_TYPE_MSIX; 320 } else { 321 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 322 return; 323 } 324 break; 325 default: 326 error_report("rtas_ibm_change_msi(%u) is not implemented", func); 327 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 328 return; 329 } 330 331 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); 332 333 /* Releasing MSIs */ 334 if (!req_num) { 335 if (!msi) { 336 trace_spapr_pci_msi("Releasing wrong config", config_addr); 337 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 338 return; 339 } 340 341 if (!smc->legacy_irq_allocation) { 342 spapr_irq_msi_free(spapr, msi->first_irq, msi->num); 343 } 344 spapr_irq_free(spapr, msi->first_irq, msi->num); 345 if (msi_present(pdev)) { 346 spapr_msi_setmsg(pdev, 0, false, 0, 0); 347 } 348 if (msix_present(pdev)) { 349 spapr_msi_setmsg(pdev, 0, true, 0, 0); 350 } 351 g_hash_table_remove(phb->msi, &config_addr); 352 353 trace_spapr_pci_msi("Released MSIs", config_addr); 354 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 355 rtas_st(rets, 1, 0); 356 return; 357 } 358 359 /* Enabling MSI */ 360 361 /* Check if the device supports as many IRQs as requested */ 362 if (ret_intr_type == RTAS_TYPE_MSI) { 363 max_irqs = msi_nr_vectors_allocated(pdev); 364 } else if (ret_intr_type == RTAS_TYPE_MSIX) { 365 max_irqs = pdev->msix_entries_nr; 366 } 367 if (!max_irqs) { 368 error_report("Requested interrupt type %d is not enabled for device %x", 369 ret_intr_type, config_addr); 370 rtas_st(rets, 0, -1); /* Hardware error */ 371 return; 372 } 373 /* Correct the number if the guest asked for too many */ 374 if (req_num > max_irqs) { 375 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); 376 req_num = max_irqs; 377 irq = 0; /* to avoid misleading trace */ 378 goto out; 379 } 380 381 /* Allocate MSIs */ 382 if (smc->legacy_irq_allocation) { 383 irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI, 384 &err); 385 } else { 386 irq = spapr_irq_msi_alloc(spapr, req_num, 387 ret_intr_type == RTAS_TYPE_MSI, &err); 388 } 389 if (err) { 390 error_reportf_err(err, "Can't allocate MSIs for device %x: ", 391 config_addr); 392 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 393 return; 394 } 395 396 for (i = 0; i < req_num; i++) { 397 spapr_irq_claim(spapr, irq + i, false, &err); 398 if (err) { 399 if (i) { 400 spapr_irq_free(spapr, irq, i); 401 } 402 if (!smc->legacy_irq_allocation) { 403 spapr_irq_msi_free(spapr, irq, req_num); 404 } 405 error_reportf_err(err, "Can't allocate MSIs for device %x: ", 406 config_addr); 407 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 408 return; 409 } 410 } 411 412 /* Release previous MSIs */ 413 if (msi) { 414 if (!smc->legacy_irq_allocation) { 415 spapr_irq_msi_free(spapr, msi->first_irq, msi->num); 416 } 417 spapr_irq_free(spapr, msi->first_irq, msi->num); 418 g_hash_table_remove(phb->msi, &config_addr); 419 } 420 421 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ 422 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, 423 irq, req_num); 424 425 /* Add MSI device to cache */ 426 msi = g_new(spapr_pci_msi, 1); 427 msi->first_irq = irq; 428 msi->num = req_num; 429 config_addr_key = g_new(int, 1); 430 *config_addr_key = config_addr; 431 g_hash_table_insert(phb->msi, config_addr_key, msi); 432 433 out: 434 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 435 rtas_st(rets, 1, req_num); 436 rtas_st(rets, 2, ++seq_num); 437 if (nret > 3) { 438 rtas_st(rets, 3, ret_intr_type); 439 } 440 441 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); 442 } 443 444 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, 445 SpaprMachineState *spapr, 446 uint32_t token, 447 uint32_t nargs, 448 target_ulong args, 449 uint32_t nret, 450 target_ulong rets) 451 { 452 uint32_t config_addr = rtas_ld(args, 0); 453 uint64_t buid = rtas_ldq(args, 1); 454 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); 455 SpaprPhbState *phb = NULL; 456 PCIDevice *pdev = NULL; 457 spapr_pci_msi *msi; 458 459 /* Find SpaprPhbState */ 460 phb = spapr_pci_find_phb(spapr, buid); 461 if (phb) { 462 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 463 } 464 if (!phb || !pdev) { 465 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 466 return; 467 } 468 469 /* Find device descriptor and start IRQ */ 470 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); 471 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { 472 trace_spapr_pci_msi("Failed to return vector", config_addr); 473 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 474 return; 475 } 476 intr_src_num = msi->first_irq + ioa_intr_num; 477 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, 478 intr_src_num); 479 480 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 481 rtas_st(rets, 1, intr_src_num); 482 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ 483 } 484 485 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, 486 SpaprMachineState *spapr, 487 uint32_t token, uint32_t nargs, 488 target_ulong args, uint32_t nret, 489 target_ulong rets) 490 { 491 SpaprPhbState *sphb; 492 uint32_t addr, option; 493 uint64_t buid; 494 int ret; 495 496 if ((nargs != 4) || (nret != 1)) { 497 goto param_error_exit; 498 } 499 500 buid = rtas_ldq(args, 1); 501 addr = rtas_ld(args, 0); 502 option = rtas_ld(args, 3); 503 504 sphb = spapr_pci_find_phb(spapr, buid); 505 if (!sphb) { 506 goto param_error_exit; 507 } 508 509 if (!spapr_phb_eeh_available(sphb)) { 510 goto param_error_exit; 511 } 512 513 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option); 514 rtas_st(rets, 0, ret); 515 return; 516 517 param_error_exit: 518 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 519 } 520 521 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, 522 SpaprMachineState *spapr, 523 uint32_t token, uint32_t nargs, 524 target_ulong args, uint32_t nret, 525 target_ulong rets) 526 { 527 SpaprPhbState *sphb; 528 PCIDevice *pdev; 529 uint32_t addr, option; 530 uint64_t buid; 531 532 if ((nargs != 4) || (nret != 2)) { 533 goto param_error_exit; 534 } 535 536 buid = rtas_ldq(args, 1); 537 sphb = spapr_pci_find_phb(spapr, buid); 538 if (!sphb) { 539 goto param_error_exit; 540 } 541 542 if (!spapr_phb_eeh_available(sphb)) { 543 goto param_error_exit; 544 } 545 546 /* 547 * We always have PE address of form "00BB0001". "BB" 548 * represents the bus number of PE's primary bus. 549 */ 550 option = rtas_ld(args, 3); 551 switch (option) { 552 case RTAS_GET_PE_ADDR: 553 addr = rtas_ld(args, 0); 554 pdev = spapr_pci_find_dev(spapr, buid, addr); 555 if (!pdev) { 556 goto param_error_exit; 557 } 558 559 rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1); 560 break; 561 case RTAS_GET_PE_MODE: 562 rtas_st(rets, 1, RTAS_PE_MODE_SHARED); 563 break; 564 default: 565 goto param_error_exit; 566 } 567 568 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 569 return; 570 571 param_error_exit: 572 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 573 } 574 575 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, 576 SpaprMachineState *spapr, 577 uint32_t token, uint32_t nargs, 578 target_ulong args, uint32_t nret, 579 target_ulong rets) 580 { 581 SpaprPhbState *sphb; 582 uint64_t buid; 583 int state, ret; 584 585 if ((nargs != 3) || (nret != 4 && nret != 5)) { 586 goto param_error_exit; 587 } 588 589 buid = rtas_ldq(args, 1); 590 sphb = spapr_pci_find_phb(spapr, buid); 591 if (!sphb) { 592 goto param_error_exit; 593 } 594 595 if (!spapr_phb_eeh_available(sphb)) { 596 goto param_error_exit; 597 } 598 599 ret = spapr_phb_vfio_eeh_get_state(sphb, &state); 600 rtas_st(rets, 0, ret); 601 if (ret != RTAS_OUT_SUCCESS) { 602 return; 603 } 604 605 rtas_st(rets, 1, state); 606 rtas_st(rets, 2, RTAS_EEH_SUPPORT); 607 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); 608 if (nret >= 5) { 609 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); 610 } 611 return; 612 613 param_error_exit: 614 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 615 } 616 617 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, 618 SpaprMachineState *spapr, 619 uint32_t token, uint32_t nargs, 620 target_ulong args, uint32_t nret, 621 target_ulong rets) 622 { 623 SpaprPhbState *sphb; 624 uint32_t option; 625 uint64_t buid; 626 int ret; 627 628 if ((nargs != 4) || (nret != 1)) { 629 goto param_error_exit; 630 } 631 632 buid = rtas_ldq(args, 1); 633 option = rtas_ld(args, 3); 634 sphb = spapr_pci_find_phb(spapr, buid); 635 if (!sphb) { 636 goto param_error_exit; 637 } 638 639 if (!spapr_phb_eeh_available(sphb)) { 640 goto param_error_exit; 641 } 642 643 ret = spapr_phb_vfio_eeh_reset(sphb, option); 644 rtas_st(rets, 0, ret); 645 return; 646 647 param_error_exit: 648 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 649 } 650 651 static void rtas_ibm_configure_pe(PowerPCCPU *cpu, 652 SpaprMachineState *spapr, 653 uint32_t token, uint32_t nargs, 654 target_ulong args, uint32_t nret, 655 target_ulong rets) 656 { 657 SpaprPhbState *sphb; 658 uint64_t buid; 659 int ret; 660 661 if ((nargs != 3) || (nret != 1)) { 662 goto param_error_exit; 663 } 664 665 buid = rtas_ldq(args, 1); 666 sphb = spapr_pci_find_phb(spapr, buid); 667 if (!sphb) { 668 goto param_error_exit; 669 } 670 671 if (!spapr_phb_eeh_available(sphb)) { 672 goto param_error_exit; 673 } 674 675 ret = spapr_phb_vfio_eeh_configure(sphb); 676 rtas_st(rets, 0, ret); 677 return; 678 679 param_error_exit: 680 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 681 } 682 683 /* To support it later */ 684 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, 685 SpaprMachineState *spapr, 686 uint32_t token, uint32_t nargs, 687 target_ulong args, uint32_t nret, 688 target_ulong rets) 689 { 690 SpaprPhbState *sphb; 691 int option; 692 uint64_t buid; 693 694 if ((nargs != 8) || (nret != 1)) { 695 goto param_error_exit; 696 } 697 698 buid = rtas_ldq(args, 1); 699 sphb = spapr_pci_find_phb(spapr, buid); 700 if (!sphb) { 701 goto param_error_exit; 702 } 703 704 if (!spapr_phb_eeh_available(sphb)) { 705 goto param_error_exit; 706 } 707 708 option = rtas_ld(args, 7); 709 switch (option) { 710 case RTAS_SLOT_TEMP_ERR_LOG: 711 case RTAS_SLOT_PERM_ERR_LOG: 712 break; 713 default: 714 goto param_error_exit; 715 } 716 717 /* We don't have error log yet */ 718 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); 719 return; 720 721 param_error_exit: 722 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 723 } 724 725 static void pci_spapr_set_irq(void *opaque, int irq_num, int level) 726 { 727 /* 728 * Here we use the number returned by pci_swizzle_map_irq_fn to find a 729 * corresponding qemu_irq. 730 */ 731 SpaprPhbState *phb = opaque; 732 733 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); 734 qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); 735 } 736 737 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) 738 { 739 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); 740 PCIINTxRoute route; 741 742 route.mode = PCI_INTX_ENABLED; 743 route.irq = sphb->lsi_table[pin].irq; 744 745 return route; 746 } 747 748 /* 749 * MSI/MSIX memory region implementation. 750 * The handler handles both MSI and MSIX. 751 * The vector number is encoded in least bits in data. 752 */ 753 static void spapr_msi_write(void *opaque, hwaddr addr, 754 uint64_t data, unsigned size) 755 { 756 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 757 uint32_t irq = data; 758 759 trace_spapr_pci_msi_write(addr, data, irq); 760 761 qemu_irq_pulse(spapr_qirq(spapr, irq)); 762 } 763 764 static const MemoryRegionOps spapr_msi_ops = { 765 /* There is no .read as the read result is undefined by PCI spec */ 766 .read = NULL, 767 .write = spapr_msi_write, 768 .endianness = DEVICE_LITTLE_ENDIAN 769 }; 770 771 /* 772 * PHB PCI device 773 */ 774 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 775 { 776 SpaprPhbState *phb = opaque; 777 778 return &phb->iommu_as; 779 } 780 781 static char *spapr_phb_vfio_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) 782 { 783 char *path = NULL, *buf = NULL, *host = NULL; 784 785 /* Get the PCI VFIO host id */ 786 host = object_property_get_str(OBJECT(pdev), "host", NULL); 787 if (!host) { 788 goto err_out; 789 } 790 791 /* Construct the path of the file that will give us the DT location */ 792 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); 793 g_free(host); 794 if (!g_file_get_contents(path, &buf, NULL, NULL)) { 795 goto err_out; 796 } 797 g_free(path); 798 799 /* Construct and read from host device tree the loc-code */ 800 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); 801 g_free(buf); 802 if (!g_file_get_contents(path, &buf, NULL, NULL)) { 803 goto err_out; 804 } 805 return buf; 806 807 err_out: 808 g_free(path); 809 return NULL; 810 } 811 812 static char *spapr_phb_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) 813 { 814 char *buf; 815 const char *devtype = "qemu"; 816 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 817 818 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 819 buf = spapr_phb_vfio_get_loc_code(sphb, pdev); 820 if (buf) { 821 return buf; 822 } 823 devtype = "vfio"; 824 } 825 /* 826 * For emulated devices and VFIO-failure case, make up 827 * the loc-code. 828 */ 829 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", 830 devtype, pdev->name, sphb->index, busnr, 831 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 832 return buf; 833 } 834 835 /* Macros to operate with address in OF binding to PCI */ 836 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) 837 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ 838 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ 839 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ 840 #define b_ss(x) b_x((x), 24, 2) /* the space code */ 841 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ 842 #define b_ddddd(x) b_x((x), 11, 5) /* device number */ 843 #define b_fff(x) b_x((x), 8, 3) /* function number */ 844 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ 845 846 /* for 'reg'/'assigned-addresses' OF properties */ 847 #define RESOURCE_CELLS_SIZE 2 848 #define RESOURCE_CELLS_ADDRESS 3 849 850 typedef struct ResourceFields { 851 uint32_t phys_hi; 852 uint32_t phys_mid; 853 uint32_t phys_lo; 854 uint32_t size_hi; 855 uint32_t size_lo; 856 } QEMU_PACKED ResourceFields; 857 858 typedef struct ResourceProps { 859 ResourceFields reg[8]; 860 ResourceFields assigned[7]; 861 uint32_t reg_len; 862 uint32_t assigned_len; 863 } ResourceProps; 864 865 /* fill in the 'reg'/'assigned-resources' OF properties for 866 * a PCI device. 'reg' describes resource requirements for a 867 * device's IO/MEM regions, 'assigned-addresses' describes the 868 * actual resource assignments. 869 * 870 * the properties are arrays of ('phys-addr', 'size') pairs describing 871 * the addressable regions of the PCI device, where 'phys-addr' is a 872 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to 873 * (phys.hi, phys.mid, phys.lo), and 'size' is a 874 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). 875 * 876 * phys.hi = 0xYYXXXXZZ, where: 877 * 0xYY = npt000ss 878 * ||| | 879 * ||| +-- space code 880 * ||| | 881 * ||| + 00 if configuration space 882 * ||| + 01 if IO region, 883 * ||| + 10 if 32-bit MEM region 884 * ||| + 11 if 64-bit MEM region 885 * ||| 886 * ||+------ for non-relocatable IO: 1 if aliased 887 * || for relocatable IO: 1 if below 64KB 888 * || for MEM: 1 if below 1MB 889 * |+------- 1 if region is prefetchable 890 * +-------- 1 if region is non-relocatable 891 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function 892 * bits respectively 893 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding 894 * to the region 895 * 896 * phys.mid and phys.lo correspond respectively to the hi/lo portions 897 * of the actual address of the region. 898 * 899 * how the phys-addr/size values are used differ slightly between 900 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has 901 * an additional description for the config space region of the 902 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0 903 * to describe the region as relocatable, with an address-mapping 904 * that corresponds directly to the PHB's address space for the 905 * resource. 'assigned-addresses' always has n=1 set with an absolute 906 * address assigned for the resource. in general, 'assigned-addresses' 907 * won't be populated, since addresses for PCI devices are generally 908 * unmapped initially and left to the guest to assign. 909 * 910 * note also that addresses defined in these properties are, at least 911 * for PAPR guests, relative to the PHBs IO/MEM windows, and 912 * correspond directly to the addresses in the BARs. 913 * 914 * in accordance with PCI Bus Binding to Open Firmware, 915 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, 916 * Appendix C. 917 */ 918 static void populate_resource_props(PCIDevice *d, ResourceProps *rp) 919 { 920 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); 921 uint32_t dev_id = (b_bbbbbbbb(bus_num) | 922 b_ddddd(PCI_SLOT(d->devfn)) | 923 b_fff(PCI_FUNC(d->devfn))); 924 ResourceFields *reg, *assigned; 925 int i, reg_idx = 0, assigned_idx = 0; 926 927 /* config space region */ 928 reg = &rp->reg[reg_idx++]; 929 reg->phys_hi = cpu_to_be32(dev_id); 930 reg->phys_mid = 0; 931 reg->phys_lo = 0; 932 reg->size_hi = 0; 933 reg->size_lo = 0; 934 935 for (i = 0; i < PCI_NUM_REGIONS; i++) { 936 if (!d->io_regions[i].size) { 937 continue; 938 } 939 940 reg = &rp->reg[reg_idx++]; 941 942 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); 943 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 944 reg->phys_hi |= cpu_to_be32(b_ss(1)); 945 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 946 reg->phys_hi |= cpu_to_be32(b_ss(3)); 947 } else { 948 reg->phys_hi |= cpu_to_be32(b_ss(2)); 949 } 950 reg->phys_mid = 0; 951 reg->phys_lo = 0; 952 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); 953 reg->size_lo = cpu_to_be32(d->io_regions[i].size); 954 955 if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) { 956 continue; 957 } 958 959 assigned = &rp->assigned[assigned_idx++]; 960 assigned->phys_hi = cpu_to_be32(be32_to_cpu(reg->phys_hi) | b_n(1)); 961 assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32); 962 assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr); 963 assigned->size_hi = reg->size_hi; 964 assigned->size_lo = reg->size_lo; 965 } 966 967 rp->reg_len = reg_idx * sizeof(ResourceFields); 968 rp->assigned_len = assigned_idx * sizeof(ResourceFields); 969 } 970 971 typedef struct PCIClass PCIClass; 972 typedef struct PCISubClass PCISubClass; 973 typedef struct PCIIFace PCIIFace; 974 975 struct PCIIFace { 976 int iface; 977 const char *name; 978 }; 979 980 struct PCISubClass { 981 int subclass; 982 const char *name; 983 const PCIIFace *iface; 984 }; 985 986 struct PCIClass { 987 const char *name; 988 const PCISubClass *subc; 989 }; 990 991 static const PCISubClass undef_subclass[] = { 992 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL }, 993 { 0xFF, NULL, NULL }, 994 }; 995 996 static const PCISubClass mass_subclass[] = { 997 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL }, 998 { PCI_CLASS_STORAGE_IDE, "ide", NULL }, 999 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL }, 1000 { PCI_CLASS_STORAGE_IPI, "ipi", NULL }, 1001 { PCI_CLASS_STORAGE_RAID, "raid", NULL }, 1002 { PCI_CLASS_STORAGE_ATA, "ata", NULL }, 1003 { PCI_CLASS_STORAGE_SATA, "sata", NULL }, 1004 { PCI_CLASS_STORAGE_SAS, "sas", NULL }, 1005 { 0xFF, NULL, NULL }, 1006 }; 1007 1008 static const PCISubClass net_subclass[] = { 1009 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL }, 1010 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL }, 1011 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL }, 1012 { PCI_CLASS_NETWORK_ATM, "atm", NULL }, 1013 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL }, 1014 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL }, 1015 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL }, 1016 { 0xFF, NULL, NULL }, 1017 }; 1018 1019 static const PCISubClass displ_subclass[] = { 1020 { PCI_CLASS_DISPLAY_VGA, "vga", NULL }, 1021 { PCI_CLASS_DISPLAY_XGA, "xga", NULL }, 1022 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL }, 1023 { 0xFF, NULL, NULL }, 1024 }; 1025 1026 static const PCISubClass media_subclass[] = { 1027 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL }, 1028 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL }, 1029 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL }, 1030 { 0xFF, NULL, NULL }, 1031 }; 1032 1033 static const PCISubClass mem_subclass[] = { 1034 { PCI_CLASS_MEMORY_RAM, "memory", NULL }, 1035 { PCI_CLASS_MEMORY_FLASH, "flash", NULL }, 1036 { 0xFF, NULL, NULL }, 1037 }; 1038 1039 static const PCISubClass bridg_subclass[] = { 1040 { PCI_CLASS_BRIDGE_HOST, "host", NULL }, 1041 { PCI_CLASS_BRIDGE_ISA, "isa", NULL }, 1042 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL }, 1043 { PCI_CLASS_BRIDGE_MC, "mca", NULL }, 1044 { PCI_CLASS_BRIDGE_PCI, "pci", NULL }, 1045 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL }, 1046 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL }, 1047 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL }, 1048 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL }, 1049 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL }, 1050 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL }, 1051 { 0xFF, NULL, NULL }, 1052 }; 1053 1054 static const PCISubClass comm_subclass[] = { 1055 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL }, 1056 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL }, 1057 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL }, 1058 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL }, 1059 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL }, 1060 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL }, 1061 { 0xFF, NULL, NULL, }, 1062 }; 1063 1064 static const PCIIFace pic_iface[] = { 1065 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" }, 1066 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" }, 1067 { 0xFF, NULL }, 1068 }; 1069 1070 static const PCISubClass sys_subclass[] = { 1071 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface }, 1072 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL }, 1073 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL }, 1074 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL }, 1075 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL }, 1076 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL }, 1077 { 0xFF, NULL, NULL }, 1078 }; 1079 1080 static const PCISubClass inp_subclass[] = { 1081 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL }, 1082 { PCI_CLASS_INPUT_PEN, "pen", NULL }, 1083 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL }, 1084 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL }, 1085 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL }, 1086 { 0xFF, NULL, NULL }, 1087 }; 1088 1089 static const PCISubClass dock_subclass[] = { 1090 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL }, 1091 { 0xFF, NULL, NULL }, 1092 }; 1093 1094 static const PCISubClass cpu_subclass[] = { 1095 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL }, 1096 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL }, 1097 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL }, 1098 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL }, 1099 { 0xFF, NULL, NULL }, 1100 }; 1101 1102 static const PCIIFace usb_iface[] = { 1103 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" }, 1104 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", }, 1105 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" }, 1106 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" }, 1107 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" }, 1108 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" }, 1109 { 0xFF, NULL }, 1110 }; 1111 1112 static const PCISubClass ser_subclass[] = { 1113 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL }, 1114 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL }, 1115 { PCI_CLASS_SERIAL_SSA, "ssa", NULL }, 1116 { PCI_CLASS_SERIAL_USB, "usb", usb_iface }, 1117 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL }, 1118 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL }, 1119 { PCI_CLASS_SERIAL_IB, "infiniband", NULL }, 1120 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL }, 1121 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL }, 1122 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL }, 1123 { 0xFF, NULL, NULL }, 1124 }; 1125 1126 static const PCISubClass wrl_subclass[] = { 1127 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL }, 1128 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL }, 1129 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL }, 1130 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL }, 1131 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL }, 1132 { 0xFF, NULL, NULL }, 1133 }; 1134 1135 static const PCISubClass sat_subclass[] = { 1136 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL }, 1137 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL }, 1138 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL }, 1139 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL }, 1140 { 0xFF, NULL, NULL }, 1141 }; 1142 1143 static const PCISubClass crypt_subclass[] = { 1144 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL }, 1145 { PCI_CLASS_CRYPT_ENTERTAINMENT, 1146 "entertainment-encryption", NULL }, 1147 { 0xFF, NULL, NULL }, 1148 }; 1149 1150 static const PCISubClass spc_subclass[] = { 1151 { PCI_CLASS_SP_DPIO, "dpio", NULL }, 1152 { PCI_CLASS_SP_PERF, "counter", NULL }, 1153 { PCI_CLASS_SP_SYNCH, "measurement", NULL }, 1154 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL }, 1155 { 0xFF, NULL, NULL }, 1156 }; 1157 1158 static const PCIClass pci_classes[] = { 1159 { "legacy-device", undef_subclass }, 1160 { "mass-storage", mass_subclass }, 1161 { "network", net_subclass }, 1162 { "display", displ_subclass, }, 1163 { "multimedia-device", media_subclass }, 1164 { "memory-controller", mem_subclass }, 1165 { "unknown-bridge", bridg_subclass }, 1166 { "communication-controller", comm_subclass}, 1167 { "system-peripheral", sys_subclass }, 1168 { "input-controller", inp_subclass }, 1169 { "docking-station", dock_subclass }, 1170 { "cpu", cpu_subclass }, 1171 { "serial-bus", ser_subclass }, 1172 { "wireless-controller", wrl_subclass }, 1173 { "intelligent-io", NULL }, 1174 { "satellite-device", sat_subclass }, 1175 { "encryption", crypt_subclass }, 1176 { "data-processing-controller", spc_subclass }, 1177 }; 1178 1179 static const char *dt_name_from_class(uint8_t class, uint8_t subclass, 1180 uint8_t iface) 1181 { 1182 const PCIClass *pclass; 1183 const PCISubClass *psubclass; 1184 const PCIIFace *piface; 1185 const char *name; 1186 1187 if (class >= ARRAY_SIZE(pci_classes)) { 1188 return "pci"; 1189 } 1190 1191 pclass = pci_classes + class; 1192 name = pclass->name; 1193 1194 if (pclass->subc == NULL) { 1195 return name; 1196 } 1197 1198 psubclass = pclass->subc; 1199 while ((psubclass->subclass & 0xff) != 0xff) { 1200 if ((psubclass->subclass & 0xff) == subclass) { 1201 name = psubclass->name; 1202 break; 1203 } 1204 psubclass++; 1205 } 1206 1207 piface = psubclass->iface; 1208 if (piface == NULL) { 1209 return name; 1210 } 1211 while ((piface->iface & 0xff) != 0xff) { 1212 if ((piface->iface & 0xff) == iface) { 1213 name = piface->name; 1214 break; 1215 } 1216 piface++; 1217 } 1218 1219 return name; 1220 } 1221 1222 /* 1223 * DRC helper functions 1224 */ 1225 1226 static uint32_t drc_id_from_devfn(SpaprPhbState *phb, 1227 uint8_t chassis, int32_t devfn) 1228 { 1229 return (phb->index << 16) | (chassis << 8) | devfn; 1230 } 1231 1232 static SpaprDrc *drc_from_devfn(SpaprPhbState *phb, 1233 uint8_t chassis, int32_t devfn) 1234 { 1235 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI, 1236 drc_id_from_devfn(phb, chassis, devfn)); 1237 } 1238 1239 static uint8_t chassis_from_bus(PCIBus *bus, Error **errp) 1240 { 1241 if (pci_bus_is_root(bus)) { 1242 return 0; 1243 } else { 1244 PCIDevice *bridge = pci_bridge_get_device(bus); 1245 1246 return object_property_get_uint(OBJECT(bridge), "chassis_nr", errp); 1247 } 1248 } 1249 1250 static SpaprDrc *drc_from_dev(SpaprPhbState *phb, PCIDevice *dev) 1251 { 1252 Error *local_err = NULL; 1253 uint8_t chassis = chassis_from_bus(pci_get_bus(dev), &local_err); 1254 1255 if (local_err) { 1256 error_report_err(local_err); 1257 return NULL; 1258 } 1259 1260 return drc_from_devfn(phb, chassis, dev->devfn); 1261 } 1262 1263 static void add_drcs(SpaprPhbState *phb, PCIBus *bus, Error **errp) 1264 { 1265 Object *owner; 1266 int i; 1267 uint8_t chassis; 1268 Error *local_err = NULL; 1269 1270 if (!phb->dr_enabled) { 1271 return; 1272 } 1273 1274 chassis = chassis_from_bus(bus, &local_err); 1275 if (local_err) { 1276 error_propagate(errp, local_err); 1277 return; 1278 } 1279 1280 if (pci_bus_is_root(bus)) { 1281 owner = OBJECT(phb); 1282 } else { 1283 owner = OBJECT(pci_bridge_get_device(bus)); 1284 } 1285 1286 for (i = 0; i < PCI_SLOT_MAX * PCI_FUNC_MAX; i++) { 1287 spapr_dr_connector_new(owner, TYPE_SPAPR_DRC_PCI, 1288 drc_id_from_devfn(phb, chassis, i)); 1289 } 1290 } 1291 1292 static void remove_drcs(SpaprPhbState *phb, PCIBus *bus, Error **errp) 1293 { 1294 int i; 1295 uint8_t chassis; 1296 Error *local_err = NULL; 1297 1298 if (!phb->dr_enabled) { 1299 return; 1300 } 1301 1302 chassis = chassis_from_bus(bus, &local_err); 1303 if (local_err) { 1304 error_propagate(errp, local_err); 1305 return; 1306 } 1307 1308 for (i = PCI_SLOT_MAX * PCI_FUNC_MAX - 1; i >= 0; i--) { 1309 SpaprDrc *drc = drc_from_devfn(phb, chassis, i); 1310 1311 if (drc) { 1312 object_unparent(OBJECT(drc)); 1313 } 1314 } 1315 } 1316 1317 typedef struct PciWalkFdt { 1318 void *fdt; 1319 int offset; 1320 SpaprPhbState *sphb; 1321 int err; 1322 } PciWalkFdt; 1323 1324 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev, 1325 void *fdt, int parent_offset); 1326 1327 static void spapr_dt_pci_device_cb(PCIBus *bus, PCIDevice *pdev, 1328 void *opaque) 1329 { 1330 PciWalkFdt *p = opaque; 1331 int err; 1332 1333 if (p->err) { 1334 /* Something's already broken, don't keep going */ 1335 return; 1336 } 1337 1338 err = spapr_dt_pci_device(p->sphb, pdev, p->fdt, p->offset); 1339 if (err < 0) { 1340 p->err = err; 1341 } 1342 } 1343 1344 /* Augment PCI device node with bridge specific information */ 1345 static int spapr_dt_pci_bus(SpaprPhbState *sphb, PCIBus *bus, 1346 void *fdt, int offset) 1347 { 1348 Object *owner; 1349 PciWalkFdt cbinfo = { 1350 .fdt = fdt, 1351 .offset = offset, 1352 .sphb = sphb, 1353 .err = 0, 1354 }; 1355 int ret; 1356 1357 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 1358 RESOURCE_CELLS_ADDRESS)); 1359 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1360 RESOURCE_CELLS_SIZE)); 1361 1362 assert(bus); 1363 pci_for_each_device_reverse(bus, pci_bus_num(bus), 1364 spapr_dt_pci_device_cb, &cbinfo); 1365 if (cbinfo.err) { 1366 return cbinfo.err; 1367 } 1368 1369 if (pci_bus_is_root(bus)) { 1370 owner = OBJECT(sphb); 1371 } else { 1372 owner = OBJECT(pci_bridge_get_device(bus)); 1373 } 1374 1375 ret = spapr_dt_drc(fdt, offset, owner, 1376 SPAPR_DR_CONNECTOR_TYPE_PCI); 1377 if (ret) { 1378 return ret; 1379 } 1380 1381 return offset; 1382 } 1383 1384 /* create OF node for pci device and required OF DT properties */ 1385 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev, 1386 void *fdt, int parent_offset) 1387 { 1388 int offset; 1389 const gchar *basename; 1390 gchar *nodename; 1391 int slot = PCI_SLOT(dev->devfn); 1392 int func = PCI_FUNC(dev->devfn); 1393 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1394 ResourceProps rp; 1395 SpaprDrc *drc = drc_from_dev(sphb, dev); 1396 uint32_t vendor_id = pci_default_read_config(dev, PCI_VENDOR_ID, 2); 1397 uint32_t device_id = pci_default_read_config(dev, PCI_DEVICE_ID, 2); 1398 uint32_t revision_id = pci_default_read_config(dev, PCI_REVISION_ID, 1); 1399 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); 1400 uint32_t irq_pin = pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1); 1401 uint32_t subsystem_id = pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2); 1402 uint32_t subsystem_vendor_id = 1403 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2); 1404 uint32_t cache_line_size = 1405 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1); 1406 uint32_t pci_status = pci_default_read_config(dev, PCI_STATUS, 2); 1407 gchar *loc_code; 1408 1409 basename = dt_name_from_class((ccode >> 16) & 0xff, (ccode >> 8) & 0xff, 1410 ccode & 0xff); 1411 1412 if (func != 0) { 1413 nodename = g_strdup_printf("%s@%x,%x", basename, slot, func); 1414 } else { 1415 nodename = g_strdup_printf("%s@%x", basename, slot); 1416 } 1417 1418 _FDT(offset = fdt_add_subnode(fdt, parent_offset, nodename)); 1419 1420 g_free(nodename); 1421 1422 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ 1423 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", vendor_id)); 1424 _FDT(fdt_setprop_cell(fdt, offset, "device-id", device_id)); 1425 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", revision_id)); 1426 1427 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode)); 1428 if (irq_pin) { 1429 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", irq_pin)); 1430 } 1431 1432 if (subsystem_id) { 1433 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", subsystem_id)); 1434 } 1435 1436 if (subsystem_vendor_id) { 1437 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", 1438 subsystem_vendor_id)); 1439 } 1440 1441 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", cache_line_size)); 1442 1443 1444 /* the following fdt cells are masked off the pci status register */ 1445 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", 1446 PCI_STATUS_DEVSEL_MASK & pci_status)); 1447 1448 if (pci_status & PCI_STATUS_FAST_BACK) { 1449 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); 1450 } 1451 if (pci_status & PCI_STATUS_66MHZ) { 1452 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); 1453 } 1454 if (pci_status & PCI_STATUS_UDF) { 1455 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); 1456 } 1457 1458 loc_code = spapr_phb_get_loc_code(sphb, dev); 1459 _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", loc_code)); 1460 g_free(loc_code); 1461 1462 if (drc) { 1463 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", 1464 spapr_drc_index(drc))); 1465 } 1466 1467 if (msi_present(dev)) { 1468 uint32_t max_msi = msi_nr_vectors_allocated(dev); 1469 if (max_msi) { 1470 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi)); 1471 } 1472 } 1473 if (msix_present(dev)) { 1474 uint32_t max_msix = dev->msix_entries_nr; 1475 if (max_msix) { 1476 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix)); 1477 } 1478 } 1479 1480 populate_resource_props(dev, &rp); 1481 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); 1482 _FDT(fdt_setprop(fdt, offset, "assigned-addresses", 1483 (uint8_t *)rp.assigned, rp.assigned_len)); 1484 1485 if (sphb->pcie_ecs && pci_is_express(dev)) { 1486 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1)); 1487 } 1488 1489 spapr_phb_nvgpu_populate_pcidev_dt(dev, fdt, offset, sphb); 1490 1491 if (!pc->is_bridge) { 1492 /* Properties only for non-bridges */ 1493 uint32_t min_grant = pci_default_read_config(dev, PCI_MIN_GNT, 1); 1494 uint32_t max_latency = pci_default_read_config(dev, PCI_MAX_LAT, 1); 1495 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", min_grant)); 1496 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", max_latency)); 1497 return offset; 1498 } else { 1499 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 1500 1501 return spapr_dt_pci_bus(sphb, sec_bus, fdt, offset); 1502 } 1503 } 1504 1505 /* Callback to be called during DRC release. */ 1506 void spapr_phb_remove_pci_device_cb(DeviceState *dev) 1507 { 1508 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 1509 1510 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 1511 object_unparent(OBJECT(dev)); 1512 } 1513 1514 int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 1515 void *fdt, int *fdt_start_offset, Error **errp) 1516 { 1517 HotplugHandler *plug_handler = qdev_get_hotplug_handler(drc->dev); 1518 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(plug_handler); 1519 PCIDevice *pdev = PCI_DEVICE(drc->dev); 1520 1521 *fdt_start_offset = spapr_dt_pci_device(sphb, pdev, fdt, 0); 1522 return 0; 1523 } 1524 1525 static void spapr_pci_bridge_plug(SpaprPhbState *phb, 1526 PCIBridge *bridge, 1527 Error **errp) 1528 { 1529 Error *local_err = NULL; 1530 PCIBus *bus = pci_bridge_get_sec_bus(bridge); 1531 1532 add_drcs(phb, bus, &local_err); 1533 if (local_err) { 1534 error_propagate(errp, local_err); 1535 return; 1536 } 1537 } 1538 1539 static void spapr_pci_plug(HotplugHandler *plug_handler, 1540 DeviceState *plugged_dev, Error **errp) 1541 { 1542 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1543 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1544 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1545 SpaprDrc *drc = drc_from_dev(phb, pdev); 1546 Error *local_err = NULL; 1547 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); 1548 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1549 1550 /* if DR is disabled we don't need to do anything in the case of 1551 * hotplug or coldplug callbacks 1552 */ 1553 if (!phb->dr_enabled) { 1554 /* if this is a hotplug operation initiated by the user 1555 * we need to let them know it's not enabled 1556 */ 1557 if (plugged_dev->hotplugged) { 1558 error_setg(&local_err, QERR_BUS_NO_HOTPLUG, 1559 object_get_typename(OBJECT(phb))); 1560 } 1561 goto out; 1562 } 1563 1564 g_assert(drc); 1565 1566 if (pc->is_bridge) { 1567 spapr_pci_bridge_plug(phb, PCI_BRIDGE(plugged_dev), &local_err); 1568 if (local_err) { 1569 error_propagate(errp, local_err); 1570 return; 1571 } 1572 } 1573 1574 /* Following the QEMU convention used for PCIe multifunction 1575 * hotplug, we do not allow functions to be hotplugged to a 1576 * slot that already has function 0 present 1577 */ 1578 if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] && 1579 PCI_FUNC(pdev->devfn) != 0) { 1580 error_setg(&local_err, "PCI: slot %d function 0 already ocuppied by %s," 1581 " additional functions can no longer be exposed to guest.", 1582 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name); 1583 goto out; 1584 } 1585 1586 spapr_drc_attach(drc, DEVICE(pdev), &local_err); 1587 if (local_err) { 1588 goto out; 1589 } 1590 1591 /* If this is function 0, signal hotplug for all the device functions. 1592 * Otherwise defer sending the hotplug event. 1593 */ 1594 if (!spapr_drc_hotplugged(plugged_dev)) { 1595 spapr_drc_reset(drc); 1596 } else if (PCI_FUNC(pdev->devfn) == 0) { 1597 int i; 1598 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev), &local_err); 1599 1600 if (local_err) { 1601 error_propagate(errp, local_err); 1602 return; 1603 } 1604 1605 for (i = 0; i < 8; i++) { 1606 SpaprDrc *func_drc; 1607 SpaprDrcClass *func_drck; 1608 SpaprDREntitySense state; 1609 1610 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1611 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1612 state = func_drck->dr_entity_sense(func_drc); 1613 1614 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { 1615 spapr_hotplug_req_add_by_index(func_drc); 1616 } 1617 } 1618 } 1619 1620 out: 1621 error_propagate(errp, local_err); 1622 } 1623 1624 static void spapr_pci_bridge_unplug(SpaprPhbState *phb, 1625 PCIBridge *bridge, 1626 Error **errp) 1627 { 1628 Error *local_err = NULL; 1629 PCIBus *bus = pci_bridge_get_sec_bus(bridge); 1630 1631 remove_drcs(phb, bus, &local_err); 1632 if (local_err) { 1633 error_propagate(errp, local_err); 1634 return; 1635 } 1636 } 1637 1638 static void spapr_pci_unplug(HotplugHandler *plug_handler, 1639 DeviceState *plugged_dev, Error **errp) 1640 { 1641 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1642 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1643 1644 /* some version guests do not wait for completion of a device 1645 * cleanup (generally done asynchronously by the kernel) before 1646 * signaling to QEMU that the device is safe, but instead sleep 1647 * for some 'safe' period of time. unfortunately on a busy host 1648 * this sleep isn't guaranteed to be long enough, resulting in 1649 * bad things like IRQ lines being left asserted during final 1650 * device removal. to deal with this we call reset just prior 1651 * to finalizing the device, which will put the device back into 1652 * an 'idle' state, as the device cleanup code expects. 1653 */ 1654 pci_device_reset(PCI_DEVICE(plugged_dev)); 1655 1656 if (pc->is_bridge) { 1657 Error *local_err = NULL; 1658 spapr_pci_bridge_unplug(phb, PCI_BRIDGE(plugged_dev), &local_err); 1659 if (local_err) { 1660 error_propagate(errp, local_err); 1661 } 1662 return; 1663 } 1664 1665 object_property_set_bool(OBJECT(plugged_dev), false, "realized", NULL); 1666 } 1667 1668 static void spapr_pci_unplug_request(HotplugHandler *plug_handler, 1669 DeviceState *plugged_dev, Error **errp) 1670 { 1671 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1672 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1673 SpaprDrc *drc = drc_from_dev(phb, pdev); 1674 1675 if (!phb->dr_enabled) { 1676 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1677 object_get_typename(OBJECT(phb))); 1678 return; 1679 } 1680 1681 g_assert(drc); 1682 g_assert(drc->dev == plugged_dev); 1683 1684 if (!spapr_drc_unplug_requested(drc)) { 1685 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1686 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1687 SpaprDrc *func_drc; 1688 SpaprDrcClass *func_drck; 1689 SpaprDREntitySense state; 1690 int i; 1691 Error *local_err = NULL; 1692 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev), &local_err); 1693 1694 if (local_err) { 1695 error_propagate(errp, local_err); 1696 return; 1697 } 1698 1699 if (pc->is_bridge) { 1700 error_setg(errp, "PCI: Hot unplug of PCI bridges not supported"); 1701 } 1702 1703 /* ensure any other present functions are pending unplug */ 1704 if (PCI_FUNC(pdev->devfn) == 0) { 1705 for (i = 1; i < 8; i++) { 1706 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1707 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1708 state = func_drck->dr_entity_sense(func_drc); 1709 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT 1710 && !spapr_drc_unplug_requested(func_drc)) { 1711 error_setg(errp, 1712 "PCI: slot %d, function %d still present. " 1713 "Must unplug all non-0 functions first.", 1714 slotnr, i); 1715 return; 1716 } 1717 } 1718 } 1719 1720 spapr_drc_detach(drc); 1721 1722 /* if this isn't func 0, defer unplug event. otherwise signal removal 1723 * for all present functions 1724 */ 1725 if (PCI_FUNC(pdev->devfn) == 0) { 1726 for (i = 7; i >= 0; i--) { 1727 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1728 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1729 state = func_drck->dr_entity_sense(func_drc); 1730 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { 1731 spapr_hotplug_req_remove_by_index(func_drc); 1732 } 1733 } 1734 } 1735 } 1736 } 1737 1738 static void spapr_phb_finalizefn(Object *obj) 1739 { 1740 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(obj); 1741 1742 g_free(sphb->dtbusname); 1743 sphb->dtbusname = NULL; 1744 } 1745 1746 static void spapr_phb_unrealize(DeviceState *dev, Error **errp) 1747 { 1748 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1749 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1750 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1751 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(phb); 1752 SpaprTceTable *tcet; 1753 int i; 1754 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 1755 Error *local_err = NULL; 1756 1757 spapr_phb_nvgpu_free(sphb); 1758 1759 if (sphb->msi) { 1760 g_hash_table_unref(sphb->msi); 1761 sphb->msi = NULL; 1762 } 1763 1764 /* 1765 * Remove IO/MMIO subregions and aliases, rest should get cleaned 1766 * via PHB's unrealize->object_finalize 1767 */ 1768 for (i = windows_supported - 1; i >= 0; i--) { 1769 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); 1770 if (tcet) { 1771 memory_region_del_subregion(&sphb->iommu_root, 1772 spapr_tce_get_iommu(tcet)); 1773 } 1774 } 1775 1776 remove_drcs(sphb, phb->bus, &local_err); 1777 if (local_err) { 1778 error_propagate(errp, local_err); 1779 return; 1780 } 1781 1782 for (i = PCI_NUM_PINS - 1; i >= 0; i--) { 1783 if (sphb->lsi_table[i].irq) { 1784 spapr_irq_free(spapr, sphb->lsi_table[i].irq, 1); 1785 sphb->lsi_table[i].irq = 0; 1786 } 1787 } 1788 1789 QLIST_REMOVE(sphb, list); 1790 1791 memory_region_del_subregion(&sphb->iommu_root, &sphb->msiwindow); 1792 1793 /* 1794 * An attached PCI device may have memory listeners, eg. VFIO PCI. We have 1795 * unmapped all sections. Remove the listeners now, before destroying the 1796 * address space. 1797 */ 1798 address_space_remove_listeners(&sphb->iommu_as); 1799 address_space_destroy(&sphb->iommu_as); 1800 1801 qbus_set_hotplug_handler(BUS(phb->bus), NULL, &error_abort); 1802 pci_unregister_root_bus(phb->bus); 1803 1804 memory_region_del_subregion(get_system_memory(), &sphb->iowindow); 1805 if (sphb->mem64_win_pciaddr != (hwaddr)-1) { 1806 memory_region_del_subregion(get_system_memory(), &sphb->mem64window); 1807 } 1808 memory_region_del_subregion(get_system_memory(), &sphb->mem32window); 1809 } 1810 1811 static void spapr_phb_realize(DeviceState *dev, Error **errp) 1812 { 1813 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 1814 * tries to add a sPAPR PHB to a non-pseries machine. 1815 */ 1816 SpaprMachineState *spapr = 1817 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), 1818 TYPE_SPAPR_MACHINE); 1819 SpaprMachineClass *smc = spapr ? SPAPR_MACHINE_GET_CLASS(spapr) : NULL; 1820 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1821 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(s); 1822 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1823 char *namebuf; 1824 int i; 1825 PCIBus *bus; 1826 uint64_t msi_window_size = 4096; 1827 SpaprTceTable *tcet; 1828 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 1829 Error *local_err = NULL; 1830 1831 if (!spapr) { 1832 error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine"); 1833 return; 1834 } 1835 1836 assert(sphb->index != (uint32_t)-1); /* checked in spapr_phb_pre_plug() */ 1837 1838 if (sphb->mem64_win_size != 0) { 1839 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { 1840 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx 1841 " (max 2 GiB)", sphb->mem_win_size); 1842 return; 1843 } 1844 1845 /* 64-bit window defaults to identity mapping */ 1846 sphb->mem64_win_pciaddr = sphb->mem64_win_addr; 1847 } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { 1848 /* 1849 * For compatibility with old configuration, if no 64-bit MMIO 1850 * window is specified, but the ordinary (32-bit) memory 1851 * window is specified as > 2GiB, we treat it as a 2GiB 32-bit 1852 * window, with a 64-bit MMIO window following on immediately 1853 * afterwards 1854 */ 1855 sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE; 1856 sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE; 1857 sphb->mem64_win_pciaddr = 1858 SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE; 1859 sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE; 1860 } 1861 1862 if (spapr_pci_find_phb(spapr, sphb->buid)) { 1863 SpaprPhbState *s; 1864 1865 error_setg(errp, "PCI host bridges must have unique indexes"); 1866 error_append_hint(errp, "The following indexes are already in use:"); 1867 QLIST_FOREACH(s, &spapr->phbs, list) { 1868 error_append_hint(errp, " %d", s->index); 1869 } 1870 error_append_hint(errp, "\nTry another value for the index property\n"); 1871 return; 1872 } 1873 1874 if (sphb->numa_node != -1 && 1875 (sphb->numa_node >= MAX_NODES || !numa_info[sphb->numa_node].present)) { 1876 error_setg(errp, "Invalid NUMA node ID for PCI host bridge"); 1877 return; 1878 } 1879 1880 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); 1881 1882 /* Initialize memory regions */ 1883 namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname); 1884 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); 1885 g_free(namebuf); 1886 1887 namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname); 1888 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb), 1889 namebuf, &sphb->memspace, 1890 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); 1891 g_free(namebuf); 1892 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, 1893 &sphb->mem32window); 1894 1895 if (sphb->mem64_win_size != 0) { 1896 namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname); 1897 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb), 1898 namebuf, &sphb->memspace, 1899 sphb->mem64_win_pciaddr, sphb->mem64_win_size); 1900 g_free(namebuf); 1901 1902 memory_region_add_subregion(get_system_memory(), 1903 sphb->mem64_win_addr, 1904 &sphb->mem64window); 1905 } 1906 1907 /* Initialize IO regions */ 1908 namebuf = g_strdup_printf("%s.io", sphb->dtbusname); 1909 memory_region_init(&sphb->iospace, OBJECT(sphb), 1910 namebuf, SPAPR_PCI_IO_WIN_SIZE); 1911 g_free(namebuf); 1912 1913 namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname); 1914 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, 1915 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); 1916 g_free(namebuf); 1917 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, 1918 &sphb->iowindow); 1919 1920 bus = pci_register_root_bus(dev, NULL, 1921 pci_spapr_set_irq, pci_swizzle_map_irq_fn, sphb, 1922 &sphb->memspace, &sphb->iospace, 1923 PCI_DEVFN(0, 0), PCI_NUM_PINS, 1924 TYPE_PCI_BUS); 1925 1926 /* 1927 * Despite resembling a vanilla PCI bus in most ways, the PAPR 1928 * para-virtualized PCI bus *does* permit PCI-E extended config 1929 * space access 1930 */ 1931 if (sphb->pcie_ecs) { 1932 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 1933 } 1934 phb->bus = bus; 1935 qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb), NULL); 1936 1937 /* 1938 * Initialize PHB address space. 1939 * By default there will be at least one subregion for default 1940 * 32bit DMA window. 1941 * Later the guest might want to create another DMA window 1942 * which will become another memory subregion. 1943 */ 1944 namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname); 1945 memory_region_init(&sphb->iommu_root, OBJECT(sphb), 1946 namebuf, UINT64_MAX); 1947 g_free(namebuf); 1948 address_space_init(&sphb->iommu_as, &sphb->iommu_root, 1949 sphb->dtbusname); 1950 1951 /* 1952 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, 1953 * we need to allocate some memory to catch those writes coming 1954 * from msi_notify()/msix_notify(). 1955 * As MSIMessage:addr is going to be the same and MSIMessage:data 1956 * is going to be a VIRQ number, 4 bytes of the MSI MR will only 1957 * be used. 1958 * 1959 * For KVM we want to ensure that this memory is a full page so that 1960 * our memory slot is of page size granularity. 1961 */ 1962 if (kvm_enabled()) { 1963 msi_window_size = getpagesize(); 1964 } 1965 1966 memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr, 1967 "msi", msi_window_size); 1968 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, 1969 &sphb->msiwindow); 1970 1971 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); 1972 1973 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); 1974 1975 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); 1976 1977 /* Initialize the LSI table */ 1978 for (i = 0; i < PCI_NUM_PINS; i++) { 1979 uint32_t irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i; 1980 1981 if (smc->legacy_irq_allocation) { 1982 irq = spapr_irq_findone(spapr, &local_err); 1983 if (local_err) { 1984 error_propagate_prepend(errp, local_err, 1985 "can't allocate LSIs: "); 1986 /* 1987 * Older machines will never support PHB hotplug, ie, this is an 1988 * init only path and QEMU will terminate. No need to rollback. 1989 */ 1990 return; 1991 } 1992 } 1993 1994 spapr_irq_claim(spapr, irq, true, &local_err); 1995 if (local_err) { 1996 error_propagate_prepend(errp, local_err, "can't allocate LSIs: "); 1997 goto unrealize; 1998 } 1999 2000 sphb->lsi_table[i].irq = irq; 2001 } 2002 2003 /* allocate connectors for child PCI devices */ 2004 add_drcs(sphb, phb->bus, &local_err); 2005 if (local_err) { 2006 error_propagate(errp, local_err); 2007 goto unrealize; 2008 } 2009 2010 /* DMA setup */ 2011 for (i = 0; i < windows_supported; ++i) { 2012 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]); 2013 if (!tcet) { 2014 error_setg(errp, "Creating window#%d failed for %s", 2015 i, sphb->dtbusname); 2016 goto unrealize; 2017 } 2018 memory_region_add_subregion(&sphb->iommu_root, 0, 2019 spapr_tce_get_iommu(tcet)); 2020 } 2021 2022 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); 2023 return; 2024 2025 unrealize: 2026 spapr_phb_unrealize(dev, NULL); 2027 } 2028 2029 static int spapr_phb_children_reset(Object *child, void *opaque) 2030 { 2031 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); 2032 2033 if (dev) { 2034 device_reset(dev); 2035 } 2036 2037 return 0; 2038 } 2039 2040 void spapr_phb_dma_reset(SpaprPhbState *sphb) 2041 { 2042 int i; 2043 SpaprTceTable *tcet; 2044 2045 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) { 2046 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); 2047 2048 if (tcet && tcet->nb_table) { 2049 spapr_tce_table_disable(tcet); 2050 } 2051 } 2052 2053 /* Register default 32bit DMA window */ 2054 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]); 2055 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr, 2056 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT); 2057 } 2058 2059 static void spapr_phb_reset(DeviceState *qdev) 2060 { 2061 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev); 2062 Error *errp = NULL; 2063 2064 spapr_phb_dma_reset(sphb); 2065 spapr_phb_nvgpu_free(sphb); 2066 spapr_phb_nvgpu_setup(sphb, &errp); 2067 if (errp) { 2068 error_report_err(errp); 2069 } 2070 2071 /* Reset the IOMMU state */ 2072 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); 2073 2074 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) { 2075 spapr_phb_vfio_reset(qdev); 2076 } 2077 } 2078 2079 static Property spapr_phb_properties[] = { 2080 DEFINE_PROP_UINT32("index", SpaprPhbState, index, -1), 2081 DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState, mem_win_size, 2082 SPAPR_PCI_MEM32_WIN_SIZE), 2083 DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState, mem64_win_size, 2084 SPAPR_PCI_MEM64_WIN_SIZE), 2085 DEFINE_PROP_UINT64("io_win_size", SpaprPhbState, io_win_size, 2086 SPAPR_PCI_IO_WIN_SIZE), 2087 DEFINE_PROP_BOOL("dynamic-reconfiguration", SpaprPhbState, dr_enabled, 2088 true), 2089 /* Default DMA window is 0..1GB */ 2090 DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState, dma_win_addr, 0), 2091 DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState, dma_win_size, 0x40000000), 2092 DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState, dma64_win_addr, 2093 0x800000000000000ULL), 2094 DEFINE_PROP_BOOL("ddw", SpaprPhbState, ddw_enabled, true), 2095 DEFINE_PROP_UINT64("pgsz", SpaprPhbState, page_size_mask, 2096 (1ULL << 12) | (1ULL << 16)), 2097 DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1), 2098 DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState, 2099 pre_2_8_migration, false), 2100 DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState, 2101 pcie_ecs, true), 2102 DEFINE_PROP_UINT64("gpa", SpaprPhbState, nv2_gpa_win_addr, 0), 2103 DEFINE_PROP_UINT64("atsd", SpaprPhbState, nv2_atsd_win_addr, 0), 2104 DEFINE_PROP_END_OF_LIST(), 2105 }; 2106 2107 static const VMStateDescription vmstate_spapr_pci_lsi = { 2108 .name = "spapr_pci/lsi", 2109 .version_id = 1, 2110 .minimum_version_id = 1, 2111 .fields = (VMStateField[]) { 2112 VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi, NULL), 2113 2114 VMSTATE_END_OF_LIST() 2115 }, 2116 }; 2117 2118 static const VMStateDescription vmstate_spapr_pci_msi = { 2119 .name = "spapr_pci/msi", 2120 .version_id = 1, 2121 .minimum_version_id = 1, 2122 .fields = (VMStateField []) { 2123 VMSTATE_UINT32(key, spapr_pci_msi_mig), 2124 VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig), 2125 VMSTATE_UINT32(value.num, spapr_pci_msi_mig), 2126 VMSTATE_END_OF_LIST() 2127 }, 2128 }; 2129 2130 static int spapr_pci_pre_save(void *opaque) 2131 { 2132 SpaprPhbState *sphb = opaque; 2133 GHashTableIter iter; 2134 gpointer key, value; 2135 int i; 2136 2137 if (sphb->pre_2_8_migration) { 2138 sphb->mig_liobn = sphb->dma_liobn[0]; 2139 sphb->mig_mem_win_addr = sphb->mem_win_addr; 2140 sphb->mig_mem_win_size = sphb->mem_win_size; 2141 sphb->mig_io_win_addr = sphb->io_win_addr; 2142 sphb->mig_io_win_size = sphb->io_win_size; 2143 2144 if ((sphb->mem64_win_size != 0) 2145 && (sphb->mem64_win_addr 2146 == (sphb->mem_win_addr + sphb->mem_win_size))) { 2147 sphb->mig_mem_win_size += sphb->mem64_win_size; 2148 } 2149 } 2150 2151 g_free(sphb->msi_devs); 2152 sphb->msi_devs = NULL; 2153 sphb->msi_devs_num = g_hash_table_size(sphb->msi); 2154 if (!sphb->msi_devs_num) { 2155 return 0; 2156 } 2157 sphb->msi_devs = g_new(spapr_pci_msi_mig, sphb->msi_devs_num); 2158 2159 g_hash_table_iter_init(&iter, sphb->msi); 2160 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { 2161 sphb->msi_devs[i].key = *(uint32_t *) key; 2162 sphb->msi_devs[i].value = *(spapr_pci_msi *) value; 2163 } 2164 2165 return 0; 2166 } 2167 2168 static int spapr_pci_post_load(void *opaque, int version_id) 2169 { 2170 SpaprPhbState *sphb = opaque; 2171 gpointer key, value; 2172 int i; 2173 2174 for (i = 0; i < sphb->msi_devs_num; ++i) { 2175 key = g_memdup(&sphb->msi_devs[i].key, 2176 sizeof(sphb->msi_devs[i].key)); 2177 value = g_memdup(&sphb->msi_devs[i].value, 2178 sizeof(sphb->msi_devs[i].value)); 2179 g_hash_table_insert(sphb->msi, key, value); 2180 } 2181 g_free(sphb->msi_devs); 2182 sphb->msi_devs = NULL; 2183 sphb->msi_devs_num = 0; 2184 2185 return 0; 2186 } 2187 2188 static bool pre_2_8_migration(void *opaque, int version_id) 2189 { 2190 SpaprPhbState *sphb = opaque; 2191 2192 return sphb->pre_2_8_migration; 2193 } 2194 2195 static const VMStateDescription vmstate_spapr_pci = { 2196 .name = "spapr_pci", 2197 .version_id = 2, 2198 .minimum_version_id = 2, 2199 .pre_save = spapr_pci_pre_save, 2200 .post_load = spapr_pci_post_load, 2201 .fields = (VMStateField[]) { 2202 VMSTATE_UINT64_EQUAL(buid, SpaprPhbState, NULL), 2203 VMSTATE_UINT32_TEST(mig_liobn, SpaprPhbState, pre_2_8_migration), 2204 VMSTATE_UINT64_TEST(mig_mem_win_addr, SpaprPhbState, pre_2_8_migration), 2205 VMSTATE_UINT64_TEST(mig_mem_win_size, SpaprPhbState, pre_2_8_migration), 2206 VMSTATE_UINT64_TEST(mig_io_win_addr, SpaprPhbState, pre_2_8_migration), 2207 VMSTATE_UINT64_TEST(mig_io_win_size, SpaprPhbState, pre_2_8_migration), 2208 VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0, 2209 vmstate_spapr_pci_lsi, struct spapr_pci_lsi), 2210 VMSTATE_INT32(msi_devs_num, SpaprPhbState), 2211 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, SpaprPhbState, msi_devs_num, 0, 2212 vmstate_spapr_pci_msi, spapr_pci_msi_mig), 2213 VMSTATE_END_OF_LIST() 2214 }, 2215 }; 2216 2217 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, 2218 PCIBus *rootbus) 2219 { 2220 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); 2221 2222 return sphb->dtbusname; 2223 } 2224 2225 static void spapr_phb_class_init(ObjectClass *klass, void *data) 2226 { 2227 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 2228 DeviceClass *dc = DEVICE_CLASS(klass); 2229 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); 2230 2231 hc->root_bus_path = spapr_phb_root_bus_path; 2232 dc->realize = spapr_phb_realize; 2233 dc->unrealize = spapr_phb_unrealize; 2234 dc->props = spapr_phb_properties; 2235 dc->reset = spapr_phb_reset; 2236 dc->vmsd = &vmstate_spapr_pci; 2237 /* Supported by TYPE_SPAPR_MACHINE */ 2238 dc->user_creatable = true; 2239 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 2240 hp->plug = spapr_pci_plug; 2241 hp->unplug = spapr_pci_unplug; 2242 hp->unplug_request = spapr_pci_unplug_request; 2243 } 2244 2245 static const TypeInfo spapr_phb_info = { 2246 .name = TYPE_SPAPR_PCI_HOST_BRIDGE, 2247 .parent = TYPE_PCI_HOST_BRIDGE, 2248 .instance_size = sizeof(SpaprPhbState), 2249 .instance_finalize = spapr_phb_finalizefn, 2250 .class_init = spapr_phb_class_init, 2251 .interfaces = (InterfaceInfo[]) { 2252 { TYPE_HOTPLUG_HANDLER }, 2253 { } 2254 } 2255 }; 2256 2257 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, 2258 void *opaque) 2259 { 2260 unsigned int *bus_no = opaque; 2261 PCIBus *sec_bus = NULL; 2262 2263 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 2264 PCI_HEADER_TYPE_BRIDGE)) { 2265 return; 2266 } 2267 2268 (*bus_no)++; 2269 pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1); 2270 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); 2271 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 2272 2273 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 2274 if (!sec_bus) { 2275 return; 2276 } 2277 2278 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 2279 spapr_phb_pci_enumerate_bridge, bus_no); 2280 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 2281 } 2282 2283 static void spapr_phb_pci_enumerate(SpaprPhbState *phb) 2284 { 2285 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 2286 unsigned int bus_no = 0; 2287 2288 pci_for_each_device(bus, pci_bus_num(bus), 2289 spapr_phb_pci_enumerate_bridge, 2290 &bus_no); 2291 2292 } 2293 2294 int spapr_dt_phb(SpaprPhbState *phb, uint32_t intc_phandle, void *fdt, 2295 uint32_t nr_msis, int *node_offset) 2296 { 2297 int bus_off, i, j, ret; 2298 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; 2299 struct { 2300 uint32_t hi; 2301 uint64_t child; 2302 uint64_t parent; 2303 uint64_t size; 2304 } QEMU_PACKED ranges[] = { 2305 { 2306 cpu_to_be32(b_ss(1)), cpu_to_be64(0), 2307 cpu_to_be64(phb->io_win_addr), 2308 cpu_to_be64(memory_region_size(&phb->iospace)), 2309 }, 2310 { 2311 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), 2312 cpu_to_be64(phb->mem_win_addr), 2313 cpu_to_be64(phb->mem_win_size), 2314 }, 2315 { 2316 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr), 2317 cpu_to_be64(phb->mem64_win_addr), 2318 cpu_to_be64(phb->mem64_win_size), 2319 }, 2320 }; 2321 const unsigned sizeof_ranges = 2322 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]); 2323 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; 2324 uint32_t interrupt_map_mask[] = { 2325 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; 2326 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; 2327 uint32_t ddw_applicable[] = { 2328 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW), 2329 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW), 2330 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW) 2331 }; 2332 uint32_t ddw_extensions[] = { 2333 cpu_to_be32(1), 2334 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW) 2335 }; 2336 uint32_t associativity[] = {cpu_to_be32(0x4), 2337 cpu_to_be32(0x0), 2338 cpu_to_be32(0x0), 2339 cpu_to_be32(0x0), 2340 cpu_to_be32(phb->numa_node)}; 2341 SpaprTceTable *tcet; 2342 SpaprDrc *drc; 2343 Error *errp = NULL; 2344 2345 /* Start populating the FDT */ 2346 _FDT(bus_off = fdt_add_subnode(fdt, 0, phb->dtbusname)); 2347 if (node_offset) { 2348 *node_offset = bus_off; 2349 } 2350 2351 /* Write PHB properties */ 2352 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); 2353 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); 2354 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); 2355 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); 2356 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); 2357 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); 2358 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); 2359 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); 2360 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", nr_msis)); 2361 2362 /* Dynamic DMA window */ 2363 if (phb->ddw_enabled) { 2364 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable, 2365 sizeof(ddw_applicable))); 2366 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions", 2367 &ddw_extensions, sizeof(ddw_extensions))); 2368 } 2369 2370 /* Advertise NUMA via ibm,associativity */ 2371 if (phb->numa_node != -1) { 2372 _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity, 2373 sizeof(associativity))); 2374 } 2375 2376 /* Build the interrupt-map, this must matches what is done 2377 * in pci_swizzle_map_irq_fn 2378 */ 2379 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", 2380 &interrupt_map_mask, sizeof(interrupt_map_mask))); 2381 for (i = 0; i < PCI_SLOT_MAX; i++) { 2382 for (j = 0; j < PCI_NUM_PINS; j++) { 2383 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; 2384 int lsi_num = pci_swizzle(i, j); 2385 2386 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); 2387 irqmap[1] = 0; 2388 irqmap[2] = 0; 2389 irqmap[3] = cpu_to_be32(j+1); 2390 irqmap[4] = cpu_to_be32(intc_phandle); 2391 spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true); 2392 } 2393 } 2394 /* Write interrupt map */ 2395 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, 2396 sizeof(interrupt_map))); 2397 2398 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]); 2399 if (!tcet) { 2400 return -1; 2401 } 2402 spapr_dma_dt(fdt, bus_off, "ibm,dma-window", 2403 tcet->liobn, tcet->bus_offset, 2404 tcet->nb_table << tcet->page_shift); 2405 2406 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, phb->index); 2407 if (drc) { 2408 uint32_t drc_index = cpu_to_be32(spapr_drc_index(drc)); 2409 2410 _FDT(fdt_setprop(fdt, bus_off, "ibm,my-drc-index", &drc_index, 2411 sizeof(drc_index))); 2412 } 2413 2414 /* Walk the bridges and program the bus numbers*/ 2415 spapr_phb_pci_enumerate(phb); 2416 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); 2417 2418 /* Walk the bridge and subordinate buses */ 2419 ret = spapr_dt_pci_bus(phb, PCI_HOST_BRIDGE(phb)->bus, fdt, bus_off); 2420 if (ret < 0) { 2421 return ret; 2422 } 2423 2424 spapr_phb_nvgpu_populate_dt(phb, fdt, bus_off, &errp); 2425 if (errp) { 2426 error_report_err(errp); 2427 } 2428 spapr_phb_nvgpu_ram_populate_dt(phb, fdt); 2429 2430 return 0; 2431 } 2432 2433 void spapr_pci_rtas_init(void) 2434 { 2435 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", 2436 rtas_read_pci_config); 2437 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", 2438 rtas_write_pci_config); 2439 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", 2440 rtas_ibm_read_pci_config); 2441 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", 2442 rtas_ibm_write_pci_config); 2443 if (msi_nonbroken) { 2444 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, 2445 "ibm,query-interrupt-source-number", 2446 rtas_ibm_query_interrupt_source_number); 2447 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", 2448 rtas_ibm_change_msi); 2449 } 2450 2451 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, 2452 "ibm,set-eeh-option", 2453 rtas_ibm_set_eeh_option); 2454 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, 2455 "ibm,get-config-addr-info2", 2456 rtas_ibm_get_config_addr_info2); 2457 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, 2458 "ibm,read-slot-reset-state2", 2459 rtas_ibm_read_slot_reset_state2); 2460 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, 2461 "ibm,set-slot-reset", 2462 rtas_ibm_set_slot_reset); 2463 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, 2464 "ibm,configure-pe", 2465 rtas_ibm_configure_pe); 2466 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, 2467 "ibm,slot-error-detail", 2468 rtas_ibm_slot_error_detail); 2469 } 2470 2471 static void spapr_pci_register_types(void) 2472 { 2473 type_register_static(&spapr_phb_info); 2474 } 2475 2476 type_init(spapr_pci_register_types) 2477 2478 static int spapr_switch_one_vga(DeviceState *dev, void *opaque) 2479 { 2480 bool be = *(bool *)opaque; 2481 2482 if (object_dynamic_cast(OBJECT(dev), "VGA") 2483 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { 2484 object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", 2485 &error_abort); 2486 } 2487 return 0; 2488 } 2489 2490 void spapr_pci_switch_vga(bool big_endian) 2491 { 2492 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 2493 SpaprPhbState *sphb; 2494 2495 /* 2496 * For backward compatibility with existing guests, we switch 2497 * the endianness of the VGA controller when changing the guest 2498 * interrupt mode 2499 */ 2500 QLIST_FOREACH(sphb, &spapr->phbs, list) { 2501 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; 2502 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, 2503 &big_endian); 2504 } 2505 } 2506