1 /* 2 * QEMU sPAPR PCI host originated from Uninorth PCI host 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. 5 * Copyright (C) 2011 David Gibson, IBM Corporation. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "cpu.h" 29 #include "hw/irq.h" 30 #include "hw/sysbus.h" 31 #include "migration/vmstate.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/msi.h" 34 #include "hw/pci/msix.h" 35 #include "hw/pci/pci_host.h" 36 #include "hw/ppc/spapr.h" 37 #include "hw/pci-host/spapr.h" 38 #include "exec/address-spaces.h" 39 #include "exec/ram_addr.h" 40 #include <libfdt.h> 41 #include "trace.h" 42 #include "qemu/error-report.h" 43 #include "qemu/module.h" 44 #include "qapi/qmp/qerror.h" 45 #include "hw/ppc/fdt.h" 46 #include "hw/pci/pci_bridge.h" 47 #include "hw/pci/pci_bus.h" 48 #include "hw/pci/pci_ids.h" 49 #include "hw/ppc/spapr_drc.h" 50 #include "hw/qdev-properties.h" 51 #include "sysemu/device_tree.h" 52 #include "sysemu/kvm.h" 53 #include "sysemu/hostmem.h" 54 #include "sysemu/numa.h" 55 #include "hw/ppc/spapr_numa.h" 56 #include "qemu/log.h" 57 58 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ 59 #define RTAS_QUERY_FN 0 60 #define RTAS_CHANGE_FN 1 61 #define RTAS_RESET_FN 2 62 #define RTAS_CHANGE_MSI_FN 3 63 #define RTAS_CHANGE_MSIX_FN 4 64 65 /* Interrupt types to return on RTAS_CHANGE_* */ 66 #define RTAS_TYPE_MSI 1 67 #define RTAS_TYPE_MSIX 2 68 69 SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid) 70 { 71 SpaprPhbState *sphb; 72 73 QLIST_FOREACH(sphb, &spapr->phbs, list) { 74 if (sphb->buid != buid) { 75 continue; 76 } 77 return sphb; 78 } 79 80 return NULL; 81 } 82 83 PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid, 84 uint32_t config_addr) 85 { 86 SpaprPhbState *sphb = spapr_pci_find_phb(spapr, buid); 87 PCIHostState *phb = PCI_HOST_BRIDGE(sphb); 88 int bus_num = (config_addr >> 16) & 0xFF; 89 int devfn = (config_addr >> 8) & 0xFF; 90 91 if (!phb) { 92 return NULL; 93 } 94 95 return pci_find_device(phb->bus, bus_num, devfn); 96 } 97 98 static uint32_t rtas_pci_cfgaddr(uint32_t arg) 99 { 100 /* This handles the encoding of extended config space addresses */ 101 return ((arg >> 20) & 0xf00) | (arg & 0xff); 102 } 103 104 static void finish_read_pci_config(SpaprMachineState *spapr, uint64_t buid, 105 uint32_t addr, uint32_t size, 106 target_ulong rets) 107 { 108 PCIDevice *pci_dev; 109 uint32_t val; 110 111 if ((size != 1) && (size != 2) && (size != 4)) { 112 /* access must be 1, 2 or 4 bytes */ 113 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 114 return; 115 } 116 117 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 118 addr = rtas_pci_cfgaddr(addr); 119 120 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 121 /* Access must be to a valid device, within bounds and 122 * naturally aligned */ 123 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 124 return; 125 } 126 127 val = pci_host_config_read_common(pci_dev, addr, 128 pci_config_size(pci_dev), size); 129 130 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 131 rtas_st(rets, 1, val); 132 } 133 134 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 135 uint32_t token, uint32_t nargs, 136 target_ulong args, 137 uint32_t nret, target_ulong rets) 138 { 139 uint64_t buid; 140 uint32_t size, addr; 141 142 if ((nargs != 4) || (nret != 2)) { 143 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 144 return; 145 } 146 147 buid = rtas_ldq(args, 1); 148 size = rtas_ld(args, 3); 149 addr = rtas_ld(args, 0); 150 151 finish_read_pci_config(spapr, buid, addr, size, rets); 152 } 153 154 static void rtas_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 155 uint32_t token, uint32_t nargs, 156 target_ulong args, 157 uint32_t nret, target_ulong rets) 158 { 159 uint32_t size, addr; 160 161 if ((nargs != 2) || (nret != 2)) { 162 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 163 return; 164 } 165 166 size = rtas_ld(args, 1); 167 addr = rtas_ld(args, 0); 168 169 finish_read_pci_config(spapr, 0, addr, size, rets); 170 } 171 172 static void finish_write_pci_config(SpaprMachineState *spapr, uint64_t buid, 173 uint32_t addr, uint32_t size, 174 uint32_t val, target_ulong rets) 175 { 176 PCIDevice *pci_dev; 177 178 if ((size != 1) && (size != 2) && (size != 4)) { 179 /* access must be 1, 2 or 4 bytes */ 180 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 181 return; 182 } 183 184 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 185 addr = rtas_pci_cfgaddr(addr); 186 187 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 188 /* Access must be to a valid device, within bounds and 189 * naturally aligned */ 190 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 191 return; 192 } 193 194 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), 195 val, size); 196 197 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 198 } 199 200 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 201 uint32_t token, uint32_t nargs, 202 target_ulong args, 203 uint32_t nret, target_ulong rets) 204 { 205 uint64_t buid; 206 uint32_t val, size, addr; 207 208 if ((nargs != 5) || (nret != 1)) { 209 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 210 return; 211 } 212 213 buid = rtas_ldq(args, 1); 214 val = rtas_ld(args, 4); 215 size = rtas_ld(args, 3); 216 addr = rtas_ld(args, 0); 217 218 finish_write_pci_config(spapr, buid, addr, size, val, rets); 219 } 220 221 static void rtas_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 222 uint32_t token, uint32_t nargs, 223 target_ulong args, 224 uint32_t nret, target_ulong rets) 225 { 226 uint32_t val, size, addr; 227 228 if ((nargs != 3) || (nret != 1)) { 229 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 230 return; 231 } 232 233 234 val = rtas_ld(args, 2); 235 size = rtas_ld(args, 1); 236 addr = rtas_ld(args, 0); 237 238 finish_write_pci_config(spapr, 0, addr, size, val, rets); 239 } 240 241 /* 242 * Set MSI/MSIX message data. 243 * This is required for msi_notify()/msix_notify() which 244 * will write at the addresses via spapr_msi_write(). 245 * 246 * If hwaddr == 0, all entries will have .data == first_irq i.e. 247 * table will be reset. 248 */ 249 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, 250 unsigned first_irq, unsigned req_num) 251 { 252 unsigned i; 253 MSIMessage msg = { .address = addr, .data = first_irq }; 254 255 if (!msix) { 256 msi_set_message(pdev, msg); 257 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); 258 return; 259 } 260 261 for (i = 0; i < req_num; ++i) { 262 msix_set_message(pdev, i, msg); 263 trace_spapr_pci_msi_setup(pdev->name, i, msg.address); 264 if (addr) { 265 ++msg.data; 266 } 267 } 268 } 269 270 static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr, 271 uint32_t token, uint32_t nargs, 272 target_ulong args, uint32_t nret, 273 target_ulong rets) 274 { 275 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 276 uint32_t config_addr = rtas_ld(args, 0); 277 uint64_t buid = rtas_ldq(args, 1); 278 unsigned int func = rtas_ld(args, 3); 279 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ 280 unsigned int seq_num = rtas_ld(args, 5); 281 unsigned int ret_intr_type; 282 unsigned int irq, max_irqs = 0; 283 SpaprPhbState *phb = NULL; 284 PCIDevice *pdev = NULL; 285 SpaprPciMsi *msi; 286 int *config_addr_key; 287 Error *err = NULL; 288 int i; 289 290 /* Fins SpaprPhbState */ 291 phb = spapr_pci_find_phb(spapr, buid); 292 if (phb) { 293 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 294 } 295 if (!phb || !pdev) { 296 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 297 return; 298 } 299 300 switch (func) { 301 case RTAS_CHANGE_FN: 302 if (msi_present(pdev)) { 303 ret_intr_type = RTAS_TYPE_MSI; 304 } else if (msix_present(pdev)) { 305 ret_intr_type = RTAS_TYPE_MSIX; 306 } else { 307 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 308 return; 309 } 310 break; 311 case RTAS_CHANGE_MSI_FN: 312 if (msi_present(pdev)) { 313 ret_intr_type = RTAS_TYPE_MSI; 314 } else { 315 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 316 return; 317 } 318 break; 319 case RTAS_CHANGE_MSIX_FN: 320 if (msix_present(pdev)) { 321 ret_intr_type = RTAS_TYPE_MSIX; 322 } else { 323 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 324 return; 325 } 326 break; 327 default: 328 error_report("rtas_ibm_change_msi(%u) is not implemented", func); 329 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 330 return; 331 } 332 333 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr); 334 335 /* Releasing MSIs */ 336 if (!req_num) { 337 if (!msi) { 338 trace_spapr_pci_msi("Releasing wrong config", config_addr); 339 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 340 return; 341 } 342 343 if (msi_present(pdev)) { 344 spapr_msi_setmsg(pdev, 0, false, 0, 0); 345 } 346 if (msix_present(pdev)) { 347 spapr_msi_setmsg(pdev, 0, true, 0, 0); 348 } 349 g_hash_table_remove(phb->msi, &config_addr); 350 351 trace_spapr_pci_msi("Released MSIs", config_addr); 352 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 353 rtas_st(rets, 1, 0); 354 return; 355 } 356 357 /* Enabling MSI */ 358 359 /* Check if the device supports as many IRQs as requested */ 360 if (ret_intr_type == RTAS_TYPE_MSI) { 361 max_irqs = msi_nr_vectors_allocated(pdev); 362 } else if (ret_intr_type == RTAS_TYPE_MSIX) { 363 max_irqs = pdev->msix_entries_nr; 364 } 365 if (!max_irqs) { 366 error_report("Requested interrupt type %d is not enabled for device %x", 367 ret_intr_type, config_addr); 368 rtas_st(rets, 0, -1); /* Hardware error */ 369 return; 370 } 371 /* Correct the number if the guest asked for too many */ 372 if (req_num > max_irqs) { 373 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); 374 req_num = max_irqs; 375 irq = 0; /* to avoid misleading trace */ 376 goto out; 377 } 378 379 /* Allocate MSIs */ 380 if (smc->legacy_irq_allocation) { 381 irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI, 382 &err); 383 } else { 384 irq = spapr_irq_msi_alloc(spapr, req_num, 385 ret_intr_type == RTAS_TYPE_MSI, &err); 386 } 387 if (err) { 388 error_reportf_err(err, "Can't allocate MSIs for device %x: ", 389 config_addr); 390 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 391 return; 392 } 393 394 for (i = 0; i < req_num; i++) { 395 spapr_irq_claim(spapr, irq + i, false, &err); 396 if (err) { 397 if (i) { 398 spapr_irq_free(spapr, irq, i); 399 } 400 if (!smc->legacy_irq_allocation) { 401 spapr_irq_msi_free(spapr, irq, req_num); 402 } 403 error_reportf_err(err, "Can't allocate MSIs for device %x: ", 404 config_addr); 405 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 406 return; 407 } 408 } 409 410 /* Release previous MSIs */ 411 if (msi) { 412 g_hash_table_remove(phb->msi, &config_addr); 413 } 414 415 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ 416 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, 417 irq, req_num); 418 419 /* Add MSI device to cache */ 420 msi = g_new(SpaprPciMsi, 1); 421 msi->first_irq = irq; 422 msi->num = req_num; 423 config_addr_key = g_new(int, 1); 424 *config_addr_key = config_addr; 425 g_hash_table_insert(phb->msi, config_addr_key, msi); 426 427 out: 428 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 429 rtas_st(rets, 1, req_num); 430 rtas_st(rets, 2, ++seq_num); 431 if (nret > 3) { 432 rtas_st(rets, 3, ret_intr_type); 433 } 434 435 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); 436 } 437 438 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, 439 SpaprMachineState *spapr, 440 uint32_t token, 441 uint32_t nargs, 442 target_ulong args, 443 uint32_t nret, 444 target_ulong rets) 445 { 446 uint32_t config_addr = rtas_ld(args, 0); 447 uint64_t buid = rtas_ldq(args, 1); 448 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); 449 SpaprPhbState *phb = NULL; 450 PCIDevice *pdev = NULL; 451 SpaprPciMsi *msi; 452 453 /* Find SpaprPhbState */ 454 phb = spapr_pci_find_phb(spapr, buid); 455 if (phb) { 456 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 457 } 458 if (!phb || !pdev) { 459 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 460 return; 461 } 462 463 /* Find device descriptor and start IRQ */ 464 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr); 465 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { 466 trace_spapr_pci_msi("Failed to return vector", config_addr); 467 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 468 return; 469 } 470 intr_src_num = msi->first_irq + ioa_intr_num; 471 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, 472 intr_src_num); 473 474 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 475 rtas_st(rets, 1, intr_src_num); 476 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ 477 } 478 479 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, 480 SpaprMachineState *spapr, 481 uint32_t token, uint32_t nargs, 482 target_ulong args, uint32_t nret, 483 target_ulong rets) 484 { 485 SpaprPhbState *sphb; 486 uint32_t addr, option; 487 uint64_t buid; 488 int ret; 489 490 if ((nargs != 4) || (nret != 1)) { 491 goto param_error_exit; 492 } 493 494 buid = rtas_ldq(args, 1); 495 addr = rtas_ld(args, 0); 496 option = rtas_ld(args, 3); 497 498 sphb = spapr_pci_find_phb(spapr, buid); 499 if (!sphb) { 500 goto param_error_exit; 501 } 502 503 if (!spapr_phb_eeh_available(sphb)) { 504 goto param_error_exit; 505 } 506 507 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option); 508 rtas_st(rets, 0, ret); 509 return; 510 511 param_error_exit: 512 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 513 } 514 515 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, 516 SpaprMachineState *spapr, 517 uint32_t token, uint32_t nargs, 518 target_ulong args, uint32_t nret, 519 target_ulong rets) 520 { 521 SpaprPhbState *sphb; 522 PCIDevice *pdev; 523 uint32_t addr, option; 524 uint64_t buid; 525 526 if ((nargs != 4) || (nret != 2)) { 527 goto param_error_exit; 528 } 529 530 buid = rtas_ldq(args, 1); 531 sphb = spapr_pci_find_phb(spapr, buid); 532 if (!sphb) { 533 goto param_error_exit; 534 } 535 536 if (!spapr_phb_eeh_available(sphb)) { 537 goto param_error_exit; 538 } 539 540 /* 541 * We always have PE address of form "00BB0001". "BB" 542 * represents the bus number of PE's primary bus. 543 */ 544 option = rtas_ld(args, 3); 545 switch (option) { 546 case RTAS_GET_PE_ADDR: 547 addr = rtas_ld(args, 0); 548 pdev = spapr_pci_find_dev(spapr, buid, addr); 549 if (!pdev) { 550 goto param_error_exit; 551 } 552 553 rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1); 554 break; 555 case RTAS_GET_PE_MODE: 556 rtas_st(rets, 1, RTAS_PE_MODE_SHARED); 557 break; 558 default: 559 goto param_error_exit; 560 } 561 562 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 563 return; 564 565 param_error_exit: 566 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 567 } 568 569 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, 570 SpaprMachineState *spapr, 571 uint32_t token, uint32_t nargs, 572 target_ulong args, uint32_t nret, 573 target_ulong rets) 574 { 575 SpaprPhbState *sphb; 576 uint64_t buid; 577 int state, ret; 578 579 if ((nargs != 3) || (nret != 4 && nret != 5)) { 580 goto param_error_exit; 581 } 582 583 buid = rtas_ldq(args, 1); 584 sphb = spapr_pci_find_phb(spapr, buid); 585 if (!sphb) { 586 goto param_error_exit; 587 } 588 589 if (!spapr_phb_eeh_available(sphb)) { 590 goto param_error_exit; 591 } 592 593 ret = spapr_phb_vfio_eeh_get_state(sphb, &state); 594 rtas_st(rets, 0, ret); 595 if (ret != RTAS_OUT_SUCCESS) { 596 return; 597 } 598 599 rtas_st(rets, 1, state); 600 rtas_st(rets, 2, RTAS_EEH_SUPPORT); 601 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); 602 if (nret >= 5) { 603 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); 604 } 605 return; 606 607 param_error_exit: 608 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 609 } 610 611 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, 612 SpaprMachineState *spapr, 613 uint32_t token, uint32_t nargs, 614 target_ulong args, uint32_t nret, 615 target_ulong rets) 616 { 617 SpaprPhbState *sphb; 618 uint32_t option; 619 uint64_t buid; 620 int ret; 621 622 if ((nargs != 4) || (nret != 1)) { 623 goto param_error_exit; 624 } 625 626 buid = rtas_ldq(args, 1); 627 option = rtas_ld(args, 3); 628 sphb = spapr_pci_find_phb(spapr, buid); 629 if (!sphb) { 630 goto param_error_exit; 631 } 632 633 if (!spapr_phb_eeh_available(sphb)) { 634 goto param_error_exit; 635 } 636 637 ret = spapr_phb_vfio_eeh_reset(sphb, option); 638 rtas_st(rets, 0, ret); 639 return; 640 641 param_error_exit: 642 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 643 } 644 645 static void rtas_ibm_configure_pe(PowerPCCPU *cpu, 646 SpaprMachineState *spapr, 647 uint32_t token, uint32_t nargs, 648 target_ulong args, uint32_t nret, 649 target_ulong rets) 650 { 651 SpaprPhbState *sphb; 652 uint64_t buid; 653 int ret; 654 655 if ((nargs != 3) || (nret != 1)) { 656 goto param_error_exit; 657 } 658 659 buid = rtas_ldq(args, 1); 660 sphb = spapr_pci_find_phb(spapr, buid); 661 if (!sphb) { 662 goto param_error_exit; 663 } 664 665 if (!spapr_phb_eeh_available(sphb)) { 666 goto param_error_exit; 667 } 668 669 ret = spapr_phb_vfio_eeh_configure(sphb); 670 rtas_st(rets, 0, ret); 671 return; 672 673 param_error_exit: 674 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 675 } 676 677 /* To support it later */ 678 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, 679 SpaprMachineState *spapr, 680 uint32_t token, uint32_t nargs, 681 target_ulong args, uint32_t nret, 682 target_ulong rets) 683 { 684 SpaprPhbState *sphb; 685 int option; 686 uint64_t buid; 687 688 if ((nargs != 8) || (nret != 1)) { 689 goto param_error_exit; 690 } 691 692 buid = rtas_ldq(args, 1); 693 sphb = spapr_pci_find_phb(spapr, buid); 694 if (!sphb) { 695 goto param_error_exit; 696 } 697 698 if (!spapr_phb_eeh_available(sphb)) { 699 goto param_error_exit; 700 } 701 702 option = rtas_ld(args, 7); 703 switch (option) { 704 case RTAS_SLOT_TEMP_ERR_LOG: 705 case RTAS_SLOT_PERM_ERR_LOG: 706 break; 707 default: 708 goto param_error_exit; 709 } 710 711 /* We don't have error log yet */ 712 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); 713 return; 714 715 param_error_exit: 716 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 717 } 718 719 static void pci_spapr_set_irq(void *opaque, int irq_num, int level) 720 { 721 /* 722 * Here we use the number returned by pci_swizzle_map_irq_fn to find a 723 * corresponding qemu_irq. 724 */ 725 SpaprPhbState *phb = opaque; 726 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 727 728 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); 729 qemu_set_irq(spapr_qirq(spapr, phb->lsi_table[irq_num].irq), level); 730 } 731 732 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) 733 { 734 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); 735 PCIINTxRoute route; 736 737 route.mode = PCI_INTX_ENABLED; 738 route.irq = sphb->lsi_table[pin].irq; 739 740 return route; 741 } 742 743 static uint64_t spapr_msi_read(void *opaque, hwaddr addr, unsigned size) 744 { 745 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid access\n", __func__); 746 return 0; 747 } 748 749 /* 750 * MSI/MSIX memory region implementation. 751 * The handler handles both MSI and MSIX. 752 * The vector number is encoded in least bits in data. 753 */ 754 static void spapr_msi_write(void *opaque, hwaddr addr, 755 uint64_t data, unsigned size) 756 { 757 SpaprMachineState *spapr = opaque; 758 uint32_t irq = data; 759 760 trace_spapr_pci_msi_write(addr, data, irq); 761 762 qemu_irq_pulse(spapr_qirq(spapr, irq)); 763 } 764 765 static const MemoryRegionOps spapr_msi_ops = { 766 /* 767 * .read result is undefined by PCI spec. 768 * define .read method to avoid assert failure in memory_region_init_io 769 */ 770 .read = spapr_msi_read, 771 .write = spapr_msi_write, 772 .endianness = DEVICE_LITTLE_ENDIAN 773 }; 774 775 /* 776 * PHB PCI device 777 */ 778 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 779 { 780 SpaprPhbState *phb = opaque; 781 782 return &phb->iommu_as; 783 } 784 785 static char *spapr_phb_vfio_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) 786 { 787 char *path = NULL, *buf = NULL, *host = NULL; 788 789 /* Get the PCI VFIO host id */ 790 host = object_property_get_str(OBJECT(pdev), "host", NULL); 791 if (!host) { 792 goto err_out; 793 } 794 795 /* Construct the path of the file that will give us the DT location */ 796 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); 797 g_free(host); 798 if (!g_file_get_contents(path, &buf, NULL, NULL)) { 799 goto err_out; 800 } 801 g_free(path); 802 803 /* Construct and read from host device tree the loc-code */ 804 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); 805 g_free(buf); 806 if (!g_file_get_contents(path, &buf, NULL, NULL)) { 807 goto err_out; 808 } 809 return buf; 810 811 err_out: 812 g_free(path); 813 return NULL; 814 } 815 816 static char *spapr_phb_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) 817 { 818 char *buf; 819 const char *devtype = "qemu"; 820 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 821 822 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 823 buf = spapr_phb_vfio_get_loc_code(sphb, pdev); 824 if (buf) { 825 return buf; 826 } 827 devtype = "vfio"; 828 } 829 /* 830 * For emulated devices and VFIO-failure case, make up 831 * the loc-code. 832 */ 833 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", 834 devtype, pdev->name, sphb->index, busnr, 835 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 836 return buf; 837 } 838 839 /* Macros to operate with address in OF binding to PCI */ 840 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) 841 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ 842 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ 843 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ 844 #define b_ss(x) b_x((x), 24, 2) /* the space code */ 845 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ 846 #define b_ddddd(x) b_x((x), 11, 5) /* device number */ 847 #define b_fff(x) b_x((x), 8, 3) /* function number */ 848 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ 849 850 /* for 'reg' OF properties */ 851 #define RESOURCE_CELLS_SIZE 2 852 #define RESOURCE_CELLS_ADDRESS 3 853 854 typedef struct ResourceFields { 855 uint32_t phys_hi; 856 uint32_t phys_mid; 857 uint32_t phys_lo; 858 uint32_t size_hi; 859 uint32_t size_lo; 860 } QEMU_PACKED ResourceFields; 861 862 typedef struct ResourceProps { 863 ResourceFields reg[8]; 864 uint32_t reg_len; 865 } ResourceProps; 866 867 /* fill in the 'reg' OF properties for 868 * a PCI device. 'reg' describes resource requirements for a 869 * device's IO/MEM regions. 870 * 871 * the property is an array of ('phys-addr', 'size') pairs describing 872 * the addressable regions of the PCI device, where 'phys-addr' is a 873 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to 874 * (phys.hi, phys.mid, phys.lo), and 'size' is a 875 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). 876 * 877 * phys.hi = 0xYYXXXXZZ, where: 878 * 0xYY = npt000ss 879 * ||| | 880 * ||| +-- space code 881 * ||| | 882 * ||| + 00 if configuration space 883 * ||| + 01 if IO region, 884 * ||| + 10 if 32-bit MEM region 885 * ||| + 11 if 64-bit MEM region 886 * ||| 887 * ||+------ for non-relocatable IO: 1 if aliased 888 * || for relocatable IO: 1 if below 64KB 889 * || for MEM: 1 if below 1MB 890 * |+------- 1 if region is prefetchable 891 * +-------- 1 if region is non-relocatable 892 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function 893 * bits respectively 894 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding 895 * to the region 896 * 897 * phys.mid and phys.lo correspond respectively to the hi/lo portions 898 * of the actual address of the region. 899 * 900 * note also that addresses defined in this property are, at least 901 * for PAPR guests, relative to the PHBs IO/MEM windows, and 902 * correspond directly to the addresses in the BARs. 903 * 904 * in accordance with PCI Bus Binding to Open Firmware, 905 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, 906 * Appendix C. 907 */ 908 static void populate_resource_props(PCIDevice *d, ResourceProps *rp) 909 { 910 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); 911 uint32_t dev_id = (b_bbbbbbbb(bus_num) | 912 b_ddddd(PCI_SLOT(d->devfn)) | 913 b_fff(PCI_FUNC(d->devfn))); 914 ResourceFields *reg; 915 int i, reg_idx = 0; 916 917 /* config space region */ 918 reg = &rp->reg[reg_idx++]; 919 reg->phys_hi = cpu_to_be32(dev_id); 920 reg->phys_mid = 0; 921 reg->phys_lo = 0; 922 reg->size_hi = 0; 923 reg->size_lo = 0; 924 925 for (i = 0; i < PCI_NUM_REGIONS; i++) { 926 if (!d->io_regions[i].size) { 927 continue; 928 } 929 930 reg = &rp->reg[reg_idx++]; 931 932 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); 933 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 934 reg->phys_hi |= cpu_to_be32(b_ss(1)); 935 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 936 reg->phys_hi |= cpu_to_be32(b_ss(3)); 937 } else { 938 reg->phys_hi |= cpu_to_be32(b_ss(2)); 939 } 940 reg->phys_mid = 0; 941 reg->phys_lo = 0; 942 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); 943 reg->size_lo = cpu_to_be32(d->io_regions[i].size); 944 } 945 946 rp->reg_len = reg_idx * sizeof(ResourceFields); 947 } 948 949 typedef struct PCIClass PCIClass; 950 typedef struct PCISubClass PCISubClass; 951 typedef struct PCIIFace PCIIFace; 952 953 struct PCIIFace { 954 int iface; 955 const char *name; 956 }; 957 958 struct PCISubClass { 959 int subclass; 960 const char *name; 961 const PCIIFace *iface; 962 }; 963 964 struct PCIClass { 965 const char *name; 966 const PCISubClass *subc; 967 }; 968 969 static const PCISubClass undef_subclass[] = { 970 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL }, 971 { 0xFF, NULL, NULL }, 972 }; 973 974 static const PCISubClass mass_subclass[] = { 975 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL }, 976 { PCI_CLASS_STORAGE_IDE, "ide", NULL }, 977 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL }, 978 { PCI_CLASS_STORAGE_IPI, "ipi", NULL }, 979 { PCI_CLASS_STORAGE_RAID, "raid", NULL }, 980 { PCI_CLASS_STORAGE_ATA, "ata", NULL }, 981 { PCI_CLASS_STORAGE_SATA, "sata", NULL }, 982 { PCI_CLASS_STORAGE_SAS, "sas", NULL }, 983 { 0xFF, NULL, NULL }, 984 }; 985 986 static const PCISubClass net_subclass[] = { 987 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL }, 988 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL }, 989 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL }, 990 { PCI_CLASS_NETWORK_ATM, "atm", NULL }, 991 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL }, 992 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL }, 993 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL }, 994 { 0xFF, NULL, NULL }, 995 }; 996 997 static const PCISubClass displ_subclass[] = { 998 { PCI_CLASS_DISPLAY_VGA, "vga", NULL }, 999 { PCI_CLASS_DISPLAY_XGA, "xga", NULL }, 1000 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL }, 1001 { 0xFF, NULL, NULL }, 1002 }; 1003 1004 static const PCISubClass media_subclass[] = { 1005 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL }, 1006 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL }, 1007 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL }, 1008 { 0xFF, NULL, NULL }, 1009 }; 1010 1011 static const PCISubClass mem_subclass[] = { 1012 { PCI_CLASS_MEMORY_RAM, "memory", NULL }, 1013 { PCI_CLASS_MEMORY_FLASH, "flash", NULL }, 1014 { 0xFF, NULL, NULL }, 1015 }; 1016 1017 static const PCISubClass bridg_subclass[] = { 1018 { PCI_CLASS_BRIDGE_HOST, "host", NULL }, 1019 { PCI_CLASS_BRIDGE_ISA, "isa", NULL }, 1020 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL }, 1021 { PCI_CLASS_BRIDGE_MC, "mca", NULL }, 1022 { PCI_CLASS_BRIDGE_PCI, "pci", NULL }, 1023 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL }, 1024 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL }, 1025 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL }, 1026 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL }, 1027 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL }, 1028 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL }, 1029 { 0xFF, NULL, NULL }, 1030 }; 1031 1032 static const PCISubClass comm_subclass[] = { 1033 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL }, 1034 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL }, 1035 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL }, 1036 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL }, 1037 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL }, 1038 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL }, 1039 { 0xFF, NULL, NULL, }, 1040 }; 1041 1042 static const PCIIFace pic_iface[] = { 1043 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" }, 1044 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" }, 1045 { 0xFF, NULL }, 1046 }; 1047 1048 static const PCISubClass sys_subclass[] = { 1049 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface }, 1050 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL }, 1051 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL }, 1052 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL }, 1053 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL }, 1054 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL }, 1055 { 0xFF, NULL, NULL }, 1056 }; 1057 1058 static const PCISubClass inp_subclass[] = { 1059 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL }, 1060 { PCI_CLASS_INPUT_PEN, "pen", NULL }, 1061 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL }, 1062 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL }, 1063 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL }, 1064 { 0xFF, NULL, NULL }, 1065 }; 1066 1067 static const PCISubClass dock_subclass[] = { 1068 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL }, 1069 { 0xFF, NULL, NULL }, 1070 }; 1071 1072 static const PCISubClass cpu_subclass[] = { 1073 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL }, 1074 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL }, 1075 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL }, 1076 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL }, 1077 { 0xFF, NULL, NULL }, 1078 }; 1079 1080 static const PCIIFace usb_iface[] = { 1081 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" }, 1082 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", }, 1083 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" }, 1084 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" }, 1085 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" }, 1086 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" }, 1087 { 0xFF, NULL }, 1088 }; 1089 1090 static const PCISubClass ser_subclass[] = { 1091 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL }, 1092 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL }, 1093 { PCI_CLASS_SERIAL_SSA, "ssa", NULL }, 1094 { PCI_CLASS_SERIAL_USB, "usb", usb_iface }, 1095 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL }, 1096 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL }, 1097 { PCI_CLASS_SERIAL_IB, "infiniband", NULL }, 1098 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL }, 1099 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL }, 1100 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL }, 1101 { 0xFF, NULL, NULL }, 1102 }; 1103 1104 static const PCISubClass wrl_subclass[] = { 1105 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL }, 1106 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL }, 1107 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL }, 1108 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL }, 1109 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL }, 1110 { 0xFF, NULL, NULL }, 1111 }; 1112 1113 static const PCISubClass sat_subclass[] = { 1114 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL }, 1115 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL }, 1116 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL }, 1117 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL }, 1118 { 0xFF, NULL, NULL }, 1119 }; 1120 1121 static const PCISubClass crypt_subclass[] = { 1122 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL }, 1123 { PCI_CLASS_CRYPT_ENTERTAINMENT, 1124 "entertainment-encryption", NULL }, 1125 { 0xFF, NULL, NULL }, 1126 }; 1127 1128 static const PCISubClass spc_subclass[] = { 1129 { PCI_CLASS_SP_DPIO, "dpio", NULL }, 1130 { PCI_CLASS_SP_PERF, "counter", NULL }, 1131 { PCI_CLASS_SP_SYNCH, "measurement", NULL }, 1132 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL }, 1133 { 0xFF, NULL, NULL }, 1134 }; 1135 1136 static const PCIClass pci_classes[] = { 1137 { "legacy-device", undef_subclass }, 1138 { "mass-storage", mass_subclass }, 1139 { "network", net_subclass }, 1140 { "display", displ_subclass, }, 1141 { "multimedia-device", media_subclass }, 1142 { "memory-controller", mem_subclass }, 1143 { "unknown-bridge", bridg_subclass }, 1144 { "communication-controller", comm_subclass}, 1145 { "system-peripheral", sys_subclass }, 1146 { "input-controller", inp_subclass }, 1147 { "docking-station", dock_subclass }, 1148 { "cpu", cpu_subclass }, 1149 { "serial-bus", ser_subclass }, 1150 { "wireless-controller", wrl_subclass }, 1151 { "intelligent-io", NULL }, 1152 { "satellite-device", sat_subclass }, 1153 { "encryption", crypt_subclass }, 1154 { "data-processing-controller", spc_subclass }, 1155 }; 1156 1157 static const char *dt_name_from_class(uint8_t class, uint8_t subclass, 1158 uint8_t iface) 1159 { 1160 const PCIClass *pclass; 1161 const PCISubClass *psubclass; 1162 const PCIIFace *piface; 1163 const char *name; 1164 1165 if (class >= ARRAY_SIZE(pci_classes)) { 1166 return "pci"; 1167 } 1168 1169 pclass = pci_classes + class; 1170 name = pclass->name; 1171 1172 if (pclass->subc == NULL) { 1173 return name; 1174 } 1175 1176 psubclass = pclass->subc; 1177 while ((psubclass->subclass & 0xff) != 0xff) { 1178 if ((psubclass->subclass & 0xff) == subclass) { 1179 name = psubclass->name; 1180 break; 1181 } 1182 psubclass++; 1183 } 1184 1185 piface = psubclass->iface; 1186 if (piface == NULL) { 1187 return name; 1188 } 1189 while ((piface->iface & 0xff) != 0xff) { 1190 if ((piface->iface & 0xff) == iface) { 1191 name = piface->name; 1192 break; 1193 } 1194 piface++; 1195 } 1196 1197 return name; 1198 } 1199 1200 /* 1201 * DRC helper functions 1202 */ 1203 1204 static uint32_t drc_id_from_devfn(SpaprPhbState *phb, 1205 uint8_t chassis, int32_t devfn) 1206 { 1207 return (phb->index << 16) | (chassis << 8) | devfn; 1208 } 1209 1210 static SpaprDrc *drc_from_devfn(SpaprPhbState *phb, 1211 uint8_t chassis, int32_t devfn) 1212 { 1213 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI, 1214 drc_id_from_devfn(phb, chassis, devfn)); 1215 } 1216 1217 static uint8_t chassis_from_bus(PCIBus *bus) 1218 { 1219 if (pci_bus_is_root(bus)) { 1220 return 0; 1221 } else { 1222 PCIDevice *bridge = pci_bridge_get_device(bus); 1223 1224 return object_property_get_uint(OBJECT(bridge), "chassis_nr", 1225 &error_abort); 1226 } 1227 } 1228 1229 static SpaprDrc *drc_from_dev(SpaprPhbState *phb, PCIDevice *dev) 1230 { 1231 uint8_t chassis = chassis_from_bus(pci_get_bus(dev)); 1232 1233 return drc_from_devfn(phb, chassis, dev->devfn); 1234 } 1235 1236 static void add_drcs(SpaprPhbState *phb, PCIBus *bus) 1237 { 1238 Object *owner; 1239 int i; 1240 uint8_t chassis; 1241 1242 if (!phb->dr_enabled) { 1243 return; 1244 } 1245 1246 chassis = chassis_from_bus(bus); 1247 1248 if (pci_bus_is_root(bus)) { 1249 owner = OBJECT(phb); 1250 } else { 1251 owner = OBJECT(pci_bridge_get_device(bus)); 1252 } 1253 1254 for (i = 0; i < PCI_SLOT_MAX * PCI_FUNC_MAX; i++) { 1255 spapr_dr_connector_new(owner, TYPE_SPAPR_DRC_PCI, 1256 drc_id_from_devfn(phb, chassis, i)); 1257 } 1258 } 1259 1260 static void remove_drcs(SpaprPhbState *phb, PCIBus *bus) 1261 { 1262 int i; 1263 uint8_t chassis; 1264 1265 if (!phb->dr_enabled) { 1266 return; 1267 } 1268 1269 chassis = chassis_from_bus(bus); 1270 1271 for (i = PCI_SLOT_MAX * PCI_FUNC_MAX - 1; i >= 0; i--) { 1272 SpaprDrc *drc = drc_from_devfn(phb, chassis, i); 1273 1274 if (drc) { 1275 object_unparent(OBJECT(drc)); 1276 } 1277 } 1278 } 1279 1280 typedef struct PciWalkFdt { 1281 void *fdt; 1282 int offset; 1283 SpaprPhbState *sphb; 1284 int err; 1285 } PciWalkFdt; 1286 1287 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev, 1288 void *fdt, int parent_offset); 1289 1290 static void spapr_dt_pci_device_cb(PCIBus *bus, PCIDevice *pdev, 1291 void *opaque) 1292 { 1293 PciWalkFdt *p = opaque; 1294 int err; 1295 1296 if (p->err) { 1297 /* Something's already broken, don't keep going */ 1298 return; 1299 } 1300 1301 err = spapr_dt_pci_device(p->sphb, pdev, p->fdt, p->offset); 1302 if (err < 0) { 1303 p->err = err; 1304 } 1305 } 1306 1307 /* Augment PCI device node with bridge specific information */ 1308 static int spapr_dt_pci_bus(SpaprPhbState *sphb, PCIBus *bus, 1309 void *fdt, int offset) 1310 { 1311 Object *owner; 1312 PciWalkFdt cbinfo = { 1313 .fdt = fdt, 1314 .offset = offset, 1315 .sphb = sphb, 1316 .err = 0, 1317 }; 1318 int ret; 1319 1320 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 1321 RESOURCE_CELLS_ADDRESS)); 1322 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1323 RESOURCE_CELLS_SIZE)); 1324 1325 assert(bus); 1326 pci_for_each_device_reverse(bus, pci_bus_num(bus), 1327 spapr_dt_pci_device_cb, &cbinfo); 1328 if (cbinfo.err) { 1329 return cbinfo.err; 1330 } 1331 1332 if (pci_bus_is_root(bus)) { 1333 owner = OBJECT(sphb); 1334 } else { 1335 owner = OBJECT(pci_bridge_get_device(bus)); 1336 } 1337 1338 ret = spapr_dt_drc(fdt, offset, owner, 1339 SPAPR_DR_CONNECTOR_TYPE_PCI); 1340 if (ret) { 1341 return ret; 1342 } 1343 1344 return offset; 1345 } 1346 1347 /* create OF node for pci device and required OF DT properties */ 1348 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev, 1349 void *fdt, int parent_offset) 1350 { 1351 int offset; 1352 const gchar *basename; 1353 gchar *nodename; 1354 int slot = PCI_SLOT(dev->devfn); 1355 int func = PCI_FUNC(dev->devfn); 1356 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1357 ResourceProps rp; 1358 SpaprDrc *drc = drc_from_dev(sphb, dev); 1359 uint32_t vendor_id = pci_default_read_config(dev, PCI_VENDOR_ID, 2); 1360 uint32_t device_id = pci_default_read_config(dev, PCI_DEVICE_ID, 2); 1361 uint32_t revision_id = pci_default_read_config(dev, PCI_REVISION_ID, 1); 1362 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); 1363 uint32_t irq_pin = pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1); 1364 uint32_t subsystem_id = pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2); 1365 uint32_t subsystem_vendor_id = 1366 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2); 1367 uint32_t cache_line_size = 1368 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1); 1369 uint32_t pci_status = pci_default_read_config(dev, PCI_STATUS, 2); 1370 gchar *loc_code; 1371 1372 basename = dt_name_from_class((ccode >> 16) & 0xff, (ccode >> 8) & 0xff, 1373 ccode & 0xff); 1374 1375 if (func != 0) { 1376 nodename = g_strdup_printf("%s@%x,%x", basename, slot, func); 1377 } else { 1378 nodename = g_strdup_printf("%s@%x", basename, slot); 1379 } 1380 1381 _FDT(offset = fdt_add_subnode(fdt, parent_offset, nodename)); 1382 1383 g_free(nodename); 1384 1385 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ 1386 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", vendor_id)); 1387 _FDT(fdt_setprop_cell(fdt, offset, "device-id", device_id)); 1388 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", revision_id)); 1389 1390 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode)); 1391 if (irq_pin) { 1392 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", irq_pin)); 1393 } 1394 1395 if (subsystem_id) { 1396 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", subsystem_id)); 1397 } 1398 1399 if (subsystem_vendor_id) { 1400 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", 1401 subsystem_vendor_id)); 1402 } 1403 1404 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", cache_line_size)); 1405 1406 1407 /* the following fdt cells are masked off the pci status register */ 1408 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", 1409 PCI_STATUS_DEVSEL_MASK & pci_status)); 1410 1411 if (pci_status & PCI_STATUS_FAST_BACK) { 1412 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); 1413 } 1414 if (pci_status & PCI_STATUS_66MHZ) { 1415 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); 1416 } 1417 if (pci_status & PCI_STATUS_UDF) { 1418 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); 1419 } 1420 1421 loc_code = spapr_phb_get_loc_code(sphb, dev); 1422 _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", loc_code)); 1423 g_free(loc_code); 1424 1425 if (drc) { 1426 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", 1427 spapr_drc_index(drc))); 1428 } 1429 1430 if (msi_present(dev)) { 1431 uint32_t max_msi = msi_nr_vectors_allocated(dev); 1432 if (max_msi) { 1433 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi)); 1434 } 1435 } 1436 if (msix_present(dev)) { 1437 uint32_t max_msix = dev->msix_entries_nr; 1438 if (max_msix) { 1439 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix)); 1440 } 1441 } 1442 1443 populate_resource_props(dev, &rp); 1444 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); 1445 1446 if (sphb->pcie_ecs && pci_is_express(dev)) { 1447 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1)); 1448 } 1449 1450 spapr_phb_nvgpu_populate_pcidev_dt(dev, fdt, offset, sphb); 1451 1452 if (!pc->is_bridge) { 1453 /* Properties only for non-bridges */ 1454 uint32_t min_grant = pci_default_read_config(dev, PCI_MIN_GNT, 1); 1455 uint32_t max_latency = pci_default_read_config(dev, PCI_MAX_LAT, 1); 1456 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", min_grant)); 1457 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", max_latency)); 1458 return offset; 1459 } else { 1460 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 1461 1462 return spapr_dt_pci_bus(sphb, sec_bus, fdt, offset); 1463 } 1464 } 1465 1466 /* Callback to be called during DRC release. */ 1467 void spapr_phb_remove_pci_device_cb(DeviceState *dev) 1468 { 1469 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 1470 1471 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 1472 object_unparent(OBJECT(dev)); 1473 } 1474 1475 int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 1476 void *fdt, int *fdt_start_offset, Error **errp) 1477 { 1478 HotplugHandler *plug_handler = qdev_get_hotplug_handler(drc->dev); 1479 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(plug_handler); 1480 PCIDevice *pdev = PCI_DEVICE(drc->dev); 1481 1482 *fdt_start_offset = spapr_dt_pci_device(sphb, pdev, fdt, 0); 1483 return 0; 1484 } 1485 1486 static void spapr_pci_bridge_plug(SpaprPhbState *phb, 1487 PCIBridge *bridge) 1488 { 1489 PCIBus *bus = pci_bridge_get_sec_bus(bridge); 1490 1491 add_drcs(phb, bus); 1492 } 1493 1494 /* Returns non-zero if the value of "chassis_nr" is already in use */ 1495 static int check_chassis_nr(Object *obj, void *opaque) 1496 { 1497 int new_chassis_nr = 1498 object_property_get_uint(opaque, "chassis_nr", &error_abort); 1499 int chassis_nr = 1500 object_property_get_uint(obj, "chassis_nr", NULL); 1501 1502 if (!object_dynamic_cast(obj, TYPE_PCI_BRIDGE)) { 1503 return 0; 1504 } 1505 1506 /* Skip unsupported bridge types */ 1507 if (!chassis_nr) { 1508 return 0; 1509 } 1510 1511 /* Skip self */ 1512 if (obj == opaque) { 1513 return 0; 1514 } 1515 1516 return chassis_nr == new_chassis_nr; 1517 } 1518 1519 static bool bridge_has_valid_chassis_nr(Object *bridge, Error **errp) 1520 { 1521 int chassis_nr = 1522 object_property_get_uint(bridge, "chassis_nr", NULL); 1523 1524 /* 1525 * slotid_cap_init() already ensures that "chassis_nr" isn't null for 1526 * standard PCI bridges, so this really tells if "chassis_nr" is present 1527 * or not. 1528 */ 1529 if (!chassis_nr) { 1530 error_setg(errp, "PCI Bridge lacks a \"chassis_nr\" property"); 1531 error_append_hint(errp, "Try -device pci-bridge instead.\n"); 1532 return false; 1533 } 1534 1535 /* We want unique values for "chassis_nr" */ 1536 if (object_child_foreach_recursive(object_get_root(), check_chassis_nr, 1537 bridge)) { 1538 error_setg(errp, "Bridge chassis %d already in use", chassis_nr); 1539 return false; 1540 } 1541 1542 return true; 1543 } 1544 1545 static void spapr_pci_pre_plug(HotplugHandler *plug_handler, 1546 DeviceState *plugged_dev, Error **errp) 1547 { 1548 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1549 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1550 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1551 SpaprDrc *drc = drc_from_dev(phb, pdev); 1552 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); 1553 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1554 1555 if (!phb->dr_enabled) { 1556 /* if this is a hotplug operation initiated by the user 1557 * we need to let them know it's not enabled 1558 */ 1559 if (plugged_dev->hotplugged) { 1560 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1561 object_get_typename(OBJECT(phb))); 1562 return; 1563 } 1564 } 1565 1566 if (pc->is_bridge) { 1567 if (!bridge_has_valid_chassis_nr(OBJECT(plugged_dev), errp)) { 1568 return; 1569 } 1570 } 1571 1572 /* Following the QEMU convention used for PCIe multifunction 1573 * hotplug, we do not allow functions to be hotplugged to a 1574 * slot that already has function 0 present 1575 */ 1576 if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] && 1577 PCI_FUNC(pdev->devfn) != 0) { 1578 error_setg(errp, "PCI: slot %d function 0 already occupied by %s," 1579 " additional functions can no longer be exposed to guest.", 1580 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name); 1581 } 1582 1583 if (drc && drc->dev) { 1584 error_setg(errp, "PCI: slot %d already occupied by %s", slotnr, 1585 pci_get_function_0(PCI_DEVICE(drc->dev))->name); 1586 return; 1587 } 1588 } 1589 1590 static void spapr_pci_plug(HotplugHandler *plug_handler, 1591 DeviceState *plugged_dev, Error **errp) 1592 { 1593 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1594 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1595 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1596 SpaprDrc *drc = drc_from_dev(phb, pdev); 1597 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1598 1599 /* 1600 * If DR is disabled we don't need to do anything in the case of 1601 * hotplug or coldplug callbacks. 1602 */ 1603 if (!phb->dr_enabled) { 1604 return; 1605 } 1606 1607 g_assert(drc); 1608 1609 if (pc->is_bridge) { 1610 spapr_pci_bridge_plug(phb, PCI_BRIDGE(plugged_dev)); 1611 } 1612 1613 /* spapr_pci_pre_plug() already checked the DRC is attachable */ 1614 spapr_drc_attach(drc, DEVICE(pdev)); 1615 1616 /* If this is function 0, signal hotplug for all the device functions. 1617 * Otherwise defer sending the hotplug event. 1618 */ 1619 if (!spapr_drc_hotplugged(plugged_dev)) { 1620 spapr_drc_reset(drc); 1621 } else if (PCI_FUNC(pdev->devfn) == 0) { 1622 int i; 1623 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev)); 1624 1625 for (i = 0; i < 8; i++) { 1626 SpaprDrc *func_drc; 1627 SpaprDrcClass *func_drck; 1628 SpaprDREntitySense state; 1629 1630 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1631 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1632 state = func_drck->dr_entity_sense(func_drc); 1633 1634 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { 1635 spapr_hotplug_req_add_by_index(func_drc); 1636 } 1637 } 1638 } 1639 } 1640 1641 static void spapr_pci_bridge_unplug(SpaprPhbState *phb, 1642 PCIBridge *bridge) 1643 { 1644 PCIBus *bus = pci_bridge_get_sec_bus(bridge); 1645 1646 remove_drcs(phb, bus); 1647 } 1648 1649 static void spapr_pci_unplug(HotplugHandler *plug_handler, 1650 DeviceState *plugged_dev, Error **errp) 1651 { 1652 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1653 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1654 1655 /* some version guests do not wait for completion of a device 1656 * cleanup (generally done asynchronously by the kernel) before 1657 * signaling to QEMU that the device is safe, but instead sleep 1658 * for some 'safe' period of time. unfortunately on a busy host 1659 * this sleep isn't guaranteed to be long enough, resulting in 1660 * bad things like IRQ lines being left asserted during final 1661 * device removal. to deal with this we call reset just prior 1662 * to finalizing the device, which will put the device back into 1663 * an 'idle' state, as the device cleanup code expects. 1664 */ 1665 pci_device_reset(PCI_DEVICE(plugged_dev)); 1666 1667 if (pc->is_bridge) { 1668 spapr_pci_bridge_unplug(phb, PCI_BRIDGE(plugged_dev)); 1669 return; 1670 } 1671 1672 qdev_unrealize(plugged_dev); 1673 } 1674 1675 static void spapr_pci_unplug_request(HotplugHandler *plug_handler, 1676 DeviceState *plugged_dev, Error **errp) 1677 { 1678 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1679 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1680 SpaprDrc *drc = drc_from_dev(phb, pdev); 1681 1682 if (!phb->dr_enabled) { 1683 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1684 object_get_typename(OBJECT(phb))); 1685 return; 1686 } 1687 1688 g_assert(drc); 1689 g_assert(drc->dev == plugged_dev); 1690 1691 if (!spapr_drc_unplug_requested(drc)) { 1692 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1693 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1694 SpaprDrc *func_drc; 1695 SpaprDrcClass *func_drck; 1696 SpaprDREntitySense state; 1697 int i; 1698 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev)); 1699 1700 if (pc->is_bridge) { 1701 error_setg(errp, "PCI: Hot unplug of PCI bridges not supported"); 1702 return; 1703 } 1704 if (object_property_get_uint(OBJECT(pdev), "nvlink2-tgt", NULL)) { 1705 error_setg(errp, "PCI: Cannot unplug NVLink2 devices"); 1706 return; 1707 } 1708 1709 /* ensure any other present functions are pending unplug */ 1710 if (PCI_FUNC(pdev->devfn) == 0) { 1711 for (i = 1; i < 8; i++) { 1712 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1713 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1714 state = func_drck->dr_entity_sense(func_drc); 1715 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT 1716 && !spapr_drc_unplug_requested(func_drc)) { 1717 /* 1718 * Attempting to remove function 0 of a multifunction 1719 * device will will cascade into removing all child 1720 * functions, even if their unplug weren't requested 1721 * beforehand. 1722 */ 1723 spapr_drc_detach(func_drc); 1724 } 1725 } 1726 } 1727 1728 spapr_drc_detach(drc); 1729 1730 /* if this isn't func 0, defer unplug event. otherwise signal removal 1731 * for all present functions 1732 */ 1733 if (PCI_FUNC(pdev->devfn) == 0) { 1734 for (i = 7; i >= 0; i--) { 1735 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1736 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1737 state = func_drck->dr_entity_sense(func_drc); 1738 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { 1739 spapr_hotplug_req_remove_by_index(func_drc); 1740 } 1741 } 1742 } 1743 } 1744 } 1745 1746 static void spapr_phb_finalizefn(Object *obj) 1747 { 1748 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(obj); 1749 1750 g_free(sphb->dtbusname); 1751 sphb->dtbusname = NULL; 1752 } 1753 1754 static void spapr_phb_unrealize(DeviceState *dev) 1755 { 1756 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1757 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1758 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1759 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(phb); 1760 SpaprTceTable *tcet; 1761 int i; 1762 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 1763 1764 spapr_phb_nvgpu_free(sphb); 1765 1766 if (sphb->msi) { 1767 g_hash_table_unref(sphb->msi); 1768 sphb->msi = NULL; 1769 } 1770 1771 /* 1772 * Remove IO/MMIO subregions and aliases, rest should get cleaned 1773 * via PHB's unrealize->object_finalize 1774 */ 1775 for (i = windows_supported - 1; i >= 0; i--) { 1776 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); 1777 if (tcet) { 1778 memory_region_del_subregion(&sphb->iommu_root, 1779 spapr_tce_get_iommu(tcet)); 1780 } 1781 } 1782 1783 remove_drcs(sphb, phb->bus); 1784 1785 for (i = PCI_NUM_PINS - 1; i >= 0; i--) { 1786 if (sphb->lsi_table[i].irq) { 1787 spapr_irq_free(spapr, sphb->lsi_table[i].irq, 1); 1788 sphb->lsi_table[i].irq = 0; 1789 } 1790 } 1791 1792 QLIST_REMOVE(sphb, list); 1793 1794 memory_region_del_subregion(&sphb->iommu_root, &sphb->msiwindow); 1795 1796 /* 1797 * An attached PCI device may have memory listeners, eg. VFIO PCI. We have 1798 * unmapped all sections. Remove the listeners now, before destroying the 1799 * address space. 1800 */ 1801 address_space_remove_listeners(&sphb->iommu_as); 1802 address_space_destroy(&sphb->iommu_as); 1803 1804 qbus_set_hotplug_handler(BUS(phb->bus), NULL); 1805 pci_unregister_root_bus(phb->bus); 1806 1807 memory_region_del_subregion(get_system_memory(), &sphb->iowindow); 1808 if (sphb->mem64_win_pciaddr != (hwaddr)-1) { 1809 memory_region_del_subregion(get_system_memory(), &sphb->mem64window); 1810 } 1811 memory_region_del_subregion(get_system_memory(), &sphb->mem32window); 1812 } 1813 1814 static void spapr_phb_destroy_msi(gpointer opaque) 1815 { 1816 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1817 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1818 SpaprPciMsi *msi = opaque; 1819 1820 if (!smc->legacy_irq_allocation) { 1821 spapr_irq_msi_free(spapr, msi->first_irq, msi->num); 1822 } 1823 spapr_irq_free(spapr, msi->first_irq, msi->num); 1824 g_free(msi); 1825 } 1826 1827 static void spapr_phb_realize(DeviceState *dev, Error **errp) 1828 { 1829 ERRP_GUARD(); 1830 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 1831 * tries to add a sPAPR PHB to a non-pseries machine. 1832 */ 1833 SpaprMachineState *spapr = 1834 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), 1835 TYPE_SPAPR_MACHINE); 1836 SpaprMachineClass *smc = spapr ? SPAPR_MACHINE_GET_CLASS(spapr) : NULL; 1837 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1838 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(s); 1839 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1840 MachineState *ms = MACHINE(spapr); 1841 char *namebuf; 1842 int i; 1843 PCIBus *bus; 1844 uint64_t msi_window_size = 4096; 1845 SpaprTceTable *tcet; 1846 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 1847 1848 if (!spapr) { 1849 error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine"); 1850 return; 1851 } 1852 1853 assert(sphb->index != (uint32_t)-1); /* checked in spapr_phb_pre_plug() */ 1854 1855 if (sphb->mem64_win_size != 0) { 1856 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { 1857 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx 1858 " (max 2 GiB)", sphb->mem_win_size); 1859 return; 1860 } 1861 1862 /* 64-bit window defaults to identity mapping */ 1863 sphb->mem64_win_pciaddr = sphb->mem64_win_addr; 1864 } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { 1865 /* 1866 * For compatibility with old configuration, if no 64-bit MMIO 1867 * window is specified, but the ordinary (32-bit) memory 1868 * window is specified as > 2GiB, we treat it as a 2GiB 32-bit 1869 * window, with a 64-bit MMIO window following on immediately 1870 * afterwards 1871 */ 1872 sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE; 1873 sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE; 1874 sphb->mem64_win_pciaddr = 1875 SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE; 1876 sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE; 1877 } 1878 1879 if (spapr_pci_find_phb(spapr, sphb->buid)) { 1880 SpaprPhbState *s; 1881 1882 error_setg(errp, "PCI host bridges must have unique indexes"); 1883 error_append_hint(errp, "The following indexes are already in use:"); 1884 QLIST_FOREACH(s, &spapr->phbs, list) { 1885 error_append_hint(errp, " %d", s->index); 1886 } 1887 error_append_hint(errp, "\nTry another value for the index property\n"); 1888 return; 1889 } 1890 1891 if (sphb->numa_node != -1 && 1892 (sphb->numa_node >= MAX_NODES || 1893 !ms->numa_state->nodes[sphb->numa_node].present)) { 1894 error_setg(errp, "Invalid NUMA node ID for PCI host bridge"); 1895 return; 1896 } 1897 1898 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); 1899 1900 /* Initialize memory regions */ 1901 namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname); 1902 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); 1903 g_free(namebuf); 1904 1905 namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname); 1906 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb), 1907 namebuf, &sphb->memspace, 1908 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); 1909 g_free(namebuf); 1910 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, 1911 &sphb->mem32window); 1912 1913 if (sphb->mem64_win_size != 0) { 1914 namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname); 1915 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb), 1916 namebuf, &sphb->memspace, 1917 sphb->mem64_win_pciaddr, sphb->mem64_win_size); 1918 g_free(namebuf); 1919 1920 memory_region_add_subregion(get_system_memory(), 1921 sphb->mem64_win_addr, 1922 &sphb->mem64window); 1923 } 1924 1925 /* Initialize IO regions */ 1926 namebuf = g_strdup_printf("%s.io", sphb->dtbusname); 1927 memory_region_init(&sphb->iospace, OBJECT(sphb), 1928 namebuf, SPAPR_PCI_IO_WIN_SIZE); 1929 g_free(namebuf); 1930 1931 namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname); 1932 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, 1933 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); 1934 g_free(namebuf); 1935 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, 1936 &sphb->iowindow); 1937 1938 bus = pci_register_root_bus(dev, NULL, 1939 pci_spapr_set_irq, pci_swizzle_map_irq_fn, sphb, 1940 &sphb->memspace, &sphb->iospace, 1941 PCI_DEVFN(0, 0), PCI_NUM_PINS, 1942 TYPE_PCI_BUS); 1943 1944 /* 1945 * Despite resembling a vanilla PCI bus in most ways, the PAPR 1946 * para-virtualized PCI bus *does* permit PCI-E extended config 1947 * space access 1948 */ 1949 if (sphb->pcie_ecs) { 1950 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 1951 } 1952 phb->bus = bus; 1953 qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb)); 1954 1955 /* 1956 * Initialize PHB address space. 1957 * By default there will be at least one subregion for default 1958 * 32bit DMA window. 1959 * Later the guest might want to create another DMA window 1960 * which will become another memory subregion. 1961 */ 1962 namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname); 1963 memory_region_init(&sphb->iommu_root, OBJECT(sphb), 1964 namebuf, UINT64_MAX); 1965 g_free(namebuf); 1966 address_space_init(&sphb->iommu_as, &sphb->iommu_root, 1967 sphb->dtbusname); 1968 1969 /* 1970 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, 1971 * we need to allocate some memory to catch those writes coming 1972 * from msi_notify()/msix_notify(). 1973 * As MSIMessage:addr is going to be the same and MSIMessage:data 1974 * is going to be a VIRQ number, 4 bytes of the MSI MR will only 1975 * be used. 1976 * 1977 * For KVM we want to ensure that this memory is a full page so that 1978 * our memory slot is of page size granularity. 1979 */ 1980 if (kvm_enabled()) { 1981 msi_window_size = qemu_real_host_page_size; 1982 } 1983 1984 memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr, 1985 "msi", msi_window_size); 1986 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, 1987 &sphb->msiwindow); 1988 1989 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); 1990 1991 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); 1992 1993 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); 1994 1995 /* Initialize the LSI table */ 1996 for (i = 0; i < PCI_NUM_PINS; i++) { 1997 int irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i; 1998 1999 if (smc->legacy_irq_allocation) { 2000 irq = spapr_irq_findone(spapr, errp); 2001 if (irq < 0) { 2002 error_prepend(errp, "can't allocate LSIs: "); 2003 /* 2004 * Older machines will never support PHB hotplug, ie, this is an 2005 * init only path and QEMU will terminate. No need to rollback. 2006 */ 2007 return; 2008 } 2009 } 2010 2011 if (spapr_irq_claim(spapr, irq, true, errp) < 0) { 2012 error_prepend(errp, "can't allocate LSIs: "); 2013 goto unrealize; 2014 } 2015 2016 sphb->lsi_table[i].irq = irq; 2017 } 2018 2019 /* allocate connectors for child PCI devices */ 2020 add_drcs(sphb, phb->bus); 2021 2022 /* DMA setup */ 2023 for (i = 0; i < windows_supported; ++i) { 2024 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]); 2025 if (!tcet) { 2026 error_setg(errp, "Creating window#%d failed for %s", 2027 i, sphb->dtbusname); 2028 goto unrealize; 2029 } 2030 memory_region_add_subregion(&sphb->iommu_root, 0, 2031 spapr_tce_get_iommu(tcet)); 2032 } 2033 2034 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, 2035 spapr_phb_destroy_msi); 2036 return; 2037 2038 unrealize: 2039 spapr_phb_unrealize(dev); 2040 } 2041 2042 static int spapr_phb_children_reset(Object *child, void *opaque) 2043 { 2044 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); 2045 2046 if (dev) { 2047 device_legacy_reset(dev); 2048 } 2049 2050 return 0; 2051 } 2052 2053 void spapr_phb_dma_reset(SpaprPhbState *sphb) 2054 { 2055 int i; 2056 SpaprTceTable *tcet; 2057 2058 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) { 2059 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); 2060 2061 if (tcet && tcet->nb_table) { 2062 spapr_tce_table_disable(tcet); 2063 } 2064 } 2065 2066 /* Register default 32bit DMA window */ 2067 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]); 2068 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr, 2069 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT); 2070 } 2071 2072 static void spapr_phb_reset(DeviceState *qdev) 2073 { 2074 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev); 2075 Error *err = NULL; 2076 2077 spapr_phb_dma_reset(sphb); 2078 spapr_phb_nvgpu_free(sphb); 2079 spapr_phb_nvgpu_setup(sphb, &err); 2080 if (err) { 2081 error_report_err(err); 2082 } 2083 2084 /* Reset the IOMMU state */ 2085 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); 2086 2087 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) { 2088 spapr_phb_vfio_reset(qdev); 2089 } 2090 2091 g_hash_table_remove_all(sphb->msi); 2092 } 2093 2094 static Property spapr_phb_properties[] = { 2095 DEFINE_PROP_UINT32("index", SpaprPhbState, index, -1), 2096 DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState, mem_win_size, 2097 SPAPR_PCI_MEM32_WIN_SIZE), 2098 DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState, mem64_win_size, 2099 SPAPR_PCI_MEM64_WIN_SIZE), 2100 DEFINE_PROP_UINT64("io_win_size", SpaprPhbState, io_win_size, 2101 SPAPR_PCI_IO_WIN_SIZE), 2102 DEFINE_PROP_BOOL("dynamic-reconfiguration", SpaprPhbState, dr_enabled, 2103 true), 2104 /* Default DMA window is 0..1GB */ 2105 DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState, dma_win_addr, 0), 2106 DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState, dma_win_size, 0x40000000), 2107 DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState, dma64_win_addr, 2108 0x800000000000000ULL), 2109 DEFINE_PROP_BOOL("ddw", SpaprPhbState, ddw_enabled, true), 2110 DEFINE_PROP_UINT64("pgsz", SpaprPhbState, page_size_mask, 2111 (1ULL << 12) | (1ULL << 16) 2112 | (1ULL << 21) | (1ULL << 24)), 2113 DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1), 2114 DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState, 2115 pre_2_8_migration, false), 2116 DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState, 2117 pcie_ecs, true), 2118 DEFINE_PROP_UINT64("gpa", SpaprPhbState, nv2_gpa_win_addr, 0), 2119 DEFINE_PROP_UINT64("atsd", SpaprPhbState, nv2_atsd_win_addr, 0), 2120 DEFINE_PROP_BOOL("pre-5.1-associativity", SpaprPhbState, 2121 pre_5_1_assoc, false), 2122 DEFINE_PROP_END_OF_LIST(), 2123 }; 2124 2125 static const VMStateDescription vmstate_spapr_pci_lsi = { 2126 .name = "spapr_pci/lsi", 2127 .version_id = 1, 2128 .minimum_version_id = 1, 2129 .fields = (VMStateField[]) { 2130 VMSTATE_UINT32_EQUAL(irq, SpaprPciLsi, NULL), 2131 2132 VMSTATE_END_OF_LIST() 2133 }, 2134 }; 2135 2136 static const VMStateDescription vmstate_spapr_pci_msi = { 2137 .name = "spapr_pci/msi", 2138 .version_id = 1, 2139 .minimum_version_id = 1, 2140 .fields = (VMStateField []) { 2141 VMSTATE_UINT32(key, SpaprPciMsiMig), 2142 VMSTATE_UINT32(value.first_irq, SpaprPciMsiMig), 2143 VMSTATE_UINT32(value.num, SpaprPciMsiMig), 2144 VMSTATE_END_OF_LIST() 2145 }, 2146 }; 2147 2148 static int spapr_pci_pre_save(void *opaque) 2149 { 2150 SpaprPhbState *sphb = opaque; 2151 GHashTableIter iter; 2152 gpointer key, value; 2153 int i; 2154 2155 if (sphb->pre_2_8_migration) { 2156 sphb->mig_liobn = sphb->dma_liobn[0]; 2157 sphb->mig_mem_win_addr = sphb->mem_win_addr; 2158 sphb->mig_mem_win_size = sphb->mem_win_size; 2159 sphb->mig_io_win_addr = sphb->io_win_addr; 2160 sphb->mig_io_win_size = sphb->io_win_size; 2161 2162 if ((sphb->mem64_win_size != 0) 2163 && (sphb->mem64_win_addr 2164 == (sphb->mem_win_addr + sphb->mem_win_size))) { 2165 sphb->mig_mem_win_size += sphb->mem64_win_size; 2166 } 2167 } 2168 2169 g_free(sphb->msi_devs); 2170 sphb->msi_devs = NULL; 2171 sphb->msi_devs_num = g_hash_table_size(sphb->msi); 2172 if (!sphb->msi_devs_num) { 2173 return 0; 2174 } 2175 sphb->msi_devs = g_new(SpaprPciMsiMig, sphb->msi_devs_num); 2176 2177 g_hash_table_iter_init(&iter, sphb->msi); 2178 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { 2179 sphb->msi_devs[i].key = *(uint32_t *) key; 2180 sphb->msi_devs[i].value = *(SpaprPciMsi *) value; 2181 } 2182 2183 return 0; 2184 } 2185 2186 static int spapr_pci_post_save(void *opaque) 2187 { 2188 SpaprPhbState *sphb = opaque; 2189 2190 g_free(sphb->msi_devs); 2191 sphb->msi_devs = NULL; 2192 sphb->msi_devs_num = 0; 2193 return 0; 2194 } 2195 2196 static int spapr_pci_post_load(void *opaque, int version_id) 2197 { 2198 SpaprPhbState *sphb = opaque; 2199 gpointer key, value; 2200 int i; 2201 2202 for (i = 0; i < sphb->msi_devs_num; ++i) { 2203 key = g_memdup(&sphb->msi_devs[i].key, 2204 sizeof(sphb->msi_devs[i].key)); 2205 value = g_memdup(&sphb->msi_devs[i].value, 2206 sizeof(sphb->msi_devs[i].value)); 2207 g_hash_table_insert(sphb->msi, key, value); 2208 } 2209 g_free(sphb->msi_devs); 2210 sphb->msi_devs = NULL; 2211 sphb->msi_devs_num = 0; 2212 2213 return 0; 2214 } 2215 2216 static bool pre_2_8_migration(void *opaque, int version_id) 2217 { 2218 SpaprPhbState *sphb = opaque; 2219 2220 return sphb->pre_2_8_migration; 2221 } 2222 2223 static const VMStateDescription vmstate_spapr_pci = { 2224 .name = "spapr_pci", 2225 .version_id = 2, 2226 .minimum_version_id = 2, 2227 .pre_save = spapr_pci_pre_save, 2228 .post_save = spapr_pci_post_save, 2229 .post_load = spapr_pci_post_load, 2230 .fields = (VMStateField[]) { 2231 VMSTATE_UINT64_EQUAL(buid, SpaprPhbState, NULL), 2232 VMSTATE_UINT32_TEST(mig_liobn, SpaprPhbState, pre_2_8_migration), 2233 VMSTATE_UINT64_TEST(mig_mem_win_addr, SpaprPhbState, pre_2_8_migration), 2234 VMSTATE_UINT64_TEST(mig_mem_win_size, SpaprPhbState, pre_2_8_migration), 2235 VMSTATE_UINT64_TEST(mig_io_win_addr, SpaprPhbState, pre_2_8_migration), 2236 VMSTATE_UINT64_TEST(mig_io_win_size, SpaprPhbState, pre_2_8_migration), 2237 VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0, 2238 vmstate_spapr_pci_lsi, SpaprPciLsi), 2239 VMSTATE_INT32(msi_devs_num, SpaprPhbState), 2240 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, SpaprPhbState, msi_devs_num, 0, 2241 vmstate_spapr_pci_msi, SpaprPciMsiMig), 2242 VMSTATE_END_OF_LIST() 2243 }, 2244 }; 2245 2246 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, 2247 PCIBus *rootbus) 2248 { 2249 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); 2250 2251 return sphb->dtbusname; 2252 } 2253 2254 static void spapr_phb_class_init(ObjectClass *klass, void *data) 2255 { 2256 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 2257 DeviceClass *dc = DEVICE_CLASS(klass); 2258 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); 2259 2260 hc->root_bus_path = spapr_phb_root_bus_path; 2261 dc->realize = spapr_phb_realize; 2262 dc->unrealize = spapr_phb_unrealize; 2263 device_class_set_props(dc, spapr_phb_properties); 2264 dc->reset = spapr_phb_reset; 2265 dc->vmsd = &vmstate_spapr_pci; 2266 /* Supported by TYPE_SPAPR_MACHINE */ 2267 dc->user_creatable = true; 2268 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 2269 hp->pre_plug = spapr_pci_pre_plug; 2270 hp->plug = spapr_pci_plug; 2271 hp->unplug = spapr_pci_unplug; 2272 hp->unplug_request = spapr_pci_unplug_request; 2273 } 2274 2275 static const TypeInfo spapr_phb_info = { 2276 .name = TYPE_SPAPR_PCI_HOST_BRIDGE, 2277 .parent = TYPE_PCI_HOST_BRIDGE, 2278 .instance_size = sizeof(SpaprPhbState), 2279 .instance_finalize = spapr_phb_finalizefn, 2280 .class_init = spapr_phb_class_init, 2281 .interfaces = (InterfaceInfo[]) { 2282 { TYPE_HOTPLUG_HANDLER }, 2283 { } 2284 } 2285 }; 2286 2287 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, 2288 void *opaque) 2289 { 2290 unsigned int *bus_no = opaque; 2291 PCIBus *sec_bus = NULL; 2292 2293 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 2294 PCI_HEADER_TYPE_BRIDGE)) { 2295 return; 2296 } 2297 2298 (*bus_no)++; 2299 pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1); 2300 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); 2301 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 2302 2303 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 2304 if (!sec_bus) { 2305 return; 2306 } 2307 2308 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 2309 spapr_phb_pci_enumerate_bridge, bus_no); 2310 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 2311 } 2312 2313 static void spapr_phb_pci_enumerate(SpaprPhbState *phb) 2314 { 2315 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 2316 unsigned int bus_no = 0; 2317 2318 pci_for_each_device(bus, pci_bus_num(bus), 2319 spapr_phb_pci_enumerate_bridge, 2320 &bus_no); 2321 2322 } 2323 2324 int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb, 2325 uint32_t intc_phandle, void *fdt, int *node_offset) 2326 { 2327 int bus_off, i, j, ret; 2328 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; 2329 struct { 2330 uint32_t hi; 2331 uint64_t child; 2332 uint64_t parent; 2333 uint64_t size; 2334 } QEMU_PACKED ranges[] = { 2335 { 2336 cpu_to_be32(b_ss(1)), cpu_to_be64(0), 2337 cpu_to_be64(phb->io_win_addr), 2338 cpu_to_be64(memory_region_size(&phb->iospace)), 2339 }, 2340 { 2341 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), 2342 cpu_to_be64(phb->mem_win_addr), 2343 cpu_to_be64(phb->mem_win_size), 2344 }, 2345 { 2346 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr), 2347 cpu_to_be64(phb->mem64_win_addr), 2348 cpu_to_be64(phb->mem64_win_size), 2349 }, 2350 }; 2351 const unsigned sizeof_ranges = 2352 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]); 2353 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; 2354 uint32_t interrupt_map_mask[] = { 2355 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; 2356 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; 2357 uint32_t ddw_applicable[] = { 2358 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW), 2359 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW), 2360 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW) 2361 }; 2362 uint32_t ddw_extensions[] = { 2363 cpu_to_be32(1), 2364 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW) 2365 }; 2366 SpaprTceTable *tcet; 2367 SpaprDrc *drc; 2368 Error *err = NULL; 2369 2370 /* Start populating the FDT */ 2371 _FDT(bus_off = fdt_add_subnode(fdt, 0, phb->dtbusname)); 2372 if (node_offset) { 2373 *node_offset = bus_off; 2374 } 2375 2376 /* Write PHB properties */ 2377 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); 2378 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); 2379 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); 2380 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); 2381 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); 2382 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); 2383 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); 2384 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); 2385 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", 2386 spapr_irq_nr_msis(spapr))); 2387 2388 /* Dynamic DMA window */ 2389 if (phb->ddw_enabled) { 2390 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable, 2391 sizeof(ddw_applicable))); 2392 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions", 2393 &ddw_extensions, sizeof(ddw_extensions))); 2394 } 2395 2396 /* Advertise NUMA via ibm,associativity */ 2397 if (phb->numa_node != -1) { 2398 spapr_numa_write_associativity_dt(spapr, fdt, bus_off, phb->numa_node); 2399 } 2400 2401 /* Build the interrupt-map, this must matches what is done 2402 * in pci_swizzle_map_irq_fn 2403 */ 2404 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", 2405 &interrupt_map_mask, sizeof(interrupt_map_mask))); 2406 for (i = 0; i < PCI_SLOT_MAX; i++) { 2407 for (j = 0; j < PCI_NUM_PINS; j++) { 2408 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; 2409 int lsi_num = pci_swizzle(i, j); 2410 2411 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); 2412 irqmap[1] = 0; 2413 irqmap[2] = 0; 2414 irqmap[3] = cpu_to_be32(j+1); 2415 irqmap[4] = cpu_to_be32(intc_phandle); 2416 spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true); 2417 } 2418 } 2419 /* Write interrupt map */ 2420 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, 2421 sizeof(interrupt_map))); 2422 2423 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]); 2424 if (!tcet) { 2425 return -1; 2426 } 2427 spapr_dma_dt(fdt, bus_off, "ibm,dma-window", 2428 tcet->liobn, tcet->bus_offset, 2429 tcet->nb_table << tcet->page_shift); 2430 2431 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, phb->index); 2432 if (drc) { 2433 uint32_t drc_index = cpu_to_be32(spapr_drc_index(drc)); 2434 2435 _FDT(fdt_setprop(fdt, bus_off, "ibm,my-drc-index", &drc_index, 2436 sizeof(drc_index))); 2437 } 2438 2439 /* Walk the bridges and program the bus numbers*/ 2440 spapr_phb_pci_enumerate(phb); 2441 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); 2442 2443 /* Walk the bridge and subordinate buses */ 2444 ret = spapr_dt_pci_bus(phb, PCI_HOST_BRIDGE(phb)->bus, fdt, bus_off); 2445 if (ret < 0) { 2446 return ret; 2447 } 2448 2449 spapr_phb_nvgpu_populate_dt(phb, fdt, bus_off, &err); 2450 if (err) { 2451 error_report_err(err); 2452 } 2453 spapr_phb_nvgpu_ram_populate_dt(phb, fdt); 2454 2455 return 0; 2456 } 2457 2458 void spapr_pci_rtas_init(void) 2459 { 2460 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", 2461 rtas_read_pci_config); 2462 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", 2463 rtas_write_pci_config); 2464 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", 2465 rtas_ibm_read_pci_config); 2466 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", 2467 rtas_ibm_write_pci_config); 2468 if (msi_nonbroken) { 2469 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, 2470 "ibm,query-interrupt-source-number", 2471 rtas_ibm_query_interrupt_source_number); 2472 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", 2473 rtas_ibm_change_msi); 2474 } 2475 2476 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, 2477 "ibm,set-eeh-option", 2478 rtas_ibm_set_eeh_option); 2479 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, 2480 "ibm,get-config-addr-info2", 2481 rtas_ibm_get_config_addr_info2); 2482 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, 2483 "ibm,read-slot-reset-state2", 2484 rtas_ibm_read_slot_reset_state2); 2485 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, 2486 "ibm,set-slot-reset", 2487 rtas_ibm_set_slot_reset); 2488 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, 2489 "ibm,configure-pe", 2490 rtas_ibm_configure_pe); 2491 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, 2492 "ibm,slot-error-detail", 2493 rtas_ibm_slot_error_detail); 2494 } 2495 2496 static void spapr_pci_register_types(void) 2497 { 2498 type_register_static(&spapr_phb_info); 2499 } 2500 2501 type_init(spapr_pci_register_types) 2502 2503 static int spapr_switch_one_vga(DeviceState *dev, void *opaque) 2504 { 2505 bool be = *(bool *)opaque; 2506 2507 if (object_dynamic_cast(OBJECT(dev), "VGA") 2508 || object_dynamic_cast(OBJECT(dev), "secondary-vga") 2509 || object_dynamic_cast(OBJECT(dev), "bochs-display") 2510 || object_dynamic_cast(OBJECT(dev), "virtio-vga")) { 2511 object_property_set_bool(OBJECT(dev), "big-endian-framebuffer", be, 2512 &error_abort); 2513 } 2514 return 0; 2515 } 2516 2517 void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian) 2518 { 2519 SpaprPhbState *sphb; 2520 2521 /* 2522 * For backward compatibility with existing guests, we switch 2523 * the endianness of the VGA controller when changing the guest 2524 * interrupt mode 2525 */ 2526 QLIST_FOREACH(sphb, &spapr->phbs, list) { 2527 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; 2528 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, 2529 &big_endian); 2530 } 2531 } 2532