1 /* 2 * QEMU PAPR Storage Class Memory Interfaces 3 * 4 * Copyright (c) 2019-2020, IBM Corporation. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qemu/cutils.h" 26 #include "qapi/error.h" 27 #include "hw/ppc/spapr_drc.h" 28 #include "hw/ppc/spapr_nvdimm.h" 29 #include "hw/mem/nvdimm.h" 30 #include "qemu/nvdimm-utils.h" 31 #include "hw/ppc/fdt.h" 32 #include "qemu/range.h" 33 #include "hw/ppc/spapr_numa.h" 34 #include "block/thread-pool.h" 35 #include "migration/vmstate.h" 36 #include "qemu/pmem.h" 37 #include "hw/qdev-properties.h" 38 39 /* DIMM health bitmap bitmap indicators. Taken from kernel's papr_scm.c */ 40 /* SCM device is unable to persist memory contents */ 41 #define PAPR_PMEM_UNARMED PPC_BIT(0) 42 43 /* 44 * The nvdimm size should be aligned to SCM block size. 45 * The SCM block size should be aligned to SPAPR_MEMORY_BLOCK_SIZE 46 * in order to have SCM regions not to overlap with dimm memory regions. 47 * The SCM devices can have variable block sizes. For now, fixing the 48 * block size to the minimum value. 49 */ 50 #define SPAPR_MINIMUM_SCM_BLOCK_SIZE SPAPR_MEMORY_BLOCK_SIZE 51 52 /* Have an explicit check for alignment */ 53 QEMU_BUILD_BUG_ON(SPAPR_MINIMUM_SCM_BLOCK_SIZE % SPAPR_MEMORY_BLOCK_SIZE); 54 55 #define TYPE_SPAPR_NVDIMM "spapr-nvdimm" 56 OBJECT_DECLARE_TYPE(SpaprNVDIMMDevice, SPAPRNVDIMMClass, SPAPR_NVDIMM) 57 58 struct SPAPRNVDIMMClass { 59 /* private */ 60 NVDIMMClass parent_class; 61 62 /* public */ 63 void (*realize)(NVDIMMDevice *dimm, Error **errp); 64 void (*unrealize)(NVDIMMDevice *dimm, Error **errp); 65 }; 66 67 bool spapr_nvdimm_validate(HotplugHandler *hotplug_dev, NVDIMMDevice *nvdimm, 68 uint64_t size, Error **errp) 69 { 70 const MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 71 const MachineState *ms = MACHINE(hotplug_dev); 72 PCDIMMDevice *dimm = PC_DIMM(nvdimm); 73 MemoryRegion *mr = host_memory_backend_get_memory(dimm->hostmem); 74 g_autofree char *uuidstr = NULL; 75 QemuUUID uuid; 76 int ret; 77 78 if (!mc->nvdimm_supported) { 79 error_setg(errp, "NVDIMM hotplug not supported for this machine"); 80 return false; 81 } 82 83 if (!ms->nvdimms_state->is_enabled) { 84 error_setg(errp, "nvdimm device found but 'nvdimm=off' was set"); 85 return false; 86 } 87 88 if (object_property_get_int(OBJECT(nvdimm), NVDIMM_LABEL_SIZE_PROP, 89 &error_abort) == 0) { 90 error_setg(errp, "PAPR requires NVDIMM devices to have label-size set"); 91 return false; 92 } 93 94 if (size % SPAPR_MINIMUM_SCM_BLOCK_SIZE) { 95 error_setg(errp, "PAPR requires NVDIMM memory size (excluding label)" 96 " to be a multiple of %" PRIu64 "MB", 97 SPAPR_MINIMUM_SCM_BLOCK_SIZE / MiB); 98 return false; 99 } 100 101 uuidstr = object_property_get_str(OBJECT(nvdimm), NVDIMM_UUID_PROP, 102 &error_abort); 103 ret = qemu_uuid_parse(uuidstr, &uuid); 104 g_assert(!ret); 105 106 if (qemu_uuid_is_null(&uuid)) { 107 error_setg(errp, "NVDIMM device requires the uuid to be set"); 108 return false; 109 } 110 111 if (object_dynamic_cast(OBJECT(nvdimm), TYPE_SPAPR_NVDIMM) && 112 (memory_region_get_fd(mr) < 0)) { 113 error_setg(errp, "spapr-nvdimm device requires the " 114 "memdev %s to be of memory-backend-file type", 115 object_get_canonical_path_component(OBJECT(dimm->hostmem))); 116 return false; 117 } 118 119 return true; 120 } 121 122 123 void spapr_add_nvdimm(DeviceState *dev, uint64_t slot) 124 { 125 SpaprDrc *drc; 126 bool hotplugged = spapr_drc_hotplugged(dev); 127 128 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PMEM, slot); 129 g_assert(drc); 130 131 /* 132 * pc_dimm_get_free_slot() provided a free slot at pre-plug. The 133 * corresponding DRC is thus assumed to be attachable. 134 */ 135 spapr_drc_attach(drc, dev); 136 137 if (hotplugged) { 138 spapr_hotplug_req_add_by_index(drc); 139 } 140 } 141 142 static int spapr_dt_nvdimm(SpaprMachineState *spapr, void *fdt, 143 int parent_offset, NVDIMMDevice *nvdimm) 144 { 145 int child_offset; 146 char *buf; 147 SpaprDrc *drc; 148 uint32_t drc_idx; 149 uint32_t node = object_property_get_uint(OBJECT(nvdimm), PC_DIMM_NODE_PROP, 150 &error_abort); 151 uint64_t slot = object_property_get_uint(OBJECT(nvdimm), PC_DIMM_SLOT_PROP, 152 &error_abort); 153 uint64_t lsize = nvdimm->label_size; 154 uint64_t size = object_property_get_int(OBJECT(nvdimm), PC_DIMM_SIZE_PROP, 155 NULL); 156 157 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PMEM, slot); 158 g_assert(drc); 159 160 drc_idx = spapr_drc_index(drc); 161 162 buf = g_strdup_printf("ibm,pmemory@%x", drc_idx); 163 child_offset = fdt_add_subnode(fdt, parent_offset, buf); 164 g_free(buf); 165 166 _FDT(child_offset); 167 168 _FDT((fdt_setprop_cell(fdt, child_offset, "reg", drc_idx))); 169 _FDT((fdt_setprop_string(fdt, child_offset, "compatible", "ibm,pmemory"))); 170 _FDT((fdt_setprop_string(fdt, child_offset, "device_type", "ibm,pmemory"))); 171 172 spapr_numa_write_associativity_dt(spapr, fdt, child_offset, node); 173 174 buf = qemu_uuid_unparse_strdup(&nvdimm->uuid); 175 _FDT((fdt_setprop_string(fdt, child_offset, "ibm,unit-guid", buf))); 176 g_free(buf); 177 178 _FDT((fdt_setprop_cell(fdt, child_offset, "ibm,my-drc-index", drc_idx))); 179 180 _FDT((fdt_setprop_u64(fdt, child_offset, "ibm,block-size", 181 SPAPR_MINIMUM_SCM_BLOCK_SIZE))); 182 _FDT((fdt_setprop_u64(fdt, child_offset, "ibm,number-of-blocks", 183 size / SPAPR_MINIMUM_SCM_BLOCK_SIZE))); 184 _FDT((fdt_setprop_cell(fdt, child_offset, "ibm,metadata-size", lsize))); 185 186 _FDT((fdt_setprop_string(fdt, child_offset, "ibm,pmem-application", 187 "operating-system"))); 188 _FDT(fdt_setprop(fdt, child_offset, "ibm,cache-flush-required", NULL, 0)); 189 190 if (object_dynamic_cast(OBJECT(nvdimm), TYPE_SPAPR_NVDIMM)) { 191 bool is_pmem = false, pmem_override = false; 192 PCDIMMDevice *dimm = PC_DIMM(nvdimm); 193 HostMemoryBackend *hostmem = dimm->hostmem; 194 195 is_pmem = object_property_get_bool(OBJECT(hostmem), "pmem", NULL); 196 pmem_override = object_property_get_bool(OBJECT(nvdimm), 197 "pmem-override", NULL); 198 if (!is_pmem || pmem_override) { 199 _FDT(fdt_setprop(fdt, child_offset, "ibm,hcall-flush-required", 200 NULL, 0)); 201 } 202 } 203 204 return child_offset; 205 } 206 207 int spapr_pmem_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 208 void *fdt, int *fdt_start_offset, Error **errp) 209 { 210 NVDIMMDevice *nvdimm = NVDIMM(drc->dev); 211 212 *fdt_start_offset = spapr_dt_nvdimm(spapr, fdt, 0, nvdimm); 213 214 return 0; 215 } 216 217 void spapr_dt_persistent_memory(SpaprMachineState *spapr, void *fdt) 218 { 219 int offset = fdt_subnode_offset(fdt, 0, "ibm,persistent-memory"); 220 GSList *iter, *nvdimms = nvdimm_get_device_list(); 221 222 if (offset < 0) { 223 offset = fdt_add_subnode(fdt, 0, "ibm,persistent-memory"); 224 _FDT(offset); 225 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0x1))); 226 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0x0))); 227 _FDT((fdt_setprop_string(fdt, offset, "device_type", 228 "ibm,persistent-memory"))); 229 } 230 231 /* Create DT entries for cold plugged NVDIMM devices */ 232 for (iter = nvdimms; iter; iter = iter->next) { 233 NVDIMMDevice *nvdimm = iter->data; 234 235 spapr_dt_nvdimm(spapr, fdt, offset, nvdimm); 236 } 237 g_slist_free(nvdimms); 238 239 return; 240 } 241 242 static target_ulong h_scm_read_metadata(PowerPCCPU *cpu, 243 SpaprMachineState *spapr, 244 target_ulong opcode, 245 target_ulong *args) 246 { 247 uint32_t drc_index = args[0]; 248 uint64_t offset = args[1]; 249 uint64_t len = args[2]; 250 SpaprDrc *drc = spapr_drc_by_index(drc_index); 251 NVDIMMDevice *nvdimm; 252 NVDIMMClass *ddc; 253 uint64_t data = 0; 254 uint8_t buf[8] = { 0 }; 255 256 if (!drc || !drc->dev || 257 spapr_drc_type(drc) != SPAPR_DR_CONNECTOR_TYPE_PMEM) { 258 return H_PARAMETER; 259 } 260 261 if (len != 1 && len != 2 && 262 len != 4 && len != 8) { 263 return H_P3; 264 } 265 266 nvdimm = NVDIMM(drc->dev); 267 if ((offset + len < offset) || 268 (nvdimm->label_size < len + offset)) { 269 return H_P2; 270 } 271 272 ddc = NVDIMM_GET_CLASS(nvdimm); 273 ddc->read_label_data(nvdimm, buf, len, offset); 274 275 switch (len) { 276 case 1: 277 data = ldub_p(buf); 278 break; 279 case 2: 280 data = lduw_be_p(buf); 281 break; 282 case 4: 283 data = ldl_be_p(buf); 284 break; 285 case 8: 286 data = ldq_be_p(buf); 287 break; 288 default: 289 g_assert_not_reached(); 290 } 291 292 args[0] = data; 293 294 return H_SUCCESS; 295 } 296 297 static target_ulong h_scm_write_metadata(PowerPCCPU *cpu, 298 SpaprMachineState *spapr, 299 target_ulong opcode, 300 target_ulong *args) 301 { 302 uint32_t drc_index = args[0]; 303 uint64_t offset = args[1]; 304 uint64_t data = args[2]; 305 uint64_t len = args[3]; 306 SpaprDrc *drc = spapr_drc_by_index(drc_index); 307 NVDIMMDevice *nvdimm; 308 NVDIMMClass *ddc; 309 uint8_t buf[8] = { 0 }; 310 311 if (!drc || !drc->dev || 312 spapr_drc_type(drc) != SPAPR_DR_CONNECTOR_TYPE_PMEM) { 313 return H_PARAMETER; 314 } 315 316 if (len != 1 && len != 2 && 317 len != 4 && len != 8) { 318 return H_P4; 319 } 320 321 nvdimm = NVDIMM(drc->dev); 322 if ((offset + len < offset) || 323 (nvdimm->label_size < len + offset)) { 324 return H_P2; 325 } 326 327 switch (len) { 328 case 1: 329 if (data & 0xffffffffffffff00) { 330 return H_P2; 331 } 332 stb_p(buf, data); 333 break; 334 case 2: 335 if (data & 0xffffffffffff0000) { 336 return H_P2; 337 } 338 stw_be_p(buf, data); 339 break; 340 case 4: 341 if (data & 0xffffffff00000000) { 342 return H_P2; 343 } 344 stl_be_p(buf, data); 345 break; 346 case 8: 347 stq_be_p(buf, data); 348 break; 349 default: 350 g_assert_not_reached(); 351 } 352 353 ddc = NVDIMM_GET_CLASS(nvdimm); 354 ddc->write_label_data(nvdimm, buf, len, offset); 355 356 return H_SUCCESS; 357 } 358 359 static target_ulong h_scm_bind_mem(PowerPCCPU *cpu, SpaprMachineState *spapr, 360 target_ulong opcode, target_ulong *args) 361 { 362 uint32_t drc_index = args[0]; 363 uint64_t starting_idx = args[1]; 364 uint64_t no_of_scm_blocks_to_bind = args[2]; 365 uint64_t target_logical_mem_addr = args[3]; 366 uint64_t continue_token = args[4]; 367 uint64_t size; 368 uint64_t total_no_of_scm_blocks; 369 SpaprDrc *drc = spapr_drc_by_index(drc_index); 370 hwaddr addr; 371 NVDIMMDevice *nvdimm; 372 373 if (!drc || !drc->dev || 374 spapr_drc_type(drc) != SPAPR_DR_CONNECTOR_TYPE_PMEM) { 375 return H_PARAMETER; 376 } 377 378 /* 379 * Currently continue token should be zero qemu has already bound 380 * everything and this hcall doesnt return H_BUSY. 381 */ 382 if (continue_token > 0) { 383 return H_P5; 384 } 385 386 /* Currently qemu assigns the address. */ 387 if (target_logical_mem_addr != 0xffffffffffffffff) { 388 return H_OVERLAP; 389 } 390 391 nvdimm = NVDIMM(drc->dev); 392 393 size = object_property_get_uint(OBJECT(nvdimm), 394 PC_DIMM_SIZE_PROP, &error_abort); 395 396 total_no_of_scm_blocks = size / SPAPR_MINIMUM_SCM_BLOCK_SIZE; 397 398 if (starting_idx > total_no_of_scm_blocks) { 399 return H_P2; 400 } 401 402 if (((starting_idx + no_of_scm_blocks_to_bind) < starting_idx) || 403 ((starting_idx + no_of_scm_blocks_to_bind) > total_no_of_scm_blocks)) { 404 return H_P3; 405 } 406 407 addr = object_property_get_uint(OBJECT(nvdimm), 408 PC_DIMM_ADDR_PROP, &error_abort); 409 410 addr += starting_idx * SPAPR_MINIMUM_SCM_BLOCK_SIZE; 411 412 /* Already bound, Return target logical address in R5 */ 413 args[1] = addr; 414 args[2] = no_of_scm_blocks_to_bind; 415 416 return H_SUCCESS; 417 } 418 419 typedef struct SpaprNVDIMMDeviceFlushState { 420 uint64_t continue_token; 421 int64_t hcall_ret; 422 uint32_t drcidx; 423 424 QLIST_ENTRY(SpaprNVDIMMDeviceFlushState) node; 425 } SpaprNVDIMMDeviceFlushState; 426 427 typedef struct SpaprNVDIMMDevice SpaprNVDIMMDevice; 428 struct SpaprNVDIMMDevice { 429 /* private */ 430 NVDIMMDevice parent_obj; 431 432 bool hcall_flush_required; 433 uint64_t nvdimm_flush_token; 434 QLIST_HEAD(, SpaprNVDIMMDeviceFlushState) pending_nvdimm_flush_states; 435 QLIST_HEAD(, SpaprNVDIMMDeviceFlushState) completed_nvdimm_flush_states; 436 437 /* public */ 438 439 /* 440 * The 'on' value for this property forced the qemu to enable the hcall 441 * flush for the nvdimm device even if the backend is a pmem 442 */ 443 bool pmem_override; 444 }; 445 446 static int flush_worker_cb(void *opaque) 447 { 448 SpaprNVDIMMDeviceFlushState *state = opaque; 449 SpaprDrc *drc = spapr_drc_by_index(state->drcidx); 450 PCDIMMDevice *dimm = PC_DIMM(drc->dev); 451 HostMemoryBackend *backend = MEMORY_BACKEND(dimm->hostmem); 452 int backend_fd = memory_region_get_fd(&backend->mr); 453 454 if (object_property_get_bool(OBJECT(backend), "pmem", NULL)) { 455 MemoryRegion *mr = host_memory_backend_get_memory(dimm->hostmem); 456 void *ptr = memory_region_get_ram_ptr(mr); 457 size_t size = object_property_get_uint(OBJECT(dimm), PC_DIMM_SIZE_PROP, 458 NULL); 459 460 /* flush pmem backend */ 461 pmem_persist(ptr, size); 462 } else { 463 /* flush raw backing image */ 464 if (qemu_fdatasync(backend_fd) < 0) { 465 error_report("papr_scm: Could not sync nvdimm to backend file: %s", 466 strerror(errno)); 467 return H_HARDWARE; 468 } 469 } 470 471 return H_SUCCESS; 472 } 473 474 static void spapr_nvdimm_flush_completion_cb(void *opaque, int hcall_ret) 475 { 476 SpaprNVDIMMDeviceFlushState *state = opaque; 477 SpaprDrc *drc = spapr_drc_by_index(state->drcidx); 478 SpaprNVDIMMDevice *s_nvdimm = SPAPR_NVDIMM(drc->dev); 479 480 state->hcall_ret = hcall_ret; 481 QLIST_REMOVE(state, node); 482 QLIST_INSERT_HEAD(&s_nvdimm->completed_nvdimm_flush_states, state, node); 483 } 484 485 static int spapr_nvdimm_flush_post_load(void *opaque, int version_id) 486 { 487 SpaprNVDIMMDevice *s_nvdimm = (SpaprNVDIMMDevice *)opaque; 488 SpaprNVDIMMDeviceFlushState *state; 489 ThreadPool *pool = aio_get_thread_pool(qemu_get_aio_context()); 490 HostMemoryBackend *backend = MEMORY_BACKEND(PC_DIMM(s_nvdimm)->hostmem); 491 bool is_pmem = object_property_get_bool(OBJECT(backend), "pmem", NULL); 492 bool pmem_override = object_property_get_bool(OBJECT(s_nvdimm), 493 "pmem-override", NULL); 494 bool dest_hcall_flush_required = pmem_override || !is_pmem; 495 496 if (!s_nvdimm->hcall_flush_required && dest_hcall_flush_required) { 497 error_report("The file backend for the spapr-nvdimm device %s at " 498 "source is a pmem, use pmem=on and pmem-override=off to " 499 "continue.", DEVICE(s_nvdimm)->id); 500 return -EINVAL; 501 } 502 if (s_nvdimm->hcall_flush_required && !dest_hcall_flush_required) { 503 error_report("The guest expects hcall-flush support for the " 504 "spapr-nvdimm device %s, use pmem_override=on to " 505 "continue.", DEVICE(s_nvdimm)->id); 506 return -EINVAL; 507 } 508 509 QLIST_FOREACH(state, &s_nvdimm->pending_nvdimm_flush_states, node) { 510 thread_pool_submit_aio(pool, flush_worker_cb, state, 511 spapr_nvdimm_flush_completion_cb, state); 512 } 513 514 return 0; 515 } 516 517 static const VMStateDescription vmstate_spapr_nvdimm_flush_state = { 518 .name = "spapr_nvdimm_flush_state", 519 .version_id = 1, 520 .minimum_version_id = 1, 521 .fields = (VMStateField[]) { 522 VMSTATE_UINT64(continue_token, SpaprNVDIMMDeviceFlushState), 523 VMSTATE_INT64(hcall_ret, SpaprNVDIMMDeviceFlushState), 524 VMSTATE_UINT32(drcidx, SpaprNVDIMMDeviceFlushState), 525 VMSTATE_END_OF_LIST() 526 }, 527 }; 528 529 const VMStateDescription vmstate_spapr_nvdimm_states = { 530 .name = "spapr_nvdimm_states", 531 .version_id = 1, 532 .minimum_version_id = 1, 533 .post_load = spapr_nvdimm_flush_post_load, 534 .fields = (VMStateField[]) { 535 VMSTATE_BOOL(hcall_flush_required, SpaprNVDIMMDevice), 536 VMSTATE_UINT64(nvdimm_flush_token, SpaprNVDIMMDevice), 537 VMSTATE_QLIST_V(completed_nvdimm_flush_states, SpaprNVDIMMDevice, 1, 538 vmstate_spapr_nvdimm_flush_state, 539 SpaprNVDIMMDeviceFlushState, node), 540 VMSTATE_QLIST_V(pending_nvdimm_flush_states, SpaprNVDIMMDevice, 1, 541 vmstate_spapr_nvdimm_flush_state, 542 SpaprNVDIMMDeviceFlushState, node), 543 VMSTATE_END_OF_LIST() 544 }, 545 }; 546 547 /* 548 * Assign a token and reserve it for the new flush state. 549 */ 550 static SpaprNVDIMMDeviceFlushState *spapr_nvdimm_init_new_flush_state( 551 SpaprNVDIMMDevice *spapr_nvdimm) 552 { 553 SpaprNVDIMMDeviceFlushState *state; 554 555 state = g_malloc0(sizeof(*state)); 556 557 spapr_nvdimm->nvdimm_flush_token++; 558 /* Token zero is presumed as no job pending. Assert on overflow to zero */ 559 g_assert(spapr_nvdimm->nvdimm_flush_token != 0); 560 561 state->continue_token = spapr_nvdimm->nvdimm_flush_token; 562 563 QLIST_INSERT_HEAD(&spapr_nvdimm->pending_nvdimm_flush_states, state, node); 564 565 return state; 566 } 567 568 /* 569 * spapr_nvdimm_finish_flushes 570 * Waits for all pending flush requests to complete 571 * their execution and free the states 572 */ 573 void spapr_nvdimm_finish_flushes(void) 574 { 575 SpaprNVDIMMDeviceFlushState *state, *next; 576 GSList *list, *nvdimms; 577 578 /* 579 * Called on reset path, the main loop thread which calls 580 * the pending BHs has gotten out running in the reset path, 581 * finally reaching here. Other code path being guest 582 * h_client_architecture_support, thats early boot up. 583 */ 584 nvdimms = nvdimm_get_device_list(); 585 for (list = nvdimms; list; list = list->next) { 586 NVDIMMDevice *nvdimm = list->data; 587 if (object_dynamic_cast(OBJECT(nvdimm), TYPE_SPAPR_NVDIMM)) { 588 SpaprNVDIMMDevice *s_nvdimm = SPAPR_NVDIMM(nvdimm); 589 while (!QLIST_EMPTY(&s_nvdimm->pending_nvdimm_flush_states)) { 590 aio_poll(qemu_get_aio_context(), true); 591 } 592 593 QLIST_FOREACH_SAFE(state, &s_nvdimm->completed_nvdimm_flush_states, 594 node, next) { 595 QLIST_REMOVE(state, node); 596 g_free(state); 597 } 598 } 599 } 600 g_slist_free(nvdimms); 601 } 602 603 /* 604 * spapr_nvdimm_get_flush_status 605 * Fetches the status of the hcall worker and returns 606 * H_LONG_BUSY_ORDER_10_MSEC if the worker is still running. 607 */ 608 static int spapr_nvdimm_get_flush_status(SpaprNVDIMMDevice *s_nvdimm, 609 uint64_t token) 610 { 611 SpaprNVDIMMDeviceFlushState *state, *node; 612 613 QLIST_FOREACH(state, &s_nvdimm->pending_nvdimm_flush_states, node) { 614 if (state->continue_token == token) { 615 return H_LONG_BUSY_ORDER_10_MSEC; 616 } 617 } 618 619 QLIST_FOREACH_SAFE(state, &s_nvdimm->completed_nvdimm_flush_states, 620 node, node) { 621 if (state->continue_token == token) { 622 int ret = state->hcall_ret; 623 QLIST_REMOVE(state, node); 624 g_free(state); 625 return ret; 626 } 627 } 628 629 /* If not found in complete list too, invalid token */ 630 return H_P2; 631 } 632 633 /* 634 * H_SCM_FLUSH 635 * Input: drc_index, continue-token 636 * Out: continue-token 637 * Return Value: H_SUCCESS, H_Parameter, H_P2, H_LONG_BUSY_ORDER_10_MSEC, 638 * H_UNSUPPORTED 639 * 640 * Given a DRC Index Flush the data to backend NVDIMM device. The hcall returns 641 * H_LONG_BUSY_ORDER_10_MSEC when the flush takes longer time and the hcall 642 * needs to be issued multiple times in order to be completely serviced. The 643 * continue-token from the output to be passed in the argument list of 644 * subsequent hcalls until the hcall is completely serviced at which point 645 * H_SUCCESS or other error is returned. 646 */ 647 static target_ulong h_scm_flush(PowerPCCPU *cpu, SpaprMachineState *spapr, 648 target_ulong opcode, target_ulong *args) 649 { 650 int ret; 651 uint32_t drc_index = args[0]; 652 uint64_t continue_token = args[1]; 653 SpaprDrc *drc = spapr_drc_by_index(drc_index); 654 PCDIMMDevice *dimm; 655 HostMemoryBackend *backend = NULL; 656 SpaprNVDIMMDeviceFlushState *state; 657 ThreadPool *pool = aio_get_thread_pool(qemu_get_aio_context()); 658 int fd; 659 660 if (!drc || !drc->dev || 661 spapr_drc_type(drc) != SPAPR_DR_CONNECTOR_TYPE_PMEM) { 662 return H_PARAMETER; 663 } 664 665 dimm = PC_DIMM(drc->dev); 666 if (!object_dynamic_cast(OBJECT(dimm), TYPE_SPAPR_NVDIMM)) { 667 return H_PARAMETER; 668 } 669 if (continue_token == 0) { 670 bool is_pmem = false, pmem_override = false; 671 backend = MEMORY_BACKEND(dimm->hostmem); 672 fd = memory_region_get_fd(&backend->mr); 673 674 if (fd < 0) { 675 return H_UNSUPPORTED; 676 } 677 678 is_pmem = object_property_get_bool(OBJECT(backend), "pmem", NULL); 679 pmem_override = object_property_get_bool(OBJECT(dimm), 680 "pmem-override", NULL); 681 if (is_pmem && !pmem_override) { 682 return H_UNSUPPORTED; 683 } 684 685 state = spapr_nvdimm_init_new_flush_state(SPAPR_NVDIMM(dimm)); 686 if (!state) { 687 return H_HARDWARE; 688 } 689 690 state->drcidx = drc_index; 691 692 thread_pool_submit_aio(pool, flush_worker_cb, state, 693 spapr_nvdimm_flush_completion_cb, state); 694 695 continue_token = state->continue_token; 696 } 697 698 ret = spapr_nvdimm_get_flush_status(SPAPR_NVDIMM(dimm), continue_token); 699 if (H_IS_LONG_BUSY(ret)) { 700 args[0] = continue_token; 701 } 702 703 return ret; 704 } 705 706 static target_ulong h_scm_unbind_mem(PowerPCCPU *cpu, SpaprMachineState *spapr, 707 target_ulong opcode, target_ulong *args) 708 { 709 uint32_t drc_index = args[0]; 710 uint64_t starting_scm_logical_addr = args[1]; 711 uint64_t no_of_scm_blocks_to_unbind = args[2]; 712 uint64_t continue_token = args[3]; 713 uint64_t size_to_unbind; 714 Range blockrange = range_empty; 715 Range nvdimmrange = range_empty; 716 SpaprDrc *drc = spapr_drc_by_index(drc_index); 717 NVDIMMDevice *nvdimm; 718 uint64_t size, addr; 719 720 if (!drc || !drc->dev || 721 spapr_drc_type(drc) != SPAPR_DR_CONNECTOR_TYPE_PMEM) { 722 return H_PARAMETER; 723 } 724 725 /* continue_token should be zero as this hcall doesn't return H_BUSY. */ 726 if (continue_token > 0) { 727 return H_P4; 728 } 729 730 /* Check if starting_scm_logical_addr is block aligned */ 731 if (!QEMU_IS_ALIGNED(starting_scm_logical_addr, 732 SPAPR_MINIMUM_SCM_BLOCK_SIZE)) { 733 return H_P2; 734 } 735 736 size_to_unbind = no_of_scm_blocks_to_unbind * SPAPR_MINIMUM_SCM_BLOCK_SIZE; 737 if (no_of_scm_blocks_to_unbind == 0 || no_of_scm_blocks_to_unbind != 738 size_to_unbind / SPAPR_MINIMUM_SCM_BLOCK_SIZE) { 739 return H_P3; 740 } 741 742 nvdimm = NVDIMM(drc->dev); 743 size = object_property_get_int(OBJECT(nvdimm), PC_DIMM_SIZE_PROP, 744 &error_abort); 745 addr = object_property_get_int(OBJECT(nvdimm), PC_DIMM_ADDR_PROP, 746 &error_abort); 747 748 range_init_nofail(&nvdimmrange, addr, size); 749 range_init_nofail(&blockrange, starting_scm_logical_addr, size_to_unbind); 750 751 if (!range_contains_range(&nvdimmrange, &blockrange)) { 752 return H_P3; 753 } 754 755 args[1] = no_of_scm_blocks_to_unbind; 756 757 /* let unplug take care of actual unbind */ 758 return H_SUCCESS; 759 } 760 761 #define H_UNBIND_SCOPE_ALL 0x1 762 #define H_UNBIND_SCOPE_DRC 0x2 763 764 static target_ulong h_scm_unbind_all(PowerPCCPU *cpu, SpaprMachineState *spapr, 765 target_ulong opcode, target_ulong *args) 766 { 767 uint64_t target_scope = args[0]; 768 uint32_t drc_index = args[1]; 769 uint64_t continue_token = args[2]; 770 NVDIMMDevice *nvdimm; 771 uint64_t size; 772 uint64_t no_of_scm_blocks_unbound = 0; 773 774 /* continue_token should be zero as this hcall doesn't return H_BUSY. */ 775 if (continue_token > 0) { 776 return H_P4; 777 } 778 779 if (target_scope == H_UNBIND_SCOPE_DRC) { 780 SpaprDrc *drc = spapr_drc_by_index(drc_index); 781 782 if (!drc || !drc->dev || 783 spapr_drc_type(drc) != SPAPR_DR_CONNECTOR_TYPE_PMEM) { 784 return H_P2; 785 } 786 787 nvdimm = NVDIMM(drc->dev); 788 size = object_property_get_int(OBJECT(nvdimm), PC_DIMM_SIZE_PROP, 789 &error_abort); 790 791 no_of_scm_blocks_unbound = size / SPAPR_MINIMUM_SCM_BLOCK_SIZE; 792 } else if (target_scope == H_UNBIND_SCOPE_ALL) { 793 GSList *list, *nvdimms; 794 795 nvdimms = nvdimm_get_device_list(); 796 for (list = nvdimms; list; list = list->next) { 797 nvdimm = list->data; 798 size = object_property_get_int(OBJECT(nvdimm), PC_DIMM_SIZE_PROP, 799 &error_abort); 800 801 no_of_scm_blocks_unbound += size / SPAPR_MINIMUM_SCM_BLOCK_SIZE; 802 } 803 g_slist_free(nvdimms); 804 } else { 805 return H_PARAMETER; 806 } 807 808 args[1] = no_of_scm_blocks_unbound; 809 810 /* let unplug take care of actual unbind */ 811 return H_SUCCESS; 812 } 813 814 static target_ulong h_scm_health(PowerPCCPU *cpu, SpaprMachineState *spapr, 815 target_ulong opcode, target_ulong *args) 816 { 817 818 NVDIMMDevice *nvdimm; 819 uint64_t hbitmap = 0; 820 uint32_t drc_index = args[0]; 821 SpaprDrc *drc = spapr_drc_by_index(drc_index); 822 const uint64_t hbitmap_mask = PAPR_PMEM_UNARMED; 823 824 825 /* Ensure that the drc is valid & is valid PMEM dimm and is plugged in */ 826 if (!drc || !drc->dev || 827 spapr_drc_type(drc) != SPAPR_DR_CONNECTOR_TYPE_PMEM) { 828 return H_PARAMETER; 829 } 830 831 nvdimm = NVDIMM(drc->dev); 832 833 /* Update if the nvdimm is unarmed and send its status via health bitmaps */ 834 if (object_property_get_bool(OBJECT(nvdimm), NVDIMM_UNARMED_PROP, NULL)) { 835 hbitmap |= PAPR_PMEM_UNARMED; 836 } 837 838 /* Update the out args with health bitmap/mask */ 839 args[0] = hbitmap; 840 args[1] = hbitmap_mask; 841 842 return H_SUCCESS; 843 } 844 845 static void spapr_scm_register_types(void) 846 { 847 /* qemu/scm specific hcalls */ 848 spapr_register_hypercall(H_SCM_READ_METADATA, h_scm_read_metadata); 849 spapr_register_hypercall(H_SCM_WRITE_METADATA, h_scm_write_metadata); 850 spapr_register_hypercall(H_SCM_BIND_MEM, h_scm_bind_mem); 851 spapr_register_hypercall(H_SCM_UNBIND_MEM, h_scm_unbind_mem); 852 spapr_register_hypercall(H_SCM_UNBIND_ALL, h_scm_unbind_all); 853 spapr_register_hypercall(H_SCM_HEALTH, h_scm_health); 854 spapr_register_hypercall(H_SCM_FLUSH, h_scm_flush); 855 } 856 857 type_init(spapr_scm_register_types) 858 859 static void spapr_nvdimm_realize(NVDIMMDevice *dimm, Error **errp) 860 { 861 SpaprNVDIMMDevice *s_nvdimm = SPAPR_NVDIMM(dimm); 862 HostMemoryBackend *backend = MEMORY_BACKEND(PC_DIMM(dimm)->hostmem); 863 bool is_pmem = object_property_get_bool(OBJECT(backend), "pmem", NULL); 864 bool pmem_override = object_property_get_bool(OBJECT(dimm), "pmem-override", 865 NULL); 866 if (!is_pmem || pmem_override) { 867 s_nvdimm->hcall_flush_required = true; 868 } 869 870 vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, 871 &vmstate_spapr_nvdimm_states, dimm); 872 } 873 874 static void spapr_nvdimm_unrealize(NVDIMMDevice *dimm) 875 { 876 vmstate_unregister(NULL, &vmstate_spapr_nvdimm_states, dimm); 877 } 878 879 static Property spapr_nvdimm_properties[] = { 880 #ifdef CONFIG_LIBPMEM 881 DEFINE_PROP_BOOL("pmem-override", SpaprNVDIMMDevice, pmem_override, false), 882 #endif 883 DEFINE_PROP_END_OF_LIST(), 884 }; 885 886 static void spapr_nvdimm_class_init(ObjectClass *oc, void *data) 887 { 888 DeviceClass *dc = DEVICE_CLASS(oc); 889 NVDIMMClass *nvc = NVDIMM_CLASS(oc); 890 891 nvc->realize = spapr_nvdimm_realize; 892 nvc->unrealize = spapr_nvdimm_unrealize; 893 894 device_class_set_props(dc, spapr_nvdimm_properties); 895 } 896 897 static void spapr_nvdimm_init(Object *obj) 898 { 899 SpaprNVDIMMDevice *s_nvdimm = SPAPR_NVDIMM(obj); 900 901 s_nvdimm->hcall_flush_required = false; 902 QLIST_INIT(&s_nvdimm->pending_nvdimm_flush_states); 903 QLIST_INIT(&s_nvdimm->completed_nvdimm_flush_states); 904 } 905 906 static TypeInfo spapr_nvdimm_info = { 907 .name = TYPE_SPAPR_NVDIMM, 908 .parent = TYPE_NVDIMM, 909 .class_init = spapr_nvdimm_class_init, 910 .class_size = sizeof(SPAPRNVDIMMClass), 911 .instance_size = sizeof(SpaprNVDIMMDevice), 912 .instance_init = spapr_nvdimm_init, 913 }; 914 915 static void spapr_nvdimm_register_types(void) 916 { 917 type_register_static(&spapr_nvdimm_info); 918 } 919 920 type_init(spapr_nvdimm_register_types) 921