1 /* 2 * QEMU PowerPC sPAPR IRQ interface 3 * 4 * Copyright (c) 2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/error-report.h" 13 #include "qapi/error.h" 14 #include "hw/ppc/spapr.h" 15 #include "hw/ppc/spapr_cpu_core.h" 16 #include "hw/ppc/spapr_xive.h" 17 #include "hw/ppc/xics.h" 18 #include "hw/ppc/xics_spapr.h" 19 #include "cpu-models.h" 20 #include "sysemu/kvm.h" 21 22 #include "trace.h" 23 24 void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis) 25 { 26 spapr->irq_map_nr = nr_msis; 27 spapr->irq_map = bitmap_new(spapr->irq_map_nr); 28 } 29 30 int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align, 31 Error **errp) 32 { 33 int irq; 34 35 /* 36 * The 'align_mask' parameter of bitmap_find_next_zero_area() 37 * should be one less than a power of 2; 0 means no 38 * alignment. Adapt the 'align' value of the former allocator 39 * to fit the requirements of bitmap_find_next_zero_area() 40 */ 41 align -= 1; 42 43 irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num, 44 align); 45 if (irq == spapr->irq_map_nr) { 46 error_setg(errp, "can't find a free %d-IRQ block", num); 47 return -1; 48 } 49 50 bitmap_set(spapr->irq_map, irq, num); 51 52 return irq + SPAPR_IRQ_MSI; 53 } 54 55 void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num) 56 { 57 bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num); 58 } 59 60 void spapr_irq_msi_reset(SpaprMachineState *spapr) 61 { 62 bitmap_clear(spapr->irq_map, 0, spapr->irq_map_nr); 63 } 64 65 static void spapr_irq_init_device(SpaprMachineState *spapr, 66 SpaprIrq *irq, Error **errp) 67 { 68 MachineState *machine = MACHINE(spapr); 69 Error *local_err = NULL; 70 71 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) { 72 irq->init_kvm(spapr, &local_err); 73 if (local_err && machine_kernel_irqchip_required(machine)) { 74 error_prepend(&local_err, 75 "kernel_irqchip requested but unavailable: "); 76 error_propagate(errp, local_err); 77 return; 78 } 79 80 if (!local_err) { 81 return; 82 } 83 84 /* 85 * We failed to initialize the KVM device, fallback to 86 * emulated mode 87 */ 88 error_prepend(&local_err, "kernel_irqchip allowed but unavailable: "); 89 warn_report_err(local_err); 90 } 91 92 irq->init_emu(spapr, errp); 93 } 94 95 /* 96 * XICS IRQ backend. 97 */ 98 99 static void spapr_irq_init_xics(SpaprMachineState *spapr, int nr_irqs, 100 Error **errp) 101 { 102 Object *obj; 103 Error *local_err = NULL; 104 105 spapr_irq_init_device(spapr, &spapr_irq_xics, &local_err); 106 if (local_err) { 107 error_propagate(errp, local_err); 108 return; 109 } 110 111 obj = object_new(TYPE_ICS_SIMPLE); 112 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); 113 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), 114 &error_fatal); 115 object_property_set_int(obj, nr_irqs, "nr-irqs", &error_fatal); 116 object_property_set_bool(obj, true, "realized", &local_err); 117 if (local_err) { 118 error_propagate(errp, local_err); 119 return; 120 } 121 122 spapr->ics = ICS_BASE(obj); 123 } 124 125 #define ICS_IRQ_FREE(ics, srcno) \ 126 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) 127 128 static int spapr_irq_claim_xics(SpaprMachineState *spapr, int irq, bool lsi, 129 Error **errp) 130 { 131 ICSState *ics = spapr->ics; 132 133 assert(ics); 134 135 if (!ics_valid_irq(ics, irq)) { 136 error_setg(errp, "IRQ %d is invalid", irq); 137 return -1; 138 } 139 140 if (!ICS_IRQ_FREE(ics, irq - ics->offset)) { 141 error_setg(errp, "IRQ %d is not free", irq); 142 return -1; 143 } 144 145 ics_set_irq_type(ics, irq - ics->offset, lsi); 146 return 0; 147 } 148 149 static void spapr_irq_free_xics(SpaprMachineState *spapr, int irq, int num) 150 { 151 ICSState *ics = spapr->ics; 152 uint32_t srcno = irq - ics->offset; 153 int i; 154 155 if (ics_valid_irq(ics, irq)) { 156 trace_spapr_irq_free(0, irq, num); 157 for (i = srcno; i < srcno + num; ++i) { 158 if (ICS_IRQ_FREE(ics, i)) { 159 trace_spapr_irq_free_warn(0, i); 160 } 161 memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); 162 } 163 } 164 } 165 166 static qemu_irq spapr_qirq_xics(SpaprMachineState *spapr, int irq) 167 { 168 ICSState *ics = spapr->ics; 169 uint32_t srcno = irq - ics->offset; 170 171 if (ics_valid_irq(ics, irq)) { 172 return spapr->qirqs[srcno]; 173 } 174 175 return NULL; 176 } 177 178 static void spapr_irq_print_info_xics(SpaprMachineState *spapr, Monitor *mon) 179 { 180 CPUState *cs; 181 182 CPU_FOREACH(cs) { 183 PowerPCCPU *cpu = POWERPC_CPU(cs); 184 185 icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon); 186 } 187 188 ics_pic_print_info(spapr->ics, mon); 189 } 190 191 static void spapr_irq_cpu_intc_create_xics(SpaprMachineState *spapr, 192 PowerPCCPU *cpu, Error **errp) 193 { 194 Error *local_err = NULL; 195 Object *obj; 196 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 197 198 obj = icp_create(OBJECT(cpu), TYPE_ICP, XICS_FABRIC(spapr), 199 &local_err); 200 if (local_err) { 201 error_propagate(errp, local_err); 202 return; 203 } 204 205 spapr_cpu->icp = ICP(obj); 206 } 207 208 static int spapr_irq_post_load_xics(SpaprMachineState *spapr, int version_id) 209 { 210 if (!kvm_irqchip_in_kernel()) { 211 CPUState *cs; 212 CPU_FOREACH(cs) { 213 PowerPCCPU *cpu = POWERPC_CPU(cs); 214 icp_resend(spapr_cpu_state(cpu)->icp); 215 } 216 } 217 return 0; 218 } 219 220 static void spapr_irq_set_irq_xics(void *opaque, int srcno, int val) 221 { 222 SpaprMachineState *spapr = opaque; 223 224 ics_simple_set_irq(spapr->ics, srcno, val); 225 } 226 227 static void spapr_irq_reset_xics(SpaprMachineState *spapr, Error **errp) 228 { 229 /* TODO: create the KVM XICS device */ 230 } 231 232 static const char *spapr_irq_get_nodename_xics(SpaprMachineState *spapr) 233 { 234 return XICS_NODENAME; 235 } 236 237 static void spapr_irq_init_emu_xics(SpaprMachineState *spapr, Error **errp) 238 { 239 xics_spapr_init(spapr); 240 } 241 242 static void spapr_irq_init_kvm_xics(SpaprMachineState *spapr, Error **errp) 243 { 244 if (kvm_enabled()) { 245 xics_kvm_init(spapr, errp); 246 } 247 } 248 249 #define SPAPR_IRQ_XICS_NR_IRQS 0x1000 250 #define SPAPR_IRQ_XICS_NR_MSIS \ 251 (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI) 252 253 SpaprIrq spapr_irq_xics = { 254 .nr_irqs = SPAPR_IRQ_XICS_NR_IRQS, 255 .nr_msis = SPAPR_IRQ_XICS_NR_MSIS, 256 .ov5 = SPAPR_OV5_XIVE_LEGACY, 257 258 .init = spapr_irq_init_xics, 259 .claim = spapr_irq_claim_xics, 260 .free = spapr_irq_free_xics, 261 .qirq = spapr_qirq_xics, 262 .print_info = spapr_irq_print_info_xics, 263 .dt_populate = spapr_dt_xics, 264 .cpu_intc_create = spapr_irq_cpu_intc_create_xics, 265 .post_load = spapr_irq_post_load_xics, 266 .reset = spapr_irq_reset_xics, 267 .set_irq = spapr_irq_set_irq_xics, 268 .get_nodename = spapr_irq_get_nodename_xics, 269 .init_emu = spapr_irq_init_emu_xics, 270 .init_kvm = spapr_irq_init_kvm_xics, 271 }; 272 273 /* 274 * XIVE IRQ backend. 275 */ 276 static void spapr_irq_init_xive(SpaprMachineState *spapr, int nr_irqs, 277 Error **errp) 278 { 279 uint32_t nr_servers = spapr_max_server_number(spapr); 280 DeviceState *dev; 281 int i; 282 Error *local_err = NULL; 283 284 dev = qdev_create(NULL, TYPE_SPAPR_XIVE); 285 qdev_prop_set_uint32(dev, "nr-irqs", nr_irqs); 286 /* 287 * 8 XIVE END structures per CPU. One for each available priority 288 */ 289 qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3); 290 qdev_init_nofail(dev); 291 292 spapr->xive = SPAPR_XIVE(dev); 293 294 /* Enable the CPU IPIs */ 295 for (i = 0; i < nr_servers; ++i) { 296 spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i, false); 297 } 298 299 spapr_xive_hcall_init(spapr); 300 301 spapr_irq_init_device(spapr, &spapr_irq_xive, &local_err); 302 if (local_err) { 303 error_propagate(errp, local_err); 304 return; 305 } 306 } 307 308 static int spapr_irq_claim_xive(SpaprMachineState *spapr, int irq, bool lsi, 309 Error **errp) 310 { 311 if (!spapr_xive_irq_claim(spapr->xive, irq, lsi)) { 312 error_setg(errp, "IRQ %d is invalid", irq); 313 return -1; 314 } 315 return 0; 316 } 317 318 static void spapr_irq_free_xive(SpaprMachineState *spapr, int irq, int num) 319 { 320 int i; 321 322 for (i = irq; i < irq + num; ++i) { 323 spapr_xive_irq_free(spapr->xive, i); 324 } 325 } 326 327 static qemu_irq spapr_qirq_xive(SpaprMachineState *spapr, int irq) 328 { 329 SpaprXive *xive = spapr->xive; 330 331 if (irq >= xive->nr_irqs) { 332 return NULL; 333 } 334 335 /* The sPAPR machine/device should have claimed the IRQ before */ 336 assert(xive_eas_is_valid(&xive->eat[irq])); 337 338 return spapr->qirqs[irq]; 339 } 340 341 static void spapr_irq_print_info_xive(SpaprMachineState *spapr, 342 Monitor *mon) 343 { 344 CPUState *cs; 345 346 CPU_FOREACH(cs) { 347 PowerPCCPU *cpu = POWERPC_CPU(cs); 348 349 xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); 350 } 351 352 spapr_xive_pic_print_info(spapr->xive, mon); 353 } 354 355 static void spapr_irq_cpu_intc_create_xive(SpaprMachineState *spapr, 356 PowerPCCPU *cpu, Error **errp) 357 { 358 Error *local_err = NULL; 359 Object *obj; 360 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 361 362 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err); 363 if (local_err) { 364 error_propagate(errp, local_err); 365 return; 366 } 367 368 spapr_cpu->tctx = XIVE_TCTX(obj); 369 370 /* 371 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they 372 * don't beneficiate from the reset of the XIVE IRQ backend 373 */ 374 spapr_xive_set_tctx_os_cam(spapr_cpu->tctx); 375 } 376 377 static int spapr_irq_post_load_xive(SpaprMachineState *spapr, int version_id) 378 { 379 return spapr_xive_post_load(spapr->xive, version_id); 380 } 381 382 static void spapr_irq_reset_xive(SpaprMachineState *spapr, Error **errp) 383 { 384 CPUState *cs; 385 386 CPU_FOREACH(cs) { 387 PowerPCCPU *cpu = POWERPC_CPU(cs); 388 389 /* (TCG) Set the OS CAM line of the thread interrupt context. */ 390 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx); 391 } 392 393 /* Activate the XIVE MMIOs */ 394 spapr_xive_mmio_set_enabled(spapr->xive, true); 395 } 396 397 static void spapr_irq_set_irq_xive(void *opaque, int srcno, int val) 398 { 399 SpaprMachineState *spapr = opaque; 400 401 if (kvm_irqchip_in_kernel()) { 402 kvmppc_xive_source_set_irq(&spapr->xive->source, srcno, val); 403 } else { 404 xive_source_set_irq(&spapr->xive->source, srcno, val); 405 } 406 } 407 408 static const char *spapr_irq_get_nodename_xive(SpaprMachineState *spapr) 409 { 410 return spapr->xive->nodename; 411 } 412 413 static void spapr_irq_init_emu_xive(SpaprMachineState *spapr, Error **errp) 414 { 415 spapr_xive_init(spapr->xive, errp); 416 } 417 418 static void spapr_irq_init_kvm_xive(SpaprMachineState *spapr, Error **errp) 419 { 420 if (kvm_enabled()) { 421 kvmppc_xive_connect(spapr->xive, errp); 422 } 423 } 424 425 /* 426 * XIVE uses the full IRQ number space. Set it to 8K to be compatible 427 * with XICS. 428 */ 429 430 #define SPAPR_IRQ_XIVE_NR_IRQS 0x2000 431 #define SPAPR_IRQ_XIVE_NR_MSIS (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI) 432 433 SpaprIrq spapr_irq_xive = { 434 .nr_irqs = SPAPR_IRQ_XIVE_NR_IRQS, 435 .nr_msis = SPAPR_IRQ_XIVE_NR_MSIS, 436 .ov5 = SPAPR_OV5_XIVE_EXPLOIT, 437 438 .init = spapr_irq_init_xive, 439 .claim = spapr_irq_claim_xive, 440 .free = spapr_irq_free_xive, 441 .qirq = spapr_qirq_xive, 442 .print_info = spapr_irq_print_info_xive, 443 .dt_populate = spapr_dt_xive, 444 .cpu_intc_create = spapr_irq_cpu_intc_create_xive, 445 .post_load = spapr_irq_post_load_xive, 446 .reset = spapr_irq_reset_xive, 447 .set_irq = spapr_irq_set_irq_xive, 448 .get_nodename = spapr_irq_get_nodename_xive, 449 .init_emu = spapr_irq_init_emu_xive, 450 .init_kvm = spapr_irq_init_kvm_xive, 451 }; 452 453 /* 454 * Dual XIVE and XICS IRQ backend. 455 * 456 * Both interrupt mode, XIVE and XICS, objects are created but the 457 * machine starts in legacy interrupt mode (XICS). It can be changed 458 * by the CAS negotiation process and, in that case, the new mode is 459 * activated after an extra machine reset. 460 */ 461 462 /* 463 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the 464 * default. 465 */ 466 static SpaprIrq *spapr_irq_current(SpaprMachineState *spapr) 467 { 468 return spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) ? 469 &spapr_irq_xive : &spapr_irq_xics; 470 } 471 472 static void spapr_irq_init_dual(SpaprMachineState *spapr, int nr_irqs, 473 Error **errp) 474 { 475 MachineState *machine = MACHINE(spapr); 476 Error *local_err = NULL; 477 478 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) { 479 error_setg(errp, "No KVM support for the 'dual' machine"); 480 return; 481 } 482 483 spapr_irq_xics.init(spapr, spapr_irq_xics.nr_irqs, &local_err); 484 if (local_err) { 485 error_propagate(errp, local_err); 486 return; 487 } 488 489 spapr_irq_xive.init(spapr, spapr_irq_xive.nr_irqs, &local_err); 490 if (local_err) { 491 error_propagate(errp, local_err); 492 return; 493 } 494 } 495 496 static int spapr_irq_claim_dual(SpaprMachineState *spapr, int irq, bool lsi, 497 Error **errp) 498 { 499 Error *local_err = NULL; 500 int ret; 501 502 ret = spapr_irq_xics.claim(spapr, irq, lsi, &local_err); 503 if (local_err) { 504 error_propagate(errp, local_err); 505 return ret; 506 } 507 508 ret = spapr_irq_xive.claim(spapr, irq, lsi, &local_err); 509 if (local_err) { 510 error_propagate(errp, local_err); 511 return ret; 512 } 513 514 return ret; 515 } 516 517 static void spapr_irq_free_dual(SpaprMachineState *spapr, int irq, int num) 518 { 519 spapr_irq_xics.free(spapr, irq, num); 520 spapr_irq_xive.free(spapr, irq, num); 521 } 522 523 static qemu_irq spapr_qirq_dual(SpaprMachineState *spapr, int irq) 524 { 525 return spapr_irq_current(spapr)->qirq(spapr, irq); 526 } 527 528 static void spapr_irq_print_info_dual(SpaprMachineState *spapr, Monitor *mon) 529 { 530 spapr_irq_current(spapr)->print_info(spapr, mon); 531 } 532 533 static void spapr_irq_dt_populate_dual(SpaprMachineState *spapr, 534 uint32_t nr_servers, void *fdt, 535 uint32_t phandle) 536 { 537 spapr_irq_current(spapr)->dt_populate(spapr, nr_servers, fdt, phandle); 538 } 539 540 static void spapr_irq_cpu_intc_create_dual(SpaprMachineState *spapr, 541 PowerPCCPU *cpu, Error **errp) 542 { 543 Error *local_err = NULL; 544 545 spapr_irq_xive.cpu_intc_create(spapr, cpu, &local_err); 546 if (local_err) { 547 error_propagate(errp, local_err); 548 return; 549 } 550 551 spapr_irq_xics.cpu_intc_create(spapr, cpu, errp); 552 } 553 554 static int spapr_irq_post_load_dual(SpaprMachineState *spapr, int version_id) 555 { 556 /* 557 * Force a reset of the XIVE backend after migration. The machine 558 * defaults to XICS at startup. 559 */ 560 if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 561 spapr_irq_xive.reset(spapr, &error_fatal); 562 } 563 564 return spapr_irq_current(spapr)->post_load(spapr, version_id); 565 } 566 567 static void spapr_irq_reset_dual(SpaprMachineState *spapr, Error **errp) 568 { 569 /* 570 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them 571 * if selected. 572 */ 573 spapr_xive_mmio_set_enabled(spapr->xive, false); 574 575 spapr_irq_current(spapr)->reset(spapr, errp); 576 } 577 578 static void spapr_irq_set_irq_dual(void *opaque, int srcno, int val) 579 { 580 SpaprMachineState *spapr = opaque; 581 582 spapr_irq_current(spapr)->set_irq(spapr, srcno, val); 583 } 584 585 static const char *spapr_irq_get_nodename_dual(SpaprMachineState *spapr) 586 { 587 return spapr_irq_current(spapr)->get_nodename(spapr); 588 } 589 590 /* 591 * Define values in sync with the XIVE and XICS backend 592 */ 593 #define SPAPR_IRQ_DUAL_NR_IRQS 0x2000 594 #define SPAPR_IRQ_DUAL_NR_MSIS (SPAPR_IRQ_DUAL_NR_IRQS - SPAPR_IRQ_MSI) 595 596 SpaprIrq spapr_irq_dual = { 597 .nr_irqs = SPAPR_IRQ_DUAL_NR_IRQS, 598 .nr_msis = SPAPR_IRQ_DUAL_NR_MSIS, 599 .ov5 = SPAPR_OV5_XIVE_BOTH, 600 601 .init = spapr_irq_init_dual, 602 .claim = spapr_irq_claim_dual, 603 .free = spapr_irq_free_dual, 604 .qirq = spapr_qirq_dual, 605 .print_info = spapr_irq_print_info_dual, 606 .dt_populate = spapr_irq_dt_populate_dual, 607 .cpu_intc_create = spapr_irq_cpu_intc_create_dual, 608 .post_load = spapr_irq_post_load_dual, 609 .reset = spapr_irq_reset_dual, 610 .set_irq = spapr_irq_set_irq_dual, 611 .get_nodename = spapr_irq_get_nodename_dual, 612 .init_emu = NULL, /* should not be used */ 613 .init_kvm = NULL, /* should not be used */ 614 }; 615 616 617 static void spapr_irq_check(SpaprMachineState *spapr, Error **errp) 618 { 619 MachineState *machine = MACHINE(spapr); 620 621 /* 622 * Sanity checks on non-P9 machines. On these, XIVE is not 623 * advertised, see spapr_dt_ov5_platform_support() 624 */ 625 if (!ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 626 0, spapr->max_compat_pvr)) { 627 /* 628 * If the 'dual' interrupt mode is selected, force XICS as CAS 629 * negotiation is useless. 630 */ 631 if (spapr->irq == &spapr_irq_dual) { 632 spapr->irq = &spapr_irq_xics; 633 return; 634 } 635 636 /* 637 * Non-P9 machines using only XIVE is a bogus setup. We have two 638 * scenarios to take into account because of the compat mode: 639 * 640 * 1. POWER7/8 machines should fail to init later on when creating 641 * the XIVE interrupt presenters because a POWER9 exception 642 * model is required. 643 644 * 2. POWER9 machines using the POWER8 compat mode won't fail and 645 * will let the OS boot with a partial XIVE setup : DT 646 * properties but no hcalls. 647 * 648 * To cover both and not confuse the OS, add an early failure in 649 * QEMU. 650 */ 651 if (spapr->irq == &spapr_irq_xive) { 652 error_setg(errp, "XIVE-only machines require a POWER9 CPU"); 653 return; 654 } 655 } 656 } 657 658 /* 659 * sPAPR IRQ frontend routines for devices 660 */ 661 void spapr_irq_init(SpaprMachineState *spapr, Error **errp) 662 { 663 MachineState *machine = MACHINE(spapr); 664 Error *local_err = NULL; 665 666 if (machine_kernel_irqchip_split(machine)) { 667 error_setg(errp, "kernel_irqchip split mode not supported on pseries"); 668 return; 669 } 670 671 if (!kvm_enabled() && machine_kernel_irqchip_required(machine)) { 672 error_setg(errp, 673 "kernel_irqchip requested but only available with KVM"); 674 return; 675 } 676 677 spapr_irq_check(spapr, &local_err); 678 if (local_err) { 679 error_propagate(errp, local_err); 680 return; 681 } 682 683 /* Initialize the MSI IRQ allocator. */ 684 if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 685 spapr_irq_msi_init(spapr, spapr->irq->nr_msis); 686 } 687 688 spapr->irq->init(spapr, spapr->irq->nr_irqs, errp); 689 690 spapr->qirqs = qemu_allocate_irqs(spapr->irq->set_irq, spapr, 691 spapr->irq->nr_irqs); 692 } 693 694 int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp) 695 { 696 return spapr->irq->claim(spapr, irq, lsi, errp); 697 } 698 699 void spapr_irq_free(SpaprMachineState *spapr, int irq, int num) 700 { 701 spapr->irq->free(spapr, irq, num); 702 } 703 704 qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq) 705 { 706 return spapr->irq->qirq(spapr, irq); 707 } 708 709 int spapr_irq_post_load(SpaprMachineState *spapr, int version_id) 710 { 711 return spapr->irq->post_load(spapr, version_id); 712 } 713 714 void spapr_irq_reset(SpaprMachineState *spapr, Error **errp) 715 { 716 if (spapr->irq->reset) { 717 spapr->irq->reset(spapr, errp); 718 } 719 } 720 721 int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp) 722 { 723 const char *nodename = spapr->irq->get_nodename(spapr); 724 int offset, phandle; 725 726 offset = fdt_subnode_offset(fdt, 0, nodename); 727 if (offset < 0) { 728 error_setg(errp, "Can't find node \"%s\": %s", nodename, 729 fdt_strerror(offset)); 730 return -1; 731 } 732 733 phandle = fdt_get_phandle(fdt, offset); 734 if (!phandle) { 735 error_setg(errp, "Can't get phandle of node \"%s\"", nodename); 736 return -1; 737 } 738 739 return phandle; 740 } 741 742 /* 743 * XICS legacy routines - to deprecate one day 744 */ 745 746 static int ics_find_free_block(ICSState *ics, int num, int alignnum) 747 { 748 int first, i; 749 750 for (first = 0; first < ics->nr_irqs; first += alignnum) { 751 if (num > (ics->nr_irqs - first)) { 752 return -1; 753 } 754 for (i = first; i < first + num; ++i) { 755 if (!ICS_IRQ_FREE(ics, i)) { 756 break; 757 } 758 } 759 if (i == (first + num)) { 760 return first; 761 } 762 } 763 764 return -1; 765 } 766 767 int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp) 768 { 769 ICSState *ics = spapr->ics; 770 int first = -1; 771 772 assert(ics); 773 774 /* 775 * MSIMesage::data is used for storing VIRQ so 776 * it has to be aligned to num to support multiple 777 * MSI vectors. MSI-X is not affected by this. 778 * The hint is used for the first IRQ, the rest should 779 * be allocated continuously. 780 */ 781 if (align) { 782 assert((num == 1) || (num == 2) || (num == 4) || 783 (num == 8) || (num == 16) || (num == 32)); 784 first = ics_find_free_block(ics, num, num); 785 } else { 786 first = ics_find_free_block(ics, num, 1); 787 } 788 789 if (first < 0) { 790 error_setg(errp, "can't find a free %d-IRQ block", num); 791 return -1; 792 } 793 794 return first + ics->offset; 795 } 796 797 #define SPAPR_IRQ_XICS_LEGACY_NR_IRQS 0x400 798 799 SpaprIrq spapr_irq_xics_legacy = { 800 .nr_irqs = SPAPR_IRQ_XICS_LEGACY_NR_IRQS, 801 .nr_msis = SPAPR_IRQ_XICS_LEGACY_NR_IRQS, 802 .ov5 = SPAPR_OV5_XIVE_LEGACY, 803 804 .init = spapr_irq_init_xics, 805 .claim = spapr_irq_claim_xics, 806 .free = spapr_irq_free_xics, 807 .qirq = spapr_qirq_xics, 808 .print_info = spapr_irq_print_info_xics, 809 .dt_populate = spapr_dt_xics, 810 .cpu_intc_create = spapr_irq_cpu_intc_create_xics, 811 .post_load = spapr_irq_post_load_xics, 812 .set_irq = spapr_irq_set_irq_xics, 813 .get_nodename = spapr_irq_get_nodename_xics, 814 }; 815