1 /* 2 * QEMU PowerPC sPAPR IRQ interface 3 * 4 * Copyright (c) 2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/error-report.h" 13 #include "qapi/error.h" 14 #include "hw/irq.h" 15 #include "hw/ppc/spapr.h" 16 #include "hw/ppc/spapr_cpu_core.h" 17 #include "hw/ppc/spapr_xive.h" 18 #include "hw/ppc/xics.h" 19 #include "hw/ppc/xics_spapr.h" 20 #include "hw/qdev-properties.h" 21 #include "cpu-models.h" 22 #include "sysemu/kvm.h" 23 24 #include "trace.h" 25 26 void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis) 27 { 28 spapr->irq_map_nr = nr_msis; 29 spapr->irq_map = bitmap_new(spapr->irq_map_nr); 30 } 31 32 int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align, 33 Error **errp) 34 { 35 int irq; 36 37 /* 38 * The 'align_mask' parameter of bitmap_find_next_zero_area() 39 * should be one less than a power of 2; 0 means no 40 * alignment. Adapt the 'align' value of the former allocator 41 * to fit the requirements of bitmap_find_next_zero_area() 42 */ 43 align -= 1; 44 45 irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num, 46 align); 47 if (irq == spapr->irq_map_nr) { 48 error_setg(errp, "can't find a free %d-IRQ block", num); 49 return -1; 50 } 51 52 bitmap_set(spapr->irq_map, irq, num); 53 54 return irq + SPAPR_IRQ_MSI; 55 } 56 57 void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num) 58 { 59 bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num); 60 } 61 62 static void spapr_irq_init_kvm(SpaprMachineState *spapr, 63 SpaprIrq *irq, Error **errp) 64 { 65 MachineState *machine = MACHINE(spapr); 66 Error *local_err = NULL; 67 68 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) { 69 irq->init_kvm(spapr, &local_err); 70 if (local_err && machine_kernel_irqchip_required(machine)) { 71 error_prepend(&local_err, 72 "kernel_irqchip requested but unavailable: "); 73 error_propagate(errp, local_err); 74 return; 75 } 76 77 if (!local_err) { 78 return; 79 } 80 81 /* 82 * We failed to initialize the KVM device, fallback to 83 * emulated mode 84 */ 85 error_prepend(&local_err, "kernel_irqchip allowed but unavailable: "); 86 error_append_hint(&local_err, "Falling back to kernel-irqchip=off\n"); 87 warn_report_err(local_err); 88 } 89 } 90 91 /* 92 * XICS IRQ backend. 93 */ 94 95 static int spapr_irq_claim_xics(SpaprMachineState *spapr, int irq, bool lsi, 96 Error **errp) 97 { 98 ICSState *ics = spapr->ics; 99 100 assert(ics); 101 assert(ics_valid_irq(ics, irq)); 102 103 if (!ics_irq_free(ics, irq - ics->offset)) { 104 error_setg(errp, "IRQ %d is not free", irq); 105 return -1; 106 } 107 108 ics_set_irq_type(ics, irq - ics->offset, lsi); 109 return 0; 110 } 111 112 static void spapr_irq_free_xics(SpaprMachineState *spapr, int irq) 113 { 114 ICSState *ics = spapr->ics; 115 uint32_t srcno = irq - ics->offset; 116 117 assert(ics_valid_irq(ics, irq)); 118 119 memset(&ics->irqs[srcno], 0, sizeof(ICSIRQState)); 120 } 121 122 static void spapr_irq_print_info_xics(SpaprMachineState *spapr, Monitor *mon) 123 { 124 CPUState *cs; 125 126 CPU_FOREACH(cs) { 127 PowerPCCPU *cpu = POWERPC_CPU(cs); 128 129 icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon); 130 } 131 132 ics_pic_print_info(spapr->ics, mon); 133 } 134 135 static void spapr_irq_cpu_intc_create_xics(SpaprMachineState *spapr, 136 PowerPCCPU *cpu, Error **errp) 137 { 138 Error *local_err = NULL; 139 Object *obj; 140 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 141 142 obj = icp_create(OBJECT(cpu), TYPE_ICP, XICS_FABRIC(spapr), 143 &local_err); 144 if (local_err) { 145 error_propagate(errp, local_err); 146 return; 147 } 148 149 spapr_cpu->icp = ICP(obj); 150 } 151 152 static int spapr_irq_post_load_xics(SpaprMachineState *spapr, int version_id) 153 { 154 if (!kvm_irqchip_in_kernel()) { 155 CPUState *cs; 156 CPU_FOREACH(cs) { 157 PowerPCCPU *cpu = POWERPC_CPU(cs); 158 icp_resend(spapr_cpu_state(cpu)->icp); 159 } 160 } 161 return 0; 162 } 163 164 static void spapr_irq_set_irq_xics(void *opaque, int irq, int val) 165 { 166 SpaprMachineState *spapr = opaque; 167 uint32_t srcno = irq - spapr->ics->offset; 168 169 ics_set_irq(spapr->ics, srcno, val); 170 } 171 172 static void spapr_irq_reset_xics(SpaprMachineState *spapr, Error **errp) 173 { 174 Error *local_err = NULL; 175 176 spapr_irq_init_kvm(spapr, &spapr_irq_xics, &local_err); 177 if (local_err) { 178 error_propagate(errp, local_err); 179 return; 180 } 181 } 182 183 static void spapr_irq_init_kvm_xics(SpaprMachineState *spapr, Error **errp) 184 { 185 if (kvm_enabled()) { 186 xics_kvm_connect(spapr, errp); 187 } 188 } 189 190 SpaprIrq spapr_irq_xics = { 191 .nr_xirqs = SPAPR_NR_XIRQS, 192 .nr_msis = SPAPR_NR_MSIS, 193 .xics = true, 194 .xive = false, 195 196 .claim = spapr_irq_claim_xics, 197 .free = spapr_irq_free_xics, 198 .print_info = spapr_irq_print_info_xics, 199 .dt_populate = spapr_dt_xics, 200 .cpu_intc_create = spapr_irq_cpu_intc_create_xics, 201 .post_load = spapr_irq_post_load_xics, 202 .reset = spapr_irq_reset_xics, 203 .set_irq = spapr_irq_set_irq_xics, 204 .init_kvm = spapr_irq_init_kvm_xics, 205 }; 206 207 /* 208 * XIVE IRQ backend. 209 */ 210 211 static int spapr_irq_claim_xive(SpaprMachineState *spapr, int irq, bool lsi, 212 Error **errp) 213 { 214 return spapr_xive_irq_claim(spapr->xive, irq, lsi, errp); 215 } 216 217 static void spapr_irq_free_xive(SpaprMachineState *spapr, int irq) 218 { 219 spapr_xive_irq_free(spapr->xive, irq); 220 } 221 222 static void spapr_irq_print_info_xive(SpaprMachineState *spapr, 223 Monitor *mon) 224 { 225 CPUState *cs; 226 227 CPU_FOREACH(cs) { 228 PowerPCCPU *cpu = POWERPC_CPU(cs); 229 230 xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); 231 } 232 233 spapr_xive_pic_print_info(spapr->xive, mon); 234 } 235 236 static void spapr_irq_cpu_intc_create_xive(SpaprMachineState *spapr, 237 PowerPCCPU *cpu, Error **errp) 238 { 239 Error *local_err = NULL; 240 Object *obj; 241 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 242 243 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err); 244 if (local_err) { 245 error_propagate(errp, local_err); 246 return; 247 } 248 249 spapr_cpu->tctx = XIVE_TCTX(obj); 250 251 /* 252 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they 253 * don't beneficiate from the reset of the XIVE IRQ backend 254 */ 255 spapr_xive_set_tctx_os_cam(spapr_cpu->tctx); 256 } 257 258 static int spapr_irq_post_load_xive(SpaprMachineState *spapr, int version_id) 259 { 260 return spapr_xive_post_load(spapr->xive, version_id); 261 } 262 263 static void spapr_irq_reset_xive(SpaprMachineState *spapr, Error **errp) 264 { 265 CPUState *cs; 266 Error *local_err = NULL; 267 268 CPU_FOREACH(cs) { 269 PowerPCCPU *cpu = POWERPC_CPU(cs); 270 271 /* (TCG) Set the OS CAM line of the thread interrupt context. */ 272 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx); 273 } 274 275 spapr_irq_init_kvm(spapr, &spapr_irq_xive, &local_err); 276 if (local_err) { 277 error_propagate(errp, local_err); 278 return; 279 } 280 281 /* Activate the XIVE MMIOs */ 282 spapr_xive_mmio_set_enabled(spapr->xive, true); 283 } 284 285 static void spapr_irq_set_irq_xive(void *opaque, int irq, int val) 286 { 287 SpaprMachineState *spapr = opaque; 288 289 if (kvm_irqchip_in_kernel()) { 290 kvmppc_xive_source_set_irq(&spapr->xive->source, irq, val); 291 } else { 292 xive_source_set_irq(&spapr->xive->source, irq, val); 293 } 294 } 295 296 static void spapr_irq_init_kvm_xive(SpaprMachineState *spapr, Error **errp) 297 { 298 if (kvm_enabled()) { 299 kvmppc_xive_connect(spapr->xive, errp); 300 } 301 } 302 303 SpaprIrq spapr_irq_xive = { 304 .nr_xirqs = SPAPR_NR_XIRQS, 305 .nr_msis = SPAPR_NR_MSIS, 306 .xics = false, 307 .xive = true, 308 309 .claim = spapr_irq_claim_xive, 310 .free = spapr_irq_free_xive, 311 .print_info = spapr_irq_print_info_xive, 312 .dt_populate = spapr_dt_xive, 313 .cpu_intc_create = spapr_irq_cpu_intc_create_xive, 314 .post_load = spapr_irq_post_load_xive, 315 .reset = spapr_irq_reset_xive, 316 .set_irq = spapr_irq_set_irq_xive, 317 .init_kvm = spapr_irq_init_kvm_xive, 318 }; 319 320 /* 321 * Dual XIVE and XICS IRQ backend. 322 * 323 * Both interrupt mode, XIVE and XICS, objects are created but the 324 * machine starts in legacy interrupt mode (XICS). It can be changed 325 * by the CAS negotiation process and, in that case, the new mode is 326 * activated after an extra machine reset. 327 */ 328 329 /* 330 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the 331 * default. 332 */ 333 static SpaprIrq *spapr_irq_current(SpaprMachineState *spapr) 334 { 335 return spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) ? 336 &spapr_irq_xive : &spapr_irq_xics; 337 } 338 339 static int spapr_irq_claim_dual(SpaprMachineState *spapr, int irq, bool lsi, 340 Error **errp) 341 { 342 Error *local_err = NULL; 343 int ret; 344 345 ret = spapr_irq_xics.claim(spapr, irq, lsi, &local_err); 346 if (local_err) { 347 error_propagate(errp, local_err); 348 return ret; 349 } 350 351 ret = spapr_irq_xive.claim(spapr, irq, lsi, &local_err); 352 if (local_err) { 353 error_propagate(errp, local_err); 354 return ret; 355 } 356 357 return ret; 358 } 359 360 static void spapr_irq_free_dual(SpaprMachineState *spapr, int irq) 361 { 362 spapr_irq_xics.free(spapr, irq); 363 spapr_irq_xive.free(spapr, irq); 364 } 365 366 static void spapr_irq_print_info_dual(SpaprMachineState *spapr, Monitor *mon) 367 { 368 spapr_irq_current(spapr)->print_info(spapr, mon); 369 } 370 371 static void spapr_irq_dt_populate_dual(SpaprMachineState *spapr, 372 uint32_t nr_servers, void *fdt, 373 uint32_t phandle) 374 { 375 spapr_irq_current(spapr)->dt_populate(spapr, nr_servers, fdt, phandle); 376 } 377 378 static void spapr_irq_cpu_intc_create_dual(SpaprMachineState *spapr, 379 PowerPCCPU *cpu, Error **errp) 380 { 381 Error *local_err = NULL; 382 383 spapr_irq_xive.cpu_intc_create(spapr, cpu, &local_err); 384 if (local_err) { 385 error_propagate(errp, local_err); 386 return; 387 } 388 389 spapr_irq_xics.cpu_intc_create(spapr, cpu, errp); 390 } 391 392 static int spapr_irq_post_load_dual(SpaprMachineState *spapr, int version_id) 393 { 394 /* 395 * Force a reset of the XIVE backend after migration. The machine 396 * defaults to XICS at startup. 397 */ 398 if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 399 if (kvm_irqchip_in_kernel()) { 400 xics_kvm_disconnect(spapr, &error_fatal); 401 } 402 spapr_irq_xive.reset(spapr, &error_fatal); 403 } 404 405 return spapr_irq_current(spapr)->post_load(spapr, version_id); 406 } 407 408 static void spapr_irq_reset_dual(SpaprMachineState *spapr, Error **errp) 409 { 410 Error *local_err = NULL; 411 412 /* 413 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them 414 * if selected. 415 */ 416 spapr_xive_mmio_set_enabled(spapr->xive, false); 417 418 /* Destroy all KVM devices */ 419 if (kvm_irqchip_in_kernel()) { 420 xics_kvm_disconnect(spapr, &local_err); 421 if (local_err) { 422 error_propagate(errp, local_err); 423 error_prepend(errp, "KVM XICS disconnect failed: "); 424 return; 425 } 426 kvmppc_xive_disconnect(spapr->xive, &local_err); 427 if (local_err) { 428 error_propagate(errp, local_err); 429 error_prepend(errp, "KVM XIVE disconnect failed: "); 430 return; 431 } 432 } 433 434 spapr_irq_current(spapr)->reset(spapr, errp); 435 } 436 437 static void spapr_irq_set_irq_dual(void *opaque, int irq, int val) 438 { 439 SpaprMachineState *spapr = opaque; 440 441 spapr_irq_current(spapr)->set_irq(spapr, irq, val); 442 } 443 444 /* 445 * Define values in sync with the XIVE and XICS backend 446 */ 447 SpaprIrq spapr_irq_dual = { 448 .nr_xirqs = SPAPR_NR_XIRQS, 449 .nr_msis = SPAPR_NR_MSIS, 450 .xics = true, 451 .xive = true, 452 453 .claim = spapr_irq_claim_dual, 454 .free = spapr_irq_free_dual, 455 .print_info = spapr_irq_print_info_dual, 456 .dt_populate = spapr_irq_dt_populate_dual, 457 .cpu_intc_create = spapr_irq_cpu_intc_create_dual, 458 .post_load = spapr_irq_post_load_dual, 459 .reset = spapr_irq_reset_dual, 460 .set_irq = spapr_irq_set_irq_dual, 461 .init_kvm = NULL, /* should not be used */ 462 }; 463 464 465 static int spapr_irq_check(SpaprMachineState *spapr, Error **errp) 466 { 467 MachineState *machine = MACHINE(spapr); 468 469 /* 470 * Sanity checks on non-P9 machines. On these, XIVE is not 471 * advertised, see spapr_dt_ov5_platform_support() 472 */ 473 if (!ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 474 0, spapr->max_compat_pvr)) { 475 /* 476 * If the 'dual' interrupt mode is selected, force XICS as CAS 477 * negotiation is useless. 478 */ 479 if (spapr->irq == &spapr_irq_dual) { 480 spapr->irq = &spapr_irq_xics; 481 return 0; 482 } 483 484 /* 485 * Non-P9 machines using only XIVE is a bogus setup. We have two 486 * scenarios to take into account because of the compat mode: 487 * 488 * 1. POWER7/8 machines should fail to init later on when creating 489 * the XIVE interrupt presenters because a POWER9 exception 490 * model is required. 491 492 * 2. POWER9 machines using the POWER8 compat mode won't fail and 493 * will let the OS boot with a partial XIVE setup : DT 494 * properties but no hcalls. 495 * 496 * To cover both and not confuse the OS, add an early failure in 497 * QEMU. 498 */ 499 if (spapr->irq == &spapr_irq_xive) { 500 error_setg(errp, "XIVE-only machines require a POWER9 CPU"); 501 return -1; 502 } 503 } 504 505 /* 506 * On a POWER9 host, some older KVM XICS devices cannot be destroyed and 507 * re-created. Detect that early to avoid QEMU to exit later when the 508 * guest reboots. 509 */ 510 if (kvm_enabled() && 511 spapr->irq == &spapr_irq_dual && 512 machine_kernel_irqchip_required(machine) && 513 xics_kvm_has_broken_disconnect(spapr)) { 514 error_setg(errp, "KVM is too old to support ic-mode=dual,kernel-irqchip=on"); 515 return -1; 516 } 517 518 return 0; 519 } 520 521 /* 522 * sPAPR IRQ frontend routines for devices 523 */ 524 void spapr_irq_init(SpaprMachineState *spapr, Error **errp) 525 { 526 MachineState *machine = MACHINE(spapr); 527 528 if (machine_kernel_irqchip_split(machine)) { 529 error_setg(errp, "kernel_irqchip split mode not supported on pseries"); 530 return; 531 } 532 533 if (!kvm_enabled() && machine_kernel_irqchip_required(machine)) { 534 error_setg(errp, 535 "kernel_irqchip requested but only available with KVM"); 536 return; 537 } 538 539 if (spapr_irq_check(spapr, errp) < 0) { 540 return; 541 } 542 543 /* Initialize the MSI IRQ allocator. */ 544 if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 545 spapr_irq_msi_init(spapr, spapr->irq->nr_msis); 546 } 547 548 if (spapr->irq->xics) { 549 Error *local_err = NULL; 550 Object *obj; 551 552 obj = object_new(TYPE_ICS_SPAPR); 553 object_property_add_child(OBJECT(spapr), "ics", obj, &local_err); 554 if (local_err) { 555 error_propagate(errp, local_err); 556 return; 557 } 558 559 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), 560 &local_err); 561 if (local_err) { 562 error_propagate(errp, local_err); 563 return; 564 } 565 566 object_property_set_int(obj, spapr->irq->nr_xirqs, "nr-irqs", 567 &local_err); 568 if (local_err) { 569 error_propagate(errp, local_err); 570 return; 571 } 572 573 object_property_set_bool(obj, true, "realized", &local_err); 574 if (local_err) { 575 error_propagate(errp, local_err); 576 return; 577 } 578 579 spapr->ics = ICS_SPAPR(obj); 580 } 581 582 if (spapr->irq->xive) { 583 uint32_t nr_servers = spapr_max_server_number(spapr); 584 DeviceState *dev; 585 int i; 586 587 dev = qdev_create(NULL, TYPE_SPAPR_XIVE); 588 qdev_prop_set_uint32(dev, "nr-irqs", 589 spapr->irq->nr_xirqs + SPAPR_XIRQ_BASE); 590 /* 591 * 8 XIVE END structures per CPU. One for each available 592 * priority 593 */ 594 qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3); 595 qdev_init_nofail(dev); 596 597 spapr->xive = SPAPR_XIVE(dev); 598 599 /* Enable the CPU IPIs */ 600 for (i = 0; i < nr_servers; ++i) { 601 if (spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i, 602 false, errp) < 0) { 603 return; 604 } 605 } 606 607 spapr_xive_hcall_init(spapr); 608 } 609 610 spapr->qirqs = qemu_allocate_irqs(spapr->irq->set_irq, spapr, 611 spapr->irq->nr_xirqs + SPAPR_XIRQ_BASE); 612 } 613 614 int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp) 615 { 616 assert(irq >= SPAPR_XIRQ_BASE); 617 assert(irq < (spapr->irq->nr_xirqs + SPAPR_XIRQ_BASE)); 618 619 return spapr->irq->claim(spapr, irq, lsi, errp); 620 } 621 622 void spapr_irq_free(SpaprMachineState *spapr, int irq, int num) 623 { 624 int i; 625 626 assert(irq >= SPAPR_XIRQ_BASE); 627 assert((irq + num) <= (spapr->irq->nr_xirqs + SPAPR_XIRQ_BASE)); 628 629 for (i = irq; i < (irq + num); i++) { 630 spapr->irq->free(spapr, i); 631 } 632 } 633 634 qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq) 635 { 636 /* 637 * This interface is basically for VIO and PHB devices to find the 638 * right qemu_irq to manipulate, so we only allow access to the 639 * external irqs for now. Currently anything which needs to 640 * access the IPIs most naturally gets there via the guest side 641 * interfaces, we can change this if we need to in future. 642 */ 643 assert(irq >= SPAPR_XIRQ_BASE); 644 assert(irq < (spapr->irq->nr_xirqs + SPAPR_XIRQ_BASE)); 645 646 if (spapr->ics) { 647 assert(ics_valid_irq(spapr->ics, irq)); 648 } 649 if (spapr->xive) { 650 assert(irq < spapr->xive->nr_irqs); 651 assert(xive_eas_is_valid(&spapr->xive->eat[irq])); 652 } 653 654 return spapr->qirqs[irq]; 655 } 656 657 int spapr_irq_post_load(SpaprMachineState *spapr, int version_id) 658 { 659 return spapr->irq->post_load(spapr, version_id); 660 } 661 662 void spapr_irq_reset(SpaprMachineState *spapr, Error **errp) 663 { 664 assert(!spapr->irq_map || bitmap_empty(spapr->irq_map, spapr->irq_map_nr)); 665 666 if (spapr->irq->reset) { 667 spapr->irq->reset(spapr, errp); 668 } 669 } 670 671 int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp) 672 { 673 const char *nodename = "interrupt-controller"; 674 int offset, phandle; 675 676 offset = fdt_subnode_offset(fdt, 0, nodename); 677 if (offset < 0) { 678 error_setg(errp, "Can't find node \"%s\": %s", 679 nodename, fdt_strerror(offset)); 680 return -1; 681 } 682 683 phandle = fdt_get_phandle(fdt, offset); 684 if (!phandle) { 685 error_setg(errp, "Can't get phandle of node \"%s\"", nodename); 686 return -1; 687 } 688 689 return phandle; 690 } 691 692 /* 693 * XICS legacy routines - to deprecate one day 694 */ 695 696 static int ics_find_free_block(ICSState *ics, int num, int alignnum) 697 { 698 int first, i; 699 700 for (first = 0; first < ics->nr_irqs; first += alignnum) { 701 if (num > (ics->nr_irqs - first)) { 702 return -1; 703 } 704 for (i = first; i < first + num; ++i) { 705 if (!ics_irq_free(ics, i)) { 706 break; 707 } 708 } 709 if (i == (first + num)) { 710 return first; 711 } 712 } 713 714 return -1; 715 } 716 717 int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp) 718 { 719 ICSState *ics = spapr->ics; 720 int first = -1; 721 722 assert(ics); 723 724 /* 725 * MSIMesage::data is used for storing VIRQ so 726 * it has to be aligned to num to support multiple 727 * MSI vectors. MSI-X is not affected by this. 728 * The hint is used for the first IRQ, the rest should 729 * be allocated continuously. 730 */ 731 if (align) { 732 assert((num == 1) || (num == 2) || (num == 4) || 733 (num == 8) || (num == 16) || (num == 32)); 734 first = ics_find_free_block(ics, num, num); 735 } else { 736 first = ics_find_free_block(ics, num, 1); 737 } 738 739 if (first < 0) { 740 error_setg(errp, "can't find a free %d-IRQ block", num); 741 return -1; 742 } 743 744 return first + ics->offset; 745 } 746 747 #define SPAPR_IRQ_XICS_LEGACY_NR_XIRQS 0x400 748 749 SpaprIrq spapr_irq_xics_legacy = { 750 .nr_xirqs = SPAPR_IRQ_XICS_LEGACY_NR_XIRQS, 751 .nr_msis = SPAPR_IRQ_XICS_LEGACY_NR_XIRQS, 752 .xics = true, 753 .xive = false, 754 755 .claim = spapr_irq_claim_xics, 756 .free = spapr_irq_free_xics, 757 .print_info = spapr_irq_print_info_xics, 758 .dt_populate = spapr_dt_xics, 759 .cpu_intc_create = spapr_irq_cpu_intc_create_xics, 760 .post_load = spapr_irq_post_load_xics, 761 .reset = spapr_irq_reset_xics, 762 .set_irq = spapr_irq_set_irq_xics, 763 .init_kvm = spapr_irq_init_kvm_xics, 764 }; 765