xref: /openbmc/qemu/hw/ppc/spapr_irq.c (revision 7abc0c6d35306a41a48eda7ab2b7b2d51f32f86b)
1 /*
2  * QEMU PowerPC sPAPR IRQ interface
3  *
4  * Copyright (c) 2018, IBM Corporation.
5  *
6  * This code is licensed under the GPL version 2 or later. See the
7  * COPYING file in the top-level directory.
8  */
9 
10 #include "qemu/osdep.h"
11 #include "qemu/log.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
14 #include "hw/ppc/spapr.h"
15 #include "hw/ppc/spapr_cpu_core.h"
16 #include "hw/ppc/spapr_xive.h"
17 #include "hw/ppc/xics.h"
18 #include "hw/ppc/xics_spapr.h"
19 #include "cpu-models.h"
20 #include "sysemu/kvm.h"
21 
22 #include "trace.h"
23 
24 void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis)
25 {
26     spapr->irq_map_nr = nr_msis;
27     spapr->irq_map = bitmap_new(spapr->irq_map_nr);
28 }
29 
30 int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
31                         Error **errp)
32 {
33     int irq;
34 
35     /*
36      * The 'align_mask' parameter of bitmap_find_next_zero_area()
37      * should be one less than a power of 2; 0 means no
38      * alignment. Adapt the 'align' value of the former allocator
39      * to fit the requirements of bitmap_find_next_zero_area()
40      */
41     align -= 1;
42 
43     irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num,
44                                      align);
45     if (irq == spapr->irq_map_nr) {
46         error_setg(errp, "can't find a free %d-IRQ block", num);
47         return -1;
48     }
49 
50     bitmap_set(spapr->irq_map, irq, num);
51 
52     return irq + SPAPR_IRQ_MSI;
53 }
54 
55 void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num)
56 {
57     bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num);
58 }
59 
60 void spapr_irq_msi_reset(SpaprMachineState *spapr)
61 {
62     bitmap_clear(spapr->irq_map, 0, spapr->irq_map_nr);
63 }
64 
65 static void spapr_irq_init_device(SpaprMachineState *spapr,
66                                   SpaprIrq *irq, Error **errp)
67 {
68     MachineState *machine = MACHINE(spapr);
69     Error *local_err = NULL;
70 
71     if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) {
72         irq->init_kvm(spapr, &local_err);
73         if (local_err && machine_kernel_irqchip_required(machine)) {
74             error_prepend(&local_err,
75                           "kernel_irqchip requested but unavailable: ");
76             error_propagate(errp, local_err);
77             return;
78         }
79 
80         if (!local_err) {
81             return;
82         }
83 
84         /*
85          * We failed to initialize the KVM device, fallback to
86          * emulated mode
87          */
88         error_prepend(&local_err, "kernel_irqchip allowed but unavailable: ");
89         warn_report_err(local_err);
90     }
91 
92     irq->init_emu(spapr, errp);
93 }
94 
95 /*
96  * XICS IRQ backend.
97  */
98 
99 static void spapr_irq_init_xics(SpaprMachineState *spapr, int nr_irqs,
100                                 Error **errp)
101 {
102     Object *obj;
103     Error *local_err = NULL;
104 
105     obj = object_new(TYPE_ICS_SIMPLE);
106     object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
107     object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
108                                    &error_fatal);
109     object_property_set_int(obj, nr_irqs, "nr-irqs",  &error_fatal);
110     object_property_set_bool(obj, true, "realized", &local_err);
111     if (local_err) {
112         error_propagate(errp, local_err);
113         return;
114     }
115 
116     spapr->ics = ICS_BASE(obj);
117 
118     xics_spapr_init(spapr);
119 }
120 
121 #define ICS_IRQ_FREE(ics, srcno)   \
122     (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
123 
124 static int spapr_irq_claim_xics(SpaprMachineState *spapr, int irq, bool lsi,
125                                 Error **errp)
126 {
127     ICSState *ics = spapr->ics;
128 
129     assert(ics);
130 
131     if (!ics_valid_irq(ics, irq)) {
132         error_setg(errp, "IRQ %d is invalid", irq);
133         return -1;
134     }
135 
136     if (!ICS_IRQ_FREE(ics, irq - ics->offset)) {
137         error_setg(errp, "IRQ %d is not free", irq);
138         return -1;
139     }
140 
141     ics_set_irq_type(ics, irq - ics->offset, lsi);
142     return 0;
143 }
144 
145 static void spapr_irq_free_xics(SpaprMachineState *spapr, int irq, int num)
146 {
147     ICSState *ics = spapr->ics;
148     uint32_t srcno = irq - ics->offset;
149     int i;
150 
151     if (ics_valid_irq(ics, irq)) {
152         trace_spapr_irq_free(0, irq, num);
153         for (i = srcno; i < srcno + num; ++i) {
154             if (ICS_IRQ_FREE(ics, i)) {
155                 trace_spapr_irq_free_warn(0, i);
156             }
157             memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
158         }
159     }
160 }
161 
162 static qemu_irq spapr_qirq_xics(SpaprMachineState *spapr, int irq)
163 {
164     ICSState *ics = spapr->ics;
165     uint32_t srcno = irq - ics->offset;
166 
167     if (ics_valid_irq(ics, irq)) {
168         return spapr->qirqs[srcno];
169     }
170 
171     return NULL;
172 }
173 
174 static void spapr_irq_print_info_xics(SpaprMachineState *spapr, Monitor *mon)
175 {
176     CPUState *cs;
177 
178     CPU_FOREACH(cs) {
179         PowerPCCPU *cpu = POWERPC_CPU(cs);
180 
181         icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon);
182     }
183 
184     ics_pic_print_info(spapr->ics, mon);
185 }
186 
187 static void spapr_irq_cpu_intc_create_xics(SpaprMachineState *spapr,
188                                            PowerPCCPU *cpu, Error **errp)
189 {
190     Error *local_err = NULL;
191     Object *obj;
192     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
193 
194     obj = icp_create(OBJECT(cpu), TYPE_ICP, XICS_FABRIC(spapr),
195                      &local_err);
196     if (local_err) {
197         error_propagate(errp, local_err);
198         return;
199     }
200 
201     spapr_cpu->icp = ICP(obj);
202 }
203 
204 static int spapr_irq_post_load_xics(SpaprMachineState *spapr, int version_id)
205 {
206     if (!kvm_irqchip_in_kernel()) {
207         CPUState *cs;
208         CPU_FOREACH(cs) {
209             PowerPCCPU *cpu = POWERPC_CPU(cs);
210             icp_resend(spapr_cpu_state(cpu)->icp);
211         }
212     }
213     return 0;
214 }
215 
216 static void spapr_irq_set_irq_xics(void *opaque, int srcno, int val)
217 {
218     SpaprMachineState *spapr = opaque;
219 
220     ics_simple_set_irq(spapr->ics, srcno, val);
221 }
222 
223 static void spapr_irq_reset_xics(SpaprMachineState *spapr, Error **errp)
224 {
225     Error *local_err = NULL;
226 
227     spapr_irq_init_device(spapr, &spapr_irq_xics, &local_err);
228     if (local_err) {
229         error_propagate(errp, local_err);
230         return;
231     }
232 }
233 
234 static const char *spapr_irq_get_nodename_xics(SpaprMachineState *spapr)
235 {
236     return XICS_NODENAME;
237 }
238 
239 static void spapr_irq_init_emu_xics(SpaprMachineState *spapr, Error **errp)
240 {
241 }
242 
243 static void spapr_irq_init_kvm_xics(SpaprMachineState *spapr, Error **errp)
244 {
245     if (kvm_enabled()) {
246         xics_kvm_init(spapr, errp);
247     }
248 }
249 
250 #define SPAPR_IRQ_XICS_NR_IRQS     0x1000
251 #define SPAPR_IRQ_XICS_NR_MSIS     \
252     (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
253 
254 SpaprIrq spapr_irq_xics = {
255     .nr_irqs     = SPAPR_IRQ_XICS_NR_IRQS,
256     .nr_msis     = SPAPR_IRQ_XICS_NR_MSIS,
257     .ov5         = SPAPR_OV5_XIVE_LEGACY,
258 
259     .init        = spapr_irq_init_xics,
260     .claim       = spapr_irq_claim_xics,
261     .free        = spapr_irq_free_xics,
262     .qirq        = spapr_qirq_xics,
263     .print_info  = spapr_irq_print_info_xics,
264     .dt_populate = spapr_dt_xics,
265     .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
266     .post_load   = spapr_irq_post_load_xics,
267     .reset       = spapr_irq_reset_xics,
268     .set_irq     = spapr_irq_set_irq_xics,
269     .get_nodename = spapr_irq_get_nodename_xics,
270     .init_emu    = spapr_irq_init_emu_xics,
271     .init_kvm    = spapr_irq_init_kvm_xics,
272 };
273 
274 /*
275  * XIVE IRQ backend.
276  */
277 static void spapr_irq_init_xive(SpaprMachineState *spapr, int nr_irqs,
278                                 Error **errp)
279 {
280     uint32_t nr_servers = spapr_max_server_number(spapr);
281     DeviceState *dev;
282     int i;
283 
284     dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
285     qdev_prop_set_uint32(dev, "nr-irqs", nr_irqs);
286     /*
287      * 8 XIVE END structures per CPU. One for each available priority
288      */
289     qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
290     qdev_init_nofail(dev);
291 
292     spapr->xive = SPAPR_XIVE(dev);
293 
294     /* Enable the CPU IPIs */
295     for (i = 0; i < nr_servers; ++i) {
296         spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i, false);
297     }
298 
299     spapr_xive_hcall_init(spapr);
300 }
301 
302 static int spapr_irq_claim_xive(SpaprMachineState *spapr, int irq, bool lsi,
303                                 Error **errp)
304 {
305     if (!spapr_xive_irq_claim(spapr->xive, irq, lsi)) {
306         error_setg(errp, "IRQ %d is invalid", irq);
307         return -1;
308     }
309     return 0;
310 }
311 
312 static void spapr_irq_free_xive(SpaprMachineState *spapr, int irq, int num)
313 {
314     int i;
315 
316     for (i = irq; i < irq + num; ++i) {
317         spapr_xive_irq_free(spapr->xive, i);
318     }
319 }
320 
321 static qemu_irq spapr_qirq_xive(SpaprMachineState *spapr, int irq)
322 {
323     SpaprXive *xive = spapr->xive;
324 
325     if (irq >= xive->nr_irqs) {
326         return NULL;
327     }
328 
329     /* The sPAPR machine/device should have claimed the IRQ before */
330     assert(xive_eas_is_valid(&xive->eat[irq]));
331 
332     return spapr->qirqs[irq];
333 }
334 
335 static void spapr_irq_print_info_xive(SpaprMachineState *spapr,
336                                       Monitor *mon)
337 {
338     CPUState *cs;
339 
340     CPU_FOREACH(cs) {
341         PowerPCCPU *cpu = POWERPC_CPU(cs);
342 
343         xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon);
344     }
345 
346     spapr_xive_pic_print_info(spapr->xive, mon);
347 }
348 
349 static void spapr_irq_cpu_intc_create_xive(SpaprMachineState *spapr,
350                                            PowerPCCPU *cpu, Error **errp)
351 {
352     Error *local_err = NULL;
353     Object *obj;
354     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
355 
356     obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err);
357     if (local_err) {
358         error_propagate(errp, local_err);
359         return;
360     }
361 
362     spapr_cpu->tctx = XIVE_TCTX(obj);
363 
364     /*
365      * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
366      * don't beneficiate from the reset of the XIVE IRQ backend
367      */
368     spapr_xive_set_tctx_os_cam(spapr_cpu->tctx);
369 }
370 
371 static int spapr_irq_post_load_xive(SpaprMachineState *spapr, int version_id)
372 {
373     return spapr_xive_post_load(spapr->xive, version_id);
374 }
375 
376 static void spapr_irq_reset_xive(SpaprMachineState *spapr, Error **errp)
377 {
378     CPUState *cs;
379     Error *local_err = NULL;
380 
381     CPU_FOREACH(cs) {
382         PowerPCCPU *cpu = POWERPC_CPU(cs);
383 
384         /* (TCG) Set the OS CAM line of the thread interrupt context. */
385         spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx);
386     }
387 
388     spapr_irq_init_device(spapr, &spapr_irq_xive, &local_err);
389     if (local_err) {
390         error_propagate(errp, local_err);
391         return;
392     }
393 
394     /* Activate the XIVE MMIOs */
395     spapr_xive_mmio_set_enabled(spapr->xive, true);
396 }
397 
398 static void spapr_irq_set_irq_xive(void *opaque, int srcno, int val)
399 {
400     SpaprMachineState *spapr = opaque;
401 
402     if (kvm_irqchip_in_kernel()) {
403         kvmppc_xive_source_set_irq(&spapr->xive->source, srcno, val);
404     } else {
405         xive_source_set_irq(&spapr->xive->source, srcno, val);
406     }
407 }
408 
409 static const char *spapr_irq_get_nodename_xive(SpaprMachineState *spapr)
410 {
411     return spapr->xive->nodename;
412 }
413 
414 static void spapr_irq_init_emu_xive(SpaprMachineState *spapr, Error **errp)
415 {
416     spapr_xive_init(spapr->xive, errp);
417 }
418 
419 static void spapr_irq_init_kvm_xive(SpaprMachineState *spapr, Error **errp)
420 {
421     if (kvm_enabled()) {
422         kvmppc_xive_connect(spapr->xive, errp);
423     }
424 }
425 
426 /*
427  * XIVE uses the full IRQ number space. Set it to 8K to be compatible
428  * with XICS.
429  */
430 
431 #define SPAPR_IRQ_XIVE_NR_IRQS     0x2000
432 #define SPAPR_IRQ_XIVE_NR_MSIS     (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
433 
434 SpaprIrq spapr_irq_xive = {
435     .nr_irqs     = SPAPR_IRQ_XIVE_NR_IRQS,
436     .nr_msis     = SPAPR_IRQ_XIVE_NR_MSIS,
437     .ov5         = SPAPR_OV5_XIVE_EXPLOIT,
438 
439     .init        = spapr_irq_init_xive,
440     .claim       = spapr_irq_claim_xive,
441     .free        = spapr_irq_free_xive,
442     .qirq        = spapr_qirq_xive,
443     .print_info  = spapr_irq_print_info_xive,
444     .dt_populate = spapr_dt_xive,
445     .cpu_intc_create = spapr_irq_cpu_intc_create_xive,
446     .post_load   = spapr_irq_post_load_xive,
447     .reset       = spapr_irq_reset_xive,
448     .set_irq     = spapr_irq_set_irq_xive,
449     .get_nodename = spapr_irq_get_nodename_xive,
450     .init_emu    = spapr_irq_init_emu_xive,
451     .init_kvm    = spapr_irq_init_kvm_xive,
452 };
453 
454 /*
455  * Dual XIVE and XICS IRQ backend.
456  *
457  * Both interrupt mode, XIVE and XICS, objects are created but the
458  * machine starts in legacy interrupt mode (XICS). It can be changed
459  * by the CAS negotiation process and, in that case, the new mode is
460  * activated after an extra machine reset.
461  */
462 
463 /*
464  * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
465  * default.
466  */
467 static SpaprIrq *spapr_irq_current(SpaprMachineState *spapr)
468 {
469     return spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) ?
470         &spapr_irq_xive : &spapr_irq_xics;
471 }
472 
473 static void spapr_irq_init_dual(SpaprMachineState *spapr, int nr_irqs,
474                                 Error **errp)
475 {
476     Error *local_err = NULL;
477 
478     spapr_irq_xics.init(spapr, spapr_irq_xics.nr_irqs, &local_err);
479     if (local_err) {
480         error_propagate(errp, local_err);
481         return;
482     }
483 
484     spapr_irq_xive.init(spapr, spapr_irq_xive.nr_irqs, &local_err);
485     if (local_err) {
486         error_propagate(errp, local_err);
487         return;
488     }
489 }
490 
491 static int spapr_irq_claim_dual(SpaprMachineState *spapr, int irq, bool lsi,
492                                 Error **errp)
493 {
494     Error *local_err = NULL;
495     int ret;
496 
497     ret = spapr_irq_xics.claim(spapr, irq, lsi, &local_err);
498     if (local_err) {
499         error_propagate(errp, local_err);
500         return ret;
501     }
502 
503     ret = spapr_irq_xive.claim(spapr, irq, lsi, &local_err);
504     if (local_err) {
505         error_propagate(errp, local_err);
506         return ret;
507     }
508 
509     return ret;
510 }
511 
512 static void spapr_irq_free_dual(SpaprMachineState *spapr, int irq, int num)
513 {
514     spapr_irq_xics.free(spapr, irq, num);
515     spapr_irq_xive.free(spapr, irq, num);
516 }
517 
518 static qemu_irq spapr_qirq_dual(SpaprMachineState *spapr, int irq)
519 {
520     return spapr_irq_current(spapr)->qirq(spapr, irq);
521 }
522 
523 static void spapr_irq_print_info_dual(SpaprMachineState *spapr, Monitor *mon)
524 {
525     spapr_irq_current(spapr)->print_info(spapr, mon);
526 }
527 
528 static void spapr_irq_dt_populate_dual(SpaprMachineState *spapr,
529                                        uint32_t nr_servers, void *fdt,
530                                        uint32_t phandle)
531 {
532     spapr_irq_current(spapr)->dt_populate(spapr, nr_servers, fdt, phandle);
533 }
534 
535 static void spapr_irq_cpu_intc_create_dual(SpaprMachineState *spapr,
536                                            PowerPCCPU *cpu, Error **errp)
537 {
538     Error *local_err = NULL;
539 
540     spapr_irq_xive.cpu_intc_create(spapr, cpu, &local_err);
541     if (local_err) {
542         error_propagate(errp, local_err);
543         return;
544     }
545 
546     spapr_irq_xics.cpu_intc_create(spapr, cpu, errp);
547 }
548 
549 static int spapr_irq_post_load_dual(SpaprMachineState *spapr, int version_id)
550 {
551     /*
552      * Force a reset of the XIVE backend after migration. The machine
553      * defaults to XICS at startup.
554      */
555     if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) {
556         if (kvm_irqchip_in_kernel()) {
557             xics_kvm_disconnect(spapr, &error_fatal);
558         }
559         spapr_irq_xive.reset(spapr, &error_fatal);
560     }
561 
562     return spapr_irq_current(spapr)->post_load(spapr, version_id);
563 }
564 
565 static void spapr_irq_reset_dual(SpaprMachineState *spapr, Error **errp)
566 {
567     Error *local_err = NULL;
568 
569     /*
570      * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
571      * if selected.
572      */
573     spapr_xive_mmio_set_enabled(spapr->xive, false);
574 
575     /* Destroy all KVM devices */
576     if (kvm_irqchip_in_kernel()) {
577         xics_kvm_disconnect(spapr, &local_err);
578         if (local_err) {
579             error_propagate(errp, local_err);
580             error_prepend(errp, "KVM XICS disconnect failed: ");
581             return;
582         }
583         kvmppc_xive_disconnect(spapr->xive, &local_err);
584         if (local_err) {
585             error_propagate(errp, local_err);
586             error_prepend(errp, "KVM XIVE disconnect failed: ");
587             return;
588         }
589     }
590 
591     spapr_irq_current(spapr)->reset(spapr, errp);
592 }
593 
594 static void spapr_irq_set_irq_dual(void *opaque, int srcno, int val)
595 {
596     SpaprMachineState *spapr = opaque;
597 
598     spapr_irq_current(spapr)->set_irq(spapr, srcno, val);
599 }
600 
601 static const char *spapr_irq_get_nodename_dual(SpaprMachineState *spapr)
602 {
603     return spapr_irq_current(spapr)->get_nodename(spapr);
604 }
605 
606 /*
607  * Define values in sync with the XIVE and XICS backend
608  */
609 #define SPAPR_IRQ_DUAL_NR_IRQS     0x2000
610 #define SPAPR_IRQ_DUAL_NR_MSIS     (SPAPR_IRQ_DUAL_NR_IRQS - SPAPR_IRQ_MSI)
611 
612 SpaprIrq spapr_irq_dual = {
613     .nr_irqs     = SPAPR_IRQ_DUAL_NR_IRQS,
614     .nr_msis     = SPAPR_IRQ_DUAL_NR_MSIS,
615     .ov5         = SPAPR_OV5_XIVE_BOTH,
616 
617     .init        = spapr_irq_init_dual,
618     .claim       = spapr_irq_claim_dual,
619     .free        = spapr_irq_free_dual,
620     .qirq        = spapr_qirq_dual,
621     .print_info  = spapr_irq_print_info_dual,
622     .dt_populate = spapr_irq_dt_populate_dual,
623     .cpu_intc_create = spapr_irq_cpu_intc_create_dual,
624     .post_load   = spapr_irq_post_load_dual,
625     .reset       = spapr_irq_reset_dual,
626     .set_irq     = spapr_irq_set_irq_dual,
627     .get_nodename = spapr_irq_get_nodename_dual,
628     .init_emu    = NULL, /* should not be used */
629     .init_kvm    = NULL, /* should not be used */
630 };
631 
632 
633 static void spapr_irq_check(SpaprMachineState *spapr, Error **errp)
634 {
635     MachineState *machine = MACHINE(spapr);
636 
637     /*
638      * Sanity checks on non-P9 machines. On these, XIVE is not
639      * advertised, see spapr_dt_ov5_platform_support()
640      */
641     if (!ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00,
642                                0, spapr->max_compat_pvr)) {
643         /*
644          * If the 'dual' interrupt mode is selected, force XICS as CAS
645          * negotiation is useless.
646          */
647         if (spapr->irq == &spapr_irq_dual) {
648             spapr->irq = &spapr_irq_xics;
649             return;
650         }
651 
652         /*
653          * Non-P9 machines using only XIVE is a bogus setup. We have two
654          * scenarios to take into account because of the compat mode:
655          *
656          * 1. POWER7/8 machines should fail to init later on when creating
657          *    the XIVE interrupt presenters because a POWER9 exception
658          *    model is required.
659 
660          * 2. POWER9 machines using the POWER8 compat mode won't fail and
661          *    will let the OS boot with a partial XIVE setup : DT
662          *    properties but no hcalls.
663          *
664          * To cover both and not confuse the OS, add an early failure in
665          * QEMU.
666          */
667         if (spapr->irq == &spapr_irq_xive) {
668             error_setg(errp, "XIVE-only machines require a POWER9 CPU");
669             return;
670         }
671     }
672 
673     /*
674      * On a POWER9 host, some older KVM XICS devices cannot be destroyed and
675      * re-created. Detect that early to avoid QEMU to exit later when the
676      * guest reboots.
677      */
678     if (kvm_enabled() &&
679         spapr->irq == &spapr_irq_dual &&
680         machine_kernel_irqchip_required(machine) &&
681         xics_kvm_has_broken_disconnect(spapr)) {
682         error_setg(errp, "KVM is too old to support ic-mode=dual,kernel-irqchip=on");
683         return;
684     }
685 }
686 
687 /*
688  * sPAPR IRQ frontend routines for devices
689  */
690 void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
691 {
692     MachineState *machine = MACHINE(spapr);
693     Error *local_err = NULL;
694 
695     if (machine_kernel_irqchip_split(machine)) {
696         error_setg(errp, "kernel_irqchip split mode not supported on pseries");
697         return;
698     }
699 
700     if (!kvm_enabled() && machine_kernel_irqchip_required(machine)) {
701         error_setg(errp,
702                    "kernel_irqchip requested but only available with KVM");
703         return;
704     }
705 
706     spapr_irq_check(spapr, &local_err);
707     if (local_err) {
708         error_propagate(errp, local_err);
709         return;
710     }
711 
712     /* Initialize the MSI IRQ allocator. */
713     if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
714         spapr_irq_msi_init(spapr, spapr->irq->nr_msis);
715     }
716 
717     spapr->irq->init(spapr, spapr->irq->nr_irqs, errp);
718 
719     spapr->qirqs = qemu_allocate_irqs(spapr->irq->set_irq, spapr,
720                                       spapr->irq->nr_irqs);
721 }
722 
723 int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp)
724 {
725     return spapr->irq->claim(spapr, irq, lsi, errp);
726 }
727 
728 void spapr_irq_free(SpaprMachineState *spapr, int irq, int num)
729 {
730     spapr->irq->free(spapr, irq, num);
731 }
732 
733 qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq)
734 {
735     return spapr->irq->qirq(spapr, irq);
736 }
737 
738 int spapr_irq_post_load(SpaprMachineState *spapr, int version_id)
739 {
740     return spapr->irq->post_load(spapr, version_id);
741 }
742 
743 void spapr_irq_reset(SpaprMachineState *spapr, Error **errp)
744 {
745     if (spapr->irq->reset) {
746         spapr->irq->reset(spapr, errp);
747     }
748 }
749 
750 int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp)
751 {
752     const char *nodename = spapr->irq->get_nodename(spapr);
753     int offset, phandle;
754 
755     offset = fdt_subnode_offset(fdt, 0, nodename);
756     if (offset < 0) {
757         error_setg(errp, "Can't find node \"%s\": %s", nodename,
758                    fdt_strerror(offset));
759         return -1;
760     }
761 
762     phandle = fdt_get_phandle(fdt, offset);
763     if (!phandle) {
764         error_setg(errp, "Can't get phandle of node \"%s\"", nodename);
765         return -1;
766     }
767 
768     return phandle;
769 }
770 
771 /*
772  * XICS legacy routines - to deprecate one day
773  */
774 
775 static int ics_find_free_block(ICSState *ics, int num, int alignnum)
776 {
777     int first, i;
778 
779     for (first = 0; first < ics->nr_irqs; first += alignnum) {
780         if (num > (ics->nr_irqs - first)) {
781             return -1;
782         }
783         for (i = first; i < first + num; ++i) {
784             if (!ICS_IRQ_FREE(ics, i)) {
785                 break;
786             }
787         }
788         if (i == (first + num)) {
789             return first;
790         }
791     }
792 
793     return -1;
794 }
795 
796 int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp)
797 {
798     ICSState *ics = spapr->ics;
799     int first = -1;
800 
801     assert(ics);
802 
803     /*
804      * MSIMesage::data is used for storing VIRQ so
805      * it has to be aligned to num to support multiple
806      * MSI vectors. MSI-X is not affected by this.
807      * The hint is used for the first IRQ, the rest should
808      * be allocated continuously.
809      */
810     if (align) {
811         assert((num == 1) || (num == 2) || (num == 4) ||
812                (num == 8) || (num == 16) || (num == 32));
813         first = ics_find_free_block(ics, num, num);
814     } else {
815         first = ics_find_free_block(ics, num, 1);
816     }
817 
818     if (first < 0) {
819         error_setg(errp, "can't find a free %d-IRQ block", num);
820         return -1;
821     }
822 
823     return first + ics->offset;
824 }
825 
826 #define SPAPR_IRQ_XICS_LEGACY_NR_IRQS     0x400
827 
828 SpaprIrq spapr_irq_xics_legacy = {
829     .nr_irqs     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
830     .nr_msis     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
831     .ov5         = SPAPR_OV5_XIVE_LEGACY,
832 
833     .init        = spapr_irq_init_xics,
834     .claim       = spapr_irq_claim_xics,
835     .free        = spapr_irq_free_xics,
836     .qirq        = spapr_qirq_xics,
837     .print_info  = spapr_irq_print_info_xics,
838     .dt_populate = spapr_dt_xics,
839     .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
840     .post_load   = spapr_irq_post_load_xics,
841     .reset       = spapr_irq_reset_xics,
842     .set_irq     = spapr_irq_set_irq_xics,
843     .get_nodename = spapr_irq_get_nodename_xics,
844     .init_emu    = spapr_irq_init_emu_xics,
845     .init_kvm    = spapr_irq_init_kvm_xics,
846 };
847