1 /* 2 * QEMU sPAPR IOMMU (TCE) code 3 * 4 * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu/error-report.h" 21 #include "hw/hw.h" 22 #include "qemu/log.h" 23 #include "sysemu/kvm.h" 24 #include "hw/qdev.h" 25 #include "kvm_ppc.h" 26 #include "sysemu/dma.h" 27 #include "exec/address-spaces.h" 28 #include "trace.h" 29 30 #include "hw/ppc/spapr.h" 31 #include "hw/ppc/spapr_vio.h" 32 33 #include <libfdt.h> 34 35 enum sPAPRTCEAccess { 36 SPAPR_TCE_FAULT = 0, 37 SPAPR_TCE_RO = 1, 38 SPAPR_TCE_WO = 2, 39 SPAPR_TCE_RW = 3, 40 }; 41 42 #define IOMMU_PAGE_SIZE(shift) (1ULL << (shift)) 43 #define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1)) 44 45 static QLIST_HEAD(spapr_tce_tables, sPAPRTCETable) spapr_tce_tables; 46 47 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn) 48 { 49 sPAPRTCETable *tcet; 50 51 if (liobn & 0xFFFFFFFF00000000ULL) { 52 hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n", 53 liobn); 54 return NULL; 55 } 56 57 QLIST_FOREACH(tcet, &spapr_tce_tables, list) { 58 if (tcet->liobn == (uint32_t)liobn) { 59 return tcet; 60 } 61 } 62 63 return NULL; 64 } 65 66 static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce) 67 { 68 switch (tce & SPAPR_TCE_RW) { 69 case SPAPR_TCE_FAULT: 70 return IOMMU_NONE; 71 case SPAPR_TCE_RO: 72 return IOMMU_RO; 73 case SPAPR_TCE_WO: 74 return IOMMU_WO; 75 default: /* SPAPR_TCE_RW */ 76 return IOMMU_RW; 77 } 78 } 79 80 static uint64_t *spapr_tce_alloc_table(uint32_t liobn, 81 uint32_t page_shift, 82 uint32_t nb_table, 83 int *fd, 84 bool need_vfio) 85 { 86 uint64_t *table = NULL; 87 uint64_t window_size = (uint64_t)nb_table << page_shift; 88 89 if (kvm_enabled() && !(window_size >> 32)) { 90 table = kvmppc_create_spapr_tce(liobn, window_size, fd, need_vfio); 91 } 92 93 if (!table) { 94 *fd = -1; 95 table = g_malloc0(nb_table * sizeof(uint64_t)); 96 } 97 98 trace_spapr_iommu_new_table(liobn, table, *fd); 99 100 return table; 101 } 102 103 static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table) 104 { 105 if (!kvm_enabled() || 106 (kvmppc_remove_spapr_tce(table, fd, nb_table) != 0)) { 107 g_free(table); 108 } 109 } 110 111 /* Called from RCU critical section */ 112 static IOMMUTLBEntry spapr_tce_translate_iommu(MemoryRegion *iommu, hwaddr addr, 113 bool is_write) 114 { 115 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu); 116 uint64_t tce; 117 IOMMUTLBEntry ret = { 118 .target_as = &address_space_memory, 119 .iova = 0, 120 .translated_addr = 0, 121 .addr_mask = ~(hwaddr)0, 122 .perm = IOMMU_NONE, 123 }; 124 125 if ((addr >> tcet->page_shift) < tcet->nb_table) { 126 /* Check if we are in bound */ 127 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); 128 129 tce = tcet->table[addr >> tcet->page_shift]; 130 ret.iova = addr & page_mask; 131 ret.translated_addr = tce & page_mask; 132 ret.addr_mask = ~page_mask; 133 ret.perm = spapr_tce_iommu_access_flags(tce); 134 } 135 trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm, 136 ret.addr_mask); 137 138 return ret; 139 } 140 141 static void spapr_tce_table_pre_save(void *opaque) 142 { 143 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque); 144 145 tcet->mig_table = tcet->table; 146 tcet->mig_nb_table = tcet->nb_table; 147 148 trace_spapr_iommu_pre_save(tcet->liobn, tcet->mig_nb_table, 149 tcet->bus_offset, tcet->page_shift); 150 } 151 152 static int spapr_tce_table_post_load(void *opaque, int version_id) 153 { 154 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque); 155 uint32_t old_nb_table = tcet->nb_table; 156 uint64_t old_bus_offset = tcet->bus_offset; 157 uint32_t old_page_shift = tcet->page_shift; 158 159 if (tcet->vdev) { 160 spapr_vio_set_bypass(tcet->vdev, tcet->bypass); 161 } 162 163 if (tcet->mig_nb_table != tcet->nb_table) { 164 spapr_tce_table_disable(tcet); 165 } 166 167 if (tcet->mig_nb_table) { 168 if (!tcet->nb_table) { 169 spapr_tce_table_enable(tcet, old_page_shift, old_bus_offset, 170 tcet->mig_nb_table); 171 } 172 173 memcpy(tcet->table, tcet->mig_table, 174 tcet->nb_table * sizeof(tcet->table[0])); 175 176 free(tcet->mig_table); 177 tcet->mig_table = NULL; 178 } 179 180 trace_spapr_iommu_post_load(tcet->liobn, old_nb_table, tcet->nb_table, 181 tcet->bus_offset, tcet->page_shift); 182 183 return 0; 184 } 185 186 static bool spapr_tce_table_ex_needed(void *opaque) 187 { 188 sPAPRTCETable *tcet = opaque; 189 190 return tcet->bus_offset || tcet->page_shift != 0xC; 191 } 192 193 static const VMStateDescription vmstate_spapr_tce_table_ex = { 194 .name = "spapr_iommu_ex", 195 .version_id = 1, 196 .minimum_version_id = 1, 197 .needed = spapr_tce_table_ex_needed, 198 .fields = (VMStateField[]) { 199 VMSTATE_UINT64(bus_offset, sPAPRTCETable), 200 VMSTATE_UINT32(page_shift, sPAPRTCETable), 201 VMSTATE_END_OF_LIST() 202 }, 203 }; 204 205 static const VMStateDescription vmstate_spapr_tce_table = { 206 .name = "spapr_iommu", 207 .version_id = 2, 208 .minimum_version_id = 2, 209 .pre_save = spapr_tce_table_pre_save, 210 .post_load = spapr_tce_table_post_load, 211 .fields = (VMStateField []) { 212 /* Sanity check */ 213 VMSTATE_UINT32_EQUAL(liobn, sPAPRTCETable), 214 215 /* IOMMU state */ 216 VMSTATE_UINT32(mig_nb_table, sPAPRTCETable), 217 VMSTATE_BOOL(bypass, sPAPRTCETable), 218 VMSTATE_VARRAY_UINT32_ALLOC(mig_table, sPAPRTCETable, mig_nb_table, 0, 219 vmstate_info_uint64, uint64_t), 220 221 VMSTATE_END_OF_LIST() 222 }, 223 .subsections = (const VMStateDescription*[]) { 224 &vmstate_spapr_tce_table_ex, 225 NULL 226 } 227 }; 228 229 static MemoryRegionIOMMUOps spapr_iommu_ops = { 230 .translate = spapr_tce_translate_iommu, 231 }; 232 233 static int spapr_tce_table_realize(DeviceState *dev) 234 { 235 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); 236 Object *tcetobj = OBJECT(tcet); 237 char tmp[32]; 238 239 tcet->fd = -1; 240 tcet->need_vfio = false; 241 snprintf(tmp, sizeof(tmp), "tce-root-%x", tcet->liobn); 242 memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX); 243 244 snprintf(tmp, sizeof(tmp), "tce-iommu-%x", tcet->liobn); 245 memory_region_init_iommu(&tcet->iommu, tcetobj, &spapr_iommu_ops, tmp, 0); 246 247 QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list); 248 249 vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table, 250 tcet); 251 252 return 0; 253 } 254 255 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio) 256 { 257 size_t table_size = tcet->nb_table * sizeof(uint64_t); 258 void *newtable; 259 260 if (need_vfio == tcet->need_vfio) { 261 /* Nothing to do */ 262 return; 263 } 264 265 if (!need_vfio) { 266 /* FIXME: We don't support transition back to KVM accelerated 267 * TCEs yet */ 268 return; 269 } 270 271 tcet->need_vfio = true; 272 273 if (tcet->fd < 0) { 274 /* Table is already in userspace, nothing to be do */ 275 return; 276 } 277 278 newtable = g_malloc(table_size); 279 memcpy(newtable, tcet->table, table_size); 280 281 kvmppc_remove_spapr_tce(tcet->table, tcet->fd, tcet->nb_table); 282 283 tcet->fd = -1; 284 tcet->table = newtable; 285 } 286 287 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn) 288 { 289 sPAPRTCETable *tcet; 290 char tmp[32]; 291 292 if (spapr_tce_find_by_liobn(liobn)) { 293 fprintf(stderr, "Attempted to create TCE table with duplicate" 294 " LIOBN 0x%x\n", liobn); 295 return NULL; 296 } 297 298 tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE)); 299 tcet->liobn = liobn; 300 301 snprintf(tmp, sizeof(tmp), "tce-table-%x", liobn); 302 object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL); 303 304 object_property_set_bool(OBJECT(tcet), true, "realized", NULL); 305 306 return tcet; 307 } 308 309 void spapr_tce_table_enable(sPAPRTCETable *tcet, 310 uint32_t page_shift, uint64_t bus_offset, 311 uint32_t nb_table) 312 { 313 if (tcet->nb_table) { 314 error_report("Warning: trying to enable already enabled TCE table"); 315 return; 316 } 317 318 tcet->bus_offset = bus_offset; 319 tcet->page_shift = page_shift; 320 tcet->nb_table = nb_table; 321 tcet->table = spapr_tce_alloc_table(tcet->liobn, 322 tcet->page_shift, 323 tcet->nb_table, 324 &tcet->fd, 325 tcet->need_vfio); 326 327 memory_region_set_size(&tcet->iommu, 328 (uint64_t)tcet->nb_table << tcet->page_shift); 329 memory_region_add_subregion(&tcet->root, tcet->bus_offset, &tcet->iommu); 330 } 331 332 void spapr_tce_table_disable(sPAPRTCETable *tcet) 333 { 334 if (!tcet->nb_table) { 335 return; 336 } 337 338 memory_region_del_subregion(&tcet->root, &tcet->iommu); 339 memory_region_set_size(&tcet->iommu, 0); 340 341 spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table); 342 tcet->fd = -1; 343 tcet->table = NULL; 344 tcet->bus_offset = 0; 345 tcet->page_shift = 0; 346 tcet->nb_table = 0; 347 } 348 349 static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp) 350 { 351 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); 352 353 QLIST_REMOVE(tcet, list); 354 355 spapr_tce_table_disable(tcet); 356 } 357 358 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet) 359 { 360 return &tcet->root; 361 } 362 363 static void spapr_tce_reset(DeviceState *dev) 364 { 365 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); 366 size_t table_size = tcet->nb_table * sizeof(uint64_t); 367 368 memset(tcet->table, 0, table_size); 369 } 370 371 static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba, 372 target_ulong tce) 373 { 374 IOMMUTLBEntry entry; 375 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); 376 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift; 377 378 if (index >= tcet->nb_table) { 379 hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x" 380 TARGET_FMT_lx "\n", ioba); 381 return H_PARAMETER; 382 } 383 384 tcet->table[index] = tce; 385 386 entry.target_as = &address_space_memory, 387 entry.iova = (ioba - tcet->bus_offset) & page_mask; 388 entry.translated_addr = tce & page_mask; 389 entry.addr_mask = ~page_mask; 390 entry.perm = spapr_tce_iommu_access_flags(tce); 391 memory_region_notify_iommu(&tcet->iommu, entry); 392 393 return H_SUCCESS; 394 } 395 396 static target_ulong h_put_tce_indirect(PowerPCCPU *cpu, 397 sPAPRMachineState *spapr, 398 target_ulong opcode, target_ulong *args) 399 { 400 int i; 401 target_ulong liobn = args[0]; 402 target_ulong ioba = args[1]; 403 target_ulong ioba1 = ioba; 404 target_ulong tce_list = args[2]; 405 target_ulong npages = args[3]; 406 target_ulong ret = H_PARAMETER, tce = 0; 407 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn); 408 CPUState *cs = CPU(cpu); 409 hwaddr page_mask, page_size; 410 411 if (!tcet) { 412 return H_PARAMETER; 413 } 414 415 if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) { 416 return H_PARAMETER; 417 } 418 419 page_mask = IOMMU_PAGE_MASK(tcet->page_shift); 420 page_size = IOMMU_PAGE_SIZE(tcet->page_shift); 421 ioba &= page_mask; 422 423 for (i = 0; i < npages; ++i, ioba += page_size) { 424 tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong)); 425 426 ret = put_tce_emu(tcet, ioba, tce); 427 if (ret) { 428 break; 429 } 430 } 431 432 /* Trace last successful or the first problematic entry */ 433 i = i ? (i - 1) : 0; 434 if (SPAPR_IS_PCI_LIOBN(liobn)) { 435 trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret); 436 } else { 437 trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret); 438 } 439 return ret; 440 } 441 442 static target_ulong h_stuff_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr, 443 target_ulong opcode, target_ulong *args) 444 { 445 int i; 446 target_ulong liobn = args[0]; 447 target_ulong ioba = args[1]; 448 target_ulong tce_value = args[2]; 449 target_ulong npages = args[3]; 450 target_ulong ret = H_PARAMETER; 451 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn); 452 hwaddr page_mask, page_size; 453 454 if (!tcet) { 455 return H_PARAMETER; 456 } 457 458 if (npages > tcet->nb_table) { 459 return H_PARAMETER; 460 } 461 462 page_mask = IOMMU_PAGE_MASK(tcet->page_shift); 463 page_size = IOMMU_PAGE_SIZE(tcet->page_shift); 464 ioba &= page_mask; 465 466 for (i = 0; i < npages; ++i, ioba += page_size) { 467 ret = put_tce_emu(tcet, ioba, tce_value); 468 if (ret) { 469 break; 470 } 471 } 472 if (SPAPR_IS_PCI_LIOBN(liobn)) { 473 trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret); 474 } else { 475 trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret); 476 } 477 478 return ret; 479 } 480 481 static target_ulong h_put_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr, 482 target_ulong opcode, target_ulong *args) 483 { 484 target_ulong liobn = args[0]; 485 target_ulong ioba = args[1]; 486 target_ulong tce = args[2]; 487 target_ulong ret = H_PARAMETER; 488 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn); 489 490 if (tcet) { 491 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); 492 493 ioba &= page_mask; 494 495 ret = put_tce_emu(tcet, ioba, tce); 496 } 497 if (SPAPR_IS_PCI_LIOBN(liobn)) { 498 trace_spapr_iommu_pci_put(liobn, ioba, tce, ret); 499 } else { 500 trace_spapr_iommu_put(liobn, ioba, tce, ret); 501 } 502 503 return ret; 504 } 505 506 static target_ulong get_tce_emu(sPAPRTCETable *tcet, target_ulong ioba, 507 target_ulong *tce) 508 { 509 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift; 510 511 if (index >= tcet->nb_table) { 512 hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x" 513 TARGET_FMT_lx "\n", ioba); 514 return H_PARAMETER; 515 } 516 517 *tce = tcet->table[index]; 518 519 return H_SUCCESS; 520 } 521 522 static target_ulong h_get_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr, 523 target_ulong opcode, target_ulong *args) 524 { 525 target_ulong liobn = args[0]; 526 target_ulong ioba = args[1]; 527 target_ulong tce = 0; 528 target_ulong ret = H_PARAMETER; 529 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn); 530 531 if (tcet) { 532 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); 533 534 ioba &= page_mask; 535 536 ret = get_tce_emu(tcet, ioba, &tce); 537 if (!ret) { 538 args[0] = tce; 539 } 540 } 541 if (SPAPR_IS_PCI_LIOBN(liobn)) { 542 trace_spapr_iommu_pci_get(liobn, ioba, ret, tce); 543 } else { 544 trace_spapr_iommu_get(liobn, ioba, ret, tce); 545 } 546 547 return ret; 548 } 549 550 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 551 uint32_t liobn, uint64_t window, uint32_t size) 552 { 553 uint32_t dma_prop[5]; 554 int ret; 555 556 dma_prop[0] = cpu_to_be32(liobn); 557 dma_prop[1] = cpu_to_be32(window >> 32); 558 dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF); 559 dma_prop[3] = 0; /* window size is 32 bits */ 560 dma_prop[4] = cpu_to_be32(size); 561 562 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2); 563 if (ret < 0) { 564 return ret; 565 } 566 567 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2); 568 if (ret < 0) { 569 return ret; 570 } 571 572 ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop)); 573 if (ret < 0) { 574 return ret; 575 } 576 577 return 0; 578 } 579 580 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 581 sPAPRTCETable *tcet) 582 { 583 if (!tcet) { 584 return 0; 585 } 586 587 return spapr_dma_dt(fdt, node_off, propname, 588 tcet->liobn, 0, tcet->nb_table << tcet->page_shift); 589 } 590 591 static void spapr_tce_table_class_init(ObjectClass *klass, void *data) 592 { 593 DeviceClass *dc = DEVICE_CLASS(klass); 594 dc->init = spapr_tce_table_realize; 595 dc->reset = spapr_tce_reset; 596 dc->unrealize = spapr_tce_table_unrealize; 597 598 QLIST_INIT(&spapr_tce_tables); 599 600 /* hcall-tce */ 601 spapr_register_hypercall(H_PUT_TCE, h_put_tce); 602 spapr_register_hypercall(H_GET_TCE, h_get_tce); 603 spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect); 604 spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce); 605 } 606 607 static TypeInfo spapr_tce_table_info = { 608 .name = TYPE_SPAPR_TCE_TABLE, 609 .parent = TYPE_DEVICE, 610 .instance_size = sizeof(sPAPRTCETable), 611 .class_init = spapr_tce_table_class_init, 612 }; 613 614 static void register_types(void) 615 { 616 type_register_static(&spapr_tce_table_info); 617 } 618 619 type_init(register_types); 620