1 /* 2 * QEMU sPAPR IOMMU (TCE) code 3 * 4 * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu/error-report.h" 21 #include "hw/hw.h" 22 #include "qemu/log.h" 23 #include "sysemu/kvm.h" 24 #include "hw/qdev.h" 25 #include "kvm_ppc.h" 26 #include "sysemu/dma.h" 27 #include "exec/address-spaces.h" 28 #include "trace.h" 29 30 #include "hw/ppc/spapr.h" 31 #include "hw/ppc/spapr_vio.h" 32 33 #include <libfdt.h> 34 35 enum sPAPRTCEAccess { 36 SPAPR_TCE_FAULT = 0, 37 SPAPR_TCE_RO = 1, 38 SPAPR_TCE_WO = 2, 39 SPAPR_TCE_RW = 3, 40 }; 41 42 #define IOMMU_PAGE_SIZE(shift) (1ULL << (shift)) 43 #define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1)) 44 45 static QLIST_HEAD(spapr_tce_tables, sPAPRTCETable) spapr_tce_tables; 46 47 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn) 48 { 49 sPAPRTCETable *tcet; 50 51 if (liobn & 0xFFFFFFFF00000000ULL) { 52 hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n", 53 liobn); 54 return NULL; 55 } 56 57 QLIST_FOREACH(tcet, &spapr_tce_tables, list) { 58 if (tcet->liobn == (uint32_t)liobn) { 59 return tcet; 60 } 61 } 62 63 return NULL; 64 } 65 66 static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce) 67 { 68 switch (tce & SPAPR_TCE_RW) { 69 case SPAPR_TCE_FAULT: 70 return IOMMU_NONE; 71 case SPAPR_TCE_RO: 72 return IOMMU_RO; 73 case SPAPR_TCE_WO: 74 return IOMMU_WO; 75 default: /* SPAPR_TCE_RW */ 76 return IOMMU_RW; 77 } 78 } 79 80 static uint64_t *spapr_tce_alloc_table(uint32_t liobn, 81 uint32_t page_shift, 82 uint64_t bus_offset, 83 uint32_t nb_table, 84 int *fd, 85 bool need_vfio) 86 { 87 uint64_t *table = NULL; 88 89 if (kvm_enabled()) { 90 table = kvmppc_create_spapr_tce(liobn, page_shift, bus_offset, nb_table, 91 fd, need_vfio); 92 } 93 94 if (!table) { 95 *fd = -1; 96 table = g_malloc0(nb_table * sizeof(uint64_t)); 97 } 98 99 trace_spapr_iommu_new_table(liobn, table, *fd); 100 101 return table; 102 } 103 104 static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table) 105 { 106 if (!kvm_enabled() || 107 (kvmppc_remove_spapr_tce(table, fd, nb_table) != 0)) { 108 g_free(table); 109 } 110 } 111 112 /* Called from RCU critical section */ 113 static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu, 114 hwaddr addr, 115 IOMMUAccessFlags flag, 116 int iommu_idx) 117 { 118 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu); 119 uint64_t tce; 120 IOMMUTLBEntry ret = { 121 .target_as = &address_space_memory, 122 .iova = 0, 123 .translated_addr = 0, 124 .addr_mask = ~(hwaddr)0, 125 .perm = IOMMU_NONE, 126 }; 127 128 if ((addr >> tcet->page_shift) < tcet->nb_table) { 129 /* Check if we are in bound */ 130 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); 131 132 tce = tcet->table[addr >> tcet->page_shift]; 133 ret.iova = addr & page_mask; 134 ret.translated_addr = tce & page_mask; 135 ret.addr_mask = ~page_mask; 136 ret.perm = spapr_tce_iommu_access_flags(tce); 137 } 138 trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm, 139 ret.addr_mask); 140 141 return ret; 142 } 143 144 static int spapr_tce_table_pre_save(void *opaque) 145 { 146 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque); 147 148 tcet->mig_table = tcet->table; 149 tcet->mig_nb_table = tcet->nb_table; 150 151 trace_spapr_iommu_pre_save(tcet->liobn, tcet->mig_nb_table, 152 tcet->bus_offset, tcet->page_shift); 153 154 return 0; 155 } 156 157 static uint64_t spapr_tce_get_min_page_size(IOMMUMemoryRegion *iommu) 158 { 159 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu); 160 161 return 1ULL << tcet->page_shift; 162 } 163 164 static int spapr_tce_get_attr(IOMMUMemoryRegion *iommu, 165 enum IOMMUMemoryRegionAttr attr, void *data) 166 { 167 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu); 168 169 if (attr == IOMMU_ATTR_SPAPR_TCE_FD && kvmppc_has_cap_spapr_vfio()) { 170 *(int *) data = tcet->fd; 171 return 0; 172 } 173 174 return -EINVAL; 175 } 176 177 static void spapr_tce_notify_flag_changed(IOMMUMemoryRegion *iommu, 178 IOMMUNotifierFlag old, 179 IOMMUNotifierFlag new) 180 { 181 struct sPAPRTCETable *tbl = container_of(iommu, sPAPRTCETable, iommu); 182 183 if (old == IOMMU_NOTIFIER_NONE && new != IOMMU_NOTIFIER_NONE) { 184 spapr_tce_set_need_vfio(tbl, true); 185 } else if (old != IOMMU_NOTIFIER_NONE && new == IOMMU_NOTIFIER_NONE) { 186 spapr_tce_set_need_vfio(tbl, false); 187 } 188 } 189 190 static int spapr_tce_table_post_load(void *opaque, int version_id) 191 { 192 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque); 193 uint32_t old_nb_table = tcet->nb_table; 194 uint64_t old_bus_offset = tcet->bus_offset; 195 uint32_t old_page_shift = tcet->page_shift; 196 197 if (tcet->vdev) { 198 spapr_vio_set_bypass(tcet->vdev, tcet->bypass); 199 } 200 201 if (tcet->mig_nb_table != tcet->nb_table) { 202 spapr_tce_table_disable(tcet); 203 } 204 205 if (tcet->mig_nb_table) { 206 if (!tcet->nb_table) { 207 spapr_tce_table_enable(tcet, old_page_shift, old_bus_offset, 208 tcet->mig_nb_table); 209 } 210 211 memcpy(tcet->table, tcet->mig_table, 212 tcet->nb_table * sizeof(tcet->table[0])); 213 214 free(tcet->mig_table); 215 tcet->mig_table = NULL; 216 } 217 218 trace_spapr_iommu_post_load(tcet->liobn, old_nb_table, tcet->nb_table, 219 tcet->bus_offset, tcet->page_shift); 220 221 return 0; 222 } 223 224 static bool spapr_tce_table_ex_needed(void *opaque) 225 { 226 sPAPRTCETable *tcet = opaque; 227 228 return tcet->bus_offset || tcet->page_shift != 0xC; 229 } 230 231 static const VMStateDescription vmstate_spapr_tce_table_ex = { 232 .name = "spapr_iommu_ex", 233 .version_id = 1, 234 .minimum_version_id = 1, 235 .needed = spapr_tce_table_ex_needed, 236 .fields = (VMStateField[]) { 237 VMSTATE_UINT64(bus_offset, sPAPRTCETable), 238 VMSTATE_UINT32(page_shift, sPAPRTCETable), 239 VMSTATE_END_OF_LIST() 240 }, 241 }; 242 243 static const VMStateDescription vmstate_spapr_tce_table = { 244 .name = "spapr_iommu", 245 .version_id = 2, 246 .minimum_version_id = 2, 247 .pre_save = spapr_tce_table_pre_save, 248 .post_load = spapr_tce_table_post_load, 249 .fields = (VMStateField []) { 250 /* Sanity check */ 251 VMSTATE_UINT32_EQUAL(liobn, sPAPRTCETable, NULL), 252 253 /* IOMMU state */ 254 VMSTATE_UINT32(mig_nb_table, sPAPRTCETable), 255 VMSTATE_BOOL(bypass, sPAPRTCETable), 256 VMSTATE_VARRAY_UINT32_ALLOC(mig_table, sPAPRTCETable, mig_nb_table, 0, 257 vmstate_info_uint64, uint64_t), 258 259 VMSTATE_END_OF_LIST() 260 }, 261 .subsections = (const VMStateDescription*[]) { 262 &vmstate_spapr_tce_table_ex, 263 NULL 264 } 265 }; 266 267 static void spapr_tce_table_realize(DeviceState *dev, Error **errp) 268 { 269 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); 270 Object *tcetobj = OBJECT(tcet); 271 gchar *tmp; 272 273 tcet->fd = -1; 274 tcet->need_vfio = false; 275 tmp = g_strdup_printf("tce-root-%x", tcet->liobn); 276 memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX); 277 g_free(tmp); 278 279 tmp = g_strdup_printf("tce-iommu-%x", tcet->liobn); 280 memory_region_init_iommu(&tcet->iommu, sizeof(tcet->iommu), 281 TYPE_SPAPR_IOMMU_MEMORY_REGION, 282 tcetobj, tmp, 0); 283 g_free(tmp); 284 285 QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list); 286 287 vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table, 288 tcet); 289 } 290 291 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio) 292 { 293 size_t table_size = tcet->nb_table * sizeof(uint64_t); 294 uint64_t *oldtable; 295 int newfd = -1; 296 297 g_assert(need_vfio != tcet->need_vfio); 298 299 tcet->need_vfio = need_vfio; 300 301 if (!need_vfio || (tcet->fd != -1 && kvmppc_has_cap_spapr_vfio())) { 302 return; 303 } 304 305 oldtable = tcet->table; 306 307 tcet->table = spapr_tce_alloc_table(tcet->liobn, 308 tcet->page_shift, 309 tcet->bus_offset, 310 tcet->nb_table, 311 &newfd, 312 need_vfio); 313 memcpy(tcet->table, oldtable, table_size); 314 315 spapr_tce_free_table(oldtable, tcet->fd, tcet->nb_table); 316 317 tcet->fd = newfd; 318 } 319 320 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn) 321 { 322 sPAPRTCETable *tcet; 323 gchar *tmp; 324 325 if (spapr_tce_find_by_liobn(liobn)) { 326 error_report("Attempted to create TCE table with duplicate" 327 " LIOBN 0x%x", liobn); 328 return NULL; 329 } 330 331 tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE)); 332 tcet->liobn = liobn; 333 334 tmp = g_strdup_printf("tce-table-%x", liobn); 335 object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL); 336 g_free(tmp); 337 object_unref(OBJECT(tcet)); 338 339 object_property_set_bool(OBJECT(tcet), true, "realized", NULL); 340 341 return tcet; 342 } 343 344 void spapr_tce_table_enable(sPAPRTCETable *tcet, 345 uint32_t page_shift, uint64_t bus_offset, 346 uint32_t nb_table) 347 { 348 if (tcet->nb_table) { 349 warn_report("trying to enable already enabled TCE table"); 350 return; 351 } 352 353 tcet->bus_offset = bus_offset; 354 tcet->page_shift = page_shift; 355 tcet->nb_table = nb_table; 356 tcet->table = spapr_tce_alloc_table(tcet->liobn, 357 tcet->page_shift, 358 tcet->bus_offset, 359 tcet->nb_table, 360 &tcet->fd, 361 tcet->need_vfio); 362 363 memory_region_set_size(MEMORY_REGION(&tcet->iommu), 364 (uint64_t)tcet->nb_table << tcet->page_shift); 365 memory_region_add_subregion(&tcet->root, tcet->bus_offset, 366 MEMORY_REGION(&tcet->iommu)); 367 } 368 369 void spapr_tce_table_disable(sPAPRTCETable *tcet) 370 { 371 if (!tcet->nb_table) { 372 return; 373 } 374 375 memory_region_del_subregion(&tcet->root, MEMORY_REGION(&tcet->iommu)); 376 memory_region_set_size(MEMORY_REGION(&tcet->iommu), 0); 377 378 spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table); 379 tcet->fd = -1; 380 tcet->table = NULL; 381 tcet->bus_offset = 0; 382 tcet->page_shift = 0; 383 tcet->nb_table = 0; 384 } 385 386 static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp) 387 { 388 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); 389 390 vmstate_unregister(DEVICE(tcet), &vmstate_spapr_tce_table, tcet); 391 392 QLIST_REMOVE(tcet, list); 393 394 spapr_tce_table_disable(tcet); 395 } 396 397 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet) 398 { 399 return &tcet->root; 400 } 401 402 static void spapr_tce_reset(DeviceState *dev) 403 { 404 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); 405 size_t table_size = tcet->nb_table * sizeof(uint64_t); 406 407 if (tcet->nb_table) { 408 memset(tcet->table, 0, table_size); 409 } 410 } 411 412 static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba, 413 target_ulong tce) 414 { 415 IOMMUTLBEntry entry; 416 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); 417 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift; 418 419 if (index >= tcet->nb_table) { 420 hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x" 421 TARGET_FMT_lx "\n", ioba); 422 return H_PARAMETER; 423 } 424 425 tcet->table[index] = tce; 426 427 entry.target_as = &address_space_memory, 428 entry.iova = (ioba - tcet->bus_offset) & page_mask; 429 entry.translated_addr = tce & page_mask; 430 entry.addr_mask = ~page_mask; 431 entry.perm = spapr_tce_iommu_access_flags(tce); 432 memory_region_notify_iommu(&tcet->iommu, 0, entry); 433 434 return H_SUCCESS; 435 } 436 437 static target_ulong h_put_tce_indirect(PowerPCCPU *cpu, 438 sPAPRMachineState *spapr, 439 target_ulong opcode, target_ulong *args) 440 { 441 int i; 442 target_ulong liobn = args[0]; 443 target_ulong ioba = args[1]; 444 target_ulong ioba1 = ioba; 445 target_ulong tce_list = args[2]; 446 target_ulong npages = args[3]; 447 target_ulong ret = H_PARAMETER, tce = 0; 448 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn); 449 CPUState *cs = CPU(cpu); 450 hwaddr page_mask, page_size; 451 452 if (!tcet) { 453 return H_PARAMETER; 454 } 455 456 if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) { 457 return H_PARAMETER; 458 } 459 460 page_mask = IOMMU_PAGE_MASK(tcet->page_shift); 461 page_size = IOMMU_PAGE_SIZE(tcet->page_shift); 462 ioba &= page_mask; 463 464 for (i = 0; i < npages; ++i, ioba += page_size) { 465 tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong)); 466 467 ret = put_tce_emu(tcet, ioba, tce); 468 if (ret) { 469 break; 470 } 471 } 472 473 /* Trace last successful or the first problematic entry */ 474 i = i ? (i - 1) : 0; 475 if (SPAPR_IS_PCI_LIOBN(liobn)) { 476 trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret); 477 } else { 478 trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret); 479 } 480 return ret; 481 } 482 483 static target_ulong h_stuff_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr, 484 target_ulong opcode, target_ulong *args) 485 { 486 int i; 487 target_ulong liobn = args[0]; 488 target_ulong ioba = args[1]; 489 target_ulong tce_value = args[2]; 490 target_ulong npages = args[3]; 491 target_ulong ret = H_PARAMETER; 492 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn); 493 hwaddr page_mask, page_size; 494 495 if (!tcet) { 496 return H_PARAMETER; 497 } 498 499 if (npages > tcet->nb_table) { 500 return H_PARAMETER; 501 } 502 503 page_mask = IOMMU_PAGE_MASK(tcet->page_shift); 504 page_size = IOMMU_PAGE_SIZE(tcet->page_shift); 505 ioba &= page_mask; 506 507 for (i = 0; i < npages; ++i, ioba += page_size) { 508 ret = put_tce_emu(tcet, ioba, tce_value); 509 if (ret) { 510 break; 511 } 512 } 513 if (SPAPR_IS_PCI_LIOBN(liobn)) { 514 trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret); 515 } else { 516 trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret); 517 } 518 519 return ret; 520 } 521 522 static target_ulong h_put_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr, 523 target_ulong opcode, target_ulong *args) 524 { 525 target_ulong liobn = args[0]; 526 target_ulong ioba = args[1]; 527 target_ulong tce = args[2]; 528 target_ulong ret = H_PARAMETER; 529 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn); 530 531 if (tcet) { 532 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); 533 534 ioba &= page_mask; 535 536 ret = put_tce_emu(tcet, ioba, tce); 537 } 538 if (SPAPR_IS_PCI_LIOBN(liobn)) { 539 trace_spapr_iommu_pci_put(liobn, ioba, tce, ret); 540 } else { 541 trace_spapr_iommu_put(liobn, ioba, tce, ret); 542 } 543 544 return ret; 545 } 546 547 static target_ulong get_tce_emu(sPAPRTCETable *tcet, target_ulong ioba, 548 target_ulong *tce) 549 { 550 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift; 551 552 if (index >= tcet->nb_table) { 553 hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x" 554 TARGET_FMT_lx "\n", ioba); 555 return H_PARAMETER; 556 } 557 558 *tce = tcet->table[index]; 559 560 return H_SUCCESS; 561 } 562 563 static target_ulong h_get_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr, 564 target_ulong opcode, target_ulong *args) 565 { 566 target_ulong liobn = args[0]; 567 target_ulong ioba = args[1]; 568 target_ulong tce = 0; 569 target_ulong ret = H_PARAMETER; 570 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn); 571 572 if (tcet) { 573 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); 574 575 ioba &= page_mask; 576 577 ret = get_tce_emu(tcet, ioba, &tce); 578 if (!ret) { 579 args[0] = tce; 580 } 581 } 582 if (SPAPR_IS_PCI_LIOBN(liobn)) { 583 trace_spapr_iommu_pci_get(liobn, ioba, ret, tce); 584 } else { 585 trace_spapr_iommu_get(liobn, ioba, ret, tce); 586 } 587 588 return ret; 589 } 590 591 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 592 uint32_t liobn, uint64_t window, uint32_t size) 593 { 594 uint32_t dma_prop[5]; 595 int ret; 596 597 dma_prop[0] = cpu_to_be32(liobn); 598 dma_prop[1] = cpu_to_be32(window >> 32); 599 dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF); 600 dma_prop[3] = 0; /* window size is 32 bits */ 601 dma_prop[4] = cpu_to_be32(size); 602 603 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2); 604 if (ret < 0) { 605 return ret; 606 } 607 608 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2); 609 if (ret < 0) { 610 return ret; 611 } 612 613 ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop)); 614 if (ret < 0) { 615 return ret; 616 } 617 618 return 0; 619 } 620 621 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 622 sPAPRTCETable *tcet) 623 { 624 if (!tcet) { 625 return 0; 626 } 627 628 return spapr_dma_dt(fdt, node_off, propname, 629 tcet->liobn, 0, tcet->nb_table << tcet->page_shift); 630 } 631 632 static void spapr_tce_table_class_init(ObjectClass *klass, void *data) 633 { 634 DeviceClass *dc = DEVICE_CLASS(klass); 635 dc->realize = spapr_tce_table_realize; 636 dc->reset = spapr_tce_reset; 637 dc->unrealize = spapr_tce_table_unrealize; 638 /* Reason: This is just an internal device for handling the hypercalls */ 639 dc->user_creatable = false; 640 641 QLIST_INIT(&spapr_tce_tables); 642 643 /* hcall-tce */ 644 spapr_register_hypercall(H_PUT_TCE, h_put_tce); 645 spapr_register_hypercall(H_GET_TCE, h_get_tce); 646 spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect); 647 spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce); 648 } 649 650 static TypeInfo spapr_tce_table_info = { 651 .name = TYPE_SPAPR_TCE_TABLE, 652 .parent = TYPE_DEVICE, 653 .instance_size = sizeof(sPAPRTCETable), 654 .class_init = spapr_tce_table_class_init, 655 }; 656 657 static void spapr_iommu_memory_region_class_init(ObjectClass *klass, void *data) 658 { 659 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); 660 661 imrc->translate = spapr_tce_translate_iommu; 662 imrc->get_min_page_size = spapr_tce_get_min_page_size; 663 imrc->notify_flag_changed = spapr_tce_notify_flag_changed; 664 imrc->get_attr = spapr_tce_get_attr; 665 } 666 667 static const TypeInfo spapr_iommu_memory_region_info = { 668 .parent = TYPE_IOMMU_MEMORY_REGION, 669 .name = TYPE_SPAPR_IOMMU_MEMORY_REGION, 670 .class_init = spapr_iommu_memory_region_class_init, 671 }; 672 673 static void register_types(void) 674 { 675 type_register_static(&spapr_tce_table_info); 676 type_register_static(&spapr_iommu_memory_region_info); 677 } 678 679 type_init(register_types); 680