1 #include "qemu/osdep.h" 2 #include "qemu/cutils.h" 3 #include "qapi/error.h" 4 #include "sysemu/hw_accel.h" 5 #include "sysemu/runstate.h" 6 #include "qemu/log.h" 7 #include "qemu/main-loop.h" 8 #include "qemu/module.h" 9 #include "qemu/error-report.h" 10 #include "exec/exec-all.h" 11 #include "helper_regs.h" 12 #include "hw/ppc/ppc.h" 13 #include "hw/ppc/spapr.h" 14 #include "hw/ppc/spapr_cpu_core.h" 15 #include "mmu-hash64.h" 16 #include "cpu-models.h" 17 #include "trace.h" 18 #include "kvm_ppc.h" 19 #include "hw/ppc/fdt.h" 20 #include "hw/ppc/spapr_ovec.h" 21 #include "hw/ppc/spapr_numa.h" 22 #include "mmu-book3s-v3.h" 23 #include "hw/mem/memory-device.h" 24 25 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) 26 { 27 MachineState *machine = MACHINE(spapr); 28 DeviceMemoryState *dms = machine->device_memory; 29 30 if (addr < machine->ram_size) { 31 return true; 32 } 33 if ((addr >= dms->base) 34 && ((addr - dms->base) < memory_region_size(&dms->mr))) { 35 return true; 36 } 37 38 return false; 39 } 40 41 /* Convert a return code from the KVM ioctl()s implementing resize HPT 42 * into a PAPR hypercall return code */ 43 static target_ulong resize_hpt_convert_rc(int ret) 44 { 45 if (ret >= 100000) { 46 return H_LONG_BUSY_ORDER_100_SEC; 47 } else if (ret >= 10000) { 48 return H_LONG_BUSY_ORDER_10_SEC; 49 } else if (ret >= 1000) { 50 return H_LONG_BUSY_ORDER_1_SEC; 51 } else if (ret >= 100) { 52 return H_LONG_BUSY_ORDER_100_MSEC; 53 } else if (ret >= 10) { 54 return H_LONG_BUSY_ORDER_10_MSEC; 55 } else if (ret > 0) { 56 return H_LONG_BUSY_ORDER_1_MSEC; 57 } 58 59 switch (ret) { 60 case 0: 61 return H_SUCCESS; 62 case -EPERM: 63 return H_AUTHORITY; 64 case -EINVAL: 65 return H_PARAMETER; 66 case -ENXIO: 67 return H_CLOSED; 68 case -ENOSPC: 69 return H_PTEG_FULL; 70 case -EBUSY: 71 return H_BUSY; 72 case -ENOMEM: 73 return H_NO_MEM; 74 default: 75 return H_HARDWARE; 76 } 77 } 78 79 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 80 SpaprMachineState *spapr, 81 target_ulong opcode, 82 target_ulong *args) 83 { 84 target_ulong flags = args[0]; 85 int shift = args[1]; 86 uint64_t current_ram_size; 87 int rc; 88 89 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 90 return H_AUTHORITY; 91 } 92 93 if (!spapr->htab_shift) { 94 /* Radix guest, no HPT */ 95 return H_NOT_AVAILABLE; 96 } 97 98 trace_spapr_h_resize_hpt_prepare(flags, shift); 99 100 if (flags != 0) { 101 return H_PARAMETER; 102 } 103 104 if (shift && ((shift < 18) || (shift > 46))) { 105 return H_PARAMETER; 106 } 107 108 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 109 110 /* We only allow the guest to allocate an HPT one order above what 111 * we'd normally give them (to stop a small guest claiming a huge 112 * chunk of resources in the HPT */ 113 if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 114 return H_RESOURCE; 115 } 116 117 rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 118 if (rc != -ENOSYS) { 119 return resize_hpt_convert_rc(rc); 120 } 121 122 if (kvm_enabled()) { 123 return H_HARDWARE; 124 } 125 126 return softmmu_resize_hpt_prepare(cpu, spapr, shift); 127 } 128 129 static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 130 { 131 int ret; 132 133 cpu_synchronize_state(cs); 134 135 ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 136 if (ret < 0) { 137 error_report("failed to push sregs to KVM: %s", strerror(-ret)); 138 exit(1); 139 } 140 } 141 142 void push_sregs_to_kvm_pr(SpaprMachineState *spapr) 143 { 144 CPUState *cs; 145 146 /* 147 * This is a hack for the benefit of KVM PR - it abuses the SDR1 148 * slot in kvm_sregs to communicate the userspace address of the 149 * HPT 150 */ 151 if (!kvm_enabled() || !spapr->htab) { 152 return; 153 } 154 155 CPU_FOREACH(cs) { 156 run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 157 } 158 } 159 160 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 161 SpaprMachineState *spapr, 162 target_ulong opcode, 163 target_ulong *args) 164 { 165 target_ulong flags = args[0]; 166 target_ulong shift = args[1]; 167 int rc; 168 169 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 170 return H_AUTHORITY; 171 } 172 173 if (!spapr->htab_shift) { 174 /* Radix guest, no HPT */ 175 return H_NOT_AVAILABLE; 176 } 177 178 trace_spapr_h_resize_hpt_commit(flags, shift); 179 180 rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 181 if (rc != -ENOSYS) { 182 rc = resize_hpt_convert_rc(rc); 183 if (rc == H_SUCCESS) { 184 /* Need to set the new htab_shift in the machine state */ 185 spapr->htab_shift = shift; 186 } 187 return rc; 188 } 189 190 if (kvm_enabled()) { 191 return H_HARDWARE; 192 } 193 194 return softmmu_resize_hpt_commit(cpu, spapr, flags, shift); 195 } 196 197 198 199 static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, 200 target_ulong opcode, target_ulong *args) 201 { 202 cpu_synchronize_state(CPU(cpu)); 203 cpu->env.spr[SPR_SPRG0] = args[0]; 204 205 return H_SUCCESS; 206 } 207 208 static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 209 target_ulong opcode, target_ulong *args) 210 { 211 if (!ppc_has_spr(cpu, SPR_DABR)) { 212 return H_HARDWARE; /* DABR register not available */ 213 } 214 cpu_synchronize_state(CPU(cpu)); 215 216 if (ppc_has_spr(cpu, SPR_DABRX)) { 217 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 218 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 219 return H_RESERVED_DABR; 220 } 221 222 cpu->env.spr[SPR_DABR] = args[0]; 223 return H_SUCCESS; 224 } 225 226 static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 227 target_ulong opcode, target_ulong *args) 228 { 229 target_ulong dabrx = args[1]; 230 231 if (!ppc_has_spr(cpu, SPR_DABR) || !ppc_has_spr(cpu, SPR_DABRX)) { 232 return H_HARDWARE; 233 } 234 235 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 236 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 237 return H_PARAMETER; 238 } 239 240 cpu_synchronize_state(CPU(cpu)); 241 cpu->env.spr[SPR_DABRX] = dabrx; 242 cpu->env.spr[SPR_DABR] = args[0]; 243 244 return H_SUCCESS; 245 } 246 247 static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, 248 target_ulong opcode, target_ulong *args) 249 { 250 target_ulong flags = args[0]; 251 hwaddr dst = args[1]; 252 hwaddr src = args[2]; 253 hwaddr len = TARGET_PAGE_SIZE; 254 uint8_t *pdst, *psrc; 255 target_long ret = H_SUCCESS; 256 257 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 258 | H_COPY_PAGE | H_ZERO_PAGE)) { 259 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 260 flags); 261 return H_PARAMETER; 262 } 263 264 /* Map-in destination */ 265 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 266 return H_PARAMETER; 267 } 268 pdst = cpu_physical_memory_map(dst, &len, true); 269 if (!pdst || len != TARGET_PAGE_SIZE) { 270 return H_PARAMETER; 271 } 272 273 if (flags & H_COPY_PAGE) { 274 /* Map-in source, copy to destination, and unmap source again */ 275 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 276 ret = H_PARAMETER; 277 goto unmap_out; 278 } 279 psrc = cpu_physical_memory_map(src, &len, false); 280 if (!psrc || len != TARGET_PAGE_SIZE) { 281 ret = H_PARAMETER; 282 goto unmap_out; 283 } 284 memcpy(pdst, psrc, len); 285 cpu_physical_memory_unmap(psrc, len, 0, len); 286 } else if (flags & H_ZERO_PAGE) { 287 memset(pdst, 0, len); /* Just clear the destination page */ 288 } 289 290 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 291 kvmppc_dcbst_range(cpu, pdst, len); 292 } 293 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 294 if (kvm_enabled()) { 295 kvmppc_icbi_range(cpu, pdst, len); 296 } else { 297 tb_flush(CPU(cpu)); 298 } 299 } 300 301 unmap_out: 302 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 303 return ret; 304 } 305 306 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 307 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 308 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 309 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 310 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 311 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 312 313 static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) 314 { 315 CPUState *cs = CPU(cpu); 316 CPUPPCState *env = &cpu->env; 317 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 318 uint16_t size; 319 uint8_t tmp; 320 321 if (vpa == 0) { 322 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 323 return H_HARDWARE; 324 } 325 326 if (vpa % env->dcache_line_size) { 327 return H_PARAMETER; 328 } 329 /* FIXME: bounds check the address */ 330 331 size = lduw_be_phys(cs->as, vpa + 0x4); 332 333 if (size < VPA_MIN_SIZE) { 334 return H_PARAMETER; 335 } 336 337 /* VPA is not allowed to cross a page boundary */ 338 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 339 return H_PARAMETER; 340 } 341 342 spapr_cpu->vpa_addr = vpa; 343 344 tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET); 345 tmp |= VPA_SHARED_PROC_VAL; 346 stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 347 348 return H_SUCCESS; 349 } 350 351 static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) 352 { 353 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 354 355 if (spapr_cpu->slb_shadow_addr) { 356 return H_RESOURCE; 357 } 358 359 if (spapr_cpu->dtl_addr) { 360 return H_RESOURCE; 361 } 362 363 spapr_cpu->vpa_addr = 0; 364 return H_SUCCESS; 365 } 366 367 static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 368 { 369 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 370 uint32_t size; 371 372 if (addr == 0) { 373 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 374 return H_HARDWARE; 375 } 376 377 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 378 if (size < 0x8) { 379 return H_PARAMETER; 380 } 381 382 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 383 return H_PARAMETER; 384 } 385 386 if (!spapr_cpu->vpa_addr) { 387 return H_RESOURCE; 388 } 389 390 spapr_cpu->slb_shadow_addr = addr; 391 spapr_cpu->slb_shadow_size = size; 392 393 return H_SUCCESS; 394 } 395 396 static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 397 { 398 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 399 400 spapr_cpu->slb_shadow_addr = 0; 401 spapr_cpu->slb_shadow_size = 0; 402 return H_SUCCESS; 403 } 404 405 static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) 406 { 407 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 408 uint32_t size; 409 410 if (addr == 0) { 411 hcall_dprintf("Can't cope with DTL at logical 0\n"); 412 return H_HARDWARE; 413 } 414 415 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 416 417 if (size < 48) { 418 return H_PARAMETER; 419 } 420 421 if (!spapr_cpu->vpa_addr) { 422 return H_RESOURCE; 423 } 424 425 spapr_cpu->dtl_addr = addr; 426 spapr_cpu->dtl_size = size; 427 428 return H_SUCCESS; 429 } 430 431 static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) 432 { 433 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 434 435 spapr_cpu->dtl_addr = 0; 436 spapr_cpu->dtl_size = 0; 437 438 return H_SUCCESS; 439 } 440 441 static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr, 442 target_ulong opcode, target_ulong *args) 443 { 444 target_ulong flags = args[0]; 445 target_ulong procno = args[1]; 446 target_ulong vpa = args[2]; 447 target_ulong ret = H_PARAMETER; 448 PowerPCCPU *tcpu; 449 450 tcpu = spapr_find_cpu(procno); 451 if (!tcpu) { 452 return H_PARAMETER; 453 } 454 455 switch (flags) { 456 case FLAGS_REGISTER_VPA: 457 ret = register_vpa(tcpu, vpa); 458 break; 459 460 case FLAGS_DEREGISTER_VPA: 461 ret = deregister_vpa(tcpu, vpa); 462 break; 463 464 case FLAGS_REGISTER_SLBSHADOW: 465 ret = register_slb_shadow(tcpu, vpa); 466 break; 467 468 case FLAGS_DEREGISTER_SLBSHADOW: 469 ret = deregister_slb_shadow(tcpu, vpa); 470 break; 471 472 case FLAGS_REGISTER_DTL: 473 ret = register_dtl(tcpu, vpa); 474 break; 475 476 case FLAGS_DEREGISTER_DTL: 477 ret = deregister_dtl(tcpu, vpa); 478 break; 479 } 480 481 return ret; 482 } 483 484 static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, 485 target_ulong opcode, target_ulong *args) 486 { 487 CPUPPCState *env = &cpu->env; 488 CPUState *cs = CPU(cpu); 489 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 490 491 env->msr |= (1ULL << MSR_EE); 492 hreg_compute_hflags(env); 493 494 if (spapr_cpu->prod) { 495 spapr_cpu->prod = false; 496 return H_SUCCESS; 497 } 498 499 if (!cpu_has_work(cs)) { 500 cs->halted = 1; 501 cs->exception_index = EXCP_HLT; 502 cs->exit_request = 1; 503 } 504 505 return H_SUCCESS; 506 } 507 508 /* 509 * Confer to self, aka join. Cede could use the same pattern as well, if 510 * EXCP_HLT can be changed to ECXP_HALTED. 511 */ 512 static target_ulong h_confer_self(PowerPCCPU *cpu) 513 { 514 CPUState *cs = CPU(cpu); 515 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 516 517 if (spapr_cpu->prod) { 518 spapr_cpu->prod = false; 519 return H_SUCCESS; 520 } 521 cs->halted = 1; 522 cs->exception_index = EXCP_HALTED; 523 cs->exit_request = 1; 524 525 return H_SUCCESS; 526 } 527 528 static target_ulong h_join(PowerPCCPU *cpu, SpaprMachineState *spapr, 529 target_ulong opcode, target_ulong *args) 530 { 531 CPUPPCState *env = &cpu->env; 532 CPUState *cs; 533 bool last_unjoined = true; 534 535 if (env->msr & (1ULL << MSR_EE)) { 536 return H_BAD_MODE; 537 } 538 539 /* 540 * Must not join the last CPU running. Interestingly, no such restriction 541 * for H_CONFER-to-self, but that is probably not intended to be used 542 * when H_JOIN is available. 543 */ 544 CPU_FOREACH(cs) { 545 PowerPCCPU *c = POWERPC_CPU(cs); 546 CPUPPCState *e = &c->env; 547 if (c == cpu) { 548 continue; 549 } 550 551 /* Don't have a way to indicate joined, so use halted && MSR[EE]=0 */ 552 if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { 553 last_unjoined = false; 554 break; 555 } 556 } 557 if (last_unjoined) { 558 return H_CONTINUE; 559 } 560 561 return h_confer_self(cpu); 562 } 563 564 static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr, 565 target_ulong opcode, target_ulong *args) 566 { 567 target_long target = args[0]; 568 uint32_t dispatch = args[1]; 569 CPUState *cs = CPU(cpu); 570 SpaprCpuState *spapr_cpu; 571 572 /* 573 * -1 means confer to all other CPUs without dispatch counter check, 574 * otherwise it's a targeted confer. 575 */ 576 if (target != -1) { 577 PowerPCCPU *target_cpu = spapr_find_cpu(target); 578 uint32_t target_dispatch; 579 580 if (!target_cpu) { 581 return H_PARAMETER; 582 } 583 584 /* 585 * target == self is a special case, we wait until prodded, without 586 * dispatch counter check. 587 */ 588 if (cpu == target_cpu) { 589 return h_confer_self(cpu); 590 } 591 592 spapr_cpu = spapr_cpu_state(target_cpu); 593 if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) { 594 return H_SUCCESS; 595 } 596 597 target_dispatch = ldl_be_phys(cs->as, 598 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 599 if (target_dispatch != dispatch) { 600 return H_SUCCESS; 601 } 602 603 /* 604 * The targeted confer does not do anything special beyond yielding 605 * the current vCPU, but even this should be better than nothing. 606 * At least for single-threaded tcg, it gives the target a chance to 607 * run before we run again. Multi-threaded tcg does not really do 608 * anything with EXCP_YIELD yet. 609 */ 610 } 611 612 cs->exception_index = EXCP_YIELD; 613 cs->exit_request = 1; 614 cpu_loop_exit(cs); 615 616 return H_SUCCESS; 617 } 618 619 static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr, 620 target_ulong opcode, target_ulong *args) 621 { 622 target_long target = args[0]; 623 PowerPCCPU *tcpu; 624 CPUState *cs; 625 SpaprCpuState *spapr_cpu; 626 627 tcpu = spapr_find_cpu(target); 628 cs = CPU(tcpu); 629 if (!cs) { 630 return H_PARAMETER; 631 } 632 633 spapr_cpu = spapr_cpu_state(tcpu); 634 spapr_cpu->prod = true; 635 cs->halted = 0; 636 qemu_cpu_kick(cs); 637 638 return H_SUCCESS; 639 } 640 641 static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, 642 target_ulong opcode, target_ulong *args) 643 { 644 target_ulong rtas_r3 = args[0]; 645 uint32_t token = rtas_ld(rtas_r3, 0); 646 uint32_t nargs = rtas_ld(rtas_r3, 1); 647 uint32_t nret = rtas_ld(rtas_r3, 2); 648 649 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 650 nret, rtas_r3 + 12 + 4*nargs); 651 } 652 653 static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr, 654 target_ulong opcode, target_ulong *args) 655 { 656 CPUState *cs = CPU(cpu); 657 target_ulong size = args[0]; 658 target_ulong addr = args[1]; 659 660 switch (size) { 661 case 1: 662 args[0] = ldub_phys(cs->as, addr); 663 return H_SUCCESS; 664 case 2: 665 args[0] = lduw_phys(cs->as, addr); 666 return H_SUCCESS; 667 case 4: 668 args[0] = ldl_phys(cs->as, addr); 669 return H_SUCCESS; 670 case 8: 671 args[0] = ldq_phys(cs->as, addr); 672 return H_SUCCESS; 673 } 674 return H_PARAMETER; 675 } 676 677 static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr, 678 target_ulong opcode, target_ulong *args) 679 { 680 CPUState *cs = CPU(cpu); 681 682 target_ulong size = args[0]; 683 target_ulong addr = args[1]; 684 target_ulong val = args[2]; 685 686 switch (size) { 687 case 1: 688 stb_phys(cs->as, addr, val); 689 return H_SUCCESS; 690 case 2: 691 stw_phys(cs->as, addr, val); 692 return H_SUCCESS; 693 case 4: 694 stl_phys(cs->as, addr, val); 695 return H_SUCCESS; 696 case 8: 697 stq_phys(cs->as, addr, val); 698 return H_SUCCESS; 699 } 700 return H_PARAMETER; 701 } 702 703 static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr, 704 target_ulong opcode, target_ulong *args) 705 { 706 CPUState *cs = CPU(cpu); 707 708 target_ulong dst = args[0]; /* Destination address */ 709 target_ulong src = args[1]; /* Source address */ 710 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 711 target_ulong count = args[3]; /* Element count */ 712 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 713 uint64_t tmp; 714 unsigned int mask = (1 << esize) - 1; 715 int step = 1 << esize; 716 717 if (count > 0x80000000) { 718 return H_PARAMETER; 719 } 720 721 if ((dst & mask) || (src & mask) || (op > 1)) { 722 return H_PARAMETER; 723 } 724 725 if (dst >= src && dst < (src + (count << esize))) { 726 dst = dst + ((count - 1) << esize); 727 src = src + ((count - 1) << esize); 728 step = -step; 729 } 730 731 while (count--) { 732 switch (esize) { 733 case 0: 734 tmp = ldub_phys(cs->as, src); 735 break; 736 case 1: 737 tmp = lduw_phys(cs->as, src); 738 break; 739 case 2: 740 tmp = ldl_phys(cs->as, src); 741 break; 742 case 3: 743 tmp = ldq_phys(cs->as, src); 744 break; 745 default: 746 return H_PARAMETER; 747 } 748 if (op == 1) { 749 tmp = ~tmp; 750 } 751 switch (esize) { 752 case 0: 753 stb_phys(cs->as, dst, tmp); 754 break; 755 case 1: 756 stw_phys(cs->as, dst, tmp); 757 break; 758 case 2: 759 stl_phys(cs->as, dst, tmp); 760 break; 761 case 3: 762 stq_phys(cs->as, dst, tmp); 763 break; 764 } 765 dst = dst + step; 766 src = src + step; 767 } 768 769 return H_SUCCESS; 770 } 771 772 static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr, 773 target_ulong opcode, target_ulong *args) 774 { 775 /* Nothing to do on emulation, KVM will trap this in the kernel */ 776 return H_SUCCESS; 777 } 778 779 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, 780 target_ulong opcode, target_ulong *args) 781 { 782 /* Nothing to do on emulation, KVM will trap this in the kernel */ 783 return H_SUCCESS; 784 } 785 786 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 787 SpaprMachineState *spapr, 788 target_ulong mflags, 789 target_ulong value1, 790 target_ulong value2) 791 { 792 if (value1) { 793 return H_P3; 794 } 795 if (value2) { 796 return H_P4; 797 } 798 799 switch (mflags) { 800 case H_SET_MODE_ENDIAN_BIG: 801 spapr_set_all_lpcrs(0, LPCR_ILE); 802 spapr_pci_switch_vga(spapr, true); 803 return H_SUCCESS; 804 805 case H_SET_MODE_ENDIAN_LITTLE: 806 spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); 807 spapr_pci_switch_vga(spapr, false); 808 return H_SUCCESS; 809 } 810 811 return H_UNSUPPORTED_FLAG; 812 } 813 814 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 815 target_ulong mflags, 816 target_ulong value1, 817 target_ulong value2) 818 { 819 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 820 821 if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 822 return H_P2; 823 } 824 if (value1) { 825 return H_P3; 826 } 827 if (value2) { 828 return H_P4; 829 } 830 831 if (mflags == 1) { 832 /* AIL=1 is reserved in POWER8/POWER9/POWER10 */ 833 return H_UNSUPPORTED_FLAG; 834 } 835 836 if (mflags == 2 && (pcc->insns_flags2 & PPC2_ISA310)) { 837 /* AIL=2 is reserved in POWER10 (ISA v3.1) */ 838 return H_UNSUPPORTED_FLAG; 839 } 840 841 spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); 842 843 return H_SUCCESS; 844 } 845 846 static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, 847 target_ulong opcode, target_ulong *args) 848 { 849 target_ulong resource = args[1]; 850 target_ulong ret = H_P2; 851 852 switch (resource) { 853 case H_SET_MODE_RESOURCE_LE: 854 ret = h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[3]); 855 break; 856 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 857 ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 858 args[2], args[3]); 859 break; 860 } 861 862 return ret; 863 } 864 865 static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, 866 target_ulong opcode, target_ulong *args) 867 { 868 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 869 opcode, " (H_CLEAN_SLB)"); 870 return H_FUNCTION; 871 } 872 873 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr, 874 target_ulong opcode, target_ulong *args) 875 { 876 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 877 opcode, " (H_INVALIDATE_PID)"); 878 return H_FUNCTION; 879 } 880 881 static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, 882 uint64_t patbe_old, uint64_t patbe_new) 883 { 884 /* 885 * We have 4 Options: 886 * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 887 * HASH->RADIX : Free HPT 888 * RADIX->HASH : Allocate HPT 889 * NOTHING->HASH : Allocate HPT 890 * Note: NOTHING implies the case where we said the guest could choose 891 * later and so assumed radix and now it's called H_REG_PROC_TBL 892 */ 893 894 if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) { 895 /* We assume RADIX, so this catches all the "Do Nothing" cases */ 896 } else if (!(patbe_old & PATE1_GR)) { 897 /* HASH->RADIX : Free HPT */ 898 spapr_free_hpt(spapr); 899 } else if (!(patbe_new & PATE1_GR)) { 900 /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 901 spapr_setup_hpt(spapr); 902 } 903 return; 904 } 905 906 #define FLAGS_MASK 0x01FULL 907 #define FLAG_MODIFY 0x10 908 #define FLAG_REGISTER 0x08 909 #define FLAG_RADIX 0x04 910 #define FLAG_HASH_PROC_TBL 0x02 911 #define FLAG_GTSE 0x01 912 913 static target_ulong h_register_process_table(PowerPCCPU *cpu, 914 SpaprMachineState *spapr, 915 target_ulong opcode, 916 target_ulong *args) 917 { 918 target_ulong flags = args[0]; 919 target_ulong proc_tbl = args[1]; 920 target_ulong page_size = args[2]; 921 target_ulong table_size = args[3]; 922 target_ulong update_lpcr = 0; 923 target_ulong table_byte_size; 924 uint64_t cproc; 925 926 if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 927 return H_PARAMETER; 928 } 929 if (flags & FLAG_MODIFY) { 930 if (flags & FLAG_REGISTER) { 931 /* Check process table alignment */ 932 table_byte_size = 1ULL << (table_size + 12); 933 if (proc_tbl & (table_byte_size - 1)) { 934 qemu_log_mask(LOG_GUEST_ERROR, 935 "%s: process table not properly aligned: proc_tbl 0x" 936 TARGET_FMT_lx" proc_tbl_size 0x"TARGET_FMT_lx"\n", 937 __func__, proc_tbl, table_byte_size); 938 } 939 if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 940 if (proc_tbl & 0xfff || proc_tbl >> 60) { 941 return H_P2; 942 } else if (page_size) { 943 return H_P3; 944 } else if (table_size > 24) { 945 return H_P4; 946 } 947 cproc = PATE1_GR | proc_tbl | table_size; 948 } else { /* Register new HPT process table */ 949 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 950 /* TODO - Not Supported */ 951 /* Technically caused by flag bits => H_PARAMETER */ 952 return H_PARAMETER; 953 } else { /* Hash with SLB */ 954 if (proc_tbl >> 38) { 955 return H_P2; 956 } else if (page_size & ~0x7) { 957 return H_P3; 958 } else if (table_size > 24) { 959 return H_P4; 960 } 961 } 962 cproc = (proc_tbl << 25) | page_size << 5 | table_size; 963 } 964 965 } else { /* Deregister current process table */ 966 /* 967 * Set to benign value: (current GR) | 0. This allows 968 * deregistration in KVM to succeed even if the radix bit 969 * in flags doesn't match the radix bit in the old PATE. 970 */ 971 cproc = spapr->patb_entry & PATE1_GR; 972 } 973 } else { /* Maintain current registration */ 974 if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) { 975 /* Technically caused by flag bits => H_PARAMETER */ 976 return H_PARAMETER; /* Existing Process Table Mismatch */ 977 } 978 cproc = spapr->patb_entry; 979 } 980 981 /* Check if we need to setup OR free the hpt */ 982 spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 983 984 spapr->patb_entry = cproc; /* Save new process table */ 985 986 /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ 987 if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */ 988 update_lpcr |= (LPCR_UPRT | LPCR_HR); 989 else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ 990 update_lpcr |= LPCR_UPRT; 991 if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ 992 update_lpcr |= LPCR_GTSE; 993 994 spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); 995 996 if (kvm_enabled()) { 997 return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 998 flags & FLAG_GTSE, cproc); 999 } 1000 return H_SUCCESS; 1001 } 1002 1003 #define H_SIGNAL_SYS_RESET_ALL -1 1004 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 1005 1006 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1007 SpaprMachineState *spapr, 1008 target_ulong opcode, target_ulong *args) 1009 { 1010 target_long target = args[0]; 1011 CPUState *cs; 1012 1013 if (target < 0) { 1014 /* Broadcast */ 1015 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1016 return H_PARAMETER; 1017 } 1018 1019 CPU_FOREACH(cs) { 1020 PowerPCCPU *c = POWERPC_CPU(cs); 1021 1022 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1023 if (c == cpu) { 1024 continue; 1025 } 1026 } 1027 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1028 } 1029 return H_SUCCESS; 1030 1031 } else { 1032 /* Unicast */ 1033 cs = CPU(spapr_find_cpu(target)); 1034 if (cs) { 1035 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1036 return H_SUCCESS; 1037 } 1038 return H_PARAMETER; 1039 } 1040 } 1041 1042 /* Returns either a logical PVR or zero if none was found */ 1043 static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32_t max_compat, 1044 target_ulong *addr, bool *raw_mode_supported) 1045 { 1046 bool explicit_match = false; /* Matched the CPU's real PVR */ 1047 uint32_t best_compat = 0; 1048 int i; 1049 1050 /* 1051 * We scan the supplied table of PVRs looking for two things 1052 * 1. Is our real CPU PVR in the list? 1053 * 2. What's the "best" listed logical PVR 1054 */ 1055 for (i = 0; i < 512; ++i) { 1056 uint32_t pvr, pvr_mask; 1057 1058 pvr_mask = ldl_be_phys(&address_space_memory, *addr); 1059 pvr = ldl_be_phys(&address_space_memory, *addr + 4); 1060 *addr += 8; 1061 1062 if (~pvr_mask & pvr) { 1063 break; /* Terminator record */ 1064 } 1065 1066 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1067 explicit_match = true; 1068 } else { 1069 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1070 best_compat = pvr; 1071 } 1072 } 1073 } 1074 1075 *raw_mode_supported = explicit_match; 1076 1077 /* Parsing finished */ 1078 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 1079 1080 return best_compat; 1081 } 1082 1083 static 1084 target_ulong do_client_architecture_support(PowerPCCPU *cpu, 1085 SpaprMachineState *spapr, 1086 target_ulong vec, 1087 target_ulong fdt_bufsize) 1088 { 1089 target_ulong ov_table; /* Working address in data buffer */ 1090 uint32_t cas_pvr; 1091 SpaprOptionVector *ov1_guest, *ov5_guest; 1092 bool guest_radix; 1093 bool raw_mode_supported = false; 1094 bool guest_xive; 1095 CPUState *cs; 1096 void *fdt; 1097 uint32_t max_compat = spapr->max_compat_pvr; 1098 1099 /* CAS is supposed to be called early when only the boot vCPU is active. */ 1100 CPU_FOREACH(cs) { 1101 if (cs == CPU(cpu)) { 1102 continue; 1103 } 1104 if (!cs->halted) { 1105 warn_report("guest has multiple active vCPUs at CAS, which is not allowed"); 1106 return H_MULTI_THREADS_ACTIVE; 1107 } 1108 } 1109 1110 cas_pvr = cas_check_pvr(cpu, max_compat, &vec, &raw_mode_supported); 1111 if (!cas_pvr && (!raw_mode_supported || max_compat)) { 1112 /* 1113 * We couldn't find a suitable compatibility mode, and either 1114 * the guest doesn't support "raw" mode for this CPU, or "raw" 1115 * mode is disabled because a maximum compat mode is set. 1116 */ 1117 error_report("Couldn't negotiate a suitable PVR during CAS"); 1118 return H_HARDWARE; 1119 } 1120 1121 /* Update CPUs */ 1122 if (cpu->compat_pvr != cas_pvr) { 1123 Error *local_err = NULL; 1124 1125 if (ppc_set_compat_all(cas_pvr, &local_err) < 0) { 1126 /* We fail to set compat mode (likely because running with KVM PR), 1127 * but maybe we can fallback to raw mode if the guest supports it. 1128 */ 1129 if (!raw_mode_supported) { 1130 error_report_err(local_err); 1131 return H_HARDWARE; 1132 } 1133 error_free(local_err); 1134 } 1135 } 1136 1137 /* For the future use: here @ov_table points to the first option vector */ 1138 ov_table = vec; 1139 1140 ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1141 if (!ov1_guest) { 1142 warn_report("guest didn't provide option vector 1"); 1143 return H_PARAMETER; 1144 } 1145 ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1146 if (!ov5_guest) { 1147 spapr_ovec_cleanup(ov1_guest); 1148 warn_report("guest didn't provide option vector 5"); 1149 return H_PARAMETER; 1150 } 1151 if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 1152 error_report("guest requested hash and radix MMU, which is invalid."); 1153 exit(EXIT_FAILURE); 1154 } 1155 if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { 1156 error_report("guest requested an invalid interrupt mode"); 1157 exit(EXIT_FAILURE); 1158 } 1159 1160 guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 1161 1162 guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); 1163 1164 /* 1165 * HPT resizing is a bit of a special case, because when enabled 1166 * we assume an HPT guest will support it until it says it 1167 * doesn't, instead of assuming it won't support it until it says 1168 * it does. Strictly speaking that approach could break for 1169 * guests which don't make a CAS call, but those are so old we 1170 * don't care about them. Without that assumption we'd have to 1171 * make at least a temporary allocation of an HPT sized for max 1172 * memory, which could be impossibly difficult under KVM HV if 1173 * maxram is large. 1174 */ 1175 if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 1176 int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1177 1178 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 1179 error_report( 1180 "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 1181 exit(1); 1182 } 1183 1184 if (spapr->htab_shift < maxshift) { 1185 /* Guest doesn't know about HPT resizing, so we 1186 * pre-emptively resize for the maximum permitted RAM. At 1187 * the point this is called, nothing should have been 1188 * entered into the existing HPT */ 1189 spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 1190 push_sregs_to_kvm_pr(spapr); 1191 } 1192 } 1193 1194 /* NOTE: there are actually a number of ov5 bits where input from the 1195 * guest is always zero, and the platform/QEMU enables them independently 1196 * of guest input. To model these properly we'd want some sort of mask, 1197 * but since they only currently apply to memory migration as defined 1198 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 1199 * to worry about this for now. 1200 */ 1201 1202 /* full range of negotiated ov5 capabilities */ 1203 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1204 spapr_ovec_cleanup(ov5_guest); 1205 1206 spapr_check_mmu_mode(guest_radix); 1207 1208 spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00); 1209 spapr_ovec_cleanup(ov1_guest); 1210 1211 /* 1212 * Check for NUMA affinity conditions now that we know which NUMA 1213 * affinity the guest will use. 1214 */ 1215 spapr_numa_associativity_check(spapr); 1216 1217 /* 1218 * Ensure the guest asks for an interrupt mode we support; 1219 * otherwise terminate the boot. 1220 */ 1221 if (guest_xive) { 1222 if (!spapr->irq->xive) { 1223 error_report( 1224 "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property"); 1225 exit(EXIT_FAILURE); 1226 } 1227 } else { 1228 if (!spapr->irq->xics) { 1229 error_report( 1230 "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual"); 1231 exit(EXIT_FAILURE); 1232 } 1233 } 1234 1235 spapr_irq_update_active_intc(spapr); 1236 1237 /* 1238 * Process all pending hot-plug/unplug requests now. An updated full 1239 * rendered FDT will be returned to the guest. 1240 */ 1241 spapr_drc_reset_all(spapr); 1242 spapr_clear_pending_hotplug_events(spapr); 1243 1244 /* 1245 * If spapr_machine_reset() did not set up a HPT but one is necessary 1246 * (because the guest isn't going to use radix) then set it up here. 1247 */ 1248 if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { 1249 /* legacy hash or new hash: */ 1250 spapr_setup_hpt(spapr); 1251 } 1252 1253 fdt = spapr_build_fdt(spapr, spapr->vof != NULL, fdt_bufsize); 1254 g_free(spapr->fdt_blob); 1255 spapr->fdt_size = fdt_totalsize(fdt); 1256 spapr->fdt_initial_size = spapr->fdt_size; 1257 spapr->fdt_blob = fdt; 1258 1259 /* 1260 * Set the machine->fdt pointer again since we just freed 1261 * it above (by freeing spapr->fdt_blob). We set this 1262 * pointer to enable support for the 'dumpdtb' QMP/HMP 1263 * command. 1264 */ 1265 MACHINE(spapr)->fdt = fdt; 1266 1267 return H_SUCCESS; 1268 } 1269 1270 static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1271 SpaprMachineState *spapr, 1272 target_ulong opcode, 1273 target_ulong *args) 1274 { 1275 target_ulong vec = ppc64_phys_to_real(args[0]); 1276 target_ulong fdt_buf = args[1]; 1277 target_ulong fdt_bufsize = args[2]; 1278 target_ulong ret; 1279 SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 1280 1281 if (fdt_bufsize < sizeof(hdr)) { 1282 error_report("SLOF provided insufficient CAS buffer " 1283 TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr)); 1284 exit(EXIT_FAILURE); 1285 } 1286 1287 fdt_bufsize -= sizeof(hdr); 1288 1289 ret = do_client_architecture_support(cpu, spapr, vec, fdt_bufsize); 1290 if (ret == H_SUCCESS) { 1291 _FDT((fdt_pack(spapr->fdt_blob))); 1292 spapr->fdt_size = fdt_totalsize(spapr->fdt_blob); 1293 spapr->fdt_initial_size = spapr->fdt_size; 1294 1295 cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr)); 1296 cpu_physical_memory_write(fdt_buf + sizeof(hdr), spapr->fdt_blob, 1297 spapr->fdt_size); 1298 trace_spapr_cas_continue(spapr->fdt_size + sizeof(hdr)); 1299 } 1300 1301 return ret; 1302 } 1303 1304 target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1305 CPUState *cs, 1306 target_ulong ovec_addr) 1307 { 1308 SpaprMachineState *spapr = SPAPR_MACHINE(ms); 1309 1310 target_ulong ret = do_client_architecture_support(POWERPC_CPU(cs), spapr, 1311 ovec_addr, FDT_MAX_SIZE); 1312 1313 /* 1314 * This adds stdout and generates phandles for boottime and CAS FDTs. 1315 * It is alright to update the FDT here as do_client_architecture_support() 1316 * does not pack it. 1317 */ 1318 spapr_vof_client_dt_finalize(spapr, spapr->fdt_blob); 1319 1320 return ret; 1321 } 1322 1323 static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1324 SpaprMachineState *spapr, 1325 target_ulong opcode, 1326 target_ulong *args) 1327 { 1328 uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1329 ~H_CPU_CHAR_THR_RECONF_TRIG; 1330 uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1331 uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1332 uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1333 uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 1334 uint8_t count_cache_flush_assist = spapr_get_cap(spapr, 1335 SPAPR_CAP_CCF_ASSIST); 1336 1337 switch (safe_cache) { 1338 case SPAPR_CAP_WORKAROUND: 1339 characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1340 characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1341 characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1342 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1343 break; 1344 case SPAPR_CAP_FIXED: 1345 behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY; 1346 behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS; 1347 break; 1348 default: /* broken */ 1349 assert(safe_cache == SPAPR_CAP_BROKEN); 1350 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1351 break; 1352 } 1353 1354 switch (safe_bounds_check) { 1355 case SPAPR_CAP_WORKAROUND: 1356 characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1357 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1358 break; 1359 case SPAPR_CAP_FIXED: 1360 break; 1361 default: /* broken */ 1362 assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1363 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1364 break; 1365 } 1366 1367 switch (safe_indirect_branch) { 1368 case SPAPR_CAP_FIXED_NA: 1369 break; 1370 case SPAPR_CAP_FIXED_CCD: 1371 characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; 1372 break; 1373 case SPAPR_CAP_FIXED_IBS: 1374 characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1375 break; 1376 case SPAPR_CAP_WORKAROUND: 1377 behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE; 1378 if (count_cache_flush_assist) { 1379 characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST; 1380 } 1381 break; 1382 default: /* broken */ 1383 assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1384 break; 1385 } 1386 1387 args[0] = characteristics; 1388 args[1] = behaviour; 1389 return H_SUCCESS; 1390 } 1391 1392 static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, 1393 target_ulong opcode, target_ulong *args) 1394 { 1395 target_ulong dt = ppc64_phys_to_real(args[0]); 1396 struct fdt_header hdr = { 0 }; 1397 unsigned cb; 1398 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1399 void *fdt; 1400 1401 cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); 1402 cb = fdt32_to_cpu(hdr.totalsize); 1403 1404 if (!smc->update_dt_enabled) { 1405 return H_SUCCESS; 1406 } 1407 1408 /* Check that the fdt did not grow out of proportion */ 1409 if (cb > spapr->fdt_initial_size * 2) { 1410 trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, 1411 fdt32_to_cpu(hdr.magic)); 1412 return H_PARAMETER; 1413 } 1414 1415 fdt = g_malloc0(cb); 1416 cpu_physical_memory_read(dt, fdt, cb); 1417 1418 /* Check the fdt consistency */ 1419 if (fdt_check_full(fdt, cb)) { 1420 trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, 1421 fdt32_to_cpu(hdr.magic)); 1422 return H_PARAMETER; 1423 } 1424 1425 g_free(spapr->fdt_blob); 1426 spapr->fdt_size = cb; 1427 spapr->fdt_blob = fdt; 1428 trace_spapr_update_dt(cb); 1429 1430 return H_SUCCESS; 1431 } 1432 1433 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 1434 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 1435 static spapr_hcall_fn svm_hypercall_table[(SVM_HCALL_MAX - SVM_HCALL_BASE) / 4 + 1]; 1436 1437 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 1438 { 1439 spapr_hcall_fn *slot; 1440 1441 if (opcode <= MAX_HCALL_OPCODE) { 1442 assert((opcode & 0x3) == 0); 1443 1444 slot = &papr_hypercall_table[opcode / 4]; 1445 } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { 1446 /* we only have SVM-related hcall numbers assigned in multiples of 4 */ 1447 assert((opcode & 0x3) == 0); 1448 1449 slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1450 } else { 1451 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1452 1453 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1454 } 1455 1456 assert(!(*slot)); 1457 *slot = fn; 1458 } 1459 1460 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 1461 target_ulong *args) 1462 { 1463 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1464 1465 if ((opcode <= MAX_HCALL_OPCODE) 1466 && ((opcode & 0x3) == 0)) { 1467 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 1468 1469 if (fn) { 1470 return fn(cpu, spapr, opcode, args); 1471 } 1472 } else if ((opcode >= SVM_HCALL_BASE) && 1473 (opcode <= SVM_HCALL_MAX)) { 1474 spapr_hcall_fn fn = svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1475 1476 if (fn) { 1477 return fn(cpu, spapr, opcode, args); 1478 } 1479 } else if ((opcode >= KVMPPC_HCALL_BASE) && 1480 (opcode <= KVMPPC_HCALL_MAX)) { 1481 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1482 1483 if (fn) { 1484 return fn(cpu, spapr, opcode, args); 1485 } 1486 } 1487 1488 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1489 opcode); 1490 return H_FUNCTION; 1491 } 1492 1493 #ifdef CONFIG_TCG 1494 #define PRTS_MASK 0x1f 1495 1496 static target_ulong h_set_ptbl(PowerPCCPU *cpu, 1497 SpaprMachineState *spapr, 1498 target_ulong opcode, 1499 target_ulong *args) 1500 { 1501 target_ulong ptcr = args[0]; 1502 1503 if (!spapr_get_cap(spapr, SPAPR_CAP_NESTED_KVM_HV)) { 1504 return H_FUNCTION; 1505 } 1506 1507 if ((ptcr & PRTS_MASK) + 12 - 4 > 12) { 1508 return H_PARAMETER; 1509 } 1510 1511 spapr->nested_ptcr = ptcr; /* Save new partition table */ 1512 1513 return H_SUCCESS; 1514 } 1515 1516 static target_ulong h_tlb_invalidate(PowerPCCPU *cpu, 1517 SpaprMachineState *spapr, 1518 target_ulong opcode, 1519 target_ulong *args) 1520 { 1521 /* 1522 * The spapr virtual hypervisor nested HV implementation retains no L2 1523 * translation state except for TLB. And the TLB is always invalidated 1524 * across L1<->L2 transitions, so nothing is required here. 1525 */ 1526 1527 return H_SUCCESS; 1528 } 1529 1530 static target_ulong h_copy_tofrom_guest(PowerPCCPU *cpu, 1531 SpaprMachineState *spapr, 1532 target_ulong opcode, 1533 target_ulong *args) 1534 { 1535 /* 1536 * This HCALL is not required, L1 KVM will take a slow path and walk the 1537 * page tables manually to do the data copy. 1538 */ 1539 return H_FUNCTION; 1540 } 1541 1542 /* 1543 * When this handler returns, the environment is switched to the L2 guest 1544 * and TCG begins running that. spapr_exit_nested() performs the switch from 1545 * L2 back to L1 and returns from the H_ENTER_NESTED hcall. 1546 */ 1547 static target_ulong h_enter_nested(PowerPCCPU *cpu, 1548 SpaprMachineState *spapr, 1549 target_ulong opcode, 1550 target_ulong *args) 1551 { 1552 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 1553 CPUState *cs = CPU(cpu); 1554 CPUPPCState *env = &cpu->env; 1555 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1556 target_ulong hv_ptr = args[0]; 1557 target_ulong regs_ptr = args[1]; 1558 target_ulong hdec, now = cpu_ppc_load_tbl(env); 1559 target_ulong lpcr, lpcr_mask; 1560 struct kvmppc_hv_guest_state *hvstate; 1561 struct kvmppc_hv_guest_state hv_state; 1562 struct kvmppc_pt_regs *regs; 1563 hwaddr len; 1564 uint64_t cr; 1565 int i; 1566 1567 if (spapr->nested_ptcr == 0) { 1568 return H_NOT_AVAILABLE; 1569 } 1570 1571 len = sizeof(*hvstate); 1572 hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, false, 1573 MEMTXATTRS_UNSPECIFIED); 1574 if (len != sizeof(*hvstate)) { 1575 address_space_unmap(CPU(cpu)->as, hvstate, len, 0, false); 1576 return H_PARAMETER; 1577 } 1578 1579 memcpy(&hv_state, hvstate, len); 1580 1581 address_space_unmap(CPU(cpu)->as, hvstate, len, len, false); 1582 1583 /* 1584 * We accept versions 1 and 2. Version 2 fields are unused because TCG 1585 * does not implement DAWR*. 1586 */ 1587 if (hv_state.version > HV_GUEST_STATE_VERSION) { 1588 return H_PARAMETER; 1589 } 1590 1591 spapr_cpu->nested_host_state = g_try_new(CPUPPCState, 1); 1592 if (!spapr_cpu->nested_host_state) { 1593 return H_NO_MEM; 1594 } 1595 1596 memcpy(spapr_cpu->nested_host_state, env, sizeof(CPUPPCState)); 1597 1598 len = sizeof(*regs); 1599 regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, false, 1600 MEMTXATTRS_UNSPECIFIED); 1601 if (!regs || len != sizeof(*regs)) { 1602 address_space_unmap(CPU(cpu)->as, regs, len, 0, false); 1603 g_free(spapr_cpu->nested_host_state); 1604 return H_P2; 1605 } 1606 1607 len = sizeof(env->gpr); 1608 assert(len == sizeof(regs->gpr)); 1609 memcpy(env->gpr, regs->gpr, len); 1610 1611 env->lr = regs->link; 1612 env->ctr = regs->ctr; 1613 cpu_write_xer(env, regs->xer); 1614 1615 cr = regs->ccr; 1616 for (i = 7; i >= 0; i--) { 1617 env->crf[i] = cr & 15; 1618 cr >>= 4; 1619 } 1620 1621 env->msr = regs->msr; 1622 env->nip = regs->nip; 1623 1624 address_space_unmap(CPU(cpu)->as, regs, len, len, false); 1625 1626 env->cfar = hv_state.cfar; 1627 1628 assert(env->spr[SPR_LPIDR] == 0); 1629 env->spr[SPR_LPIDR] = hv_state.lpid; 1630 1631 lpcr_mask = LPCR_DPFD | LPCR_ILE | LPCR_AIL | LPCR_LD | LPCR_MER; 1632 lpcr = (env->spr[SPR_LPCR] & ~lpcr_mask) | (hv_state.lpcr & lpcr_mask); 1633 lpcr |= LPCR_HR | LPCR_UPRT | LPCR_GTSE | LPCR_HVICE | LPCR_HDICE; 1634 lpcr &= ~LPCR_LPES0; 1635 env->spr[SPR_LPCR] = lpcr & pcc->lpcr_mask; 1636 1637 env->spr[SPR_PCR] = hv_state.pcr; 1638 /* hv_state.amor is not used */ 1639 env->spr[SPR_DPDES] = hv_state.dpdes; 1640 env->spr[SPR_HFSCR] = hv_state.hfscr; 1641 hdec = hv_state.hdec_expiry - now; 1642 spapr_cpu->nested_tb_offset = hv_state.tb_offset; 1643 /* TCG does not implement DAWR*, CIABR, PURR, SPURR, IC, VTB, HEIR SPRs*/ 1644 env->spr[SPR_SRR0] = hv_state.srr0; 1645 env->spr[SPR_SRR1] = hv_state.srr1; 1646 env->spr[SPR_SPRG0] = hv_state.sprg[0]; 1647 env->spr[SPR_SPRG1] = hv_state.sprg[1]; 1648 env->spr[SPR_SPRG2] = hv_state.sprg[2]; 1649 env->spr[SPR_SPRG3] = hv_state.sprg[3]; 1650 env->spr[SPR_BOOKS_PID] = hv_state.pidr; 1651 env->spr[SPR_PPR] = hv_state.ppr; 1652 1653 cpu_ppc_hdecr_init(env); 1654 cpu_ppc_store_hdecr(env, hdec); 1655 1656 /* 1657 * The hv_state.vcpu_token is not needed. It is used by the KVM 1658 * implementation to remember which L2 vCPU last ran on which physical 1659 * CPU so as to invalidate process scope translations if it is moved 1660 * between physical CPUs. For now TLBs are always flushed on L1<->L2 1661 * transitions so this is not a problem. 1662 * 1663 * Could validate that the same vcpu_token does not attempt to run on 1664 * different L1 vCPUs at the same time, but that would be a L1 KVM bug 1665 * and it's not obviously worth a new data structure to do it. 1666 */ 1667 1668 env->tb_env->tb_offset += spapr_cpu->nested_tb_offset; 1669 spapr_cpu->in_nested = true; 1670 1671 hreg_compute_hflags(env); 1672 tlb_flush(cs); 1673 env->reserve_addr = -1; /* Reset the reservation */ 1674 1675 /* 1676 * The spapr hcall helper sets env->gpr[3] to the return value, but at 1677 * this point the L1 is not returning from the hcall but rather we 1678 * start running the L2, so r3 must not be clobbered, so return env->gpr[3] 1679 * to leave it unchanged. 1680 */ 1681 return env->gpr[3]; 1682 } 1683 1684 void spapr_exit_nested(PowerPCCPU *cpu, int excp) 1685 { 1686 CPUState *cs = CPU(cpu); 1687 CPUPPCState *env = &cpu->env; 1688 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1689 target_ulong r3_return = env->excp_vectors[excp]; /* hcall return value */ 1690 target_ulong hv_ptr = spapr_cpu->nested_host_state->gpr[4]; 1691 target_ulong regs_ptr = spapr_cpu->nested_host_state->gpr[5]; 1692 struct kvmppc_hv_guest_state *hvstate; 1693 struct kvmppc_pt_regs *regs; 1694 hwaddr len; 1695 uint64_t cr; 1696 int i; 1697 1698 assert(spapr_cpu->in_nested); 1699 1700 cpu_ppc_hdecr_exit(env); 1701 1702 len = sizeof(*hvstate); 1703 hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, true, 1704 MEMTXATTRS_UNSPECIFIED); 1705 if (len != sizeof(*hvstate)) { 1706 address_space_unmap(CPU(cpu)->as, hvstate, len, 0, true); 1707 r3_return = H_PARAMETER; 1708 goto out_restore_l1; 1709 } 1710 1711 hvstate->cfar = env->cfar; 1712 hvstate->lpcr = env->spr[SPR_LPCR]; 1713 hvstate->pcr = env->spr[SPR_PCR]; 1714 hvstate->dpdes = env->spr[SPR_DPDES]; 1715 hvstate->hfscr = env->spr[SPR_HFSCR]; 1716 1717 if (excp == POWERPC_EXCP_HDSI) { 1718 hvstate->hdar = env->spr[SPR_HDAR]; 1719 hvstate->hdsisr = env->spr[SPR_HDSISR]; 1720 hvstate->asdr = env->spr[SPR_ASDR]; 1721 } else if (excp == POWERPC_EXCP_HISI) { 1722 hvstate->asdr = env->spr[SPR_ASDR]; 1723 } 1724 1725 /* HEIR should be implemented for HV mode and saved here. */ 1726 hvstate->srr0 = env->spr[SPR_SRR0]; 1727 hvstate->srr1 = env->spr[SPR_SRR1]; 1728 hvstate->sprg[0] = env->spr[SPR_SPRG0]; 1729 hvstate->sprg[1] = env->spr[SPR_SPRG1]; 1730 hvstate->sprg[2] = env->spr[SPR_SPRG2]; 1731 hvstate->sprg[3] = env->spr[SPR_SPRG3]; 1732 hvstate->pidr = env->spr[SPR_BOOKS_PID]; 1733 hvstate->ppr = env->spr[SPR_PPR]; 1734 1735 /* Is it okay to specify write length larger than actual data written? */ 1736 address_space_unmap(CPU(cpu)->as, hvstate, len, len, true); 1737 1738 len = sizeof(*regs); 1739 regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, true, 1740 MEMTXATTRS_UNSPECIFIED); 1741 if (!regs || len != sizeof(*regs)) { 1742 address_space_unmap(CPU(cpu)->as, regs, len, 0, true); 1743 r3_return = H_P2; 1744 goto out_restore_l1; 1745 } 1746 1747 len = sizeof(env->gpr); 1748 assert(len == sizeof(regs->gpr)); 1749 memcpy(regs->gpr, env->gpr, len); 1750 1751 regs->link = env->lr; 1752 regs->ctr = env->ctr; 1753 regs->xer = cpu_read_xer(env); 1754 1755 cr = 0; 1756 for (i = 0; i < 8; i++) { 1757 cr |= (env->crf[i] & 15) << (4 * (7 - i)); 1758 } 1759 regs->ccr = cr; 1760 1761 if (excp == POWERPC_EXCP_MCHECK || 1762 excp == POWERPC_EXCP_RESET || 1763 excp == POWERPC_EXCP_SYSCALL) { 1764 regs->nip = env->spr[SPR_SRR0]; 1765 regs->msr = env->spr[SPR_SRR1] & env->msr_mask; 1766 } else { 1767 regs->nip = env->spr[SPR_HSRR0]; 1768 regs->msr = env->spr[SPR_HSRR1] & env->msr_mask; 1769 } 1770 1771 /* Is it okay to specify write length larger than actual data written? */ 1772 address_space_unmap(CPU(cpu)->as, regs, len, len, true); 1773 1774 out_restore_l1: 1775 memcpy(env->gpr, spapr_cpu->nested_host_state->gpr, sizeof(env->gpr)); 1776 env->lr = spapr_cpu->nested_host_state->lr; 1777 env->ctr = spapr_cpu->nested_host_state->ctr; 1778 memcpy(env->crf, spapr_cpu->nested_host_state->crf, sizeof(env->crf)); 1779 env->cfar = spapr_cpu->nested_host_state->cfar; 1780 env->xer = spapr_cpu->nested_host_state->xer; 1781 env->so = spapr_cpu->nested_host_state->so; 1782 env->ov = spapr_cpu->nested_host_state->ov; 1783 env->ov32 = spapr_cpu->nested_host_state->ov32; 1784 env->ca32 = spapr_cpu->nested_host_state->ca32; 1785 env->msr = spapr_cpu->nested_host_state->msr; 1786 env->nip = spapr_cpu->nested_host_state->nip; 1787 1788 assert(env->spr[SPR_LPIDR] != 0); 1789 env->spr[SPR_LPCR] = spapr_cpu->nested_host_state->spr[SPR_LPCR]; 1790 env->spr[SPR_LPIDR] = spapr_cpu->nested_host_state->spr[SPR_LPIDR]; 1791 env->spr[SPR_PCR] = spapr_cpu->nested_host_state->spr[SPR_PCR]; 1792 env->spr[SPR_DPDES] = 0; 1793 env->spr[SPR_HFSCR] = spapr_cpu->nested_host_state->spr[SPR_HFSCR]; 1794 env->spr[SPR_SRR0] = spapr_cpu->nested_host_state->spr[SPR_SRR0]; 1795 env->spr[SPR_SRR1] = spapr_cpu->nested_host_state->spr[SPR_SRR1]; 1796 env->spr[SPR_SPRG0] = spapr_cpu->nested_host_state->spr[SPR_SPRG0]; 1797 env->spr[SPR_SPRG1] = spapr_cpu->nested_host_state->spr[SPR_SPRG1]; 1798 env->spr[SPR_SPRG2] = spapr_cpu->nested_host_state->spr[SPR_SPRG2]; 1799 env->spr[SPR_SPRG3] = spapr_cpu->nested_host_state->spr[SPR_SPRG3]; 1800 env->spr[SPR_BOOKS_PID] = spapr_cpu->nested_host_state->spr[SPR_BOOKS_PID]; 1801 env->spr[SPR_PPR] = spapr_cpu->nested_host_state->spr[SPR_PPR]; 1802 1803 /* 1804 * Return the interrupt vector address from H_ENTER_NESTED to the L1 1805 * (or error code). 1806 */ 1807 env->gpr[3] = r3_return; 1808 1809 env->tb_env->tb_offset -= spapr_cpu->nested_tb_offset; 1810 spapr_cpu->in_nested = false; 1811 1812 hreg_compute_hflags(env); 1813 tlb_flush(cs); 1814 env->reserve_addr = -1; /* Reset the reservation */ 1815 1816 g_free(spapr_cpu->nested_host_state); 1817 spapr_cpu->nested_host_state = NULL; 1818 } 1819 1820 static void hypercall_register_nested(void) 1821 { 1822 spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl); 1823 spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested); 1824 spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate); 1825 spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_guest); 1826 } 1827 1828 static void hypercall_register_softmmu(void) 1829 { 1830 /* DO NOTHING */ 1831 } 1832 #else 1833 void spapr_exit_nested(PowerPCCPU *cpu, int excp) 1834 { 1835 g_assert_not_reached(); 1836 } 1837 1838 static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr, 1839 target_ulong opcode, target_ulong *args) 1840 { 1841 g_assert_not_reached(); 1842 } 1843 1844 static void hypercall_register_nested(void) 1845 { 1846 /* DO NOTHING */ 1847 } 1848 1849 static void hypercall_register_softmmu(void) 1850 { 1851 /* hcall-pft */ 1852 spapr_register_hypercall(H_ENTER, h_softmmu); 1853 spapr_register_hypercall(H_REMOVE, h_softmmu); 1854 spapr_register_hypercall(H_PROTECT, h_softmmu); 1855 spapr_register_hypercall(H_READ, h_softmmu); 1856 1857 /* hcall-bulk */ 1858 spapr_register_hypercall(H_BULK_REMOVE, h_softmmu); 1859 } 1860 #endif 1861 1862 static void hypercall_register_types(void) 1863 { 1864 hypercall_register_softmmu(); 1865 1866 /* hcall-hpt-resize */ 1867 spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 1868 spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 1869 1870 /* hcall-splpar */ 1871 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 1872 spapr_register_hypercall(H_CEDE, h_cede); 1873 spapr_register_hypercall(H_CONFER, h_confer); 1874 spapr_register_hypercall(H_PROD, h_prod); 1875 1876 /* hcall-join */ 1877 spapr_register_hypercall(H_JOIN, h_join); 1878 1879 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 1880 1881 /* processor register resource access h-calls */ 1882 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1883 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1884 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 1885 spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1886 spapr_register_hypercall(H_SET_MODE, h_set_mode); 1887 1888 /* In Memory Table MMU h-calls */ 1889 spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1890 spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1891 spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1892 1893 /* hcall-get-cpu-characteristics */ 1894 spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 1895 h_get_cpu_characteristics); 1896 1897 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 1898 * here between the "CI" and the "CACHE" variants, they will use whatever 1899 * mapping attributes qemu is using. When using KVM, the kernel will 1900 * enforce the attributes more strongly 1901 */ 1902 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 1903 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 1904 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 1905 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 1906 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 1907 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 1908 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 1909 1910 /* qemu/KVM-PPC specific hcalls */ 1911 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 1912 1913 /* ibm,client-architecture-support support */ 1914 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1915 1916 spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); 1917 1918 hypercall_register_nested(); 1919 } 1920 1921 type_init(hypercall_register_types) 1922