1 #include "qemu/osdep.h" 2 #include "qemu/cutils.h" 3 #include "qapi/error.h" 4 #include "sysemu/hw_accel.h" 5 #include "sysemu/runstate.h" 6 #include "qemu/log.h" 7 #include "qemu/main-loop.h" 8 #include "qemu/module.h" 9 #include "qemu/error-report.h" 10 #include "exec/exec-all.h" 11 #include "exec/tb-flush.h" 12 #include "helper_regs.h" 13 #include "hw/ppc/ppc.h" 14 #include "hw/ppc/spapr.h" 15 #include "hw/ppc/spapr_cpu_core.h" 16 #include "mmu-hash64.h" 17 #include "cpu-models.h" 18 #include "trace.h" 19 #include "kvm_ppc.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr_ovec.h" 22 #include "hw/ppc/spapr_numa.h" 23 #include "mmu-book3s-v3.h" 24 #include "hw/mem/memory-device.h" 25 26 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) 27 { 28 MachineState *machine = MACHINE(spapr); 29 DeviceMemoryState *dms = machine->device_memory; 30 31 if (addr < machine->ram_size) { 32 return true; 33 } 34 if ((addr >= dms->base) 35 && ((addr - dms->base) < memory_region_size(&dms->mr))) { 36 return true; 37 } 38 39 return false; 40 } 41 42 /* Convert a return code from the KVM ioctl()s implementing resize HPT 43 * into a PAPR hypercall return code */ 44 static target_ulong resize_hpt_convert_rc(int ret) 45 { 46 if (ret >= 100000) { 47 return H_LONG_BUSY_ORDER_100_SEC; 48 } else if (ret >= 10000) { 49 return H_LONG_BUSY_ORDER_10_SEC; 50 } else if (ret >= 1000) { 51 return H_LONG_BUSY_ORDER_1_SEC; 52 } else if (ret >= 100) { 53 return H_LONG_BUSY_ORDER_100_MSEC; 54 } else if (ret >= 10) { 55 return H_LONG_BUSY_ORDER_10_MSEC; 56 } else if (ret > 0) { 57 return H_LONG_BUSY_ORDER_1_MSEC; 58 } 59 60 switch (ret) { 61 case 0: 62 return H_SUCCESS; 63 case -EPERM: 64 return H_AUTHORITY; 65 case -EINVAL: 66 return H_PARAMETER; 67 case -ENXIO: 68 return H_CLOSED; 69 case -ENOSPC: 70 return H_PTEG_FULL; 71 case -EBUSY: 72 return H_BUSY; 73 case -ENOMEM: 74 return H_NO_MEM; 75 default: 76 return H_HARDWARE; 77 } 78 } 79 80 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 81 SpaprMachineState *spapr, 82 target_ulong opcode, 83 target_ulong *args) 84 { 85 target_ulong flags = args[0]; 86 int shift = args[1]; 87 uint64_t current_ram_size; 88 int rc; 89 90 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 91 return H_AUTHORITY; 92 } 93 94 if (!spapr->htab_shift) { 95 /* Radix guest, no HPT */ 96 return H_NOT_AVAILABLE; 97 } 98 99 trace_spapr_h_resize_hpt_prepare(flags, shift); 100 101 if (flags != 0) { 102 return H_PARAMETER; 103 } 104 105 if (shift && ((shift < 18) || (shift > 46))) { 106 return H_PARAMETER; 107 } 108 109 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 110 111 /* We only allow the guest to allocate an HPT one order above what 112 * we'd normally give them (to stop a small guest claiming a huge 113 * chunk of resources in the HPT */ 114 if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 115 return H_RESOURCE; 116 } 117 118 rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 119 if (rc != -ENOSYS) { 120 return resize_hpt_convert_rc(rc); 121 } 122 123 if (kvm_enabled()) { 124 return H_HARDWARE; 125 } 126 127 return softmmu_resize_hpt_prepare(cpu, spapr, shift); 128 } 129 130 static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 131 { 132 int ret; 133 134 cpu_synchronize_state(cs); 135 136 ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 137 if (ret < 0) { 138 error_report("failed to push sregs to KVM: %s", strerror(-ret)); 139 exit(1); 140 } 141 } 142 143 void push_sregs_to_kvm_pr(SpaprMachineState *spapr) 144 { 145 CPUState *cs; 146 147 /* 148 * This is a hack for the benefit of KVM PR - it abuses the SDR1 149 * slot in kvm_sregs to communicate the userspace address of the 150 * HPT 151 */ 152 if (!kvm_enabled() || !spapr->htab) { 153 return; 154 } 155 156 CPU_FOREACH(cs) { 157 run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 158 } 159 } 160 161 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 162 SpaprMachineState *spapr, 163 target_ulong opcode, 164 target_ulong *args) 165 { 166 target_ulong flags = args[0]; 167 target_ulong shift = args[1]; 168 int rc; 169 170 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 171 return H_AUTHORITY; 172 } 173 174 if (!spapr->htab_shift) { 175 /* Radix guest, no HPT */ 176 return H_NOT_AVAILABLE; 177 } 178 179 trace_spapr_h_resize_hpt_commit(flags, shift); 180 181 rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 182 if (rc != -ENOSYS) { 183 rc = resize_hpt_convert_rc(rc); 184 if (rc == H_SUCCESS) { 185 /* Need to set the new htab_shift in the machine state */ 186 spapr->htab_shift = shift; 187 } 188 return rc; 189 } 190 191 if (kvm_enabled()) { 192 return H_HARDWARE; 193 } 194 195 return softmmu_resize_hpt_commit(cpu, spapr, flags, shift); 196 } 197 198 199 200 static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, 201 target_ulong opcode, target_ulong *args) 202 { 203 cpu_synchronize_state(CPU(cpu)); 204 cpu->env.spr[SPR_SPRG0] = args[0]; 205 206 return H_SUCCESS; 207 } 208 209 static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 210 target_ulong opcode, target_ulong *args) 211 { 212 if (!ppc_has_spr(cpu, SPR_DABR)) { 213 return H_HARDWARE; /* DABR register not available */ 214 } 215 cpu_synchronize_state(CPU(cpu)); 216 217 if (ppc_has_spr(cpu, SPR_DABRX)) { 218 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 219 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 220 return H_RESERVED_DABR; 221 } 222 223 cpu->env.spr[SPR_DABR] = args[0]; 224 return H_SUCCESS; 225 } 226 227 static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 228 target_ulong opcode, target_ulong *args) 229 { 230 target_ulong dabrx = args[1]; 231 232 if (!ppc_has_spr(cpu, SPR_DABR) || !ppc_has_spr(cpu, SPR_DABRX)) { 233 return H_HARDWARE; 234 } 235 236 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 237 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 238 return H_PARAMETER; 239 } 240 241 cpu_synchronize_state(CPU(cpu)); 242 cpu->env.spr[SPR_DABRX] = dabrx; 243 cpu->env.spr[SPR_DABR] = args[0]; 244 245 return H_SUCCESS; 246 } 247 248 static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, 249 target_ulong opcode, target_ulong *args) 250 { 251 target_ulong flags = args[0]; 252 hwaddr dst = args[1]; 253 hwaddr src = args[2]; 254 hwaddr len = TARGET_PAGE_SIZE; 255 uint8_t *pdst, *psrc; 256 target_long ret = H_SUCCESS; 257 258 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 259 | H_COPY_PAGE | H_ZERO_PAGE)) { 260 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 261 flags); 262 return H_PARAMETER; 263 } 264 265 /* Map-in destination */ 266 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 267 return H_PARAMETER; 268 } 269 pdst = cpu_physical_memory_map(dst, &len, true); 270 if (!pdst || len != TARGET_PAGE_SIZE) { 271 return H_PARAMETER; 272 } 273 274 if (flags & H_COPY_PAGE) { 275 /* Map-in source, copy to destination, and unmap source again */ 276 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 277 ret = H_PARAMETER; 278 goto unmap_out; 279 } 280 psrc = cpu_physical_memory_map(src, &len, false); 281 if (!psrc || len != TARGET_PAGE_SIZE) { 282 ret = H_PARAMETER; 283 goto unmap_out; 284 } 285 memcpy(pdst, psrc, len); 286 cpu_physical_memory_unmap(psrc, len, 0, len); 287 } else if (flags & H_ZERO_PAGE) { 288 memset(pdst, 0, len); /* Just clear the destination page */ 289 } 290 291 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 292 kvmppc_dcbst_range(cpu, pdst, len); 293 } 294 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 295 if (kvm_enabled()) { 296 kvmppc_icbi_range(cpu, pdst, len); 297 } else { 298 tb_flush(CPU(cpu)); 299 } 300 } 301 302 unmap_out: 303 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 304 return ret; 305 } 306 307 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 308 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 309 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 310 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 311 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 312 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 313 314 static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) 315 { 316 CPUState *cs = CPU(cpu); 317 CPUPPCState *env = &cpu->env; 318 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 319 uint16_t size; 320 uint8_t tmp; 321 322 if (vpa == 0) { 323 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 324 return H_HARDWARE; 325 } 326 327 if (vpa % env->dcache_line_size) { 328 return H_PARAMETER; 329 } 330 /* FIXME: bounds check the address */ 331 332 size = lduw_be_phys(cs->as, vpa + 0x4); 333 334 if (size < VPA_MIN_SIZE) { 335 return H_PARAMETER; 336 } 337 338 /* VPA is not allowed to cross a page boundary */ 339 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 340 return H_PARAMETER; 341 } 342 343 spapr_cpu->vpa_addr = vpa; 344 345 tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET); 346 tmp |= VPA_SHARED_PROC_VAL; 347 stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 348 349 return H_SUCCESS; 350 } 351 352 static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) 353 { 354 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 355 356 if (spapr_cpu->slb_shadow_addr) { 357 return H_RESOURCE; 358 } 359 360 if (spapr_cpu->dtl_addr) { 361 return H_RESOURCE; 362 } 363 364 spapr_cpu->vpa_addr = 0; 365 return H_SUCCESS; 366 } 367 368 static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 369 { 370 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 371 uint32_t size; 372 373 if (addr == 0) { 374 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 375 return H_HARDWARE; 376 } 377 378 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 379 if (size < 0x8) { 380 return H_PARAMETER; 381 } 382 383 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 384 return H_PARAMETER; 385 } 386 387 if (!spapr_cpu->vpa_addr) { 388 return H_RESOURCE; 389 } 390 391 spapr_cpu->slb_shadow_addr = addr; 392 spapr_cpu->slb_shadow_size = size; 393 394 return H_SUCCESS; 395 } 396 397 static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 398 { 399 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 400 401 spapr_cpu->slb_shadow_addr = 0; 402 spapr_cpu->slb_shadow_size = 0; 403 return H_SUCCESS; 404 } 405 406 static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) 407 { 408 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 409 uint32_t size; 410 411 if (addr == 0) { 412 hcall_dprintf("Can't cope with DTL at logical 0\n"); 413 return H_HARDWARE; 414 } 415 416 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 417 418 if (size < 48) { 419 return H_PARAMETER; 420 } 421 422 if (!spapr_cpu->vpa_addr) { 423 return H_RESOURCE; 424 } 425 426 spapr_cpu->dtl_addr = addr; 427 spapr_cpu->dtl_size = size; 428 429 return H_SUCCESS; 430 } 431 432 static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) 433 { 434 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 435 436 spapr_cpu->dtl_addr = 0; 437 spapr_cpu->dtl_size = 0; 438 439 return H_SUCCESS; 440 } 441 442 static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr, 443 target_ulong opcode, target_ulong *args) 444 { 445 target_ulong flags = args[0]; 446 target_ulong procno = args[1]; 447 target_ulong vpa = args[2]; 448 target_ulong ret = H_PARAMETER; 449 PowerPCCPU *tcpu; 450 451 tcpu = spapr_find_cpu(procno); 452 if (!tcpu) { 453 return H_PARAMETER; 454 } 455 456 switch (flags) { 457 case FLAGS_REGISTER_VPA: 458 ret = register_vpa(tcpu, vpa); 459 break; 460 461 case FLAGS_DEREGISTER_VPA: 462 ret = deregister_vpa(tcpu, vpa); 463 break; 464 465 case FLAGS_REGISTER_SLBSHADOW: 466 ret = register_slb_shadow(tcpu, vpa); 467 break; 468 469 case FLAGS_DEREGISTER_SLBSHADOW: 470 ret = deregister_slb_shadow(tcpu, vpa); 471 break; 472 473 case FLAGS_REGISTER_DTL: 474 ret = register_dtl(tcpu, vpa); 475 break; 476 477 case FLAGS_DEREGISTER_DTL: 478 ret = deregister_dtl(tcpu, vpa); 479 break; 480 } 481 482 return ret; 483 } 484 485 static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, 486 target_ulong opcode, target_ulong *args) 487 { 488 CPUPPCState *env = &cpu->env; 489 CPUState *cs = CPU(cpu); 490 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 491 492 env->msr |= (1ULL << MSR_EE); 493 hreg_compute_hflags(env); 494 ppc_maybe_interrupt(env); 495 496 if (spapr_cpu->prod) { 497 spapr_cpu->prod = false; 498 return H_SUCCESS; 499 } 500 501 if (!cpu_has_work(cs)) { 502 cs->halted = 1; 503 cs->exception_index = EXCP_HLT; 504 cs->exit_request = 1; 505 ppc_maybe_interrupt(env); 506 } 507 508 return H_SUCCESS; 509 } 510 511 /* 512 * Confer to self, aka join. Cede could use the same pattern as well, if 513 * EXCP_HLT can be changed to ECXP_HALTED. 514 */ 515 static target_ulong h_confer_self(PowerPCCPU *cpu) 516 { 517 CPUState *cs = CPU(cpu); 518 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 519 520 if (spapr_cpu->prod) { 521 spapr_cpu->prod = false; 522 return H_SUCCESS; 523 } 524 cs->halted = 1; 525 cs->exception_index = EXCP_HALTED; 526 cs->exit_request = 1; 527 ppc_maybe_interrupt(&cpu->env); 528 529 return H_SUCCESS; 530 } 531 532 static target_ulong h_join(PowerPCCPU *cpu, SpaprMachineState *spapr, 533 target_ulong opcode, target_ulong *args) 534 { 535 CPUPPCState *env = &cpu->env; 536 CPUState *cs; 537 bool last_unjoined = true; 538 539 if (env->msr & (1ULL << MSR_EE)) { 540 return H_BAD_MODE; 541 } 542 543 /* 544 * Must not join the last CPU running. Interestingly, no such restriction 545 * for H_CONFER-to-self, but that is probably not intended to be used 546 * when H_JOIN is available. 547 */ 548 CPU_FOREACH(cs) { 549 PowerPCCPU *c = POWERPC_CPU(cs); 550 CPUPPCState *e = &c->env; 551 if (c == cpu) { 552 continue; 553 } 554 555 /* Don't have a way to indicate joined, so use halted && MSR[EE]=0 */ 556 if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { 557 last_unjoined = false; 558 break; 559 } 560 } 561 if (last_unjoined) { 562 return H_CONTINUE; 563 } 564 565 return h_confer_self(cpu); 566 } 567 568 static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr, 569 target_ulong opcode, target_ulong *args) 570 { 571 target_long target = args[0]; 572 uint32_t dispatch = args[1]; 573 CPUState *cs = CPU(cpu); 574 SpaprCpuState *spapr_cpu; 575 576 /* 577 * -1 means confer to all other CPUs without dispatch counter check, 578 * otherwise it's a targeted confer. 579 */ 580 if (target != -1) { 581 PowerPCCPU *target_cpu = spapr_find_cpu(target); 582 uint32_t target_dispatch; 583 584 if (!target_cpu) { 585 return H_PARAMETER; 586 } 587 588 /* 589 * target == self is a special case, we wait until prodded, without 590 * dispatch counter check. 591 */ 592 if (cpu == target_cpu) { 593 return h_confer_self(cpu); 594 } 595 596 spapr_cpu = spapr_cpu_state(target_cpu); 597 if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) { 598 return H_SUCCESS; 599 } 600 601 target_dispatch = ldl_be_phys(cs->as, 602 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 603 if (target_dispatch != dispatch) { 604 return H_SUCCESS; 605 } 606 607 /* 608 * The targeted confer does not do anything special beyond yielding 609 * the current vCPU, but even this should be better than nothing. 610 * At least for single-threaded tcg, it gives the target a chance to 611 * run before we run again. Multi-threaded tcg does not really do 612 * anything with EXCP_YIELD yet. 613 */ 614 } 615 616 cs->exception_index = EXCP_YIELD; 617 cs->exit_request = 1; 618 cpu_loop_exit(cs); 619 620 return H_SUCCESS; 621 } 622 623 static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr, 624 target_ulong opcode, target_ulong *args) 625 { 626 target_long target = args[0]; 627 PowerPCCPU *tcpu; 628 CPUState *cs; 629 SpaprCpuState *spapr_cpu; 630 631 tcpu = spapr_find_cpu(target); 632 cs = CPU(tcpu); 633 if (!cs) { 634 return H_PARAMETER; 635 } 636 637 spapr_cpu = spapr_cpu_state(tcpu); 638 spapr_cpu->prod = true; 639 cs->halted = 0; 640 ppc_maybe_interrupt(&cpu->env); 641 qemu_cpu_kick(cs); 642 643 return H_SUCCESS; 644 } 645 646 static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, 647 target_ulong opcode, target_ulong *args) 648 { 649 target_ulong rtas_r3 = args[0]; 650 uint32_t token = rtas_ld(rtas_r3, 0); 651 uint32_t nargs = rtas_ld(rtas_r3, 1); 652 uint32_t nret = rtas_ld(rtas_r3, 2); 653 654 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 655 nret, rtas_r3 + 12 + 4*nargs); 656 } 657 658 static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr, 659 target_ulong opcode, target_ulong *args) 660 { 661 CPUState *cs = CPU(cpu); 662 target_ulong size = args[0]; 663 target_ulong addr = args[1]; 664 665 switch (size) { 666 case 1: 667 args[0] = ldub_phys(cs->as, addr); 668 return H_SUCCESS; 669 case 2: 670 args[0] = lduw_phys(cs->as, addr); 671 return H_SUCCESS; 672 case 4: 673 args[0] = ldl_phys(cs->as, addr); 674 return H_SUCCESS; 675 case 8: 676 args[0] = ldq_phys(cs->as, addr); 677 return H_SUCCESS; 678 } 679 return H_PARAMETER; 680 } 681 682 static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr, 683 target_ulong opcode, target_ulong *args) 684 { 685 CPUState *cs = CPU(cpu); 686 687 target_ulong size = args[0]; 688 target_ulong addr = args[1]; 689 target_ulong val = args[2]; 690 691 switch (size) { 692 case 1: 693 stb_phys(cs->as, addr, val); 694 return H_SUCCESS; 695 case 2: 696 stw_phys(cs->as, addr, val); 697 return H_SUCCESS; 698 case 4: 699 stl_phys(cs->as, addr, val); 700 return H_SUCCESS; 701 case 8: 702 stq_phys(cs->as, addr, val); 703 return H_SUCCESS; 704 } 705 return H_PARAMETER; 706 } 707 708 static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr, 709 target_ulong opcode, target_ulong *args) 710 { 711 CPUState *cs = CPU(cpu); 712 713 target_ulong dst = args[0]; /* Destination address */ 714 target_ulong src = args[1]; /* Source address */ 715 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 716 target_ulong count = args[3]; /* Element count */ 717 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 718 uint64_t tmp; 719 unsigned int mask = (1 << esize) - 1; 720 int step = 1 << esize; 721 722 if (count > 0x80000000) { 723 return H_PARAMETER; 724 } 725 726 if ((dst & mask) || (src & mask) || (op > 1)) { 727 return H_PARAMETER; 728 } 729 730 if (dst >= src && dst < (src + (count << esize))) { 731 dst = dst + ((count - 1) << esize); 732 src = src + ((count - 1) << esize); 733 step = -step; 734 } 735 736 while (count--) { 737 switch (esize) { 738 case 0: 739 tmp = ldub_phys(cs->as, src); 740 break; 741 case 1: 742 tmp = lduw_phys(cs->as, src); 743 break; 744 case 2: 745 tmp = ldl_phys(cs->as, src); 746 break; 747 case 3: 748 tmp = ldq_phys(cs->as, src); 749 break; 750 default: 751 return H_PARAMETER; 752 } 753 if (op == 1) { 754 tmp = ~tmp; 755 } 756 switch (esize) { 757 case 0: 758 stb_phys(cs->as, dst, tmp); 759 break; 760 case 1: 761 stw_phys(cs->as, dst, tmp); 762 break; 763 case 2: 764 stl_phys(cs->as, dst, tmp); 765 break; 766 case 3: 767 stq_phys(cs->as, dst, tmp); 768 break; 769 } 770 dst = dst + step; 771 src = src + step; 772 } 773 774 return H_SUCCESS; 775 } 776 777 static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr, 778 target_ulong opcode, target_ulong *args) 779 { 780 /* Nothing to do on emulation, KVM will trap this in the kernel */ 781 return H_SUCCESS; 782 } 783 784 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, 785 target_ulong opcode, target_ulong *args) 786 { 787 /* Nothing to do on emulation, KVM will trap this in the kernel */ 788 return H_SUCCESS; 789 } 790 791 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 792 SpaprMachineState *spapr, 793 target_ulong mflags, 794 target_ulong value1, 795 target_ulong value2) 796 { 797 if (value1) { 798 return H_P3; 799 } 800 if (value2) { 801 return H_P4; 802 } 803 804 switch (mflags) { 805 case H_SET_MODE_ENDIAN_BIG: 806 spapr_set_all_lpcrs(0, LPCR_ILE); 807 spapr_pci_switch_vga(spapr, true); 808 return H_SUCCESS; 809 810 case H_SET_MODE_ENDIAN_LITTLE: 811 spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); 812 spapr_pci_switch_vga(spapr, false); 813 return H_SUCCESS; 814 } 815 816 return H_UNSUPPORTED_FLAG; 817 } 818 819 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 820 SpaprMachineState *spapr, 821 target_ulong mflags, 822 target_ulong value1, 823 target_ulong value2) 824 { 825 if (value1) { 826 return H_P3; 827 } 828 829 if (value2) { 830 return H_P4; 831 } 832 833 /* 834 * AIL-1 is not architected, and AIL-2 is not supported by QEMU spapr. 835 * It is supported for faithful emulation of bare metal systems, but for 836 * compatibility concerns we leave it out of the pseries machine. 837 */ 838 if (mflags != 0 && mflags != 3) { 839 return H_UNSUPPORTED_FLAG; 840 } 841 842 if (mflags == 3) { 843 if (!spapr_get_cap(spapr, SPAPR_CAP_AIL_MODE_3)) { 844 return H_UNSUPPORTED_FLAG; 845 } 846 } 847 848 spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); 849 850 return H_SUCCESS; 851 } 852 853 static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, 854 target_ulong opcode, target_ulong *args) 855 { 856 target_ulong resource = args[1]; 857 target_ulong ret = H_P2; 858 859 switch (resource) { 860 case H_SET_MODE_RESOURCE_LE: 861 ret = h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[3]); 862 break; 863 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 864 ret = h_set_mode_resource_addr_trans_mode(cpu, spapr, args[0], 865 args[2], args[3]); 866 break; 867 } 868 869 return ret; 870 } 871 872 static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, 873 target_ulong opcode, target_ulong *args) 874 { 875 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 876 opcode, " (H_CLEAN_SLB)"); 877 return H_FUNCTION; 878 } 879 880 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr, 881 target_ulong opcode, target_ulong *args) 882 { 883 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 884 opcode, " (H_INVALIDATE_PID)"); 885 return H_FUNCTION; 886 } 887 888 static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, 889 uint64_t patbe_old, uint64_t patbe_new) 890 { 891 /* 892 * We have 4 Options: 893 * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 894 * HASH->RADIX : Free HPT 895 * RADIX->HASH : Allocate HPT 896 * NOTHING->HASH : Allocate HPT 897 * Note: NOTHING implies the case where we said the guest could choose 898 * later and so assumed radix and now it's called H_REG_PROC_TBL 899 */ 900 901 if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) { 902 /* We assume RADIX, so this catches all the "Do Nothing" cases */ 903 } else if (!(patbe_old & PATE1_GR)) { 904 /* HASH->RADIX : Free HPT */ 905 spapr_free_hpt(spapr); 906 } else if (!(patbe_new & PATE1_GR)) { 907 /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 908 spapr_setup_hpt(spapr); 909 } 910 return; 911 } 912 913 #define FLAGS_MASK 0x01FULL 914 #define FLAG_MODIFY 0x10 915 #define FLAG_REGISTER 0x08 916 #define FLAG_RADIX 0x04 917 #define FLAG_HASH_PROC_TBL 0x02 918 #define FLAG_GTSE 0x01 919 920 static target_ulong h_register_process_table(PowerPCCPU *cpu, 921 SpaprMachineState *spapr, 922 target_ulong opcode, 923 target_ulong *args) 924 { 925 target_ulong flags = args[0]; 926 target_ulong proc_tbl = args[1]; 927 target_ulong page_size = args[2]; 928 target_ulong table_size = args[3]; 929 target_ulong update_lpcr = 0; 930 target_ulong table_byte_size; 931 uint64_t cproc; 932 933 if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 934 return H_PARAMETER; 935 } 936 if (flags & FLAG_MODIFY) { 937 if (flags & FLAG_REGISTER) { 938 /* Check process table alignment */ 939 table_byte_size = 1ULL << (table_size + 12); 940 if (proc_tbl & (table_byte_size - 1)) { 941 qemu_log_mask(LOG_GUEST_ERROR, 942 "%s: process table not properly aligned: proc_tbl 0x" 943 TARGET_FMT_lx" proc_tbl_size 0x"TARGET_FMT_lx"\n", 944 __func__, proc_tbl, table_byte_size); 945 } 946 if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 947 if (proc_tbl & 0xfff || proc_tbl >> 60) { 948 return H_P2; 949 } else if (page_size) { 950 return H_P3; 951 } else if (table_size > 24) { 952 return H_P4; 953 } 954 cproc = PATE1_GR | proc_tbl | table_size; 955 } else { /* Register new HPT process table */ 956 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 957 /* TODO - Not Supported */ 958 /* Technically caused by flag bits => H_PARAMETER */ 959 return H_PARAMETER; 960 } else { /* Hash with SLB */ 961 if (proc_tbl >> 38) { 962 return H_P2; 963 } else if (page_size & ~0x7) { 964 return H_P3; 965 } else if (table_size > 24) { 966 return H_P4; 967 } 968 } 969 cproc = (proc_tbl << 25) | page_size << 5 | table_size; 970 } 971 972 } else { /* Deregister current process table */ 973 /* 974 * Set to benign value: (current GR) | 0. This allows 975 * deregistration in KVM to succeed even if the radix bit 976 * in flags doesn't match the radix bit in the old PATE. 977 */ 978 cproc = spapr->patb_entry & PATE1_GR; 979 } 980 } else { /* Maintain current registration */ 981 if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) { 982 /* Technically caused by flag bits => H_PARAMETER */ 983 return H_PARAMETER; /* Existing Process Table Mismatch */ 984 } 985 cproc = spapr->patb_entry; 986 } 987 988 /* Check if we need to setup OR free the hpt */ 989 spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 990 991 spapr->patb_entry = cproc; /* Save new process table */ 992 993 /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ 994 if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */ 995 update_lpcr |= (LPCR_UPRT | LPCR_HR); 996 else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ 997 update_lpcr |= LPCR_UPRT; 998 if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ 999 update_lpcr |= LPCR_GTSE; 1000 1001 spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); 1002 1003 if (kvm_enabled()) { 1004 return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1005 flags & FLAG_GTSE, cproc); 1006 } 1007 return H_SUCCESS; 1008 } 1009 1010 #define H_SIGNAL_SYS_RESET_ALL -1 1011 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 1012 1013 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1014 SpaprMachineState *spapr, 1015 target_ulong opcode, target_ulong *args) 1016 { 1017 target_long target = args[0]; 1018 CPUState *cs; 1019 1020 if (target < 0) { 1021 /* Broadcast */ 1022 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1023 return H_PARAMETER; 1024 } 1025 1026 CPU_FOREACH(cs) { 1027 PowerPCCPU *c = POWERPC_CPU(cs); 1028 1029 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1030 if (c == cpu) { 1031 continue; 1032 } 1033 } 1034 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1035 } 1036 return H_SUCCESS; 1037 1038 } else { 1039 /* Unicast */ 1040 cs = CPU(spapr_find_cpu(target)); 1041 if (cs) { 1042 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1043 return H_SUCCESS; 1044 } 1045 return H_PARAMETER; 1046 } 1047 } 1048 1049 /* Returns either a logical PVR or zero if none was found */ 1050 static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32_t max_compat, 1051 target_ulong *addr, bool *raw_mode_supported) 1052 { 1053 bool explicit_match = false; /* Matched the CPU's real PVR */ 1054 uint32_t best_compat = 0; 1055 int i; 1056 1057 /* 1058 * We scan the supplied table of PVRs looking for two things 1059 * 1. Is our real CPU PVR in the list? 1060 * 2. What's the "best" listed logical PVR 1061 */ 1062 for (i = 0; i < 512; ++i) { 1063 uint32_t pvr, pvr_mask; 1064 1065 pvr_mask = ldl_be_phys(&address_space_memory, *addr); 1066 pvr = ldl_be_phys(&address_space_memory, *addr + 4); 1067 *addr += 8; 1068 1069 if (~pvr_mask & pvr) { 1070 break; /* Terminator record */ 1071 } 1072 1073 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1074 explicit_match = true; 1075 } else { 1076 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1077 best_compat = pvr; 1078 } 1079 } 1080 } 1081 1082 *raw_mode_supported = explicit_match; 1083 1084 /* Parsing finished */ 1085 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 1086 1087 return best_compat; 1088 } 1089 1090 static 1091 target_ulong do_client_architecture_support(PowerPCCPU *cpu, 1092 SpaprMachineState *spapr, 1093 target_ulong vec, 1094 target_ulong fdt_bufsize) 1095 { 1096 target_ulong ov_table; /* Working address in data buffer */ 1097 uint32_t cas_pvr; 1098 SpaprOptionVector *ov1_guest, *ov5_guest; 1099 bool guest_radix; 1100 bool raw_mode_supported = false; 1101 bool guest_xive; 1102 CPUState *cs; 1103 void *fdt; 1104 uint32_t max_compat = spapr->max_compat_pvr; 1105 1106 /* CAS is supposed to be called early when only the boot vCPU is active. */ 1107 CPU_FOREACH(cs) { 1108 if (cs == CPU(cpu)) { 1109 continue; 1110 } 1111 if (!cs->halted) { 1112 warn_report("guest has multiple active vCPUs at CAS, which is not allowed"); 1113 return H_MULTI_THREADS_ACTIVE; 1114 } 1115 } 1116 1117 cas_pvr = cas_check_pvr(cpu, max_compat, &vec, &raw_mode_supported); 1118 if (!cas_pvr && (!raw_mode_supported || max_compat)) { 1119 /* 1120 * We couldn't find a suitable compatibility mode, and either 1121 * the guest doesn't support "raw" mode for this CPU, or "raw" 1122 * mode is disabled because a maximum compat mode is set. 1123 */ 1124 error_report("Couldn't negotiate a suitable PVR during CAS"); 1125 return H_HARDWARE; 1126 } 1127 1128 /* Update CPUs */ 1129 if (cpu->compat_pvr != cas_pvr) { 1130 Error *local_err = NULL; 1131 1132 if (ppc_set_compat_all(cas_pvr, &local_err) < 0) { 1133 /* We fail to set compat mode (likely because running with KVM PR), 1134 * but maybe we can fallback to raw mode if the guest supports it. 1135 */ 1136 if (!raw_mode_supported) { 1137 error_report_err(local_err); 1138 return H_HARDWARE; 1139 } 1140 error_free(local_err); 1141 } 1142 } 1143 1144 /* For the future use: here @ov_table points to the first option vector */ 1145 ov_table = vec; 1146 1147 ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1148 if (!ov1_guest) { 1149 warn_report("guest didn't provide option vector 1"); 1150 return H_PARAMETER; 1151 } 1152 ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1153 if (!ov5_guest) { 1154 spapr_ovec_cleanup(ov1_guest); 1155 warn_report("guest didn't provide option vector 5"); 1156 return H_PARAMETER; 1157 } 1158 if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 1159 error_report("guest requested hash and radix MMU, which is invalid."); 1160 exit(EXIT_FAILURE); 1161 } 1162 if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { 1163 error_report("guest requested an invalid interrupt mode"); 1164 exit(EXIT_FAILURE); 1165 } 1166 1167 guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 1168 1169 guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); 1170 1171 /* 1172 * HPT resizing is a bit of a special case, because when enabled 1173 * we assume an HPT guest will support it until it says it 1174 * doesn't, instead of assuming it won't support it until it says 1175 * it does. Strictly speaking that approach could break for 1176 * guests which don't make a CAS call, but those are so old we 1177 * don't care about them. Without that assumption we'd have to 1178 * make at least a temporary allocation of an HPT sized for max 1179 * memory, which could be impossibly difficult under KVM HV if 1180 * maxram is large. 1181 */ 1182 if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 1183 int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1184 1185 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 1186 error_report( 1187 "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 1188 exit(1); 1189 } 1190 1191 if (spapr->htab_shift < maxshift) { 1192 /* Guest doesn't know about HPT resizing, so we 1193 * pre-emptively resize for the maximum permitted RAM. At 1194 * the point this is called, nothing should have been 1195 * entered into the existing HPT */ 1196 spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 1197 push_sregs_to_kvm_pr(spapr); 1198 } 1199 } 1200 1201 /* NOTE: there are actually a number of ov5 bits where input from the 1202 * guest is always zero, and the platform/QEMU enables them independently 1203 * of guest input. To model these properly we'd want some sort of mask, 1204 * but since they only currently apply to memory migration as defined 1205 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 1206 * to worry about this for now. 1207 */ 1208 1209 /* full range of negotiated ov5 capabilities */ 1210 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1211 spapr_ovec_cleanup(ov5_guest); 1212 1213 spapr_check_mmu_mode(guest_radix); 1214 1215 spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00); 1216 spapr_ovec_cleanup(ov1_guest); 1217 1218 /* 1219 * Check for NUMA affinity conditions now that we know which NUMA 1220 * affinity the guest will use. 1221 */ 1222 spapr_numa_associativity_check(spapr); 1223 1224 /* 1225 * Ensure the guest asks for an interrupt mode we support; 1226 * otherwise terminate the boot. 1227 */ 1228 if (guest_xive) { 1229 if (!spapr->irq->xive) { 1230 error_report( 1231 "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property"); 1232 exit(EXIT_FAILURE); 1233 } 1234 } else { 1235 if (!spapr->irq->xics) { 1236 error_report( 1237 "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual"); 1238 exit(EXIT_FAILURE); 1239 } 1240 } 1241 1242 spapr_irq_update_active_intc(spapr); 1243 1244 /* 1245 * Process all pending hot-plug/unplug requests now. An updated full 1246 * rendered FDT will be returned to the guest. 1247 */ 1248 spapr_drc_reset_all(spapr); 1249 spapr_clear_pending_hotplug_events(spapr); 1250 1251 /* 1252 * If spapr_machine_reset() did not set up a HPT but one is necessary 1253 * (because the guest isn't going to use radix) then set it up here. 1254 */ 1255 if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { 1256 /* legacy hash or new hash: */ 1257 spapr_setup_hpt(spapr); 1258 } 1259 1260 fdt = spapr_build_fdt(spapr, spapr->vof != NULL, fdt_bufsize); 1261 g_free(spapr->fdt_blob); 1262 spapr->fdt_size = fdt_totalsize(fdt); 1263 spapr->fdt_initial_size = spapr->fdt_size; 1264 spapr->fdt_blob = fdt; 1265 1266 /* 1267 * Set the machine->fdt pointer again since we just freed 1268 * it above (by freeing spapr->fdt_blob). We set this 1269 * pointer to enable support for the 'dumpdtb' QMP/HMP 1270 * command. 1271 */ 1272 MACHINE(spapr)->fdt = fdt; 1273 1274 return H_SUCCESS; 1275 } 1276 1277 static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1278 SpaprMachineState *spapr, 1279 target_ulong opcode, 1280 target_ulong *args) 1281 { 1282 target_ulong vec = ppc64_phys_to_real(args[0]); 1283 target_ulong fdt_buf = args[1]; 1284 target_ulong fdt_bufsize = args[2]; 1285 target_ulong ret; 1286 SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 1287 1288 if (fdt_bufsize < sizeof(hdr)) { 1289 error_report("SLOF provided insufficient CAS buffer " 1290 TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr)); 1291 exit(EXIT_FAILURE); 1292 } 1293 1294 fdt_bufsize -= sizeof(hdr); 1295 1296 ret = do_client_architecture_support(cpu, spapr, vec, fdt_bufsize); 1297 if (ret == H_SUCCESS) { 1298 _FDT((fdt_pack(spapr->fdt_blob))); 1299 spapr->fdt_size = fdt_totalsize(spapr->fdt_blob); 1300 spapr->fdt_initial_size = spapr->fdt_size; 1301 1302 cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr)); 1303 cpu_physical_memory_write(fdt_buf + sizeof(hdr), spapr->fdt_blob, 1304 spapr->fdt_size); 1305 trace_spapr_cas_continue(spapr->fdt_size + sizeof(hdr)); 1306 } 1307 1308 return ret; 1309 } 1310 1311 target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1312 CPUState *cs, 1313 target_ulong ovec_addr) 1314 { 1315 SpaprMachineState *spapr = SPAPR_MACHINE(ms); 1316 1317 target_ulong ret = do_client_architecture_support(POWERPC_CPU(cs), spapr, 1318 ovec_addr, FDT_MAX_SIZE); 1319 1320 /* 1321 * This adds stdout and generates phandles for boottime and CAS FDTs. 1322 * It is alright to update the FDT here as do_client_architecture_support() 1323 * does not pack it. 1324 */ 1325 spapr_vof_client_dt_finalize(spapr, spapr->fdt_blob); 1326 1327 return ret; 1328 } 1329 1330 static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1331 SpaprMachineState *spapr, 1332 target_ulong opcode, 1333 target_ulong *args) 1334 { 1335 uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1336 ~H_CPU_CHAR_THR_RECONF_TRIG; 1337 uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1338 uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1339 uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1340 uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 1341 uint8_t count_cache_flush_assist = spapr_get_cap(spapr, 1342 SPAPR_CAP_CCF_ASSIST); 1343 1344 switch (safe_cache) { 1345 case SPAPR_CAP_WORKAROUND: 1346 characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1347 characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1348 characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1349 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1350 break; 1351 case SPAPR_CAP_FIXED: 1352 behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY; 1353 behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS; 1354 break; 1355 default: /* broken */ 1356 assert(safe_cache == SPAPR_CAP_BROKEN); 1357 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1358 break; 1359 } 1360 1361 switch (safe_bounds_check) { 1362 case SPAPR_CAP_WORKAROUND: 1363 characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1364 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1365 break; 1366 case SPAPR_CAP_FIXED: 1367 break; 1368 default: /* broken */ 1369 assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1370 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1371 break; 1372 } 1373 1374 switch (safe_indirect_branch) { 1375 case SPAPR_CAP_FIXED_NA: 1376 break; 1377 case SPAPR_CAP_FIXED_CCD: 1378 characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; 1379 break; 1380 case SPAPR_CAP_FIXED_IBS: 1381 characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1382 break; 1383 case SPAPR_CAP_WORKAROUND: 1384 behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE; 1385 if (count_cache_flush_assist) { 1386 characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST; 1387 } 1388 break; 1389 default: /* broken */ 1390 assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1391 break; 1392 } 1393 1394 args[0] = characteristics; 1395 args[1] = behaviour; 1396 return H_SUCCESS; 1397 } 1398 1399 static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, 1400 target_ulong opcode, target_ulong *args) 1401 { 1402 target_ulong dt = ppc64_phys_to_real(args[0]); 1403 struct fdt_header hdr = { 0 }; 1404 unsigned cb; 1405 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1406 void *fdt; 1407 1408 cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); 1409 cb = fdt32_to_cpu(hdr.totalsize); 1410 1411 if (!smc->update_dt_enabled) { 1412 return H_SUCCESS; 1413 } 1414 1415 /* Check that the fdt did not grow out of proportion */ 1416 if (cb > spapr->fdt_initial_size * 2) { 1417 trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, 1418 fdt32_to_cpu(hdr.magic)); 1419 return H_PARAMETER; 1420 } 1421 1422 fdt = g_malloc0(cb); 1423 cpu_physical_memory_read(dt, fdt, cb); 1424 1425 /* Check the fdt consistency */ 1426 if (fdt_check_full(fdt, cb)) { 1427 trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, 1428 fdt32_to_cpu(hdr.magic)); 1429 return H_PARAMETER; 1430 } 1431 1432 g_free(spapr->fdt_blob); 1433 spapr->fdt_size = cb; 1434 spapr->fdt_blob = fdt; 1435 trace_spapr_update_dt(cb); 1436 1437 return H_SUCCESS; 1438 } 1439 1440 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 1441 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 1442 static spapr_hcall_fn svm_hypercall_table[(SVM_HCALL_MAX - SVM_HCALL_BASE) / 4 + 1]; 1443 1444 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 1445 { 1446 spapr_hcall_fn *slot; 1447 1448 if (opcode <= MAX_HCALL_OPCODE) { 1449 assert((opcode & 0x3) == 0); 1450 1451 slot = &papr_hypercall_table[opcode / 4]; 1452 } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { 1453 /* we only have SVM-related hcall numbers assigned in multiples of 4 */ 1454 assert((opcode & 0x3) == 0); 1455 1456 slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1457 } else { 1458 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1459 1460 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1461 } 1462 1463 assert(!(*slot)); 1464 *slot = fn; 1465 } 1466 1467 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 1468 target_ulong *args) 1469 { 1470 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1471 1472 if ((opcode <= MAX_HCALL_OPCODE) 1473 && ((opcode & 0x3) == 0)) { 1474 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 1475 1476 if (fn) { 1477 return fn(cpu, spapr, opcode, args); 1478 } 1479 } else if ((opcode >= SVM_HCALL_BASE) && 1480 (opcode <= SVM_HCALL_MAX)) { 1481 spapr_hcall_fn fn = svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1482 1483 if (fn) { 1484 return fn(cpu, spapr, opcode, args); 1485 } 1486 } else if ((opcode >= KVMPPC_HCALL_BASE) && 1487 (opcode <= KVMPPC_HCALL_MAX)) { 1488 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1489 1490 if (fn) { 1491 return fn(cpu, spapr, opcode, args); 1492 } 1493 } 1494 1495 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1496 opcode); 1497 return H_FUNCTION; 1498 } 1499 1500 #ifdef CONFIG_TCG 1501 #define PRTS_MASK 0x1f 1502 1503 static target_ulong h_set_ptbl(PowerPCCPU *cpu, 1504 SpaprMachineState *spapr, 1505 target_ulong opcode, 1506 target_ulong *args) 1507 { 1508 target_ulong ptcr = args[0]; 1509 1510 if (!spapr_get_cap(spapr, SPAPR_CAP_NESTED_KVM_HV)) { 1511 return H_FUNCTION; 1512 } 1513 1514 if ((ptcr & PRTS_MASK) + 12 - 4 > 12) { 1515 return H_PARAMETER; 1516 } 1517 1518 spapr->nested_ptcr = ptcr; /* Save new partition table */ 1519 1520 return H_SUCCESS; 1521 } 1522 1523 static target_ulong h_tlb_invalidate(PowerPCCPU *cpu, 1524 SpaprMachineState *spapr, 1525 target_ulong opcode, 1526 target_ulong *args) 1527 { 1528 /* 1529 * The spapr virtual hypervisor nested HV implementation retains no L2 1530 * translation state except for TLB. And the TLB is always invalidated 1531 * across L1<->L2 transitions, so nothing is required here. 1532 */ 1533 1534 return H_SUCCESS; 1535 } 1536 1537 static target_ulong h_copy_tofrom_guest(PowerPCCPU *cpu, 1538 SpaprMachineState *spapr, 1539 target_ulong opcode, 1540 target_ulong *args) 1541 { 1542 /* 1543 * This HCALL is not required, L1 KVM will take a slow path and walk the 1544 * page tables manually to do the data copy. 1545 */ 1546 return H_FUNCTION; 1547 } 1548 1549 /* 1550 * When this handler returns, the environment is switched to the L2 guest 1551 * and TCG begins running that. spapr_exit_nested() performs the switch from 1552 * L2 back to L1 and returns from the H_ENTER_NESTED hcall. 1553 */ 1554 static target_ulong h_enter_nested(PowerPCCPU *cpu, 1555 SpaprMachineState *spapr, 1556 target_ulong opcode, 1557 target_ulong *args) 1558 { 1559 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 1560 CPUState *cs = CPU(cpu); 1561 CPUPPCState *env = &cpu->env; 1562 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1563 target_ulong hv_ptr = args[0]; 1564 target_ulong regs_ptr = args[1]; 1565 target_ulong hdec, now = cpu_ppc_load_tbl(env); 1566 target_ulong lpcr, lpcr_mask; 1567 struct kvmppc_hv_guest_state *hvstate; 1568 struct kvmppc_hv_guest_state hv_state; 1569 struct kvmppc_pt_regs *regs; 1570 hwaddr len; 1571 1572 if (spapr->nested_ptcr == 0) { 1573 return H_NOT_AVAILABLE; 1574 } 1575 1576 len = sizeof(*hvstate); 1577 hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, false, 1578 MEMTXATTRS_UNSPECIFIED); 1579 if (len != sizeof(*hvstate)) { 1580 address_space_unmap(CPU(cpu)->as, hvstate, len, 0, false); 1581 return H_PARAMETER; 1582 } 1583 1584 memcpy(&hv_state, hvstate, len); 1585 1586 address_space_unmap(CPU(cpu)->as, hvstate, len, len, false); 1587 1588 /* 1589 * We accept versions 1 and 2. Version 2 fields are unused because TCG 1590 * does not implement DAWR*. 1591 */ 1592 if (hv_state.version > HV_GUEST_STATE_VERSION) { 1593 return H_PARAMETER; 1594 } 1595 1596 spapr_cpu->nested_host_state = g_try_new(CPUPPCState, 1); 1597 if (!spapr_cpu->nested_host_state) { 1598 return H_NO_MEM; 1599 } 1600 1601 memcpy(spapr_cpu->nested_host_state, env, sizeof(CPUPPCState)); 1602 1603 len = sizeof(*regs); 1604 regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, false, 1605 MEMTXATTRS_UNSPECIFIED); 1606 if (!regs || len != sizeof(*regs)) { 1607 address_space_unmap(CPU(cpu)->as, regs, len, 0, false); 1608 g_free(spapr_cpu->nested_host_state); 1609 return H_P2; 1610 } 1611 1612 len = sizeof(env->gpr); 1613 assert(len == sizeof(regs->gpr)); 1614 memcpy(env->gpr, regs->gpr, len); 1615 1616 env->lr = regs->link; 1617 env->ctr = regs->ctr; 1618 cpu_write_xer(env, regs->xer); 1619 ppc_set_cr(env, regs->ccr); 1620 1621 env->msr = regs->msr; 1622 env->nip = regs->nip; 1623 1624 address_space_unmap(CPU(cpu)->as, regs, len, len, false); 1625 1626 env->cfar = hv_state.cfar; 1627 1628 assert(env->spr[SPR_LPIDR] == 0); 1629 env->spr[SPR_LPIDR] = hv_state.lpid; 1630 1631 lpcr_mask = LPCR_DPFD | LPCR_ILE | LPCR_AIL | LPCR_LD | LPCR_MER; 1632 lpcr = (env->spr[SPR_LPCR] & ~lpcr_mask) | (hv_state.lpcr & lpcr_mask); 1633 lpcr |= LPCR_HR | LPCR_UPRT | LPCR_GTSE | LPCR_HVICE | LPCR_HDICE; 1634 lpcr &= ~LPCR_LPES0; 1635 env->spr[SPR_LPCR] = lpcr & pcc->lpcr_mask; 1636 1637 env->spr[SPR_PCR] = hv_state.pcr; 1638 /* hv_state.amor is not used */ 1639 env->spr[SPR_DPDES] = hv_state.dpdes; 1640 env->spr[SPR_HFSCR] = hv_state.hfscr; 1641 hdec = hv_state.hdec_expiry - now; 1642 spapr_cpu->nested_tb_offset = hv_state.tb_offset; 1643 /* TCG does not implement DAWR*, CIABR, PURR, SPURR, IC, VTB, HEIR SPRs*/ 1644 env->spr[SPR_SRR0] = hv_state.srr0; 1645 env->spr[SPR_SRR1] = hv_state.srr1; 1646 env->spr[SPR_SPRG0] = hv_state.sprg[0]; 1647 env->spr[SPR_SPRG1] = hv_state.sprg[1]; 1648 env->spr[SPR_SPRG2] = hv_state.sprg[2]; 1649 env->spr[SPR_SPRG3] = hv_state.sprg[3]; 1650 env->spr[SPR_BOOKS_PID] = hv_state.pidr; 1651 env->spr[SPR_PPR] = hv_state.ppr; 1652 1653 cpu_ppc_hdecr_init(env); 1654 cpu_ppc_store_hdecr(env, hdec); 1655 1656 /* 1657 * The hv_state.vcpu_token is not needed. It is used by the KVM 1658 * implementation to remember which L2 vCPU last ran on which physical 1659 * CPU so as to invalidate process scope translations if it is moved 1660 * between physical CPUs. For now TLBs are always flushed on L1<->L2 1661 * transitions so this is not a problem. 1662 * 1663 * Could validate that the same vcpu_token does not attempt to run on 1664 * different L1 vCPUs at the same time, but that would be a L1 KVM bug 1665 * and it's not obviously worth a new data structure to do it. 1666 */ 1667 1668 env->tb_env->tb_offset += spapr_cpu->nested_tb_offset; 1669 spapr_cpu->in_nested = true; 1670 1671 hreg_compute_hflags(env); 1672 ppc_maybe_interrupt(env); 1673 tlb_flush(cs); 1674 env->reserve_addr = -1; /* Reset the reservation */ 1675 1676 /* 1677 * The spapr hcall helper sets env->gpr[3] to the return value, but at 1678 * this point the L1 is not returning from the hcall but rather we 1679 * start running the L2, so r3 must not be clobbered, so return env->gpr[3] 1680 * to leave it unchanged. 1681 */ 1682 return env->gpr[3]; 1683 } 1684 1685 void spapr_exit_nested(PowerPCCPU *cpu, int excp) 1686 { 1687 CPUState *cs = CPU(cpu); 1688 CPUPPCState *env = &cpu->env; 1689 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1690 target_ulong r3_return = env->excp_vectors[excp]; /* hcall return value */ 1691 target_ulong hv_ptr = spapr_cpu->nested_host_state->gpr[4]; 1692 target_ulong regs_ptr = spapr_cpu->nested_host_state->gpr[5]; 1693 struct kvmppc_hv_guest_state *hvstate; 1694 struct kvmppc_pt_regs *regs; 1695 hwaddr len; 1696 1697 assert(spapr_cpu->in_nested); 1698 1699 cpu_ppc_hdecr_exit(env); 1700 1701 len = sizeof(*hvstate); 1702 hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, true, 1703 MEMTXATTRS_UNSPECIFIED); 1704 if (len != sizeof(*hvstate)) { 1705 address_space_unmap(CPU(cpu)->as, hvstate, len, 0, true); 1706 r3_return = H_PARAMETER; 1707 goto out_restore_l1; 1708 } 1709 1710 hvstate->cfar = env->cfar; 1711 hvstate->lpcr = env->spr[SPR_LPCR]; 1712 hvstate->pcr = env->spr[SPR_PCR]; 1713 hvstate->dpdes = env->spr[SPR_DPDES]; 1714 hvstate->hfscr = env->spr[SPR_HFSCR]; 1715 1716 if (excp == POWERPC_EXCP_HDSI) { 1717 hvstate->hdar = env->spr[SPR_HDAR]; 1718 hvstate->hdsisr = env->spr[SPR_HDSISR]; 1719 hvstate->asdr = env->spr[SPR_ASDR]; 1720 } else if (excp == POWERPC_EXCP_HISI) { 1721 hvstate->asdr = env->spr[SPR_ASDR]; 1722 } 1723 1724 /* HEIR should be implemented for HV mode and saved here. */ 1725 hvstate->srr0 = env->spr[SPR_SRR0]; 1726 hvstate->srr1 = env->spr[SPR_SRR1]; 1727 hvstate->sprg[0] = env->spr[SPR_SPRG0]; 1728 hvstate->sprg[1] = env->spr[SPR_SPRG1]; 1729 hvstate->sprg[2] = env->spr[SPR_SPRG2]; 1730 hvstate->sprg[3] = env->spr[SPR_SPRG3]; 1731 hvstate->pidr = env->spr[SPR_BOOKS_PID]; 1732 hvstate->ppr = env->spr[SPR_PPR]; 1733 1734 /* Is it okay to specify write length larger than actual data written? */ 1735 address_space_unmap(CPU(cpu)->as, hvstate, len, len, true); 1736 1737 len = sizeof(*regs); 1738 regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, true, 1739 MEMTXATTRS_UNSPECIFIED); 1740 if (!regs || len != sizeof(*regs)) { 1741 address_space_unmap(CPU(cpu)->as, regs, len, 0, true); 1742 r3_return = H_P2; 1743 goto out_restore_l1; 1744 } 1745 1746 len = sizeof(env->gpr); 1747 assert(len == sizeof(regs->gpr)); 1748 memcpy(regs->gpr, env->gpr, len); 1749 1750 regs->link = env->lr; 1751 regs->ctr = env->ctr; 1752 regs->xer = cpu_read_xer(env); 1753 regs->ccr = ppc_get_cr(env); 1754 1755 if (excp == POWERPC_EXCP_MCHECK || 1756 excp == POWERPC_EXCP_RESET || 1757 excp == POWERPC_EXCP_SYSCALL) { 1758 regs->nip = env->spr[SPR_SRR0]; 1759 regs->msr = env->spr[SPR_SRR1] & env->msr_mask; 1760 } else { 1761 regs->nip = env->spr[SPR_HSRR0]; 1762 regs->msr = env->spr[SPR_HSRR1] & env->msr_mask; 1763 } 1764 1765 /* Is it okay to specify write length larger than actual data written? */ 1766 address_space_unmap(CPU(cpu)->as, regs, len, len, true); 1767 1768 out_restore_l1: 1769 memcpy(env->gpr, spapr_cpu->nested_host_state->gpr, sizeof(env->gpr)); 1770 env->lr = spapr_cpu->nested_host_state->lr; 1771 env->ctr = spapr_cpu->nested_host_state->ctr; 1772 memcpy(env->crf, spapr_cpu->nested_host_state->crf, sizeof(env->crf)); 1773 env->cfar = spapr_cpu->nested_host_state->cfar; 1774 env->xer = spapr_cpu->nested_host_state->xer; 1775 env->so = spapr_cpu->nested_host_state->so; 1776 env->ov = spapr_cpu->nested_host_state->ov; 1777 env->ov32 = spapr_cpu->nested_host_state->ov32; 1778 env->ca32 = spapr_cpu->nested_host_state->ca32; 1779 env->msr = spapr_cpu->nested_host_state->msr; 1780 env->nip = spapr_cpu->nested_host_state->nip; 1781 1782 assert(env->spr[SPR_LPIDR] != 0); 1783 env->spr[SPR_LPCR] = spapr_cpu->nested_host_state->spr[SPR_LPCR]; 1784 env->spr[SPR_LPIDR] = spapr_cpu->nested_host_state->spr[SPR_LPIDR]; 1785 env->spr[SPR_PCR] = spapr_cpu->nested_host_state->spr[SPR_PCR]; 1786 env->spr[SPR_DPDES] = 0; 1787 env->spr[SPR_HFSCR] = spapr_cpu->nested_host_state->spr[SPR_HFSCR]; 1788 env->spr[SPR_SRR0] = spapr_cpu->nested_host_state->spr[SPR_SRR0]; 1789 env->spr[SPR_SRR1] = spapr_cpu->nested_host_state->spr[SPR_SRR1]; 1790 env->spr[SPR_SPRG0] = spapr_cpu->nested_host_state->spr[SPR_SPRG0]; 1791 env->spr[SPR_SPRG1] = spapr_cpu->nested_host_state->spr[SPR_SPRG1]; 1792 env->spr[SPR_SPRG2] = spapr_cpu->nested_host_state->spr[SPR_SPRG2]; 1793 env->spr[SPR_SPRG3] = spapr_cpu->nested_host_state->spr[SPR_SPRG3]; 1794 env->spr[SPR_BOOKS_PID] = spapr_cpu->nested_host_state->spr[SPR_BOOKS_PID]; 1795 env->spr[SPR_PPR] = spapr_cpu->nested_host_state->spr[SPR_PPR]; 1796 1797 /* 1798 * Return the interrupt vector address from H_ENTER_NESTED to the L1 1799 * (or error code). 1800 */ 1801 env->gpr[3] = r3_return; 1802 1803 env->tb_env->tb_offset -= spapr_cpu->nested_tb_offset; 1804 spapr_cpu->in_nested = false; 1805 1806 hreg_compute_hflags(env); 1807 ppc_maybe_interrupt(env); 1808 tlb_flush(cs); 1809 env->reserve_addr = -1; /* Reset the reservation */ 1810 1811 g_free(spapr_cpu->nested_host_state); 1812 spapr_cpu->nested_host_state = NULL; 1813 } 1814 1815 static void hypercall_register_nested(void) 1816 { 1817 spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl); 1818 spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested); 1819 spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate); 1820 spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_guest); 1821 } 1822 1823 static void hypercall_register_softmmu(void) 1824 { 1825 /* DO NOTHING */ 1826 } 1827 #else 1828 void spapr_exit_nested(PowerPCCPU *cpu, int excp) 1829 { 1830 g_assert_not_reached(); 1831 } 1832 1833 static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr, 1834 target_ulong opcode, target_ulong *args) 1835 { 1836 g_assert_not_reached(); 1837 } 1838 1839 static void hypercall_register_nested(void) 1840 { 1841 /* DO NOTHING */ 1842 } 1843 1844 static void hypercall_register_softmmu(void) 1845 { 1846 /* hcall-pft */ 1847 spapr_register_hypercall(H_ENTER, h_softmmu); 1848 spapr_register_hypercall(H_REMOVE, h_softmmu); 1849 spapr_register_hypercall(H_PROTECT, h_softmmu); 1850 spapr_register_hypercall(H_READ, h_softmmu); 1851 1852 /* hcall-bulk */ 1853 spapr_register_hypercall(H_BULK_REMOVE, h_softmmu); 1854 } 1855 #endif 1856 1857 static void hypercall_register_types(void) 1858 { 1859 hypercall_register_softmmu(); 1860 1861 /* hcall-hpt-resize */ 1862 spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 1863 spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 1864 1865 /* hcall-splpar */ 1866 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 1867 spapr_register_hypercall(H_CEDE, h_cede); 1868 spapr_register_hypercall(H_CONFER, h_confer); 1869 spapr_register_hypercall(H_PROD, h_prod); 1870 1871 /* hcall-join */ 1872 spapr_register_hypercall(H_JOIN, h_join); 1873 1874 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 1875 1876 /* processor register resource access h-calls */ 1877 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1878 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1879 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 1880 spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1881 spapr_register_hypercall(H_SET_MODE, h_set_mode); 1882 1883 /* In Memory Table MMU h-calls */ 1884 spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1885 spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1886 spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1887 1888 /* hcall-get-cpu-characteristics */ 1889 spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 1890 h_get_cpu_characteristics); 1891 1892 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 1893 * here between the "CI" and the "CACHE" variants, they will use whatever 1894 * mapping attributes qemu is using. When using KVM, the kernel will 1895 * enforce the attributes more strongly 1896 */ 1897 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 1898 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 1899 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 1900 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 1901 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 1902 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 1903 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 1904 1905 /* qemu/KVM-PPC specific hcalls */ 1906 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 1907 1908 /* ibm,client-architecture-support support */ 1909 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1910 1911 spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); 1912 1913 hypercall_register_nested(); 1914 } 1915 1916 type_init(hypercall_register_types) 1917