1 #include "qemu/osdep.h" 2 #include "qemu/cutils.h" 3 #include "qapi/error.h" 4 #include "sysemu/hw_accel.h" 5 #include "sysemu/runstate.h" 6 #include "qemu/log.h" 7 #include "qemu/main-loop.h" 8 #include "qemu/module.h" 9 #include "qemu/error-report.h" 10 #include "exec/exec-all.h" 11 #include "helper_regs.h" 12 #include "hw/ppc/spapr.h" 13 #include "hw/ppc/spapr_cpu_core.h" 14 #include "mmu-hash64.h" 15 #include "cpu-models.h" 16 #include "trace.h" 17 #include "kvm_ppc.h" 18 #include "hw/ppc/fdt.h" 19 #include "hw/ppc/spapr_ovec.h" 20 #include "mmu-book3s-v3.h" 21 #include "hw/mem/memory-device.h" 22 23 static bool has_spr(PowerPCCPU *cpu, int spr) 24 { 25 /* We can test whether the SPR is defined by checking for a valid name */ 26 return cpu->env.spr_cb[spr].name != NULL; 27 } 28 29 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) 30 { 31 MachineState *machine = MACHINE(spapr); 32 DeviceMemoryState *dms = machine->device_memory; 33 34 if (addr < machine->ram_size) { 35 return true; 36 } 37 if ((addr >= dms->base) 38 && ((addr - dms->base) < memory_region_size(&dms->mr))) { 39 return true; 40 } 41 42 return false; 43 } 44 45 /* Convert a return code from the KVM ioctl()s implementing resize HPT 46 * into a PAPR hypercall return code */ 47 static target_ulong resize_hpt_convert_rc(int ret) 48 { 49 if (ret >= 100000) { 50 return H_LONG_BUSY_ORDER_100_SEC; 51 } else if (ret >= 10000) { 52 return H_LONG_BUSY_ORDER_10_SEC; 53 } else if (ret >= 1000) { 54 return H_LONG_BUSY_ORDER_1_SEC; 55 } else if (ret >= 100) { 56 return H_LONG_BUSY_ORDER_100_MSEC; 57 } else if (ret >= 10) { 58 return H_LONG_BUSY_ORDER_10_MSEC; 59 } else if (ret > 0) { 60 return H_LONG_BUSY_ORDER_1_MSEC; 61 } 62 63 switch (ret) { 64 case 0: 65 return H_SUCCESS; 66 case -EPERM: 67 return H_AUTHORITY; 68 case -EINVAL: 69 return H_PARAMETER; 70 case -ENXIO: 71 return H_CLOSED; 72 case -ENOSPC: 73 return H_PTEG_FULL; 74 case -EBUSY: 75 return H_BUSY; 76 case -ENOMEM: 77 return H_NO_MEM; 78 default: 79 return H_HARDWARE; 80 } 81 } 82 83 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 84 SpaprMachineState *spapr, 85 target_ulong opcode, 86 target_ulong *args) 87 { 88 target_ulong flags = args[0]; 89 int shift = args[1]; 90 uint64_t current_ram_size; 91 int rc; 92 93 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 94 return H_AUTHORITY; 95 } 96 97 if (!spapr->htab_shift) { 98 /* Radix guest, no HPT */ 99 return H_NOT_AVAILABLE; 100 } 101 102 trace_spapr_h_resize_hpt_prepare(flags, shift); 103 104 if (flags != 0) { 105 return H_PARAMETER; 106 } 107 108 if (shift && ((shift < 18) || (shift > 46))) { 109 return H_PARAMETER; 110 } 111 112 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 113 114 /* We only allow the guest to allocate an HPT one order above what 115 * we'd normally give them (to stop a small guest claiming a huge 116 * chunk of resources in the HPT */ 117 if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 118 return H_RESOURCE; 119 } 120 121 rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 122 if (rc != -ENOSYS) { 123 return resize_hpt_convert_rc(rc); 124 } 125 126 if (kvm_enabled()) { 127 return H_HARDWARE; 128 } 129 130 return softmmu_resize_hpt_prepare(cpu, spapr, shift); 131 } 132 133 static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 134 { 135 int ret; 136 137 cpu_synchronize_state(cs); 138 139 ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 140 if (ret < 0) { 141 error_report("failed to push sregs to KVM: %s", strerror(-ret)); 142 exit(1); 143 } 144 } 145 146 void push_sregs_to_kvm_pr(SpaprMachineState *spapr) 147 { 148 CPUState *cs; 149 150 /* 151 * This is a hack for the benefit of KVM PR - it abuses the SDR1 152 * slot in kvm_sregs to communicate the userspace address of the 153 * HPT 154 */ 155 if (!kvm_enabled() || !spapr->htab) { 156 return; 157 } 158 159 CPU_FOREACH(cs) { 160 run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 161 } 162 } 163 164 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 165 SpaprMachineState *spapr, 166 target_ulong opcode, 167 target_ulong *args) 168 { 169 target_ulong flags = args[0]; 170 target_ulong shift = args[1]; 171 int rc; 172 173 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 174 return H_AUTHORITY; 175 } 176 177 if (!spapr->htab_shift) { 178 /* Radix guest, no HPT */ 179 return H_NOT_AVAILABLE; 180 } 181 182 trace_spapr_h_resize_hpt_commit(flags, shift); 183 184 rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 185 if (rc != -ENOSYS) { 186 rc = resize_hpt_convert_rc(rc); 187 if (rc == H_SUCCESS) { 188 /* Need to set the new htab_shift in the machine state */ 189 spapr->htab_shift = shift; 190 } 191 return rc; 192 } 193 194 if (kvm_enabled()) { 195 return H_HARDWARE; 196 } 197 198 return softmmu_resize_hpt_commit(cpu, spapr, flags, shift); 199 } 200 201 202 203 static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, 204 target_ulong opcode, target_ulong *args) 205 { 206 cpu_synchronize_state(CPU(cpu)); 207 cpu->env.spr[SPR_SPRG0] = args[0]; 208 209 return H_SUCCESS; 210 } 211 212 static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 213 target_ulong opcode, target_ulong *args) 214 { 215 if (!has_spr(cpu, SPR_DABR)) { 216 return H_HARDWARE; /* DABR register not available */ 217 } 218 cpu_synchronize_state(CPU(cpu)); 219 220 if (has_spr(cpu, SPR_DABRX)) { 221 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 222 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 223 return H_RESERVED_DABR; 224 } 225 226 cpu->env.spr[SPR_DABR] = args[0]; 227 return H_SUCCESS; 228 } 229 230 static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 231 target_ulong opcode, target_ulong *args) 232 { 233 target_ulong dabrx = args[1]; 234 235 if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { 236 return H_HARDWARE; 237 } 238 239 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 240 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 241 return H_PARAMETER; 242 } 243 244 cpu_synchronize_state(CPU(cpu)); 245 cpu->env.spr[SPR_DABRX] = dabrx; 246 cpu->env.spr[SPR_DABR] = args[0]; 247 248 return H_SUCCESS; 249 } 250 251 static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, 252 target_ulong opcode, target_ulong *args) 253 { 254 target_ulong flags = args[0]; 255 hwaddr dst = args[1]; 256 hwaddr src = args[2]; 257 hwaddr len = TARGET_PAGE_SIZE; 258 uint8_t *pdst, *psrc; 259 target_long ret = H_SUCCESS; 260 261 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 262 | H_COPY_PAGE | H_ZERO_PAGE)) { 263 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 264 flags); 265 return H_PARAMETER; 266 } 267 268 /* Map-in destination */ 269 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 270 return H_PARAMETER; 271 } 272 pdst = cpu_physical_memory_map(dst, &len, true); 273 if (!pdst || len != TARGET_PAGE_SIZE) { 274 return H_PARAMETER; 275 } 276 277 if (flags & H_COPY_PAGE) { 278 /* Map-in source, copy to destination, and unmap source again */ 279 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 280 ret = H_PARAMETER; 281 goto unmap_out; 282 } 283 psrc = cpu_physical_memory_map(src, &len, false); 284 if (!psrc || len != TARGET_PAGE_SIZE) { 285 ret = H_PARAMETER; 286 goto unmap_out; 287 } 288 memcpy(pdst, psrc, len); 289 cpu_physical_memory_unmap(psrc, len, 0, len); 290 } else if (flags & H_ZERO_PAGE) { 291 memset(pdst, 0, len); /* Just clear the destination page */ 292 } 293 294 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 295 kvmppc_dcbst_range(cpu, pdst, len); 296 } 297 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 298 if (kvm_enabled()) { 299 kvmppc_icbi_range(cpu, pdst, len); 300 } else { 301 tb_flush(CPU(cpu)); 302 } 303 } 304 305 unmap_out: 306 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 307 return ret; 308 } 309 310 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 311 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 312 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 313 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 314 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 315 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 316 317 static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) 318 { 319 CPUState *cs = CPU(cpu); 320 CPUPPCState *env = &cpu->env; 321 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 322 uint16_t size; 323 uint8_t tmp; 324 325 if (vpa == 0) { 326 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 327 return H_HARDWARE; 328 } 329 330 if (vpa % env->dcache_line_size) { 331 return H_PARAMETER; 332 } 333 /* FIXME: bounds check the address */ 334 335 size = lduw_be_phys(cs->as, vpa + 0x4); 336 337 if (size < VPA_MIN_SIZE) { 338 return H_PARAMETER; 339 } 340 341 /* VPA is not allowed to cross a page boundary */ 342 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 343 return H_PARAMETER; 344 } 345 346 spapr_cpu->vpa_addr = vpa; 347 348 tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET); 349 tmp |= VPA_SHARED_PROC_VAL; 350 stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 351 352 return H_SUCCESS; 353 } 354 355 static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) 356 { 357 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 358 359 if (spapr_cpu->slb_shadow_addr) { 360 return H_RESOURCE; 361 } 362 363 if (spapr_cpu->dtl_addr) { 364 return H_RESOURCE; 365 } 366 367 spapr_cpu->vpa_addr = 0; 368 return H_SUCCESS; 369 } 370 371 static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 372 { 373 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 374 uint32_t size; 375 376 if (addr == 0) { 377 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 378 return H_HARDWARE; 379 } 380 381 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 382 if (size < 0x8) { 383 return H_PARAMETER; 384 } 385 386 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 387 return H_PARAMETER; 388 } 389 390 if (!spapr_cpu->vpa_addr) { 391 return H_RESOURCE; 392 } 393 394 spapr_cpu->slb_shadow_addr = addr; 395 spapr_cpu->slb_shadow_size = size; 396 397 return H_SUCCESS; 398 } 399 400 static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 401 { 402 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 403 404 spapr_cpu->slb_shadow_addr = 0; 405 spapr_cpu->slb_shadow_size = 0; 406 return H_SUCCESS; 407 } 408 409 static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) 410 { 411 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 412 uint32_t size; 413 414 if (addr == 0) { 415 hcall_dprintf("Can't cope with DTL at logical 0\n"); 416 return H_HARDWARE; 417 } 418 419 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 420 421 if (size < 48) { 422 return H_PARAMETER; 423 } 424 425 if (!spapr_cpu->vpa_addr) { 426 return H_RESOURCE; 427 } 428 429 spapr_cpu->dtl_addr = addr; 430 spapr_cpu->dtl_size = size; 431 432 return H_SUCCESS; 433 } 434 435 static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) 436 { 437 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 438 439 spapr_cpu->dtl_addr = 0; 440 spapr_cpu->dtl_size = 0; 441 442 return H_SUCCESS; 443 } 444 445 static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr, 446 target_ulong opcode, target_ulong *args) 447 { 448 target_ulong flags = args[0]; 449 target_ulong procno = args[1]; 450 target_ulong vpa = args[2]; 451 target_ulong ret = H_PARAMETER; 452 PowerPCCPU *tcpu; 453 454 tcpu = spapr_find_cpu(procno); 455 if (!tcpu) { 456 return H_PARAMETER; 457 } 458 459 switch (flags) { 460 case FLAGS_REGISTER_VPA: 461 ret = register_vpa(tcpu, vpa); 462 break; 463 464 case FLAGS_DEREGISTER_VPA: 465 ret = deregister_vpa(tcpu, vpa); 466 break; 467 468 case FLAGS_REGISTER_SLBSHADOW: 469 ret = register_slb_shadow(tcpu, vpa); 470 break; 471 472 case FLAGS_DEREGISTER_SLBSHADOW: 473 ret = deregister_slb_shadow(tcpu, vpa); 474 break; 475 476 case FLAGS_REGISTER_DTL: 477 ret = register_dtl(tcpu, vpa); 478 break; 479 480 case FLAGS_DEREGISTER_DTL: 481 ret = deregister_dtl(tcpu, vpa); 482 break; 483 } 484 485 return ret; 486 } 487 488 static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, 489 target_ulong opcode, target_ulong *args) 490 { 491 CPUPPCState *env = &cpu->env; 492 CPUState *cs = CPU(cpu); 493 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 494 495 env->msr |= (1ULL << MSR_EE); 496 hreg_compute_hflags(env); 497 498 if (spapr_cpu->prod) { 499 spapr_cpu->prod = false; 500 return H_SUCCESS; 501 } 502 503 if (!cpu_has_work(cs)) { 504 cs->halted = 1; 505 cs->exception_index = EXCP_HLT; 506 cs->exit_request = 1; 507 } 508 509 return H_SUCCESS; 510 } 511 512 /* 513 * Confer to self, aka join. Cede could use the same pattern as well, if 514 * EXCP_HLT can be changed to ECXP_HALTED. 515 */ 516 static target_ulong h_confer_self(PowerPCCPU *cpu) 517 { 518 CPUState *cs = CPU(cpu); 519 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 520 521 if (spapr_cpu->prod) { 522 spapr_cpu->prod = false; 523 return H_SUCCESS; 524 } 525 cs->halted = 1; 526 cs->exception_index = EXCP_HALTED; 527 cs->exit_request = 1; 528 529 return H_SUCCESS; 530 } 531 532 static target_ulong h_join(PowerPCCPU *cpu, SpaprMachineState *spapr, 533 target_ulong opcode, target_ulong *args) 534 { 535 CPUPPCState *env = &cpu->env; 536 CPUState *cs; 537 bool last_unjoined = true; 538 539 if (env->msr & (1ULL << MSR_EE)) { 540 return H_BAD_MODE; 541 } 542 543 /* 544 * Must not join the last CPU running. Interestingly, no such restriction 545 * for H_CONFER-to-self, but that is probably not intended to be used 546 * when H_JOIN is available. 547 */ 548 CPU_FOREACH(cs) { 549 PowerPCCPU *c = POWERPC_CPU(cs); 550 CPUPPCState *e = &c->env; 551 if (c == cpu) { 552 continue; 553 } 554 555 /* Don't have a way to indicate joined, so use halted && MSR[EE]=0 */ 556 if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { 557 last_unjoined = false; 558 break; 559 } 560 } 561 if (last_unjoined) { 562 return H_CONTINUE; 563 } 564 565 return h_confer_self(cpu); 566 } 567 568 static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr, 569 target_ulong opcode, target_ulong *args) 570 { 571 target_long target = args[0]; 572 uint32_t dispatch = args[1]; 573 CPUState *cs = CPU(cpu); 574 SpaprCpuState *spapr_cpu; 575 576 /* 577 * -1 means confer to all other CPUs without dispatch counter check, 578 * otherwise it's a targeted confer. 579 */ 580 if (target != -1) { 581 PowerPCCPU *target_cpu = spapr_find_cpu(target); 582 uint32_t target_dispatch; 583 584 if (!target_cpu) { 585 return H_PARAMETER; 586 } 587 588 /* 589 * target == self is a special case, we wait until prodded, without 590 * dispatch counter check. 591 */ 592 if (cpu == target_cpu) { 593 return h_confer_self(cpu); 594 } 595 596 spapr_cpu = spapr_cpu_state(target_cpu); 597 if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) { 598 return H_SUCCESS; 599 } 600 601 target_dispatch = ldl_be_phys(cs->as, 602 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 603 if (target_dispatch != dispatch) { 604 return H_SUCCESS; 605 } 606 607 /* 608 * The targeted confer does not do anything special beyond yielding 609 * the current vCPU, but even this should be better than nothing. 610 * At least for single-threaded tcg, it gives the target a chance to 611 * run before we run again. Multi-threaded tcg does not really do 612 * anything with EXCP_YIELD yet. 613 */ 614 } 615 616 cs->exception_index = EXCP_YIELD; 617 cs->exit_request = 1; 618 cpu_loop_exit(cs); 619 620 return H_SUCCESS; 621 } 622 623 static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr, 624 target_ulong opcode, target_ulong *args) 625 { 626 target_long target = args[0]; 627 PowerPCCPU *tcpu; 628 CPUState *cs; 629 SpaprCpuState *spapr_cpu; 630 631 tcpu = spapr_find_cpu(target); 632 cs = CPU(tcpu); 633 if (!cs) { 634 return H_PARAMETER; 635 } 636 637 spapr_cpu = spapr_cpu_state(tcpu); 638 spapr_cpu->prod = true; 639 cs->halted = 0; 640 qemu_cpu_kick(cs); 641 642 return H_SUCCESS; 643 } 644 645 static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, 646 target_ulong opcode, target_ulong *args) 647 { 648 target_ulong rtas_r3 = args[0]; 649 uint32_t token = rtas_ld(rtas_r3, 0); 650 uint32_t nargs = rtas_ld(rtas_r3, 1); 651 uint32_t nret = rtas_ld(rtas_r3, 2); 652 653 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 654 nret, rtas_r3 + 12 + 4*nargs); 655 } 656 657 static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr, 658 target_ulong opcode, target_ulong *args) 659 { 660 CPUState *cs = CPU(cpu); 661 target_ulong size = args[0]; 662 target_ulong addr = args[1]; 663 664 switch (size) { 665 case 1: 666 args[0] = ldub_phys(cs->as, addr); 667 return H_SUCCESS; 668 case 2: 669 args[0] = lduw_phys(cs->as, addr); 670 return H_SUCCESS; 671 case 4: 672 args[0] = ldl_phys(cs->as, addr); 673 return H_SUCCESS; 674 case 8: 675 args[0] = ldq_phys(cs->as, addr); 676 return H_SUCCESS; 677 } 678 return H_PARAMETER; 679 } 680 681 static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr, 682 target_ulong opcode, target_ulong *args) 683 { 684 CPUState *cs = CPU(cpu); 685 686 target_ulong size = args[0]; 687 target_ulong addr = args[1]; 688 target_ulong val = args[2]; 689 690 switch (size) { 691 case 1: 692 stb_phys(cs->as, addr, val); 693 return H_SUCCESS; 694 case 2: 695 stw_phys(cs->as, addr, val); 696 return H_SUCCESS; 697 case 4: 698 stl_phys(cs->as, addr, val); 699 return H_SUCCESS; 700 case 8: 701 stq_phys(cs->as, addr, val); 702 return H_SUCCESS; 703 } 704 return H_PARAMETER; 705 } 706 707 static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr, 708 target_ulong opcode, target_ulong *args) 709 { 710 CPUState *cs = CPU(cpu); 711 712 target_ulong dst = args[0]; /* Destination address */ 713 target_ulong src = args[1]; /* Source address */ 714 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 715 target_ulong count = args[3]; /* Element count */ 716 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 717 uint64_t tmp; 718 unsigned int mask = (1 << esize) - 1; 719 int step = 1 << esize; 720 721 if (count > 0x80000000) { 722 return H_PARAMETER; 723 } 724 725 if ((dst & mask) || (src & mask) || (op > 1)) { 726 return H_PARAMETER; 727 } 728 729 if (dst >= src && dst < (src + (count << esize))) { 730 dst = dst + ((count - 1) << esize); 731 src = src + ((count - 1) << esize); 732 step = -step; 733 } 734 735 while (count--) { 736 switch (esize) { 737 case 0: 738 tmp = ldub_phys(cs->as, src); 739 break; 740 case 1: 741 tmp = lduw_phys(cs->as, src); 742 break; 743 case 2: 744 tmp = ldl_phys(cs->as, src); 745 break; 746 case 3: 747 tmp = ldq_phys(cs->as, src); 748 break; 749 default: 750 return H_PARAMETER; 751 } 752 if (op == 1) { 753 tmp = ~tmp; 754 } 755 switch (esize) { 756 case 0: 757 stb_phys(cs->as, dst, tmp); 758 break; 759 case 1: 760 stw_phys(cs->as, dst, tmp); 761 break; 762 case 2: 763 stl_phys(cs->as, dst, tmp); 764 break; 765 case 3: 766 stq_phys(cs->as, dst, tmp); 767 break; 768 } 769 dst = dst + step; 770 src = src + step; 771 } 772 773 return H_SUCCESS; 774 } 775 776 static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr, 777 target_ulong opcode, target_ulong *args) 778 { 779 /* Nothing to do on emulation, KVM will trap this in the kernel */ 780 return H_SUCCESS; 781 } 782 783 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, 784 target_ulong opcode, target_ulong *args) 785 { 786 /* Nothing to do on emulation, KVM will trap this in the kernel */ 787 return H_SUCCESS; 788 } 789 790 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 791 SpaprMachineState *spapr, 792 target_ulong mflags, 793 target_ulong value1, 794 target_ulong value2) 795 { 796 if (value1) { 797 return H_P3; 798 } 799 if (value2) { 800 return H_P4; 801 } 802 803 switch (mflags) { 804 case H_SET_MODE_ENDIAN_BIG: 805 spapr_set_all_lpcrs(0, LPCR_ILE); 806 spapr_pci_switch_vga(spapr, true); 807 return H_SUCCESS; 808 809 case H_SET_MODE_ENDIAN_LITTLE: 810 spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); 811 spapr_pci_switch_vga(spapr, false); 812 return H_SUCCESS; 813 } 814 815 return H_UNSUPPORTED_FLAG; 816 } 817 818 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 819 target_ulong mflags, 820 target_ulong value1, 821 target_ulong value2) 822 { 823 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 824 825 if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 826 return H_P2; 827 } 828 if (value1) { 829 return H_P3; 830 } 831 if (value2) { 832 return H_P4; 833 } 834 835 if (mflags == 1) { 836 /* AIL=1 is reserved in POWER8/POWER9/POWER10 */ 837 return H_UNSUPPORTED_FLAG; 838 } 839 840 if (mflags == 2 && (pcc->insns_flags2 & PPC2_ISA310)) { 841 /* AIL=2 is reserved in POWER10 (ISA v3.1) */ 842 return H_UNSUPPORTED_FLAG; 843 } 844 845 spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); 846 847 return H_SUCCESS; 848 } 849 850 static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, 851 target_ulong opcode, target_ulong *args) 852 { 853 target_ulong resource = args[1]; 854 target_ulong ret = H_P2; 855 856 switch (resource) { 857 case H_SET_MODE_RESOURCE_LE: 858 ret = h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[3]); 859 break; 860 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 861 ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 862 args[2], args[3]); 863 break; 864 } 865 866 return ret; 867 } 868 869 static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, 870 target_ulong opcode, target_ulong *args) 871 { 872 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 873 opcode, " (H_CLEAN_SLB)"); 874 return H_FUNCTION; 875 } 876 877 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr, 878 target_ulong opcode, target_ulong *args) 879 { 880 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 881 opcode, " (H_INVALIDATE_PID)"); 882 return H_FUNCTION; 883 } 884 885 static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, 886 uint64_t patbe_old, uint64_t patbe_new) 887 { 888 /* 889 * We have 4 Options: 890 * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 891 * HASH->RADIX : Free HPT 892 * RADIX->HASH : Allocate HPT 893 * NOTHING->HASH : Allocate HPT 894 * Note: NOTHING implies the case where we said the guest could choose 895 * later and so assumed radix and now it's called H_REG_PROC_TBL 896 */ 897 898 if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) { 899 /* We assume RADIX, so this catches all the "Do Nothing" cases */ 900 } else if (!(patbe_old & PATE1_GR)) { 901 /* HASH->RADIX : Free HPT */ 902 spapr_free_hpt(spapr); 903 } else if (!(patbe_new & PATE1_GR)) { 904 /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 905 spapr_setup_hpt(spapr); 906 } 907 return; 908 } 909 910 #define FLAGS_MASK 0x01FULL 911 #define FLAG_MODIFY 0x10 912 #define FLAG_REGISTER 0x08 913 #define FLAG_RADIX 0x04 914 #define FLAG_HASH_PROC_TBL 0x02 915 #define FLAG_GTSE 0x01 916 917 static target_ulong h_register_process_table(PowerPCCPU *cpu, 918 SpaprMachineState *spapr, 919 target_ulong opcode, 920 target_ulong *args) 921 { 922 target_ulong flags = args[0]; 923 target_ulong proc_tbl = args[1]; 924 target_ulong page_size = args[2]; 925 target_ulong table_size = args[3]; 926 target_ulong update_lpcr = 0; 927 uint64_t cproc; 928 929 if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 930 return H_PARAMETER; 931 } 932 if (flags & FLAG_MODIFY) { 933 if (flags & FLAG_REGISTER) { 934 if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 935 if (proc_tbl & 0xfff || proc_tbl >> 60) { 936 return H_P2; 937 } else if (page_size) { 938 return H_P3; 939 } else if (table_size > 24) { 940 return H_P4; 941 } 942 cproc = PATE1_GR | proc_tbl | table_size; 943 } else { /* Register new HPT process table */ 944 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 945 /* TODO - Not Supported */ 946 /* Technically caused by flag bits => H_PARAMETER */ 947 return H_PARAMETER; 948 } else { /* Hash with SLB */ 949 if (proc_tbl >> 38) { 950 return H_P2; 951 } else if (page_size & ~0x7) { 952 return H_P3; 953 } else if (table_size > 24) { 954 return H_P4; 955 } 956 } 957 cproc = (proc_tbl << 25) | page_size << 5 | table_size; 958 } 959 960 } else { /* Deregister current process table */ 961 /* 962 * Set to benign value: (current GR) | 0. This allows 963 * deregistration in KVM to succeed even if the radix bit 964 * in flags doesn't match the radix bit in the old PATE. 965 */ 966 cproc = spapr->patb_entry & PATE1_GR; 967 } 968 } else { /* Maintain current registration */ 969 if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) { 970 /* Technically caused by flag bits => H_PARAMETER */ 971 return H_PARAMETER; /* Existing Process Table Mismatch */ 972 } 973 cproc = spapr->patb_entry; 974 } 975 976 /* Check if we need to setup OR free the hpt */ 977 spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 978 979 spapr->patb_entry = cproc; /* Save new process table */ 980 981 /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ 982 if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */ 983 update_lpcr |= (LPCR_UPRT | LPCR_HR); 984 else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ 985 update_lpcr |= LPCR_UPRT; 986 if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ 987 update_lpcr |= LPCR_GTSE; 988 989 spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); 990 991 if (kvm_enabled()) { 992 return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 993 flags & FLAG_GTSE, cproc); 994 } 995 return H_SUCCESS; 996 } 997 998 #define H_SIGNAL_SYS_RESET_ALL -1 999 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 1000 1001 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1002 SpaprMachineState *spapr, 1003 target_ulong opcode, target_ulong *args) 1004 { 1005 target_long target = args[0]; 1006 CPUState *cs; 1007 1008 if (target < 0) { 1009 /* Broadcast */ 1010 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1011 return H_PARAMETER; 1012 } 1013 1014 CPU_FOREACH(cs) { 1015 PowerPCCPU *c = POWERPC_CPU(cs); 1016 1017 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1018 if (c == cpu) { 1019 continue; 1020 } 1021 } 1022 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1023 } 1024 return H_SUCCESS; 1025 1026 } else { 1027 /* Unicast */ 1028 cs = CPU(spapr_find_cpu(target)); 1029 if (cs) { 1030 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1031 return H_SUCCESS; 1032 } 1033 return H_PARAMETER; 1034 } 1035 } 1036 1037 /* Returns either a logical PVR or zero if none was found */ 1038 static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32_t max_compat, 1039 target_ulong *addr, bool *raw_mode_supported) 1040 { 1041 bool explicit_match = false; /* Matched the CPU's real PVR */ 1042 uint32_t best_compat = 0; 1043 int i; 1044 1045 /* 1046 * We scan the supplied table of PVRs looking for two things 1047 * 1. Is our real CPU PVR in the list? 1048 * 2. What's the "best" listed logical PVR 1049 */ 1050 for (i = 0; i < 512; ++i) { 1051 uint32_t pvr, pvr_mask; 1052 1053 pvr_mask = ldl_be_phys(&address_space_memory, *addr); 1054 pvr = ldl_be_phys(&address_space_memory, *addr + 4); 1055 *addr += 8; 1056 1057 if (~pvr_mask & pvr) { 1058 break; /* Terminator record */ 1059 } 1060 1061 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1062 explicit_match = true; 1063 } else { 1064 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1065 best_compat = pvr; 1066 } 1067 } 1068 } 1069 1070 *raw_mode_supported = explicit_match; 1071 1072 /* Parsing finished */ 1073 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 1074 1075 return best_compat; 1076 } 1077 1078 static 1079 target_ulong do_client_architecture_support(PowerPCCPU *cpu, 1080 SpaprMachineState *spapr, 1081 target_ulong vec, 1082 target_ulong fdt_bufsize) 1083 { 1084 target_ulong ov_table; /* Working address in data buffer */ 1085 uint32_t cas_pvr; 1086 SpaprOptionVector *ov1_guest, *ov5_guest; 1087 bool guest_radix; 1088 bool raw_mode_supported = false; 1089 bool guest_xive; 1090 CPUState *cs; 1091 void *fdt; 1092 uint32_t max_compat = spapr->max_compat_pvr; 1093 1094 /* CAS is supposed to be called early when only the boot vCPU is active. */ 1095 CPU_FOREACH(cs) { 1096 if (cs == CPU(cpu)) { 1097 continue; 1098 } 1099 if (!cs->halted) { 1100 warn_report("guest has multiple active vCPUs at CAS, which is not allowed"); 1101 return H_MULTI_THREADS_ACTIVE; 1102 } 1103 } 1104 1105 cas_pvr = cas_check_pvr(cpu, max_compat, &vec, &raw_mode_supported); 1106 if (!cas_pvr && (!raw_mode_supported || max_compat)) { 1107 /* 1108 * We couldn't find a suitable compatibility mode, and either 1109 * the guest doesn't support "raw" mode for this CPU, or "raw" 1110 * mode is disabled because a maximum compat mode is set. 1111 */ 1112 error_report("Couldn't negotiate a suitable PVR during CAS"); 1113 return H_HARDWARE; 1114 } 1115 1116 /* Update CPUs */ 1117 if (cpu->compat_pvr != cas_pvr) { 1118 Error *local_err = NULL; 1119 1120 if (ppc_set_compat_all(cas_pvr, &local_err) < 0) { 1121 /* We fail to set compat mode (likely because running with KVM PR), 1122 * but maybe we can fallback to raw mode if the guest supports it. 1123 */ 1124 if (!raw_mode_supported) { 1125 error_report_err(local_err); 1126 return H_HARDWARE; 1127 } 1128 error_free(local_err); 1129 } 1130 } 1131 1132 /* For the future use: here @ov_table points to the first option vector */ 1133 ov_table = vec; 1134 1135 ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1136 if (!ov1_guest) { 1137 warn_report("guest didn't provide option vector 1"); 1138 return H_PARAMETER; 1139 } 1140 ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1141 if (!ov5_guest) { 1142 spapr_ovec_cleanup(ov1_guest); 1143 warn_report("guest didn't provide option vector 5"); 1144 return H_PARAMETER; 1145 } 1146 if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 1147 error_report("guest requested hash and radix MMU, which is invalid."); 1148 exit(EXIT_FAILURE); 1149 } 1150 if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { 1151 error_report("guest requested an invalid interrupt mode"); 1152 exit(EXIT_FAILURE); 1153 } 1154 1155 guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 1156 1157 guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); 1158 1159 /* 1160 * HPT resizing is a bit of a special case, because when enabled 1161 * we assume an HPT guest will support it until it says it 1162 * doesn't, instead of assuming it won't support it until it says 1163 * it does. Strictly speaking that approach could break for 1164 * guests which don't make a CAS call, but those are so old we 1165 * don't care about them. Without that assumption we'd have to 1166 * make at least a temporary allocation of an HPT sized for max 1167 * memory, which could be impossibly difficult under KVM HV if 1168 * maxram is large. 1169 */ 1170 if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 1171 int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1172 1173 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 1174 error_report( 1175 "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 1176 exit(1); 1177 } 1178 1179 if (spapr->htab_shift < maxshift) { 1180 /* Guest doesn't know about HPT resizing, so we 1181 * pre-emptively resize for the maximum permitted RAM. At 1182 * the point this is called, nothing should have been 1183 * entered into the existing HPT */ 1184 spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 1185 push_sregs_to_kvm_pr(spapr); 1186 } 1187 } 1188 1189 /* NOTE: there are actually a number of ov5 bits where input from the 1190 * guest is always zero, and the platform/QEMU enables them independently 1191 * of guest input. To model these properly we'd want some sort of mask, 1192 * but since they only currently apply to memory migration as defined 1193 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 1194 * to worry about this for now. 1195 */ 1196 1197 /* full range of negotiated ov5 capabilities */ 1198 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1199 spapr_ovec_cleanup(ov5_guest); 1200 1201 spapr_check_mmu_mode(guest_radix); 1202 1203 spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00); 1204 spapr_ovec_cleanup(ov1_guest); 1205 1206 /* 1207 * Ensure the guest asks for an interrupt mode we support; 1208 * otherwise terminate the boot. 1209 */ 1210 if (guest_xive) { 1211 if (!spapr->irq->xive) { 1212 error_report( 1213 "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property"); 1214 exit(EXIT_FAILURE); 1215 } 1216 } else { 1217 if (!spapr->irq->xics) { 1218 error_report( 1219 "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual"); 1220 exit(EXIT_FAILURE); 1221 } 1222 } 1223 1224 spapr_irq_update_active_intc(spapr); 1225 1226 /* 1227 * Process all pending hot-plug/unplug requests now. An updated full 1228 * rendered FDT will be returned to the guest. 1229 */ 1230 spapr_drc_reset_all(spapr); 1231 spapr_clear_pending_hotplug_events(spapr); 1232 1233 /* 1234 * If spapr_machine_reset() did not set up a HPT but one is necessary 1235 * (because the guest isn't going to use radix) then set it up here. 1236 */ 1237 if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { 1238 /* legacy hash or new hash: */ 1239 spapr_setup_hpt(spapr); 1240 } 1241 1242 fdt = spapr_build_fdt(spapr, false, fdt_bufsize); 1243 1244 g_free(spapr->fdt_blob); 1245 spapr->fdt_size = fdt_totalsize(fdt); 1246 spapr->fdt_initial_size = spapr->fdt_size; 1247 spapr->fdt_blob = fdt; 1248 1249 return H_SUCCESS; 1250 } 1251 1252 static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1253 SpaprMachineState *spapr, 1254 target_ulong opcode, 1255 target_ulong *args) 1256 { 1257 target_ulong vec = ppc64_phys_to_real(args[0]); 1258 target_ulong fdt_buf = args[1]; 1259 target_ulong fdt_bufsize = args[2]; 1260 target_ulong ret; 1261 SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 1262 1263 if (fdt_bufsize < sizeof(hdr)) { 1264 error_report("SLOF provided insufficient CAS buffer " 1265 TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr)); 1266 exit(EXIT_FAILURE); 1267 } 1268 1269 fdt_bufsize -= sizeof(hdr); 1270 1271 ret = do_client_architecture_support(cpu, spapr, vec, fdt_bufsize); 1272 if (ret == H_SUCCESS) { 1273 _FDT((fdt_pack(spapr->fdt_blob))); 1274 spapr->fdt_size = fdt_totalsize(spapr->fdt_blob); 1275 spapr->fdt_initial_size = spapr->fdt_size; 1276 1277 cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr)); 1278 cpu_physical_memory_write(fdt_buf + sizeof(hdr), spapr->fdt_blob, 1279 spapr->fdt_size); 1280 trace_spapr_cas_continue(spapr->fdt_size + sizeof(hdr)); 1281 } 1282 1283 return ret; 1284 } 1285 1286 static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1287 SpaprMachineState *spapr, 1288 target_ulong opcode, 1289 target_ulong *args) 1290 { 1291 uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1292 ~H_CPU_CHAR_THR_RECONF_TRIG; 1293 uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1294 uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1295 uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1296 uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 1297 uint8_t count_cache_flush_assist = spapr_get_cap(spapr, 1298 SPAPR_CAP_CCF_ASSIST); 1299 1300 switch (safe_cache) { 1301 case SPAPR_CAP_WORKAROUND: 1302 characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1303 characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1304 characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1305 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1306 break; 1307 case SPAPR_CAP_FIXED: 1308 break; 1309 default: /* broken */ 1310 assert(safe_cache == SPAPR_CAP_BROKEN); 1311 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1312 break; 1313 } 1314 1315 switch (safe_bounds_check) { 1316 case SPAPR_CAP_WORKAROUND: 1317 characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1318 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1319 break; 1320 case SPAPR_CAP_FIXED: 1321 break; 1322 default: /* broken */ 1323 assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1324 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1325 break; 1326 } 1327 1328 switch (safe_indirect_branch) { 1329 case SPAPR_CAP_FIXED_NA: 1330 break; 1331 case SPAPR_CAP_FIXED_CCD: 1332 characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; 1333 break; 1334 case SPAPR_CAP_FIXED_IBS: 1335 characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1336 break; 1337 case SPAPR_CAP_WORKAROUND: 1338 behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE; 1339 if (count_cache_flush_assist) { 1340 characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST; 1341 } 1342 break; 1343 default: /* broken */ 1344 assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1345 break; 1346 } 1347 1348 args[0] = characteristics; 1349 args[1] = behaviour; 1350 return H_SUCCESS; 1351 } 1352 1353 static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, 1354 target_ulong opcode, target_ulong *args) 1355 { 1356 target_ulong dt = ppc64_phys_to_real(args[0]); 1357 struct fdt_header hdr = { 0 }; 1358 unsigned cb; 1359 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1360 void *fdt; 1361 1362 cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); 1363 cb = fdt32_to_cpu(hdr.totalsize); 1364 1365 if (!smc->update_dt_enabled) { 1366 return H_SUCCESS; 1367 } 1368 1369 /* Check that the fdt did not grow out of proportion */ 1370 if (cb > spapr->fdt_initial_size * 2) { 1371 trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, 1372 fdt32_to_cpu(hdr.magic)); 1373 return H_PARAMETER; 1374 } 1375 1376 fdt = g_malloc0(cb); 1377 cpu_physical_memory_read(dt, fdt, cb); 1378 1379 /* Check the fdt consistency */ 1380 if (fdt_check_full(fdt, cb)) { 1381 trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, 1382 fdt32_to_cpu(hdr.magic)); 1383 return H_PARAMETER; 1384 } 1385 1386 g_free(spapr->fdt_blob); 1387 spapr->fdt_size = cb; 1388 spapr->fdt_blob = fdt; 1389 trace_spapr_update_dt(cb); 1390 1391 return H_SUCCESS; 1392 } 1393 1394 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 1395 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 1396 static spapr_hcall_fn svm_hypercall_table[(SVM_HCALL_MAX - SVM_HCALL_BASE) / 4 + 1]; 1397 1398 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 1399 { 1400 spapr_hcall_fn *slot; 1401 1402 if (opcode <= MAX_HCALL_OPCODE) { 1403 assert((opcode & 0x3) == 0); 1404 1405 slot = &papr_hypercall_table[opcode / 4]; 1406 } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { 1407 /* we only have SVM-related hcall numbers assigned in multiples of 4 */ 1408 assert((opcode & 0x3) == 0); 1409 1410 slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1411 } else { 1412 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1413 1414 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1415 } 1416 1417 assert(!(*slot)); 1418 *slot = fn; 1419 } 1420 1421 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 1422 target_ulong *args) 1423 { 1424 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1425 1426 if ((opcode <= MAX_HCALL_OPCODE) 1427 && ((opcode & 0x3) == 0)) { 1428 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 1429 1430 if (fn) { 1431 return fn(cpu, spapr, opcode, args); 1432 } 1433 } else if ((opcode >= SVM_HCALL_BASE) && 1434 (opcode <= SVM_HCALL_MAX)) { 1435 spapr_hcall_fn fn = svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1436 1437 if (fn) { 1438 return fn(cpu, spapr, opcode, args); 1439 } 1440 } else if ((opcode >= KVMPPC_HCALL_BASE) && 1441 (opcode <= KVMPPC_HCALL_MAX)) { 1442 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1443 1444 if (fn) { 1445 return fn(cpu, spapr, opcode, args); 1446 } 1447 } 1448 1449 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1450 opcode); 1451 return H_FUNCTION; 1452 } 1453 1454 #ifndef CONFIG_TCG 1455 static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr, 1456 target_ulong opcode, target_ulong *args) 1457 { 1458 g_assert_not_reached(); 1459 } 1460 1461 static void hypercall_register_softmmu(void) 1462 { 1463 /* hcall-pft */ 1464 spapr_register_hypercall(H_ENTER, h_softmmu); 1465 spapr_register_hypercall(H_REMOVE, h_softmmu); 1466 spapr_register_hypercall(H_PROTECT, h_softmmu); 1467 spapr_register_hypercall(H_READ, h_softmmu); 1468 1469 /* hcall-bulk */ 1470 spapr_register_hypercall(H_BULK_REMOVE, h_softmmu); 1471 } 1472 #else 1473 static void hypercall_register_softmmu(void) 1474 { 1475 /* DO NOTHING */ 1476 } 1477 #endif 1478 1479 static void hypercall_register_types(void) 1480 { 1481 hypercall_register_softmmu(); 1482 1483 /* hcall-hpt-resize */ 1484 spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 1485 spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 1486 1487 /* hcall-splpar */ 1488 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 1489 spapr_register_hypercall(H_CEDE, h_cede); 1490 spapr_register_hypercall(H_CONFER, h_confer); 1491 spapr_register_hypercall(H_PROD, h_prod); 1492 1493 /* hcall-join */ 1494 spapr_register_hypercall(H_JOIN, h_join); 1495 1496 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 1497 1498 /* processor register resource access h-calls */ 1499 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1500 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1501 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 1502 spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1503 spapr_register_hypercall(H_SET_MODE, h_set_mode); 1504 1505 /* In Memory Table MMU h-calls */ 1506 spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1507 spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1508 spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1509 1510 /* hcall-get-cpu-characteristics */ 1511 spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 1512 h_get_cpu_characteristics); 1513 1514 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 1515 * here between the "CI" and the "CACHE" variants, they will use whatever 1516 * mapping attributes qemu is using. When using KVM, the kernel will 1517 * enforce the attributes more strongly 1518 */ 1519 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 1520 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 1521 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 1522 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 1523 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 1524 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 1525 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 1526 1527 /* qemu/KVM-PPC specific hcalls */ 1528 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 1529 1530 /* ibm,client-architecture-support support */ 1531 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1532 1533 spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); 1534 } 1535 1536 type_init(hypercall_register_types) 1537