1 #include "qemu/osdep.h" 2 #include "qapi/error.h" 3 #include "sysemu/hw_accel.h" 4 #include "sysemu/sysemu.h" 5 #include "qemu/log.h" 6 #include "qemu/error-report.h" 7 #include "cpu.h" 8 #include "exec/exec-all.h" 9 #include "helper_regs.h" 10 #include "hw/ppc/spapr.h" 11 #include "mmu-hash64.h" 12 #include "cpu-models.h" 13 #include "trace.h" 14 #include "kvm_ppc.h" 15 #include "hw/ppc/spapr_ovec.h" 16 #include "mmu-book3s-v3.h" 17 18 struct SPRSyncState { 19 int spr; 20 target_ulong value; 21 target_ulong mask; 22 }; 23 24 static void do_spr_sync(CPUState *cs, run_on_cpu_data arg) 25 { 26 struct SPRSyncState *s = arg.host_ptr; 27 PowerPCCPU *cpu = POWERPC_CPU(cs); 28 CPUPPCState *env = &cpu->env; 29 30 cpu_synchronize_state(cs); 31 env->spr[s->spr] &= ~s->mask; 32 env->spr[s->spr] |= s->value; 33 } 34 35 static void set_spr(CPUState *cs, int spr, target_ulong value, 36 target_ulong mask) 37 { 38 struct SPRSyncState s = { 39 .spr = spr, 40 .value = value, 41 .mask = mask 42 }; 43 run_on_cpu(cs, do_spr_sync, RUN_ON_CPU_HOST_PTR(&s)); 44 } 45 46 static bool has_spr(PowerPCCPU *cpu, int spr) 47 { 48 /* We can test whether the SPR is defined by checking for a valid name */ 49 return cpu->env.spr_cb[spr].name != NULL; 50 } 51 52 static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) 53 { 54 /* 55 * hash value/pteg group index is normalized by HPT mask 56 */ 57 if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { 58 return false; 59 } 60 return true; 61 } 62 63 static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr) 64 { 65 MachineState *machine = MACHINE(spapr); 66 MemoryHotplugState *hpms = &spapr->hotplug_memory; 67 68 if (addr < machine->ram_size) { 69 return true; 70 } 71 if ((addr >= hpms->base) 72 && ((addr - hpms->base) < memory_region_size(&hpms->mr))) { 73 return true; 74 } 75 76 return false; 77 } 78 79 static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, 80 target_ulong opcode, target_ulong *args) 81 { 82 target_ulong flags = args[0]; 83 target_ulong ptex = args[1]; 84 target_ulong pteh = args[2]; 85 target_ulong ptel = args[3]; 86 unsigned apshift; 87 target_ulong raddr; 88 target_ulong slot; 89 const ppc_hash_pte64_t *hptes; 90 91 apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); 92 if (!apshift) { 93 /* Bad page size encoding */ 94 return H_PARAMETER; 95 } 96 97 raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); 98 99 if (is_ram_address(spapr, raddr)) { 100 /* Regular RAM - should have WIMG=0010 */ 101 if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 102 return H_PARAMETER; 103 } 104 } else { 105 target_ulong wimg_flags; 106 /* Looks like an IO address */ 107 /* FIXME: What WIMG combinations could be sensible for IO? 108 * For now we allow WIMG=010x, but are there others? */ 109 /* FIXME: Should we check against registered IO addresses? */ 110 wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); 111 112 if (wimg_flags != HPTE64_R_I && 113 wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { 114 return H_PARAMETER; 115 } 116 } 117 118 pteh &= ~0x60ULL; 119 120 if (!valid_ptex(cpu, ptex)) { 121 return H_PARAMETER; 122 } 123 124 slot = ptex & 7ULL; 125 ptex = ptex & ~7ULL; 126 127 if (likely((flags & H_EXACT) == 0)) { 128 hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 129 for (slot = 0; slot < 8; slot++) { 130 if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { 131 break; 132 } 133 } 134 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 135 if (slot == 8) { 136 return H_PTEG_FULL; 137 } 138 } else { 139 hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); 140 if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { 141 ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); 142 return H_PTEG_FULL; 143 } 144 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 145 } 146 147 ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); 148 149 args[0] = ptex + slot; 150 return H_SUCCESS; 151 } 152 153 typedef enum { 154 REMOVE_SUCCESS = 0, 155 REMOVE_NOT_FOUND = 1, 156 REMOVE_PARM = 2, 157 REMOVE_HW = 3, 158 } RemoveResult; 159 160 static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, 161 target_ulong avpn, 162 target_ulong flags, 163 target_ulong *vp, target_ulong *rp) 164 { 165 const ppc_hash_pte64_t *hptes; 166 target_ulong v, r; 167 168 if (!valid_ptex(cpu, ptex)) { 169 return REMOVE_PARM; 170 } 171 172 hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 173 v = ppc_hash64_hpte0(cpu, hptes, 0); 174 r = ppc_hash64_hpte1(cpu, hptes, 0); 175 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 176 177 if ((v & HPTE64_V_VALID) == 0 || 178 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 179 ((flags & H_ANDCOND) && (v & avpn) != 0)) { 180 return REMOVE_NOT_FOUND; 181 } 182 *vp = v; 183 *rp = r; 184 ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); 185 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 186 return REMOVE_SUCCESS; 187 } 188 189 static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 190 target_ulong opcode, target_ulong *args) 191 { 192 CPUPPCState *env = &cpu->env; 193 target_ulong flags = args[0]; 194 target_ulong ptex = args[1]; 195 target_ulong avpn = args[2]; 196 RemoveResult ret; 197 198 ret = remove_hpte(cpu, ptex, avpn, flags, 199 &args[0], &args[1]); 200 201 switch (ret) { 202 case REMOVE_SUCCESS: 203 check_tlb_flush(env, true); 204 return H_SUCCESS; 205 206 case REMOVE_NOT_FOUND: 207 return H_NOT_FOUND; 208 209 case REMOVE_PARM: 210 return H_PARAMETER; 211 212 case REMOVE_HW: 213 return H_HARDWARE; 214 } 215 216 g_assert_not_reached(); 217 } 218 219 #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 220 #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 221 #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 222 #define H_BULK_REMOVE_END 0xc000000000000000ULL 223 #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 224 #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 225 #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 226 #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 227 #define H_BULK_REMOVE_HW 0x3000000000000000ULL 228 #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 229 #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 230 #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 231 #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 232 #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 233 #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 234 235 #define H_BULK_REMOVE_MAX_BATCH 4 236 237 static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 238 target_ulong opcode, target_ulong *args) 239 { 240 CPUPPCState *env = &cpu->env; 241 int i; 242 target_ulong rc = H_SUCCESS; 243 244 for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 245 target_ulong *tsh = &args[i*2]; 246 target_ulong tsl = args[i*2 + 1]; 247 target_ulong v, r, ret; 248 249 if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 250 break; 251 } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 252 return H_PARAMETER; 253 } 254 255 *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 256 *tsh |= H_BULK_REMOVE_RESPONSE; 257 258 if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 259 *tsh |= H_BULK_REMOVE_PARM; 260 return H_PARAMETER; 261 } 262 263 ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, 264 (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 265 &v, &r); 266 267 *tsh |= ret << 60; 268 269 switch (ret) { 270 case REMOVE_SUCCESS: 271 *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 272 break; 273 274 case REMOVE_PARM: 275 rc = H_PARAMETER; 276 goto exit; 277 278 case REMOVE_HW: 279 rc = H_HARDWARE; 280 goto exit; 281 } 282 } 283 exit: 284 check_tlb_flush(env, true); 285 286 return rc; 287 } 288 289 static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr, 290 target_ulong opcode, target_ulong *args) 291 { 292 CPUPPCState *env = &cpu->env; 293 target_ulong flags = args[0]; 294 target_ulong ptex = args[1]; 295 target_ulong avpn = args[2]; 296 const ppc_hash_pte64_t *hptes; 297 target_ulong v, r; 298 299 if (!valid_ptex(cpu, ptex)) { 300 return H_PARAMETER; 301 } 302 303 hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 304 v = ppc_hash64_hpte0(cpu, hptes, 0); 305 r = ppc_hash64_hpte1(cpu, hptes, 0); 306 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 307 308 if ((v & HPTE64_V_VALID) == 0 || 309 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 310 return H_NOT_FOUND; 311 } 312 313 r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 314 HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 315 r |= (flags << 55) & HPTE64_R_PP0; 316 r |= (flags << 48) & HPTE64_R_KEY_HI; 317 r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 318 ppc_hash64_store_hpte(cpu, ptex, 319 (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); 320 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 321 /* Flush the tlb */ 322 check_tlb_flush(env, true); 323 /* Don't need a memory barrier, due to qemu's global lock */ 324 ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); 325 return H_SUCCESS; 326 } 327 328 static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr, 329 target_ulong opcode, target_ulong *args) 330 { 331 target_ulong flags = args[0]; 332 target_ulong ptex = args[1]; 333 uint8_t *hpte; 334 int i, ridx, n_entries = 1; 335 336 if (!valid_ptex(cpu, ptex)) { 337 return H_PARAMETER; 338 } 339 340 if (flags & H_READ_4) { 341 /* Clear the two low order bits */ 342 ptex &= ~(3ULL); 343 n_entries = 4; 344 } 345 346 hpte = spapr->htab + (ptex * HASH_PTE_SIZE_64); 347 348 for (i = 0, ridx = 0; i < n_entries; i++) { 349 args[ridx++] = ldq_p(hpte); 350 args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); 351 hpte += HASH_PTE_SIZE_64; 352 } 353 354 return H_SUCCESS; 355 } 356 357 struct sPAPRPendingHPT { 358 /* These fields are read-only after initialization */ 359 int shift; 360 QemuThread thread; 361 362 /* These fields are protected by the BQL */ 363 bool complete; 364 365 /* These fields are private to the preparation thread if 366 * !complete, otherwise protected by the BQL */ 367 int ret; 368 void *hpt; 369 }; 370 371 static void free_pending_hpt(sPAPRPendingHPT *pending) 372 { 373 if (pending->hpt) { 374 qemu_vfree(pending->hpt); 375 } 376 377 g_free(pending); 378 } 379 380 static void *hpt_prepare_thread(void *opaque) 381 { 382 sPAPRPendingHPT *pending = opaque; 383 size_t size = 1ULL << pending->shift; 384 385 pending->hpt = qemu_memalign(size, size); 386 if (pending->hpt) { 387 memset(pending->hpt, 0, size); 388 pending->ret = H_SUCCESS; 389 } else { 390 pending->ret = H_NO_MEM; 391 } 392 393 qemu_mutex_lock_iothread(); 394 395 if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) { 396 /* Ready to go */ 397 pending->complete = true; 398 } else { 399 /* We've been cancelled, clean ourselves up */ 400 free_pending_hpt(pending); 401 } 402 403 qemu_mutex_unlock_iothread(); 404 return NULL; 405 } 406 407 /* Must be called with BQL held */ 408 static void cancel_hpt_prepare(sPAPRMachineState *spapr) 409 { 410 sPAPRPendingHPT *pending = spapr->pending_hpt; 411 412 /* Let the thread know it's cancelled */ 413 spapr->pending_hpt = NULL; 414 415 if (!pending) { 416 /* Nothing to do */ 417 return; 418 } 419 420 if (!pending->complete) { 421 /* thread will clean itself up */ 422 return; 423 } 424 425 free_pending_hpt(pending); 426 } 427 428 /* Convert a return code from the KVM ioctl()s implementing resize HPT 429 * into a PAPR hypercall return code */ 430 static target_ulong resize_hpt_convert_rc(int ret) 431 { 432 if (ret >= 100000) { 433 return H_LONG_BUSY_ORDER_100_SEC; 434 } else if (ret >= 10000) { 435 return H_LONG_BUSY_ORDER_10_SEC; 436 } else if (ret >= 1000) { 437 return H_LONG_BUSY_ORDER_1_SEC; 438 } else if (ret >= 100) { 439 return H_LONG_BUSY_ORDER_100_MSEC; 440 } else if (ret >= 10) { 441 return H_LONG_BUSY_ORDER_10_MSEC; 442 } else if (ret > 0) { 443 return H_LONG_BUSY_ORDER_1_MSEC; 444 } 445 446 switch (ret) { 447 case 0: 448 return H_SUCCESS; 449 case -EPERM: 450 return H_AUTHORITY; 451 case -EINVAL: 452 return H_PARAMETER; 453 case -ENXIO: 454 return H_CLOSED; 455 case -ENOSPC: 456 return H_PTEG_FULL; 457 case -EBUSY: 458 return H_BUSY; 459 case -ENOMEM: 460 return H_NO_MEM; 461 default: 462 return H_HARDWARE; 463 } 464 } 465 466 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 467 sPAPRMachineState *spapr, 468 target_ulong opcode, 469 target_ulong *args) 470 { 471 target_ulong flags = args[0]; 472 int shift = args[1]; 473 sPAPRPendingHPT *pending = spapr->pending_hpt; 474 uint64_t current_ram_size; 475 int rc; 476 477 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 478 return H_AUTHORITY; 479 } 480 481 if (!spapr->htab_shift) { 482 /* Radix guest, no HPT */ 483 return H_NOT_AVAILABLE; 484 } 485 486 trace_spapr_h_resize_hpt_prepare(flags, shift); 487 488 if (flags != 0) { 489 return H_PARAMETER; 490 } 491 492 if (shift && ((shift < 18) || (shift > 46))) { 493 return H_PARAMETER; 494 } 495 496 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 497 498 /* We only allow the guest to allocate an HPT one order above what 499 * we'd normally give them (to stop a small guest claiming a huge 500 * chunk of resources in the HPT */ 501 if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 502 return H_RESOURCE; 503 } 504 505 rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 506 if (rc != -ENOSYS) { 507 return resize_hpt_convert_rc(rc); 508 } 509 510 if (pending) { 511 /* something already in progress */ 512 if (pending->shift == shift) { 513 /* and it's suitable */ 514 if (pending->complete) { 515 return pending->ret; 516 } else { 517 return H_LONG_BUSY_ORDER_100_MSEC; 518 } 519 } 520 521 /* not suitable, cancel and replace */ 522 cancel_hpt_prepare(spapr); 523 } 524 525 if (!shift) { 526 /* nothing to do */ 527 return H_SUCCESS; 528 } 529 530 /* start new prepare */ 531 532 pending = g_new0(sPAPRPendingHPT, 1); 533 pending->shift = shift; 534 pending->ret = H_HARDWARE; 535 536 qemu_thread_create(&pending->thread, "sPAPR HPT prepare", 537 hpt_prepare_thread, pending, QEMU_THREAD_DETACHED); 538 539 spapr->pending_hpt = pending; 540 541 /* In theory we could estimate the time more accurately based on 542 * the new size, but there's not much point */ 543 return H_LONG_BUSY_ORDER_100_MSEC; 544 } 545 546 static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot) 547 { 548 uint8_t *addr = htab; 549 550 addr += pteg * HASH_PTEG_SIZE_64; 551 addr += slot * HASH_PTE_SIZE_64; 552 return ldq_p(addr); 553 } 554 555 static void new_hpte_store(void *htab, uint64_t pteg, int slot, 556 uint64_t pte0, uint64_t pte1) 557 { 558 uint8_t *addr = htab; 559 560 addr += pteg * HASH_PTEG_SIZE_64; 561 addr += slot * HASH_PTE_SIZE_64; 562 563 stq_p(addr, pte0); 564 stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1); 565 } 566 567 static int rehash_hpte(PowerPCCPU *cpu, 568 const ppc_hash_pte64_t *hptes, 569 void *old_hpt, uint64_t oldsize, 570 void *new_hpt, uint64_t newsize, 571 uint64_t pteg, int slot) 572 { 573 uint64_t old_hash_mask = (oldsize >> 7) - 1; 574 uint64_t new_hash_mask = (newsize >> 7) - 1; 575 target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot); 576 target_ulong pte1; 577 uint64_t avpn; 578 unsigned base_pg_shift; 579 uint64_t hash, new_pteg, replace_pte0; 580 581 if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) { 582 return H_SUCCESS; 583 } 584 585 pte1 = ppc_hash64_hpte1(cpu, hptes, slot); 586 587 base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1); 588 assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */ 589 avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23); 590 591 if (pte0 & HPTE64_V_SECONDARY) { 592 pteg = ~pteg; 593 } 594 595 if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) { 596 uint64_t offset, vsid; 597 598 /* We only have 28 - 23 bits of offset in avpn */ 599 offset = (avpn & 0x1f) << 23; 600 vsid = avpn >> 5; 601 /* We can find more bits from the pteg value */ 602 if (base_pg_shift < 23) { 603 offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift; 604 } 605 606 hash = vsid ^ (offset >> base_pg_shift); 607 } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) { 608 uint64_t offset, vsid; 609 610 /* We only have 40 - 23 bits of seg_off in avpn */ 611 offset = (avpn & 0x1ffff) << 23; 612 vsid = avpn >> 17; 613 if (base_pg_shift < 23) { 614 offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask) 615 << base_pg_shift; 616 } 617 618 hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift); 619 } else { 620 error_report("rehash_pte: Bad segment size in HPTE"); 621 return H_HARDWARE; 622 } 623 624 new_pteg = hash & new_hash_mask; 625 if (pte0 & HPTE64_V_SECONDARY) { 626 assert(~pteg == (hash & old_hash_mask)); 627 new_pteg = ~new_pteg; 628 } else { 629 assert(pteg == (hash & old_hash_mask)); 630 } 631 assert((oldsize != newsize) || (pteg == new_pteg)); 632 replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot); 633 /* 634 * Strictly speaking, we don't need all these tests, since we only 635 * ever rehash bolted HPTEs. We might in future handle non-bolted 636 * HPTEs, though so make the logic correct for those cases as 637 * well. 638 */ 639 if (replace_pte0 & HPTE64_V_VALID) { 640 assert(newsize < oldsize); 641 if (replace_pte0 & HPTE64_V_BOLTED) { 642 if (pte0 & HPTE64_V_BOLTED) { 643 /* Bolted collision, nothing we can do */ 644 return H_PTEG_FULL; 645 } else { 646 /* Discard this hpte */ 647 return H_SUCCESS; 648 } 649 } 650 } 651 652 new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1); 653 return H_SUCCESS; 654 } 655 656 static int rehash_hpt(PowerPCCPU *cpu, 657 void *old_hpt, uint64_t oldsize, 658 void *new_hpt, uint64_t newsize) 659 { 660 uint64_t n_ptegs = oldsize >> 7; 661 uint64_t pteg; 662 int slot; 663 int rc; 664 665 for (pteg = 0; pteg < n_ptegs; pteg++) { 666 hwaddr ptex = pteg * HPTES_PER_GROUP; 667 const ppc_hash_pte64_t *hptes 668 = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 669 670 if (!hptes) { 671 return H_HARDWARE; 672 } 673 674 for (slot = 0; slot < HPTES_PER_GROUP; slot++) { 675 rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize, 676 pteg, slot); 677 if (rc != H_SUCCESS) { 678 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 679 return rc; 680 } 681 } 682 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 683 } 684 685 return H_SUCCESS; 686 } 687 688 static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 689 { 690 int ret; 691 692 cpu_synchronize_state(cs); 693 694 ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 695 if (ret < 0) { 696 error_report("failed to push sregs to KVM: %s", strerror(-ret)); 697 exit(1); 698 } 699 } 700 701 static void push_sregs_to_kvm_pr(sPAPRMachineState *spapr) 702 { 703 CPUState *cs; 704 705 /* 706 * This is a hack for the benefit of KVM PR - it abuses the SDR1 707 * slot in kvm_sregs to communicate the userspace address of the 708 * HPT 709 */ 710 if (!kvm_enabled() || !spapr->htab) { 711 return; 712 } 713 714 CPU_FOREACH(cs) { 715 run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 716 } 717 } 718 719 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 720 sPAPRMachineState *spapr, 721 target_ulong opcode, 722 target_ulong *args) 723 { 724 target_ulong flags = args[0]; 725 target_ulong shift = args[1]; 726 sPAPRPendingHPT *pending = spapr->pending_hpt; 727 int rc; 728 size_t newsize; 729 730 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 731 return H_AUTHORITY; 732 } 733 734 trace_spapr_h_resize_hpt_commit(flags, shift); 735 736 rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 737 if (rc != -ENOSYS) { 738 return resize_hpt_convert_rc(rc); 739 } 740 741 if (flags != 0) { 742 return H_PARAMETER; 743 } 744 745 if (!pending || (pending->shift != shift)) { 746 /* no matching prepare */ 747 return H_CLOSED; 748 } 749 750 if (!pending->complete) { 751 /* prepare has not completed */ 752 return H_BUSY; 753 } 754 755 /* Shouldn't have got past PREPARE without an HPT */ 756 g_assert(spapr->htab_shift); 757 758 newsize = 1ULL << pending->shift; 759 rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr), 760 pending->hpt, newsize); 761 if (rc == H_SUCCESS) { 762 qemu_vfree(spapr->htab); 763 spapr->htab = pending->hpt; 764 spapr->htab_shift = pending->shift; 765 766 push_sregs_to_kvm_pr(spapr); 767 768 pending->hpt = NULL; /* so it's not free()d */ 769 } 770 771 /* Clean up */ 772 spapr->pending_hpt = NULL; 773 free_pending_hpt(pending); 774 775 return rc; 776 } 777 778 static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr, 779 target_ulong opcode, target_ulong *args) 780 { 781 cpu_synchronize_state(CPU(cpu)); 782 cpu->env.spr[SPR_SPRG0] = args[0]; 783 784 return H_SUCCESS; 785 } 786 787 static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 788 target_ulong opcode, target_ulong *args) 789 { 790 if (!has_spr(cpu, SPR_DABR)) { 791 return H_HARDWARE; /* DABR register not available */ 792 } 793 cpu_synchronize_state(CPU(cpu)); 794 795 if (has_spr(cpu, SPR_DABRX)) { 796 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 797 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 798 return H_RESERVED_DABR; 799 } 800 801 cpu->env.spr[SPR_DABR] = args[0]; 802 return H_SUCCESS; 803 } 804 805 static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 806 target_ulong opcode, target_ulong *args) 807 { 808 target_ulong dabrx = args[1]; 809 810 if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { 811 return H_HARDWARE; 812 } 813 814 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 815 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 816 return H_PARAMETER; 817 } 818 819 cpu_synchronize_state(CPU(cpu)); 820 cpu->env.spr[SPR_DABRX] = dabrx; 821 cpu->env.spr[SPR_DABR] = args[0]; 822 823 return H_SUCCESS; 824 } 825 826 static target_ulong h_page_init(PowerPCCPU *cpu, sPAPRMachineState *spapr, 827 target_ulong opcode, target_ulong *args) 828 { 829 target_ulong flags = args[0]; 830 hwaddr dst = args[1]; 831 hwaddr src = args[2]; 832 hwaddr len = TARGET_PAGE_SIZE; 833 uint8_t *pdst, *psrc; 834 target_long ret = H_SUCCESS; 835 836 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 837 | H_COPY_PAGE | H_ZERO_PAGE)) { 838 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 839 flags); 840 return H_PARAMETER; 841 } 842 843 /* Map-in destination */ 844 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 845 return H_PARAMETER; 846 } 847 pdst = cpu_physical_memory_map(dst, &len, 1); 848 if (!pdst || len != TARGET_PAGE_SIZE) { 849 return H_PARAMETER; 850 } 851 852 if (flags & H_COPY_PAGE) { 853 /* Map-in source, copy to destination, and unmap source again */ 854 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 855 ret = H_PARAMETER; 856 goto unmap_out; 857 } 858 psrc = cpu_physical_memory_map(src, &len, 0); 859 if (!psrc || len != TARGET_PAGE_SIZE) { 860 ret = H_PARAMETER; 861 goto unmap_out; 862 } 863 memcpy(pdst, psrc, len); 864 cpu_physical_memory_unmap(psrc, len, 0, len); 865 } else if (flags & H_ZERO_PAGE) { 866 memset(pdst, 0, len); /* Just clear the destination page */ 867 } 868 869 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 870 kvmppc_dcbst_range(cpu, pdst, len); 871 } 872 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 873 if (kvm_enabled()) { 874 kvmppc_icbi_range(cpu, pdst, len); 875 } else { 876 tb_flush(CPU(cpu)); 877 } 878 } 879 880 unmap_out: 881 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 882 return ret; 883 } 884 885 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 886 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 887 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 888 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 889 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 890 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 891 892 #define VPA_MIN_SIZE 640 893 #define VPA_SIZE_OFFSET 0x4 894 #define VPA_SHARED_PROC_OFFSET 0x9 895 #define VPA_SHARED_PROC_VAL 0x2 896 897 static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) 898 { 899 CPUState *cs = CPU(ppc_env_get_cpu(env)); 900 uint16_t size; 901 uint8_t tmp; 902 903 if (vpa == 0) { 904 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 905 return H_HARDWARE; 906 } 907 908 if (vpa % env->dcache_line_size) { 909 return H_PARAMETER; 910 } 911 /* FIXME: bounds check the address */ 912 913 size = lduw_be_phys(cs->as, vpa + 0x4); 914 915 if (size < VPA_MIN_SIZE) { 916 return H_PARAMETER; 917 } 918 919 /* VPA is not allowed to cross a page boundary */ 920 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 921 return H_PARAMETER; 922 } 923 924 env->vpa_addr = vpa; 925 926 tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); 927 tmp |= VPA_SHARED_PROC_VAL; 928 stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 929 930 return H_SUCCESS; 931 } 932 933 static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) 934 { 935 if (env->slb_shadow_addr) { 936 return H_RESOURCE; 937 } 938 939 if (env->dtl_addr) { 940 return H_RESOURCE; 941 } 942 943 env->vpa_addr = 0; 944 return H_SUCCESS; 945 } 946 947 static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) 948 { 949 CPUState *cs = CPU(ppc_env_get_cpu(env)); 950 uint32_t size; 951 952 if (addr == 0) { 953 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 954 return H_HARDWARE; 955 } 956 957 size = ldl_be_phys(cs->as, addr + 0x4); 958 if (size < 0x8) { 959 return H_PARAMETER; 960 } 961 962 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 963 return H_PARAMETER; 964 } 965 966 if (!env->vpa_addr) { 967 return H_RESOURCE; 968 } 969 970 env->slb_shadow_addr = addr; 971 env->slb_shadow_size = size; 972 973 return H_SUCCESS; 974 } 975 976 static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) 977 { 978 env->slb_shadow_addr = 0; 979 env->slb_shadow_size = 0; 980 return H_SUCCESS; 981 } 982 983 static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) 984 { 985 CPUState *cs = CPU(ppc_env_get_cpu(env)); 986 uint32_t size; 987 988 if (addr == 0) { 989 hcall_dprintf("Can't cope with DTL at logical 0\n"); 990 return H_HARDWARE; 991 } 992 993 size = ldl_be_phys(cs->as, addr + 0x4); 994 995 if (size < 48) { 996 return H_PARAMETER; 997 } 998 999 if (!env->vpa_addr) { 1000 return H_RESOURCE; 1001 } 1002 1003 env->dtl_addr = addr; 1004 env->dtl_size = size; 1005 1006 return H_SUCCESS; 1007 } 1008 1009 static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) 1010 { 1011 env->dtl_addr = 0; 1012 env->dtl_size = 0; 1013 1014 return H_SUCCESS; 1015 } 1016 1017 static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1018 target_ulong opcode, target_ulong *args) 1019 { 1020 target_ulong flags = args[0]; 1021 target_ulong procno = args[1]; 1022 target_ulong vpa = args[2]; 1023 target_ulong ret = H_PARAMETER; 1024 CPUPPCState *tenv; 1025 PowerPCCPU *tcpu; 1026 1027 tcpu = spapr_find_cpu(procno); 1028 if (!tcpu) { 1029 return H_PARAMETER; 1030 } 1031 tenv = &tcpu->env; 1032 1033 switch (flags) { 1034 case FLAGS_REGISTER_VPA: 1035 ret = register_vpa(tenv, vpa); 1036 break; 1037 1038 case FLAGS_DEREGISTER_VPA: 1039 ret = deregister_vpa(tenv, vpa); 1040 break; 1041 1042 case FLAGS_REGISTER_SLBSHADOW: 1043 ret = register_slb_shadow(tenv, vpa); 1044 break; 1045 1046 case FLAGS_DEREGISTER_SLBSHADOW: 1047 ret = deregister_slb_shadow(tenv, vpa); 1048 break; 1049 1050 case FLAGS_REGISTER_DTL: 1051 ret = register_dtl(tenv, vpa); 1052 break; 1053 1054 case FLAGS_DEREGISTER_DTL: 1055 ret = deregister_dtl(tenv, vpa); 1056 break; 1057 } 1058 1059 return ret; 1060 } 1061 1062 static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1063 target_ulong opcode, target_ulong *args) 1064 { 1065 CPUPPCState *env = &cpu->env; 1066 CPUState *cs = CPU(cpu); 1067 1068 env->msr |= (1ULL << MSR_EE); 1069 hreg_compute_hflags(env); 1070 if (!cpu_has_work(cs)) { 1071 cs->halted = 1; 1072 cs->exception_index = EXCP_HLT; 1073 cs->exit_request = 1; 1074 } 1075 return H_SUCCESS; 1076 } 1077 1078 static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1079 target_ulong opcode, target_ulong *args) 1080 { 1081 target_ulong rtas_r3 = args[0]; 1082 uint32_t token = rtas_ld(rtas_r3, 0); 1083 uint32_t nargs = rtas_ld(rtas_r3, 1); 1084 uint32_t nret = rtas_ld(rtas_r3, 2); 1085 1086 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 1087 nret, rtas_r3 + 12 + 4*nargs); 1088 } 1089 1090 static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1091 target_ulong opcode, target_ulong *args) 1092 { 1093 CPUState *cs = CPU(cpu); 1094 target_ulong size = args[0]; 1095 target_ulong addr = args[1]; 1096 1097 switch (size) { 1098 case 1: 1099 args[0] = ldub_phys(cs->as, addr); 1100 return H_SUCCESS; 1101 case 2: 1102 args[0] = lduw_phys(cs->as, addr); 1103 return H_SUCCESS; 1104 case 4: 1105 args[0] = ldl_phys(cs->as, addr); 1106 return H_SUCCESS; 1107 case 8: 1108 args[0] = ldq_phys(cs->as, addr); 1109 return H_SUCCESS; 1110 } 1111 return H_PARAMETER; 1112 } 1113 1114 static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1115 target_ulong opcode, target_ulong *args) 1116 { 1117 CPUState *cs = CPU(cpu); 1118 1119 target_ulong size = args[0]; 1120 target_ulong addr = args[1]; 1121 target_ulong val = args[2]; 1122 1123 switch (size) { 1124 case 1: 1125 stb_phys(cs->as, addr, val); 1126 return H_SUCCESS; 1127 case 2: 1128 stw_phys(cs->as, addr, val); 1129 return H_SUCCESS; 1130 case 4: 1131 stl_phys(cs->as, addr, val); 1132 return H_SUCCESS; 1133 case 8: 1134 stq_phys(cs->as, addr, val); 1135 return H_SUCCESS; 1136 } 1137 return H_PARAMETER; 1138 } 1139 1140 static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1141 target_ulong opcode, target_ulong *args) 1142 { 1143 CPUState *cs = CPU(cpu); 1144 1145 target_ulong dst = args[0]; /* Destination address */ 1146 target_ulong src = args[1]; /* Source address */ 1147 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 1148 target_ulong count = args[3]; /* Element count */ 1149 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 1150 uint64_t tmp; 1151 unsigned int mask = (1 << esize) - 1; 1152 int step = 1 << esize; 1153 1154 if (count > 0x80000000) { 1155 return H_PARAMETER; 1156 } 1157 1158 if ((dst & mask) || (src & mask) || (op > 1)) { 1159 return H_PARAMETER; 1160 } 1161 1162 if (dst >= src && dst < (src + (count << esize))) { 1163 dst = dst + ((count - 1) << esize); 1164 src = src + ((count - 1) << esize); 1165 step = -step; 1166 } 1167 1168 while (count--) { 1169 switch (esize) { 1170 case 0: 1171 tmp = ldub_phys(cs->as, src); 1172 break; 1173 case 1: 1174 tmp = lduw_phys(cs->as, src); 1175 break; 1176 case 2: 1177 tmp = ldl_phys(cs->as, src); 1178 break; 1179 case 3: 1180 tmp = ldq_phys(cs->as, src); 1181 break; 1182 default: 1183 return H_PARAMETER; 1184 } 1185 if (op == 1) { 1186 tmp = ~tmp; 1187 } 1188 switch (esize) { 1189 case 0: 1190 stb_phys(cs->as, dst, tmp); 1191 break; 1192 case 1: 1193 stw_phys(cs->as, dst, tmp); 1194 break; 1195 case 2: 1196 stl_phys(cs->as, dst, tmp); 1197 break; 1198 case 3: 1199 stq_phys(cs->as, dst, tmp); 1200 break; 1201 } 1202 dst = dst + step; 1203 src = src + step; 1204 } 1205 1206 return H_SUCCESS; 1207 } 1208 1209 static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1210 target_ulong opcode, target_ulong *args) 1211 { 1212 /* Nothing to do on emulation, KVM will trap this in the kernel */ 1213 return H_SUCCESS; 1214 } 1215 1216 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1217 target_ulong opcode, target_ulong *args) 1218 { 1219 /* Nothing to do on emulation, KVM will trap this in the kernel */ 1220 return H_SUCCESS; 1221 } 1222 1223 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 1224 target_ulong mflags, 1225 target_ulong value1, 1226 target_ulong value2) 1227 { 1228 CPUState *cs; 1229 1230 if (value1) { 1231 return H_P3; 1232 } 1233 if (value2) { 1234 return H_P4; 1235 } 1236 1237 switch (mflags) { 1238 case H_SET_MODE_ENDIAN_BIG: 1239 CPU_FOREACH(cs) { 1240 set_spr(cs, SPR_LPCR, 0, LPCR_ILE); 1241 } 1242 spapr_pci_switch_vga(true); 1243 return H_SUCCESS; 1244 1245 case H_SET_MODE_ENDIAN_LITTLE: 1246 CPU_FOREACH(cs) { 1247 set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE); 1248 } 1249 spapr_pci_switch_vga(false); 1250 return H_SUCCESS; 1251 } 1252 1253 return H_UNSUPPORTED_FLAG; 1254 } 1255 1256 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 1257 target_ulong mflags, 1258 target_ulong value1, 1259 target_ulong value2) 1260 { 1261 CPUState *cs; 1262 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 1263 1264 if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 1265 return H_P2; 1266 } 1267 if (value1) { 1268 return H_P3; 1269 } 1270 if (value2) { 1271 return H_P4; 1272 } 1273 1274 if (mflags == AIL_RESERVED) { 1275 return H_UNSUPPORTED_FLAG; 1276 } 1277 1278 CPU_FOREACH(cs) { 1279 set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL); 1280 } 1281 1282 return H_SUCCESS; 1283 } 1284 1285 static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1286 target_ulong opcode, target_ulong *args) 1287 { 1288 target_ulong resource = args[1]; 1289 target_ulong ret = H_P2; 1290 1291 switch (resource) { 1292 case H_SET_MODE_RESOURCE_LE: 1293 ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); 1294 break; 1295 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 1296 ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 1297 args[2], args[3]); 1298 break; 1299 } 1300 1301 return ret; 1302 } 1303 1304 static target_ulong h_clean_slb(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1305 target_ulong opcode, target_ulong *args) 1306 { 1307 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1308 opcode, " (H_CLEAN_SLB)"); 1309 return H_FUNCTION; 1310 } 1311 1312 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1313 target_ulong opcode, target_ulong *args) 1314 { 1315 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1316 opcode, " (H_INVALIDATE_PID)"); 1317 return H_FUNCTION; 1318 } 1319 1320 static void spapr_check_setup_free_hpt(sPAPRMachineState *spapr, 1321 uint64_t patbe_old, uint64_t patbe_new) 1322 { 1323 /* 1324 * We have 4 Options: 1325 * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 1326 * HASH->RADIX : Free HPT 1327 * RADIX->HASH : Allocate HPT 1328 * NOTHING->HASH : Allocate HPT 1329 * Note: NOTHING implies the case where we said the guest could choose 1330 * later and so assumed radix and now it's called H_REG_PROC_TBL 1331 */ 1332 1333 if ((patbe_old & PATBE1_GR) == (patbe_new & PATBE1_GR)) { 1334 /* We assume RADIX, so this catches all the "Do Nothing" cases */ 1335 } else if (!(patbe_old & PATBE1_GR)) { 1336 /* HASH->RADIX : Free HPT */ 1337 spapr_free_hpt(spapr); 1338 } else if (!(patbe_new & PATBE1_GR)) { 1339 /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 1340 spapr_setup_hpt_and_vrma(spapr); 1341 } 1342 return; 1343 } 1344 1345 #define FLAGS_MASK 0x01FULL 1346 #define FLAG_MODIFY 0x10 1347 #define FLAG_REGISTER 0x08 1348 #define FLAG_RADIX 0x04 1349 #define FLAG_HASH_PROC_TBL 0x02 1350 #define FLAG_GTSE 0x01 1351 1352 static target_ulong h_register_process_table(PowerPCCPU *cpu, 1353 sPAPRMachineState *spapr, 1354 target_ulong opcode, 1355 target_ulong *args) 1356 { 1357 CPUState *cs; 1358 target_ulong flags = args[0]; 1359 target_ulong proc_tbl = args[1]; 1360 target_ulong page_size = args[2]; 1361 target_ulong table_size = args[3]; 1362 uint64_t cproc; 1363 1364 if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 1365 return H_PARAMETER; 1366 } 1367 if (flags & FLAG_MODIFY) { 1368 if (flags & FLAG_REGISTER) { 1369 if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 1370 if (proc_tbl & 0xfff || proc_tbl >> 60) { 1371 return H_P2; 1372 } else if (page_size) { 1373 return H_P3; 1374 } else if (table_size > 24) { 1375 return H_P4; 1376 } 1377 cproc = PATBE1_GR | proc_tbl | table_size; 1378 } else { /* Register new HPT process table */ 1379 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 1380 /* TODO - Not Supported */ 1381 /* Technically caused by flag bits => H_PARAMETER */ 1382 return H_PARAMETER; 1383 } else { /* Hash with SLB */ 1384 if (proc_tbl >> 38) { 1385 return H_P2; 1386 } else if (page_size & ~0x7) { 1387 return H_P3; 1388 } else if (table_size > 24) { 1389 return H_P4; 1390 } 1391 } 1392 cproc = (proc_tbl << 25) | page_size << 5 | table_size; 1393 } 1394 1395 } else { /* Deregister current process table */ 1396 /* Set to benign value: (current GR) | 0. This allows 1397 * deregistration in KVM to succeed even if the radix bit in flags 1398 * doesn't match the radix bit in the old PATB. */ 1399 cproc = spapr->patb_entry & PATBE1_GR; 1400 } 1401 } else { /* Maintain current registration */ 1402 if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATBE1_GR)) { 1403 /* Technically caused by flag bits => H_PARAMETER */ 1404 return H_PARAMETER; /* Existing Process Table Mismatch */ 1405 } 1406 cproc = spapr->patb_entry; 1407 } 1408 1409 /* Check if we need to setup OR free the hpt */ 1410 spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 1411 1412 spapr->patb_entry = cproc; /* Save new process table */ 1413 1414 /* Update the UPRT and GTSE bits in the LPCR for all cpus */ 1415 CPU_FOREACH(cs) { 1416 set_spr(cs, SPR_LPCR, 1417 ((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT : 0) | 1418 ((flags & FLAG_GTSE) ? LPCR_GTSE : 0), 1419 LPCR_UPRT | LPCR_GTSE); 1420 } 1421 1422 if (kvm_enabled()) { 1423 return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1424 flags & FLAG_GTSE, cproc); 1425 } 1426 return H_SUCCESS; 1427 } 1428 1429 #define H_SIGNAL_SYS_RESET_ALL -1 1430 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 1431 1432 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1433 sPAPRMachineState *spapr, 1434 target_ulong opcode, target_ulong *args) 1435 { 1436 target_long target = args[0]; 1437 CPUState *cs; 1438 1439 if (target < 0) { 1440 /* Broadcast */ 1441 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1442 return H_PARAMETER; 1443 } 1444 1445 CPU_FOREACH(cs) { 1446 PowerPCCPU *c = POWERPC_CPU(cs); 1447 1448 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1449 if (c == cpu) { 1450 continue; 1451 } 1452 } 1453 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1454 } 1455 return H_SUCCESS; 1456 1457 } else { 1458 /* Unicast */ 1459 cs = CPU(spapr_find_cpu(target)); 1460 if (cs) { 1461 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1462 return H_SUCCESS; 1463 } 1464 return H_PARAMETER; 1465 } 1466 } 1467 1468 static uint32_t cas_check_pvr(sPAPRMachineState *spapr, PowerPCCPU *cpu, 1469 target_ulong *addr, bool *raw_mode_supported, 1470 Error **errp) 1471 { 1472 bool explicit_match = false; /* Matched the CPU's real PVR */ 1473 uint32_t max_compat = spapr->max_compat_pvr; 1474 uint32_t best_compat = 0; 1475 int i; 1476 1477 /* 1478 * We scan the supplied table of PVRs looking for two things 1479 * 1. Is our real CPU PVR in the list? 1480 * 2. What's the "best" listed logical PVR 1481 */ 1482 for (i = 0; i < 512; ++i) { 1483 uint32_t pvr, pvr_mask; 1484 1485 pvr_mask = ldl_be_phys(&address_space_memory, *addr); 1486 pvr = ldl_be_phys(&address_space_memory, *addr + 4); 1487 *addr += 8; 1488 1489 if (~pvr_mask & pvr) { 1490 break; /* Terminator record */ 1491 } 1492 1493 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1494 explicit_match = true; 1495 } else { 1496 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1497 best_compat = pvr; 1498 } 1499 } 1500 } 1501 1502 if ((best_compat == 0) && (!explicit_match || max_compat)) { 1503 /* We couldn't find a suitable compatibility mode, and either 1504 * the guest doesn't support "raw" mode for this CPU, or raw 1505 * mode is disabled because a maximum compat mode is set */ 1506 error_setg(errp, "Couldn't negotiate a suitable PVR during CAS"); 1507 return 0; 1508 } 1509 1510 *raw_mode_supported = explicit_match; 1511 1512 /* Parsing finished */ 1513 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 1514 1515 return best_compat; 1516 } 1517 1518 static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1519 sPAPRMachineState *spapr, 1520 target_ulong opcode, 1521 target_ulong *args) 1522 { 1523 /* Working address in data buffer */ 1524 target_ulong addr = ppc64_phys_to_real(args[0]); 1525 target_ulong ov_table; 1526 uint32_t cas_pvr; 1527 sPAPROptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates; 1528 bool guest_radix; 1529 Error *local_err = NULL; 1530 bool raw_mode_supported = false; 1531 1532 cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err); 1533 if (local_err) { 1534 error_report_err(local_err); 1535 return H_HARDWARE; 1536 } 1537 1538 /* Update CPUs */ 1539 if (cpu->compat_pvr != cas_pvr) { 1540 ppc_set_compat_all(cas_pvr, &local_err); 1541 if (local_err) { 1542 /* We fail to set compat mode (likely because running with KVM PR), 1543 * but maybe we can fallback to raw mode if the guest supports it. 1544 */ 1545 if (!raw_mode_supported) { 1546 error_report_err(local_err); 1547 return H_HARDWARE; 1548 } 1549 local_err = NULL; 1550 } 1551 } 1552 1553 /* For the future use: here @ov_table points to the first option vector */ 1554 ov_table = addr; 1555 1556 ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1557 ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1558 if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 1559 error_report("guest requested hash and radix MMU, which is invalid."); 1560 exit(EXIT_FAILURE); 1561 } 1562 /* The radix/hash bit in byte 24 requires special handling: */ 1563 guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 1564 spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300); 1565 1566 /* 1567 * HPT resizing is a bit of a special case, because when enabled 1568 * we assume an HPT guest will support it until it says it 1569 * doesn't, instead of assuming it won't support it until it says 1570 * it does. Strictly speaking that approach could break for 1571 * guests which don't make a CAS call, but those are so old we 1572 * don't care about them. Without that assumption we'd have to 1573 * make at least a temporary allocation of an HPT sized for max 1574 * memory, which could be impossibly difficult under KVM HV if 1575 * maxram is large. 1576 */ 1577 if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 1578 int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1579 1580 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 1581 error_report( 1582 "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 1583 exit(1); 1584 } 1585 1586 if (spapr->htab_shift < maxshift) { 1587 /* Guest doesn't know about HPT resizing, so we 1588 * pre-emptively resize for the maximum permitted RAM. At 1589 * the point this is called, nothing should have been 1590 * entered into the existing HPT */ 1591 spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 1592 push_sregs_to_kvm_pr(spapr); 1593 } 1594 } 1595 1596 /* NOTE: there are actually a number of ov5 bits where input from the 1597 * guest is always zero, and the platform/QEMU enables them independently 1598 * of guest input. To model these properly we'd want some sort of mask, 1599 * but since they only currently apply to memory migration as defined 1600 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 1601 * to worry about this for now. 1602 */ 1603 ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); 1604 1605 /* also clear the radix/hash bit from the current ov5_cas bits to 1606 * be in sync with the newly ov5 bits. Else the radix bit will be 1607 * seen as being removed and this will generate a reset loop 1608 */ 1609 spapr_ovec_clear(ov5_cas_old, OV5_MMU_RADIX_300); 1610 1611 /* full range of negotiated ov5 capabilities */ 1612 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1613 spapr_ovec_cleanup(ov5_guest); 1614 /* capabilities that have been added since CAS-generated guest reset. 1615 * if capabilities have since been removed, generate another reset 1616 */ 1617 ov5_updates = spapr_ovec_new(); 1618 spapr->cas_reboot = spapr_ovec_diff(ov5_updates, 1619 ov5_cas_old, spapr->ov5_cas); 1620 /* Now that processing is finished, set the radix/hash bit for the 1621 * guest if it requested a valid mode; otherwise terminate the boot. */ 1622 if (guest_radix) { 1623 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1624 error_report("Guest requested unavailable MMU mode (radix)."); 1625 exit(EXIT_FAILURE); 1626 } 1627 spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300); 1628 } else { 1629 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1630 && !kvmppc_has_cap_mmu_hash_v3()) { 1631 error_report("Guest requested unavailable MMU mode (hash)."); 1632 exit(EXIT_FAILURE); 1633 } 1634 } 1635 spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest, 1636 OV1_PPC_3_00); 1637 if (!spapr->cas_reboot) { 1638 /* If ppc_spapr_reset() did not set up a HPT but one is necessary 1639 * (because the guest isn't going to use radix) then set it up here. */ 1640 if ((spapr->patb_entry & PATBE1_GR) && !guest_radix) { 1641 /* legacy hash or new hash: */ 1642 spapr_setup_hpt_and_vrma(spapr); 1643 } 1644 spapr->cas_reboot = 1645 (spapr_h_cas_compose_response(spapr, args[1], args[2], 1646 ov5_updates) != 0); 1647 } 1648 spapr_ovec_cleanup(ov5_updates); 1649 1650 if (spapr->cas_reboot) { 1651 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1652 } 1653 1654 return H_SUCCESS; 1655 } 1656 1657 static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1658 sPAPRMachineState *spapr, 1659 target_ulong opcode, 1660 target_ulong *args) 1661 { 1662 uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1663 ~H_CPU_CHAR_THR_RECONF_TRIG; 1664 uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1665 uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1666 uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1667 uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 1668 1669 switch (safe_cache) { 1670 case SPAPR_CAP_WORKAROUND: 1671 characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1672 characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1673 characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1674 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1675 break; 1676 case SPAPR_CAP_FIXED: 1677 break; 1678 default: /* broken */ 1679 assert(safe_cache == SPAPR_CAP_BROKEN); 1680 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1681 break; 1682 } 1683 1684 switch (safe_bounds_check) { 1685 case SPAPR_CAP_WORKAROUND: 1686 characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1687 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1688 break; 1689 case SPAPR_CAP_FIXED: 1690 break; 1691 default: /* broken */ 1692 assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1693 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1694 break; 1695 } 1696 1697 switch (safe_indirect_branch) { 1698 case SPAPR_CAP_FIXED: 1699 characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1700 default: /* broken */ 1701 assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1702 break; 1703 } 1704 1705 args[0] = characteristics; 1706 args[1] = behaviour; 1707 1708 return H_SUCCESS; 1709 } 1710 1711 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 1712 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 1713 1714 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 1715 { 1716 spapr_hcall_fn *slot; 1717 1718 if (opcode <= MAX_HCALL_OPCODE) { 1719 assert((opcode & 0x3) == 0); 1720 1721 slot = &papr_hypercall_table[opcode / 4]; 1722 } else { 1723 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1724 1725 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1726 } 1727 1728 assert(!(*slot)); 1729 *slot = fn; 1730 } 1731 1732 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 1733 target_ulong *args) 1734 { 1735 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1736 1737 if ((opcode <= MAX_HCALL_OPCODE) 1738 && ((opcode & 0x3) == 0)) { 1739 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 1740 1741 if (fn) { 1742 return fn(cpu, spapr, opcode, args); 1743 } 1744 } else if ((opcode >= KVMPPC_HCALL_BASE) && 1745 (opcode <= KVMPPC_HCALL_MAX)) { 1746 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1747 1748 if (fn) { 1749 return fn(cpu, spapr, opcode, args); 1750 } 1751 } 1752 1753 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1754 opcode); 1755 return H_FUNCTION; 1756 } 1757 1758 static void hypercall_register_types(void) 1759 { 1760 /* hcall-pft */ 1761 spapr_register_hypercall(H_ENTER, h_enter); 1762 spapr_register_hypercall(H_REMOVE, h_remove); 1763 spapr_register_hypercall(H_PROTECT, h_protect); 1764 spapr_register_hypercall(H_READ, h_read); 1765 1766 /* hcall-bulk */ 1767 spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 1768 1769 /* hcall-hpt-resize */ 1770 spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 1771 spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 1772 1773 /* hcall-splpar */ 1774 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 1775 spapr_register_hypercall(H_CEDE, h_cede); 1776 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 1777 1778 /* processor register resource access h-calls */ 1779 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1780 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1781 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 1782 spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1783 spapr_register_hypercall(H_SET_MODE, h_set_mode); 1784 1785 /* In Memory Table MMU h-calls */ 1786 spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1787 spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1788 spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1789 1790 /* hcall-get-cpu-characteristics */ 1791 spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 1792 h_get_cpu_characteristics); 1793 1794 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 1795 * here between the "CI" and the "CACHE" variants, they will use whatever 1796 * mapping attributes qemu is using. When using KVM, the kernel will 1797 * enforce the attributes more strongly 1798 */ 1799 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 1800 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 1801 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 1802 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 1803 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 1804 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 1805 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 1806 1807 /* qemu/KVM-PPC specific hcalls */ 1808 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 1809 1810 /* ibm,client-architecture-support support */ 1811 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1812 } 1813 1814 type_init(hypercall_register_types) 1815