1 #include "qemu/osdep.h" 2 #include "sysemu/sysemu.h" 3 #include "cpu.h" 4 #include "helper_regs.h" 5 #include "hw/ppc/spapr.h" 6 #include "mmu-hash64.h" 7 #include "cpu-models.h" 8 #include "trace.h" 9 #include "kvm_ppc.h" 10 11 struct SPRSyncState { 12 CPUState *cs; 13 int spr; 14 target_ulong value; 15 target_ulong mask; 16 }; 17 18 static void do_spr_sync(void *arg) 19 { 20 struct SPRSyncState *s = arg; 21 PowerPCCPU *cpu = POWERPC_CPU(s->cs); 22 CPUPPCState *env = &cpu->env; 23 24 cpu_synchronize_state(s->cs); 25 env->spr[s->spr] &= ~s->mask; 26 env->spr[s->spr] |= s->value; 27 } 28 29 static void set_spr(CPUState *cs, int spr, target_ulong value, 30 target_ulong mask) 31 { 32 struct SPRSyncState s = { 33 .cs = cs, 34 .spr = spr, 35 .value = value, 36 .mask = mask 37 }; 38 run_on_cpu(cs, do_spr_sync, &s); 39 } 40 41 static bool has_spr(PowerPCCPU *cpu, int spr) 42 { 43 /* We can test whether the SPR is defined by checking for a valid name */ 44 return cpu->env.spr_cb[spr].name != NULL; 45 } 46 47 static inline bool valid_pte_index(CPUPPCState *env, target_ulong pte_index) 48 { 49 /* 50 * hash value/pteg group index is normalized by htab_mask 51 */ 52 if (((pte_index & ~7ULL) / HPTES_PER_GROUP) & ~env->htab_mask) { 53 return false; 54 } 55 return true; 56 } 57 58 static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr) 59 { 60 MachineState *machine = MACHINE(spapr); 61 MemoryHotplugState *hpms = &spapr->hotplug_memory; 62 63 if (addr < machine->ram_size) { 64 return true; 65 } 66 if ((addr >= hpms->base) 67 && ((addr - hpms->base) < memory_region_size(&hpms->mr))) { 68 return true; 69 } 70 71 return false; 72 } 73 74 static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, 75 target_ulong opcode, target_ulong *args) 76 { 77 CPUPPCState *env = &cpu->env; 78 target_ulong flags = args[0]; 79 target_ulong pte_index = args[1]; 80 target_ulong pteh = args[2]; 81 target_ulong ptel = args[3]; 82 unsigned apshift, spshift; 83 target_ulong raddr; 84 target_ulong index; 85 uint64_t token; 86 87 apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel, &spshift); 88 if (!apshift) { 89 /* Bad page size encoding */ 90 return H_PARAMETER; 91 } 92 93 raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); 94 95 if (is_ram_address(spapr, raddr)) { 96 /* Regular RAM - should have WIMG=0010 */ 97 if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 98 return H_PARAMETER; 99 } 100 } else { 101 /* Looks like an IO address */ 102 /* FIXME: What WIMG combinations could be sensible for IO? 103 * For now we allow WIMG=010x, but are there others? */ 104 /* FIXME: Should we check against registered IO addresses? */ 105 if ((ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)) != HPTE64_R_I) { 106 return H_PARAMETER; 107 } 108 } 109 110 pteh &= ~0x60ULL; 111 112 if (!valid_pte_index(env, pte_index)) { 113 return H_PARAMETER; 114 } 115 116 index = 0; 117 if (likely((flags & H_EXACT) == 0)) { 118 pte_index &= ~7ULL; 119 token = ppc_hash64_start_access(cpu, pte_index); 120 for (; index < 8; index++) { 121 if (!(ppc_hash64_load_hpte0(cpu, token, index) & HPTE64_V_VALID)) { 122 break; 123 } 124 } 125 ppc_hash64_stop_access(token); 126 if (index == 8) { 127 return H_PTEG_FULL; 128 } 129 } else { 130 token = ppc_hash64_start_access(cpu, pte_index); 131 if (ppc_hash64_load_hpte0(cpu, token, 0) & HPTE64_V_VALID) { 132 ppc_hash64_stop_access(token); 133 return H_PTEG_FULL; 134 } 135 ppc_hash64_stop_access(token); 136 } 137 138 ppc_hash64_store_hpte(cpu, pte_index + index, 139 pteh | HPTE64_V_HPTE_DIRTY, ptel); 140 141 args[0] = pte_index + index; 142 return H_SUCCESS; 143 } 144 145 typedef enum { 146 REMOVE_SUCCESS = 0, 147 REMOVE_NOT_FOUND = 1, 148 REMOVE_PARM = 2, 149 REMOVE_HW = 3, 150 } RemoveResult; 151 152 static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, 153 target_ulong avpn, 154 target_ulong flags, 155 target_ulong *vp, target_ulong *rp) 156 { 157 CPUPPCState *env = &cpu->env; 158 uint64_t token; 159 target_ulong v, r; 160 161 if (!valid_pte_index(env, ptex)) { 162 return REMOVE_PARM; 163 } 164 165 token = ppc_hash64_start_access(cpu, ptex); 166 v = ppc_hash64_load_hpte0(cpu, token, 0); 167 r = ppc_hash64_load_hpte1(cpu, token, 0); 168 ppc_hash64_stop_access(token); 169 170 if ((v & HPTE64_V_VALID) == 0 || 171 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 172 ((flags & H_ANDCOND) && (v & avpn) != 0)) { 173 return REMOVE_NOT_FOUND; 174 } 175 *vp = v; 176 *rp = r; 177 ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); 178 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 179 return REMOVE_SUCCESS; 180 } 181 182 static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 183 target_ulong opcode, target_ulong *args) 184 { 185 target_ulong flags = args[0]; 186 target_ulong pte_index = args[1]; 187 target_ulong avpn = args[2]; 188 RemoveResult ret; 189 190 ret = remove_hpte(cpu, pte_index, avpn, flags, 191 &args[0], &args[1]); 192 193 switch (ret) { 194 case REMOVE_SUCCESS: 195 return H_SUCCESS; 196 197 case REMOVE_NOT_FOUND: 198 return H_NOT_FOUND; 199 200 case REMOVE_PARM: 201 return H_PARAMETER; 202 203 case REMOVE_HW: 204 return H_HARDWARE; 205 } 206 207 g_assert_not_reached(); 208 } 209 210 #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 211 #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 212 #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 213 #define H_BULK_REMOVE_END 0xc000000000000000ULL 214 #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 215 #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 216 #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 217 #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 218 #define H_BULK_REMOVE_HW 0x3000000000000000ULL 219 #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 220 #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 221 #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 222 #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 223 #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 224 #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 225 226 #define H_BULK_REMOVE_MAX_BATCH 4 227 228 static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 229 target_ulong opcode, target_ulong *args) 230 { 231 int i; 232 233 for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 234 target_ulong *tsh = &args[i*2]; 235 target_ulong tsl = args[i*2 + 1]; 236 target_ulong v, r, ret; 237 238 if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 239 break; 240 } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 241 return H_PARAMETER; 242 } 243 244 *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 245 *tsh |= H_BULK_REMOVE_RESPONSE; 246 247 if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 248 *tsh |= H_BULK_REMOVE_PARM; 249 return H_PARAMETER; 250 } 251 252 ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, 253 (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 254 &v, &r); 255 256 *tsh |= ret << 60; 257 258 switch (ret) { 259 case REMOVE_SUCCESS: 260 *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 261 break; 262 263 case REMOVE_PARM: 264 return H_PARAMETER; 265 266 case REMOVE_HW: 267 return H_HARDWARE; 268 } 269 } 270 271 return H_SUCCESS; 272 } 273 274 static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr, 275 target_ulong opcode, target_ulong *args) 276 { 277 CPUPPCState *env = &cpu->env; 278 target_ulong flags = args[0]; 279 target_ulong pte_index = args[1]; 280 target_ulong avpn = args[2]; 281 uint64_t token; 282 target_ulong v, r; 283 284 if (!valid_pte_index(env, pte_index)) { 285 return H_PARAMETER; 286 } 287 288 token = ppc_hash64_start_access(cpu, pte_index); 289 v = ppc_hash64_load_hpte0(cpu, token, 0); 290 r = ppc_hash64_load_hpte1(cpu, token, 0); 291 ppc_hash64_stop_access(token); 292 293 if ((v & HPTE64_V_VALID) == 0 || 294 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 295 return H_NOT_FOUND; 296 } 297 298 r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 299 HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 300 r |= (flags << 55) & HPTE64_R_PP0; 301 r |= (flags << 48) & HPTE64_R_KEY_HI; 302 r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 303 ppc_hash64_store_hpte(cpu, pte_index, 304 (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); 305 ppc_hash64_tlb_flush_hpte(cpu, pte_index, v, r); 306 /* Don't need a memory barrier, due to qemu's global lock */ 307 ppc_hash64_store_hpte(cpu, pte_index, v | HPTE64_V_HPTE_DIRTY, r); 308 return H_SUCCESS; 309 } 310 311 static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr, 312 target_ulong opcode, target_ulong *args) 313 { 314 CPUPPCState *env = &cpu->env; 315 target_ulong flags = args[0]; 316 target_ulong pte_index = args[1]; 317 uint8_t *hpte; 318 int i, ridx, n_entries = 1; 319 320 if (!valid_pte_index(env, pte_index)) { 321 return H_PARAMETER; 322 } 323 324 if (flags & H_READ_4) { 325 /* Clear the two low order bits */ 326 pte_index &= ~(3ULL); 327 n_entries = 4; 328 } 329 330 hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); 331 332 for (i = 0, ridx = 0; i < n_entries; i++) { 333 args[ridx++] = ldq_p(hpte); 334 args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); 335 hpte += HASH_PTE_SIZE_64; 336 } 337 338 return H_SUCCESS; 339 } 340 341 static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr, 342 target_ulong opcode, target_ulong *args) 343 { 344 cpu_synchronize_state(CPU(cpu)); 345 cpu->env.spr[SPR_SPRG0] = args[0]; 346 347 return H_SUCCESS; 348 } 349 350 static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 351 target_ulong opcode, target_ulong *args) 352 { 353 if (!has_spr(cpu, SPR_DABR)) { 354 return H_HARDWARE; /* DABR register not available */ 355 } 356 cpu_synchronize_state(CPU(cpu)); 357 358 if (has_spr(cpu, SPR_DABRX)) { 359 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 360 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 361 return H_RESERVED_DABR; 362 } 363 364 cpu->env.spr[SPR_DABR] = args[0]; 365 return H_SUCCESS; 366 } 367 368 static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 369 target_ulong opcode, target_ulong *args) 370 { 371 target_ulong dabrx = args[1]; 372 373 if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { 374 return H_HARDWARE; 375 } 376 377 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 378 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 379 return H_PARAMETER; 380 } 381 382 cpu_synchronize_state(CPU(cpu)); 383 cpu->env.spr[SPR_DABRX] = dabrx; 384 cpu->env.spr[SPR_DABR] = args[0]; 385 386 return H_SUCCESS; 387 } 388 389 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 390 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 391 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 392 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 393 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 394 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 395 396 #define VPA_MIN_SIZE 640 397 #define VPA_SIZE_OFFSET 0x4 398 #define VPA_SHARED_PROC_OFFSET 0x9 399 #define VPA_SHARED_PROC_VAL 0x2 400 401 static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) 402 { 403 CPUState *cs = CPU(ppc_env_get_cpu(env)); 404 uint16_t size; 405 uint8_t tmp; 406 407 if (vpa == 0) { 408 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 409 return H_HARDWARE; 410 } 411 412 if (vpa % env->dcache_line_size) { 413 return H_PARAMETER; 414 } 415 /* FIXME: bounds check the address */ 416 417 size = lduw_be_phys(cs->as, vpa + 0x4); 418 419 if (size < VPA_MIN_SIZE) { 420 return H_PARAMETER; 421 } 422 423 /* VPA is not allowed to cross a page boundary */ 424 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 425 return H_PARAMETER; 426 } 427 428 env->vpa_addr = vpa; 429 430 tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); 431 tmp |= VPA_SHARED_PROC_VAL; 432 stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 433 434 return H_SUCCESS; 435 } 436 437 static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) 438 { 439 if (env->slb_shadow_addr) { 440 return H_RESOURCE; 441 } 442 443 if (env->dtl_addr) { 444 return H_RESOURCE; 445 } 446 447 env->vpa_addr = 0; 448 return H_SUCCESS; 449 } 450 451 static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) 452 { 453 CPUState *cs = CPU(ppc_env_get_cpu(env)); 454 uint32_t size; 455 456 if (addr == 0) { 457 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 458 return H_HARDWARE; 459 } 460 461 size = ldl_be_phys(cs->as, addr + 0x4); 462 if (size < 0x8) { 463 return H_PARAMETER; 464 } 465 466 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 467 return H_PARAMETER; 468 } 469 470 if (!env->vpa_addr) { 471 return H_RESOURCE; 472 } 473 474 env->slb_shadow_addr = addr; 475 env->slb_shadow_size = size; 476 477 return H_SUCCESS; 478 } 479 480 static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) 481 { 482 env->slb_shadow_addr = 0; 483 env->slb_shadow_size = 0; 484 return H_SUCCESS; 485 } 486 487 static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) 488 { 489 CPUState *cs = CPU(ppc_env_get_cpu(env)); 490 uint32_t size; 491 492 if (addr == 0) { 493 hcall_dprintf("Can't cope with DTL at logical 0\n"); 494 return H_HARDWARE; 495 } 496 497 size = ldl_be_phys(cs->as, addr + 0x4); 498 499 if (size < 48) { 500 return H_PARAMETER; 501 } 502 503 if (!env->vpa_addr) { 504 return H_RESOURCE; 505 } 506 507 env->dtl_addr = addr; 508 env->dtl_size = size; 509 510 return H_SUCCESS; 511 } 512 513 static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) 514 { 515 env->dtl_addr = 0; 516 env->dtl_size = 0; 517 518 return H_SUCCESS; 519 } 520 521 static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr, 522 target_ulong opcode, target_ulong *args) 523 { 524 target_ulong flags = args[0]; 525 target_ulong procno = args[1]; 526 target_ulong vpa = args[2]; 527 target_ulong ret = H_PARAMETER; 528 CPUPPCState *tenv; 529 PowerPCCPU *tcpu; 530 531 tcpu = ppc_get_vcpu_by_dt_id(procno); 532 if (!tcpu) { 533 return H_PARAMETER; 534 } 535 tenv = &tcpu->env; 536 537 switch (flags) { 538 case FLAGS_REGISTER_VPA: 539 ret = register_vpa(tenv, vpa); 540 break; 541 542 case FLAGS_DEREGISTER_VPA: 543 ret = deregister_vpa(tenv, vpa); 544 break; 545 546 case FLAGS_REGISTER_SLBSHADOW: 547 ret = register_slb_shadow(tenv, vpa); 548 break; 549 550 case FLAGS_DEREGISTER_SLBSHADOW: 551 ret = deregister_slb_shadow(tenv, vpa); 552 break; 553 554 case FLAGS_REGISTER_DTL: 555 ret = register_dtl(tenv, vpa); 556 break; 557 558 case FLAGS_DEREGISTER_DTL: 559 ret = deregister_dtl(tenv, vpa); 560 break; 561 } 562 563 return ret; 564 } 565 566 static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr, 567 target_ulong opcode, target_ulong *args) 568 { 569 CPUPPCState *env = &cpu->env; 570 CPUState *cs = CPU(cpu); 571 572 env->msr |= (1ULL << MSR_EE); 573 hreg_compute_hflags(env); 574 if (!cpu_has_work(cs)) { 575 cs->halted = 1; 576 cs->exception_index = EXCP_HLT; 577 cs->exit_request = 1; 578 } 579 return H_SUCCESS; 580 } 581 582 static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr, 583 target_ulong opcode, target_ulong *args) 584 { 585 target_ulong rtas_r3 = args[0]; 586 uint32_t token = rtas_ld(rtas_r3, 0); 587 uint32_t nargs = rtas_ld(rtas_r3, 1); 588 uint32_t nret = rtas_ld(rtas_r3, 2); 589 590 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 591 nret, rtas_r3 + 12 + 4*nargs); 592 } 593 594 static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr, 595 target_ulong opcode, target_ulong *args) 596 { 597 CPUState *cs = CPU(cpu); 598 target_ulong size = args[0]; 599 target_ulong addr = args[1]; 600 601 switch (size) { 602 case 1: 603 args[0] = ldub_phys(cs->as, addr); 604 return H_SUCCESS; 605 case 2: 606 args[0] = lduw_phys(cs->as, addr); 607 return H_SUCCESS; 608 case 4: 609 args[0] = ldl_phys(cs->as, addr); 610 return H_SUCCESS; 611 case 8: 612 args[0] = ldq_phys(cs->as, addr); 613 return H_SUCCESS; 614 } 615 return H_PARAMETER; 616 } 617 618 static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, 619 target_ulong opcode, target_ulong *args) 620 { 621 CPUState *cs = CPU(cpu); 622 623 target_ulong size = args[0]; 624 target_ulong addr = args[1]; 625 target_ulong val = args[2]; 626 627 switch (size) { 628 case 1: 629 stb_phys(cs->as, addr, val); 630 return H_SUCCESS; 631 case 2: 632 stw_phys(cs->as, addr, val); 633 return H_SUCCESS; 634 case 4: 635 stl_phys(cs->as, addr, val); 636 return H_SUCCESS; 637 case 8: 638 stq_phys(cs->as, addr, val); 639 return H_SUCCESS; 640 } 641 return H_PARAMETER; 642 } 643 644 static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr, 645 target_ulong opcode, target_ulong *args) 646 { 647 CPUState *cs = CPU(cpu); 648 649 target_ulong dst = args[0]; /* Destination address */ 650 target_ulong src = args[1]; /* Source address */ 651 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 652 target_ulong count = args[3]; /* Element count */ 653 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 654 uint64_t tmp; 655 unsigned int mask = (1 << esize) - 1; 656 int step = 1 << esize; 657 658 if (count > 0x80000000) { 659 return H_PARAMETER; 660 } 661 662 if ((dst & mask) || (src & mask) || (op > 1)) { 663 return H_PARAMETER; 664 } 665 666 if (dst >= src && dst < (src + (count << esize))) { 667 dst = dst + ((count - 1) << esize); 668 src = src + ((count - 1) << esize); 669 step = -step; 670 } 671 672 while (count--) { 673 switch (esize) { 674 case 0: 675 tmp = ldub_phys(cs->as, src); 676 break; 677 case 1: 678 tmp = lduw_phys(cs->as, src); 679 break; 680 case 2: 681 tmp = ldl_phys(cs->as, src); 682 break; 683 case 3: 684 tmp = ldq_phys(cs->as, src); 685 break; 686 default: 687 return H_PARAMETER; 688 } 689 if (op == 1) { 690 tmp = ~tmp; 691 } 692 switch (esize) { 693 case 0: 694 stb_phys(cs->as, dst, tmp); 695 break; 696 case 1: 697 stw_phys(cs->as, dst, tmp); 698 break; 699 case 2: 700 stl_phys(cs->as, dst, tmp); 701 break; 702 case 3: 703 stq_phys(cs->as, dst, tmp); 704 break; 705 } 706 dst = dst + step; 707 src = src + step; 708 } 709 710 return H_SUCCESS; 711 } 712 713 static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 714 target_ulong opcode, target_ulong *args) 715 { 716 /* Nothing to do on emulation, KVM will trap this in the kernel */ 717 return H_SUCCESS; 718 } 719 720 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr, 721 target_ulong opcode, target_ulong *args) 722 { 723 /* Nothing to do on emulation, KVM will trap this in the kernel */ 724 return H_SUCCESS; 725 } 726 727 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 728 target_ulong mflags, 729 target_ulong value1, 730 target_ulong value2) 731 { 732 CPUState *cs; 733 734 if (value1) { 735 return H_P3; 736 } 737 if (value2) { 738 return H_P4; 739 } 740 741 switch (mflags) { 742 case H_SET_MODE_ENDIAN_BIG: 743 CPU_FOREACH(cs) { 744 set_spr(cs, SPR_LPCR, 0, LPCR_ILE); 745 } 746 spapr_pci_switch_vga(true); 747 return H_SUCCESS; 748 749 case H_SET_MODE_ENDIAN_LITTLE: 750 CPU_FOREACH(cs) { 751 set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE); 752 } 753 spapr_pci_switch_vga(false); 754 return H_SUCCESS; 755 } 756 757 return H_UNSUPPORTED_FLAG; 758 } 759 760 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 761 target_ulong mflags, 762 target_ulong value1, 763 target_ulong value2) 764 { 765 CPUState *cs; 766 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 767 target_ulong prefix; 768 769 if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 770 return H_P2; 771 } 772 if (value1) { 773 return H_P3; 774 } 775 if (value2) { 776 return H_P4; 777 } 778 779 switch (mflags) { 780 case H_SET_MODE_ADDR_TRANS_NONE: 781 prefix = 0; 782 break; 783 case H_SET_MODE_ADDR_TRANS_0001_8000: 784 prefix = 0x18000; 785 break; 786 case H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000: 787 prefix = 0xC000000000004000ULL; 788 break; 789 default: 790 return H_UNSUPPORTED_FLAG; 791 } 792 793 CPU_FOREACH(cs) { 794 CPUPPCState *env = &POWERPC_CPU(cpu)->env; 795 796 set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL); 797 env->excp_prefix = prefix; 798 } 799 800 return H_SUCCESS; 801 } 802 803 static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr, 804 target_ulong opcode, target_ulong *args) 805 { 806 target_ulong resource = args[1]; 807 target_ulong ret = H_P2; 808 809 switch (resource) { 810 case H_SET_MODE_RESOURCE_LE: 811 ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); 812 break; 813 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 814 ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 815 args[2], args[3]); 816 break; 817 } 818 819 return ret; 820 } 821 822 /* 823 * Return the offset to the requested option vector @vector in the 824 * option vector table @table. 825 */ 826 static target_ulong cas_get_option_vector(int vector, target_ulong table) 827 { 828 int i; 829 char nr_vectors, nr_entries; 830 831 if (!table) { 832 return 0; 833 } 834 835 nr_vectors = (ldl_phys(&address_space_memory, table) >> 24) + 1; 836 if (!vector || vector > nr_vectors) { 837 return 0; 838 } 839 table++; /* skip nr option vectors */ 840 841 for (i = 0; i < vector - 1; i++) { 842 nr_entries = ldl_phys(&address_space_memory, table) >> 24; 843 table += nr_entries + 2; 844 } 845 return table; 846 } 847 848 typedef struct { 849 PowerPCCPU *cpu; 850 uint32_t cpu_version; 851 Error *err; 852 } SetCompatState; 853 854 static void do_set_compat(void *arg) 855 { 856 SetCompatState *s = arg; 857 858 cpu_synchronize_state(CPU(s->cpu)); 859 ppc_set_compat(s->cpu, s->cpu_version, &s->err); 860 } 861 862 #define get_compat_level(cpuver) ( \ 863 ((cpuver) == CPU_POWERPC_LOGICAL_2_05) ? 2050 : \ 864 ((cpuver) == CPU_POWERPC_LOGICAL_2_06) ? 2060 : \ 865 ((cpuver) == CPU_POWERPC_LOGICAL_2_06_PLUS) ? 2061 : \ 866 ((cpuver) == CPU_POWERPC_LOGICAL_2_07) ? 2070 : 0) 867 868 #define OV5_DRCONF_MEMORY 0x20 869 870 static target_ulong h_client_architecture_support(PowerPCCPU *cpu_, 871 sPAPRMachineState *spapr, 872 target_ulong opcode, 873 target_ulong *args) 874 { 875 target_ulong list = ppc64_phys_to_real(args[0]); 876 target_ulong ov_table, ov5; 877 PowerPCCPUClass *pcc_ = POWERPC_CPU_GET_CLASS(cpu_); 878 CPUState *cs; 879 bool cpu_match = false, cpu_update = true, memory_update = false; 880 unsigned old_cpu_version = cpu_->cpu_version; 881 unsigned compat_lvl = 0, cpu_version = 0; 882 unsigned max_lvl = get_compat_level(cpu_->max_compat); 883 int counter; 884 char ov5_byte2; 885 886 /* Parse PVR list */ 887 for (counter = 0; counter < 512; ++counter) { 888 uint32_t pvr, pvr_mask; 889 890 pvr_mask = ldl_be_phys(&address_space_memory, list); 891 list += 4; 892 pvr = ldl_be_phys(&address_space_memory, list); 893 list += 4; 894 895 trace_spapr_cas_pvr_try(pvr); 896 if (!max_lvl && 897 ((cpu_->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask))) { 898 cpu_match = true; 899 cpu_version = 0; 900 } else if (pvr == cpu_->cpu_version) { 901 cpu_match = true; 902 cpu_version = cpu_->cpu_version; 903 } else if (!cpu_match) { 904 /* If it is a logical PVR, try to determine the highest level */ 905 unsigned lvl = get_compat_level(pvr); 906 if (lvl) { 907 bool is205 = (pcc_->pcr_mask & PCR_COMPAT_2_05) && 908 (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_05)); 909 bool is206 = (pcc_->pcr_mask & PCR_COMPAT_2_06) && 910 ((lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06)) || 911 (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06_PLUS))); 912 913 if (is205 || is206) { 914 if (!max_lvl) { 915 /* User did not set the level, choose the highest */ 916 if (compat_lvl <= lvl) { 917 compat_lvl = lvl; 918 cpu_version = pvr; 919 } 920 } else if (max_lvl >= lvl) { 921 /* User chose the level, don't set higher than this */ 922 compat_lvl = lvl; 923 cpu_version = pvr; 924 } 925 } 926 } 927 } 928 /* Terminator record */ 929 if (~pvr_mask & pvr) { 930 break; 931 } 932 } 933 934 /* Parsing finished */ 935 trace_spapr_cas_pvr(cpu_->cpu_version, cpu_match, 936 cpu_version, pcc_->pcr_mask); 937 938 /* Update CPUs */ 939 if (old_cpu_version != cpu_version) { 940 CPU_FOREACH(cs) { 941 SetCompatState s = { 942 .cpu = POWERPC_CPU(cs), 943 .cpu_version = cpu_version, 944 .err = NULL, 945 }; 946 947 run_on_cpu(cs, do_set_compat, &s); 948 949 if (s.err) { 950 error_report_err(s.err); 951 return H_HARDWARE; 952 } 953 } 954 } 955 956 if (!cpu_version) { 957 cpu_update = false; 958 } 959 960 /* For the future use: here @ov_table points to the first option vector */ 961 ov_table = list; 962 963 ov5 = cas_get_option_vector(5, ov_table); 964 if (!ov5) { 965 return H_SUCCESS; 966 } 967 968 /* @list now points to OV 5 */ 969 ov5_byte2 = ldub_phys(&address_space_memory, ov5 + 2); 970 if (ov5_byte2 & OV5_DRCONF_MEMORY) { 971 memory_update = true; 972 } 973 974 if (spapr_h_cas_compose_response(spapr, args[1], args[2], 975 cpu_update, memory_update)) { 976 qemu_system_reset_request(); 977 } 978 979 return H_SUCCESS; 980 } 981 982 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 983 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 984 985 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 986 { 987 spapr_hcall_fn *slot; 988 989 if (opcode <= MAX_HCALL_OPCODE) { 990 assert((opcode & 0x3) == 0); 991 992 slot = &papr_hypercall_table[opcode / 4]; 993 } else { 994 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 995 996 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 997 } 998 999 assert(!(*slot)); 1000 *slot = fn; 1001 } 1002 1003 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 1004 target_ulong *args) 1005 { 1006 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1007 1008 if ((opcode <= MAX_HCALL_OPCODE) 1009 && ((opcode & 0x3) == 0)) { 1010 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 1011 1012 if (fn) { 1013 return fn(cpu, spapr, opcode, args); 1014 } 1015 } else if ((opcode >= KVMPPC_HCALL_BASE) && 1016 (opcode <= KVMPPC_HCALL_MAX)) { 1017 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1018 1019 if (fn) { 1020 return fn(cpu, spapr, opcode, args); 1021 } 1022 } 1023 1024 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1025 opcode); 1026 return H_FUNCTION; 1027 } 1028 1029 static void hypercall_register_types(void) 1030 { 1031 /* hcall-pft */ 1032 spapr_register_hypercall(H_ENTER, h_enter); 1033 spapr_register_hypercall(H_REMOVE, h_remove); 1034 spapr_register_hypercall(H_PROTECT, h_protect); 1035 spapr_register_hypercall(H_READ, h_read); 1036 1037 /* hcall-bulk */ 1038 spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 1039 1040 /* hcall-splpar */ 1041 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 1042 spapr_register_hypercall(H_CEDE, h_cede); 1043 1044 /* processor register resource access h-calls */ 1045 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1046 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1047 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 1048 spapr_register_hypercall(H_SET_MODE, h_set_mode); 1049 1050 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 1051 * here between the "CI" and the "CACHE" variants, they will use whatever 1052 * mapping attributes qemu is using. When using KVM, the kernel will 1053 * enforce the attributes more strongly 1054 */ 1055 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 1056 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 1057 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 1058 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 1059 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 1060 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 1061 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 1062 1063 /* qemu/KVM-PPC specific hcalls */ 1064 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 1065 1066 /* ibm,client-architecture-support support */ 1067 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1068 } 1069 1070 type_init(hypercall_register_types) 1071