1 #include "qemu/osdep.h" 2 #include "qemu/cutils.h" 3 #include "qapi/error.h" 4 #include "sysemu/hw_accel.h" 5 #include "sysemu/runstate.h" 6 #include "sysemu/tcg.h" 7 #include "qemu/log.h" 8 #include "qemu/main-loop.h" 9 #include "qemu/module.h" 10 #include "qemu/error-report.h" 11 #include "exec/tb-flush.h" 12 #include "helper_regs.h" 13 #include "hw/ppc/ppc.h" 14 #include "hw/ppc/spapr.h" 15 #include "hw/ppc/spapr_cpu_core.h" 16 #include "hw/ppc/spapr_nested.h" 17 #include "mmu-hash64.h" 18 #include "cpu-models.h" 19 #include "trace.h" 20 #include "kvm_ppc.h" 21 #include "hw/ppc/fdt.h" 22 #include "hw/ppc/spapr_ovec.h" 23 #include "hw/ppc/spapr_numa.h" 24 #include "mmu-book3s-v3.h" 25 #include "hw/mem/memory-device.h" 26 27 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) 28 { 29 MachineState *machine = MACHINE(spapr); 30 DeviceMemoryState *dms = machine->device_memory; 31 32 if (addr < machine->ram_size) { 33 return true; 34 } 35 if (dms && (addr >= dms->base) 36 && ((addr - dms->base) < memory_region_size(&dms->mr))) { 37 return true; 38 } 39 40 return false; 41 } 42 43 /* Convert a return code from the KVM ioctl()s implementing resize HPT 44 * into a PAPR hypercall return code */ 45 static target_ulong resize_hpt_convert_rc(int ret) 46 { 47 if (ret >= 100000) { 48 return H_LONG_BUSY_ORDER_100_SEC; 49 } else if (ret >= 10000) { 50 return H_LONG_BUSY_ORDER_10_SEC; 51 } else if (ret >= 1000) { 52 return H_LONG_BUSY_ORDER_1_SEC; 53 } else if (ret >= 100) { 54 return H_LONG_BUSY_ORDER_100_MSEC; 55 } else if (ret >= 10) { 56 return H_LONG_BUSY_ORDER_10_MSEC; 57 } else if (ret > 0) { 58 return H_LONG_BUSY_ORDER_1_MSEC; 59 } 60 61 switch (ret) { 62 case 0: 63 return H_SUCCESS; 64 case -EPERM: 65 return H_AUTHORITY; 66 case -EINVAL: 67 return H_PARAMETER; 68 case -ENXIO: 69 return H_CLOSED; 70 case -ENOSPC: 71 return H_PTEG_FULL; 72 case -EBUSY: 73 return H_BUSY; 74 case -ENOMEM: 75 return H_NO_MEM; 76 default: 77 return H_HARDWARE; 78 } 79 } 80 81 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 82 SpaprMachineState *spapr, 83 target_ulong opcode, 84 target_ulong *args) 85 { 86 target_ulong flags = args[0]; 87 int shift = args[1]; 88 uint64_t current_ram_size; 89 int rc; 90 91 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 92 return H_AUTHORITY; 93 } 94 95 if (!spapr->htab_shift) { 96 /* Radix guest, no HPT */ 97 return H_NOT_AVAILABLE; 98 } 99 100 trace_spapr_h_resize_hpt_prepare(flags, shift); 101 102 if (flags != 0) { 103 return H_PARAMETER; 104 } 105 106 if (shift && ((shift < 18) || (shift > 46))) { 107 return H_PARAMETER; 108 } 109 110 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 111 112 /* We only allow the guest to allocate an HPT one order above what 113 * we'd normally give them (to stop a small guest claiming a huge 114 * chunk of resources in the HPT */ 115 if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 116 return H_RESOURCE; 117 } 118 119 rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 120 if (rc != -ENOSYS) { 121 return resize_hpt_convert_rc(rc); 122 } 123 124 if (kvm_enabled()) { 125 return H_HARDWARE; 126 } 127 128 return softmmu_resize_hpt_prepare(cpu, spapr, shift); 129 } 130 131 static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 132 { 133 int ret; 134 135 cpu_synchronize_state(cs); 136 137 ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 138 if (ret < 0) { 139 error_report("failed to push sregs to KVM: %s", strerror(-ret)); 140 exit(1); 141 } 142 } 143 144 void push_sregs_to_kvm_pr(SpaprMachineState *spapr) 145 { 146 CPUState *cs; 147 148 /* 149 * This is a hack for the benefit of KVM PR - it abuses the SDR1 150 * slot in kvm_sregs to communicate the userspace address of the 151 * HPT 152 */ 153 if (!kvm_enabled() || !spapr->htab) { 154 return; 155 } 156 157 CPU_FOREACH(cs) { 158 run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 159 } 160 } 161 162 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 163 SpaprMachineState *spapr, 164 target_ulong opcode, 165 target_ulong *args) 166 { 167 target_ulong flags = args[0]; 168 target_ulong shift = args[1]; 169 int rc; 170 171 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 172 return H_AUTHORITY; 173 } 174 175 if (!spapr->htab_shift) { 176 /* Radix guest, no HPT */ 177 return H_NOT_AVAILABLE; 178 } 179 180 trace_spapr_h_resize_hpt_commit(flags, shift); 181 182 rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 183 if (rc != -ENOSYS) { 184 rc = resize_hpt_convert_rc(rc); 185 if (rc == H_SUCCESS) { 186 /* Need to set the new htab_shift in the machine state */ 187 spapr->htab_shift = shift; 188 } 189 return rc; 190 } 191 192 if (kvm_enabled()) { 193 return H_HARDWARE; 194 } 195 196 return softmmu_resize_hpt_commit(cpu, spapr, flags, shift); 197 } 198 199 200 201 static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, 202 target_ulong opcode, target_ulong *args) 203 { 204 cpu_synchronize_state(CPU(cpu)); 205 cpu->env.spr[SPR_SPRG0] = args[0]; 206 207 return H_SUCCESS; 208 } 209 210 static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 211 target_ulong opcode, target_ulong *args) 212 { 213 if (!ppc_has_spr(cpu, SPR_DABR)) { 214 return H_HARDWARE; /* DABR register not available */ 215 } 216 cpu_synchronize_state(CPU(cpu)); 217 218 if (ppc_has_spr(cpu, SPR_DABRX)) { 219 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 220 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 221 return H_RESERVED_DABR; 222 } 223 224 cpu->env.spr[SPR_DABR] = args[0]; 225 return H_SUCCESS; 226 } 227 228 static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 229 target_ulong opcode, target_ulong *args) 230 { 231 target_ulong dabrx = args[1]; 232 233 if (!ppc_has_spr(cpu, SPR_DABR) || !ppc_has_spr(cpu, SPR_DABRX)) { 234 return H_HARDWARE; 235 } 236 237 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 238 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 239 return H_PARAMETER; 240 } 241 242 cpu_synchronize_state(CPU(cpu)); 243 cpu->env.spr[SPR_DABRX] = dabrx; 244 cpu->env.spr[SPR_DABR] = args[0]; 245 246 return H_SUCCESS; 247 } 248 249 static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, 250 target_ulong opcode, target_ulong *args) 251 { 252 target_ulong flags = args[0]; 253 hwaddr dst = args[1]; 254 hwaddr src = args[2]; 255 hwaddr len = TARGET_PAGE_SIZE; 256 uint8_t *pdst, *psrc; 257 target_long ret = H_SUCCESS; 258 259 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 260 | H_COPY_PAGE | H_ZERO_PAGE)) { 261 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 262 flags); 263 return H_PARAMETER; 264 } 265 266 /* Map-in destination */ 267 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 268 return H_PARAMETER; 269 } 270 pdst = cpu_physical_memory_map(dst, &len, true); 271 if (!pdst || len != TARGET_PAGE_SIZE) { 272 return H_PARAMETER; 273 } 274 275 if (flags & H_COPY_PAGE) { 276 /* Map-in source, copy to destination, and unmap source again */ 277 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 278 ret = H_PARAMETER; 279 goto unmap_out; 280 } 281 psrc = cpu_physical_memory_map(src, &len, false); 282 if (!psrc || len != TARGET_PAGE_SIZE) { 283 ret = H_PARAMETER; 284 goto unmap_out; 285 } 286 memcpy(pdst, psrc, len); 287 cpu_physical_memory_unmap(psrc, len, 0, len); 288 } else if (flags & H_ZERO_PAGE) { 289 memset(pdst, 0, len); /* Just clear the destination page */ 290 } 291 292 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 293 kvmppc_dcbst_range(cpu, pdst, len); 294 } 295 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 296 if (kvm_enabled()) { 297 kvmppc_icbi_range(cpu, pdst, len); 298 } else { 299 tb_flush(CPU(cpu)); 300 } 301 } 302 303 unmap_out: 304 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 305 return ret; 306 } 307 308 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 309 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 310 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 311 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 312 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 313 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 314 315 static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) 316 { 317 CPUState *cs = CPU(cpu); 318 CPUPPCState *env = &cpu->env; 319 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 320 uint16_t size; 321 uint8_t tmp; 322 323 if (vpa == 0) { 324 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 325 return H_HARDWARE; 326 } 327 328 if (vpa % env->dcache_line_size) { 329 return H_PARAMETER; 330 } 331 /* FIXME: bounds check the address */ 332 333 size = lduw_be_phys(cs->as, vpa + 0x4); 334 335 if (size < VPA_MIN_SIZE) { 336 return H_PARAMETER; 337 } 338 339 /* VPA is not allowed to cross a page boundary */ 340 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 341 return H_PARAMETER; 342 } 343 344 spapr_cpu->vpa_addr = vpa; 345 346 tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET); 347 tmp |= VPA_SHARED_PROC_VAL; 348 stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 349 350 return H_SUCCESS; 351 } 352 353 static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) 354 { 355 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 356 357 if (spapr_cpu->slb_shadow_addr) { 358 return H_RESOURCE; 359 } 360 361 if (spapr_cpu->dtl_addr) { 362 return H_RESOURCE; 363 } 364 365 spapr_cpu->vpa_addr = 0; 366 return H_SUCCESS; 367 } 368 369 static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 370 { 371 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 372 uint32_t size; 373 374 if (addr == 0) { 375 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 376 return H_HARDWARE; 377 } 378 379 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 380 if (size < 0x8) { 381 return H_PARAMETER; 382 } 383 384 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 385 return H_PARAMETER; 386 } 387 388 if (!spapr_cpu->vpa_addr) { 389 return H_RESOURCE; 390 } 391 392 spapr_cpu->slb_shadow_addr = addr; 393 spapr_cpu->slb_shadow_size = size; 394 395 return H_SUCCESS; 396 } 397 398 static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 399 { 400 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 401 402 spapr_cpu->slb_shadow_addr = 0; 403 spapr_cpu->slb_shadow_size = 0; 404 return H_SUCCESS; 405 } 406 407 static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) 408 { 409 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 410 uint32_t size; 411 412 if (addr == 0) { 413 hcall_dprintf("Can't cope with DTL at logical 0\n"); 414 return H_HARDWARE; 415 } 416 417 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 418 419 if (size < 48) { 420 return H_PARAMETER; 421 } 422 423 if (!spapr_cpu->vpa_addr) { 424 return H_RESOURCE; 425 } 426 427 spapr_cpu->dtl_addr = addr; 428 spapr_cpu->dtl_size = size; 429 430 return H_SUCCESS; 431 } 432 433 static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) 434 { 435 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 436 437 spapr_cpu->dtl_addr = 0; 438 spapr_cpu->dtl_size = 0; 439 440 return H_SUCCESS; 441 } 442 443 static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr, 444 target_ulong opcode, target_ulong *args) 445 { 446 target_ulong flags = args[0]; 447 target_ulong procno = args[1]; 448 target_ulong vpa = args[2]; 449 target_ulong ret = H_PARAMETER; 450 PowerPCCPU *tcpu; 451 452 tcpu = spapr_find_cpu(procno); 453 if (!tcpu) { 454 return H_PARAMETER; 455 } 456 457 switch (flags) { 458 case FLAGS_REGISTER_VPA: 459 ret = register_vpa(tcpu, vpa); 460 break; 461 462 case FLAGS_DEREGISTER_VPA: 463 ret = deregister_vpa(tcpu, vpa); 464 break; 465 466 case FLAGS_REGISTER_SLBSHADOW: 467 ret = register_slb_shadow(tcpu, vpa); 468 break; 469 470 case FLAGS_DEREGISTER_SLBSHADOW: 471 ret = deregister_slb_shadow(tcpu, vpa); 472 break; 473 474 case FLAGS_REGISTER_DTL: 475 ret = register_dtl(tcpu, vpa); 476 break; 477 478 case FLAGS_DEREGISTER_DTL: 479 ret = deregister_dtl(tcpu, vpa); 480 break; 481 } 482 483 return ret; 484 } 485 486 static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, 487 target_ulong opcode, target_ulong *args) 488 { 489 CPUPPCState *env = &cpu->env; 490 CPUState *cs = CPU(cpu); 491 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 492 493 env->msr |= (1ULL << MSR_EE); 494 hreg_compute_hflags(env); 495 ppc_maybe_interrupt(env); 496 497 if (spapr_cpu->prod) { 498 spapr_cpu->prod = false; 499 return H_SUCCESS; 500 } 501 502 if (!cpu_has_work(cs)) { 503 cs->halted = 1; 504 cs->exception_index = EXCP_HLT; 505 cs->exit_request = 1; 506 ppc_maybe_interrupt(env); 507 } 508 509 return H_SUCCESS; 510 } 511 512 /* 513 * Confer to self, aka join. Cede could use the same pattern as well, if 514 * EXCP_HLT can be changed to ECXP_HALTED. 515 */ 516 static target_ulong h_confer_self(PowerPCCPU *cpu) 517 { 518 CPUState *cs = CPU(cpu); 519 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 520 521 if (spapr_cpu->prod) { 522 spapr_cpu->prod = false; 523 return H_SUCCESS; 524 } 525 cs->halted = 1; 526 cs->exception_index = EXCP_HALTED; 527 cs->exit_request = 1; 528 ppc_maybe_interrupt(&cpu->env); 529 530 return H_SUCCESS; 531 } 532 533 static target_ulong h_join(PowerPCCPU *cpu, SpaprMachineState *spapr, 534 target_ulong opcode, target_ulong *args) 535 { 536 CPUPPCState *env = &cpu->env; 537 CPUState *cs; 538 bool last_unjoined = true; 539 540 if (env->msr & (1ULL << MSR_EE)) { 541 return H_BAD_MODE; 542 } 543 544 /* 545 * Must not join the last CPU running. Interestingly, no such restriction 546 * for H_CONFER-to-self, but that is probably not intended to be used 547 * when H_JOIN is available. 548 */ 549 CPU_FOREACH(cs) { 550 PowerPCCPU *c = POWERPC_CPU(cs); 551 CPUPPCState *e = &c->env; 552 if (c == cpu) { 553 continue; 554 } 555 556 /* Don't have a way to indicate joined, so use halted && MSR[EE]=0 */ 557 if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { 558 last_unjoined = false; 559 break; 560 } 561 } 562 if (last_unjoined) { 563 return H_CONTINUE; 564 } 565 566 return h_confer_self(cpu); 567 } 568 569 static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr, 570 target_ulong opcode, target_ulong *args) 571 { 572 target_long target = args[0]; 573 uint32_t dispatch = args[1]; 574 CPUState *cs = CPU(cpu); 575 SpaprCpuState *spapr_cpu; 576 577 /* 578 * -1 means confer to all other CPUs without dispatch counter check, 579 * otherwise it's a targeted confer. 580 */ 581 if (target != -1) { 582 PowerPCCPU *target_cpu = spapr_find_cpu(target); 583 uint32_t target_dispatch; 584 585 if (!target_cpu) { 586 return H_PARAMETER; 587 } 588 589 /* 590 * target == self is a special case, we wait until prodded, without 591 * dispatch counter check. 592 */ 593 if (cpu == target_cpu) { 594 return h_confer_self(cpu); 595 } 596 597 spapr_cpu = spapr_cpu_state(target_cpu); 598 if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) { 599 return H_SUCCESS; 600 } 601 602 target_dispatch = ldl_be_phys(cs->as, 603 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 604 if (target_dispatch != dispatch) { 605 return H_SUCCESS; 606 } 607 608 /* 609 * The targeted confer does not do anything special beyond yielding 610 * the current vCPU, but even this should be better than nothing. 611 * At least for single-threaded tcg, it gives the target a chance to 612 * run before we run again. Multi-threaded tcg does not really do 613 * anything with EXCP_YIELD yet. 614 */ 615 } 616 617 cs->exception_index = EXCP_YIELD; 618 cs->exit_request = 1; 619 cpu_loop_exit(cs); 620 621 return H_SUCCESS; 622 } 623 624 static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr, 625 target_ulong opcode, target_ulong *args) 626 { 627 target_long target = args[0]; 628 PowerPCCPU *tcpu; 629 CPUState *cs; 630 SpaprCpuState *spapr_cpu; 631 632 tcpu = spapr_find_cpu(target); 633 cs = CPU(tcpu); 634 if (!cs) { 635 return H_PARAMETER; 636 } 637 638 spapr_cpu = spapr_cpu_state(tcpu); 639 spapr_cpu->prod = true; 640 cs->halted = 0; 641 ppc_maybe_interrupt(&cpu->env); 642 qemu_cpu_kick(cs); 643 644 return H_SUCCESS; 645 } 646 647 static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, 648 target_ulong opcode, target_ulong *args) 649 { 650 target_ulong rtas_r3 = args[0]; 651 uint32_t token = rtas_ld(rtas_r3, 0); 652 uint32_t nargs = rtas_ld(rtas_r3, 1); 653 uint32_t nret = rtas_ld(rtas_r3, 2); 654 655 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 656 nret, rtas_r3 + 12 + 4*nargs); 657 } 658 659 static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr, 660 target_ulong opcode, target_ulong *args) 661 { 662 CPUState *cs = CPU(cpu); 663 target_ulong size = args[0]; 664 target_ulong addr = args[1]; 665 666 switch (size) { 667 case 1: 668 args[0] = ldub_phys(cs->as, addr); 669 return H_SUCCESS; 670 case 2: 671 args[0] = lduw_phys(cs->as, addr); 672 return H_SUCCESS; 673 case 4: 674 args[0] = ldl_phys(cs->as, addr); 675 return H_SUCCESS; 676 case 8: 677 args[0] = ldq_phys(cs->as, addr); 678 return H_SUCCESS; 679 } 680 return H_PARAMETER; 681 } 682 683 static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr, 684 target_ulong opcode, target_ulong *args) 685 { 686 CPUState *cs = CPU(cpu); 687 688 target_ulong size = args[0]; 689 target_ulong addr = args[1]; 690 target_ulong val = args[2]; 691 692 switch (size) { 693 case 1: 694 stb_phys(cs->as, addr, val); 695 return H_SUCCESS; 696 case 2: 697 stw_phys(cs->as, addr, val); 698 return H_SUCCESS; 699 case 4: 700 stl_phys(cs->as, addr, val); 701 return H_SUCCESS; 702 case 8: 703 stq_phys(cs->as, addr, val); 704 return H_SUCCESS; 705 } 706 return H_PARAMETER; 707 } 708 709 static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr, 710 target_ulong opcode, target_ulong *args) 711 { 712 CPUState *cs = CPU(cpu); 713 714 target_ulong dst = args[0]; /* Destination address */ 715 target_ulong src = args[1]; /* Source address */ 716 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 717 target_ulong count = args[3]; /* Element count */ 718 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 719 uint64_t tmp; 720 unsigned int mask = (1 << esize) - 1; 721 int step = 1 << esize; 722 723 if (count > 0x80000000) { 724 return H_PARAMETER; 725 } 726 727 if ((dst & mask) || (src & mask) || (op > 1)) { 728 return H_PARAMETER; 729 } 730 731 if (dst >= src && dst < (src + (count << esize))) { 732 dst = dst + ((count - 1) << esize); 733 src = src + ((count - 1) << esize); 734 step = -step; 735 } 736 737 while (count--) { 738 switch (esize) { 739 case 0: 740 tmp = ldub_phys(cs->as, src); 741 break; 742 case 1: 743 tmp = lduw_phys(cs->as, src); 744 break; 745 case 2: 746 tmp = ldl_phys(cs->as, src); 747 break; 748 case 3: 749 tmp = ldq_phys(cs->as, src); 750 break; 751 default: 752 return H_PARAMETER; 753 } 754 if (op == 1) { 755 tmp = ~tmp; 756 } 757 switch (esize) { 758 case 0: 759 stb_phys(cs->as, dst, tmp); 760 break; 761 case 1: 762 stw_phys(cs->as, dst, tmp); 763 break; 764 case 2: 765 stl_phys(cs->as, dst, tmp); 766 break; 767 case 3: 768 stq_phys(cs->as, dst, tmp); 769 break; 770 } 771 dst = dst + step; 772 src = src + step; 773 } 774 775 return H_SUCCESS; 776 } 777 778 static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr, 779 target_ulong opcode, target_ulong *args) 780 { 781 /* Nothing to do on emulation, KVM will trap this in the kernel */ 782 return H_SUCCESS; 783 } 784 785 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, 786 target_ulong opcode, target_ulong *args) 787 { 788 /* Nothing to do on emulation, KVM will trap this in the kernel */ 789 return H_SUCCESS; 790 } 791 792 static target_ulong h_set_mode_resource_set_ciabr(PowerPCCPU *cpu, 793 SpaprMachineState *spapr, 794 target_ulong mflags, 795 target_ulong value1, 796 target_ulong value2) 797 { 798 CPUPPCState *env = &cpu->env; 799 800 assert(tcg_enabled()); /* KVM will have handled this */ 801 802 if (mflags) { 803 return H_UNSUPPORTED_FLAG; 804 } 805 if (value2) { 806 return H_P4; 807 } 808 if ((value1 & PPC_BITMASK(62, 63)) == 0x3) { 809 return H_P3; 810 } 811 812 ppc_store_ciabr(env, value1); 813 814 return H_SUCCESS; 815 } 816 817 static target_ulong h_set_mode_resource_set_dawr0(PowerPCCPU *cpu, 818 SpaprMachineState *spapr, 819 target_ulong mflags, 820 target_ulong value1, 821 target_ulong value2) 822 { 823 CPUPPCState *env = &cpu->env; 824 825 assert(tcg_enabled()); /* KVM will have handled this */ 826 827 if (mflags) { 828 return H_UNSUPPORTED_FLAG; 829 } 830 if (value2 & PPC_BIT(61)) { 831 return H_P4; 832 } 833 834 ppc_store_dawr0(env, value1); 835 ppc_store_dawrx0(env, value2); 836 837 return H_SUCCESS; 838 } 839 840 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 841 SpaprMachineState *spapr, 842 target_ulong mflags, 843 target_ulong value1, 844 target_ulong value2) 845 { 846 if (value1) { 847 return H_P3; 848 } 849 if (value2) { 850 return H_P4; 851 } 852 853 switch (mflags) { 854 case H_SET_MODE_ENDIAN_BIG: 855 spapr_set_all_lpcrs(0, LPCR_ILE); 856 spapr_pci_switch_vga(spapr, true); 857 return H_SUCCESS; 858 859 case H_SET_MODE_ENDIAN_LITTLE: 860 spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); 861 spapr_pci_switch_vga(spapr, false); 862 return H_SUCCESS; 863 } 864 865 return H_UNSUPPORTED_FLAG; 866 } 867 868 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 869 SpaprMachineState *spapr, 870 target_ulong mflags, 871 target_ulong value1, 872 target_ulong value2) 873 { 874 if (value1) { 875 return H_P3; 876 } 877 878 if (value2) { 879 return H_P4; 880 } 881 882 /* 883 * AIL-1 is not architected, and AIL-2 is not supported by QEMU spapr. 884 * It is supported for faithful emulation of bare metal systems, but for 885 * compatibility concerns we leave it out of the pseries machine. 886 */ 887 if (mflags != 0 && mflags != 3) { 888 return H_UNSUPPORTED_FLAG; 889 } 890 891 if (mflags == 3) { 892 if (!spapr_get_cap(spapr, SPAPR_CAP_AIL_MODE_3)) { 893 return H_UNSUPPORTED_FLAG; 894 } 895 } 896 897 spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); 898 899 return H_SUCCESS; 900 } 901 902 static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, 903 target_ulong opcode, target_ulong *args) 904 { 905 target_ulong resource = args[1]; 906 target_ulong ret = H_P2; 907 908 switch (resource) { 909 case H_SET_MODE_RESOURCE_SET_CIABR: 910 ret = h_set_mode_resource_set_ciabr(cpu, spapr, args[0], args[2], 911 args[3]); 912 break; 913 case H_SET_MODE_RESOURCE_SET_DAWR0: 914 ret = h_set_mode_resource_set_dawr0(cpu, spapr, args[0], args[2], 915 args[3]); 916 break; 917 case H_SET_MODE_RESOURCE_LE: 918 ret = h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[3]); 919 break; 920 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 921 ret = h_set_mode_resource_addr_trans_mode(cpu, spapr, args[0], 922 args[2], args[3]); 923 break; 924 } 925 926 return ret; 927 } 928 929 static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, 930 target_ulong opcode, target_ulong *args) 931 { 932 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 933 opcode, " (H_CLEAN_SLB)"); 934 return H_FUNCTION; 935 } 936 937 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr, 938 target_ulong opcode, target_ulong *args) 939 { 940 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 941 opcode, " (H_INVALIDATE_PID)"); 942 return H_FUNCTION; 943 } 944 945 static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, 946 uint64_t patbe_old, uint64_t patbe_new) 947 { 948 /* 949 * We have 4 Options: 950 * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 951 * HASH->RADIX : Free HPT 952 * RADIX->HASH : Allocate HPT 953 * NOTHING->HASH : Allocate HPT 954 * Note: NOTHING implies the case where we said the guest could choose 955 * later and so assumed radix and now it's called H_REG_PROC_TBL 956 */ 957 958 if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) { 959 /* We assume RADIX, so this catches all the "Do Nothing" cases */ 960 } else if (!(patbe_old & PATE1_GR)) { 961 /* HASH->RADIX : Free HPT */ 962 spapr_free_hpt(spapr); 963 } else if (!(patbe_new & PATE1_GR)) { 964 /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 965 spapr_setup_hpt(spapr); 966 } 967 return; 968 } 969 970 #define FLAGS_MASK 0x01FULL 971 #define FLAG_MODIFY 0x10 972 #define FLAG_REGISTER 0x08 973 #define FLAG_RADIX 0x04 974 #define FLAG_HASH_PROC_TBL 0x02 975 #define FLAG_GTSE 0x01 976 977 static target_ulong h_register_process_table(PowerPCCPU *cpu, 978 SpaprMachineState *spapr, 979 target_ulong opcode, 980 target_ulong *args) 981 { 982 target_ulong flags = args[0]; 983 target_ulong proc_tbl = args[1]; 984 target_ulong page_size = args[2]; 985 target_ulong table_size = args[3]; 986 target_ulong update_lpcr = 0; 987 target_ulong table_byte_size; 988 uint64_t cproc; 989 990 if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 991 return H_PARAMETER; 992 } 993 if (flags & FLAG_MODIFY) { 994 if (flags & FLAG_REGISTER) { 995 /* Check process table alignment */ 996 table_byte_size = 1ULL << (table_size + 12); 997 if (proc_tbl & (table_byte_size - 1)) { 998 qemu_log_mask(LOG_GUEST_ERROR, 999 "%s: process table not properly aligned: proc_tbl 0x" 1000 TARGET_FMT_lx" proc_tbl_size 0x"TARGET_FMT_lx"\n", 1001 __func__, proc_tbl, table_byte_size); 1002 } 1003 if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 1004 if (proc_tbl & 0xfff || proc_tbl >> 60) { 1005 return H_P2; 1006 } else if (page_size) { 1007 return H_P3; 1008 } else if (table_size > 24) { 1009 return H_P4; 1010 } 1011 cproc = PATE1_GR | proc_tbl | table_size; 1012 } else { /* Register new HPT process table */ 1013 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 1014 /* TODO - Not Supported */ 1015 /* Technically caused by flag bits => H_PARAMETER */ 1016 return H_PARAMETER; 1017 } else { /* Hash with SLB */ 1018 if (proc_tbl >> 38) { 1019 return H_P2; 1020 } else if (page_size & ~0x7) { 1021 return H_P3; 1022 } else if (table_size > 24) { 1023 return H_P4; 1024 } 1025 } 1026 cproc = (proc_tbl << 25) | page_size << 5 | table_size; 1027 } 1028 1029 } else { /* Deregister current process table */ 1030 /* 1031 * Set to benign value: (current GR) | 0. This allows 1032 * deregistration in KVM to succeed even if the radix bit 1033 * in flags doesn't match the radix bit in the old PATE. 1034 */ 1035 cproc = spapr->patb_entry & PATE1_GR; 1036 } 1037 } else { /* Maintain current registration */ 1038 if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) { 1039 /* Technically caused by flag bits => H_PARAMETER */ 1040 return H_PARAMETER; /* Existing Process Table Mismatch */ 1041 } 1042 cproc = spapr->patb_entry; 1043 } 1044 1045 /* Check if we need to setup OR free the hpt */ 1046 spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 1047 1048 spapr->patb_entry = cproc; /* Save new process table */ 1049 1050 /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ 1051 if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */ 1052 update_lpcr |= (LPCR_UPRT | LPCR_HR); 1053 else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ 1054 update_lpcr |= LPCR_UPRT; 1055 if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ 1056 update_lpcr |= LPCR_GTSE; 1057 1058 spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); 1059 1060 if (kvm_enabled()) { 1061 return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1062 flags & FLAG_GTSE, cproc); 1063 } 1064 return H_SUCCESS; 1065 } 1066 1067 #define H_SIGNAL_SYS_RESET_ALL -1 1068 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 1069 1070 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1071 SpaprMachineState *spapr, 1072 target_ulong opcode, target_ulong *args) 1073 { 1074 target_long target = args[0]; 1075 CPUState *cs; 1076 1077 if (target < 0) { 1078 /* Broadcast */ 1079 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1080 return H_PARAMETER; 1081 } 1082 1083 CPU_FOREACH(cs) { 1084 PowerPCCPU *c = POWERPC_CPU(cs); 1085 1086 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1087 if (c == cpu) { 1088 continue; 1089 } 1090 } 1091 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1092 } 1093 return H_SUCCESS; 1094 1095 } else { 1096 /* Unicast */ 1097 cs = CPU(spapr_find_cpu(target)); 1098 if (cs) { 1099 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1100 return H_SUCCESS; 1101 } 1102 return H_PARAMETER; 1103 } 1104 } 1105 1106 /* Returns either a logical PVR or zero if none was found */ 1107 static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32_t max_compat, 1108 target_ulong *addr, bool *raw_mode_supported) 1109 { 1110 bool explicit_match = false; /* Matched the CPU's real PVR */ 1111 uint32_t best_compat = 0; 1112 int i; 1113 1114 /* 1115 * We scan the supplied table of PVRs looking for two things 1116 * 1. Is our real CPU PVR in the list? 1117 * 2. What's the "best" listed logical PVR 1118 */ 1119 for (i = 0; i < 512; ++i) { 1120 uint32_t pvr, pvr_mask; 1121 1122 pvr_mask = ldl_be_phys(&address_space_memory, *addr); 1123 pvr = ldl_be_phys(&address_space_memory, *addr + 4); 1124 *addr += 8; 1125 1126 if (~pvr_mask & pvr) { 1127 break; /* Terminator record */ 1128 } 1129 1130 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1131 explicit_match = true; 1132 } else { 1133 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1134 best_compat = pvr; 1135 } 1136 } 1137 } 1138 1139 *raw_mode_supported = explicit_match; 1140 1141 /* Parsing finished */ 1142 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 1143 1144 return best_compat; 1145 } 1146 1147 static 1148 target_ulong do_client_architecture_support(PowerPCCPU *cpu, 1149 SpaprMachineState *spapr, 1150 target_ulong vec, 1151 target_ulong fdt_bufsize) 1152 { 1153 target_ulong ov_table; /* Working address in data buffer */ 1154 uint32_t cas_pvr; 1155 SpaprOptionVector *ov1_guest, *ov5_guest; 1156 bool guest_radix; 1157 bool raw_mode_supported = false; 1158 bool guest_xive; 1159 CPUState *cs; 1160 void *fdt; 1161 uint32_t max_compat = spapr->max_compat_pvr; 1162 1163 /* CAS is supposed to be called early when only the boot vCPU is active. */ 1164 CPU_FOREACH(cs) { 1165 if (cs == CPU(cpu)) { 1166 continue; 1167 } 1168 if (!cs->halted) { 1169 warn_report("guest has multiple active vCPUs at CAS, which is not allowed"); 1170 return H_MULTI_THREADS_ACTIVE; 1171 } 1172 } 1173 1174 cas_pvr = cas_check_pvr(cpu, max_compat, &vec, &raw_mode_supported); 1175 if (!cas_pvr && (!raw_mode_supported || max_compat)) { 1176 /* 1177 * We couldn't find a suitable compatibility mode, and either 1178 * the guest doesn't support "raw" mode for this CPU, or "raw" 1179 * mode is disabled because a maximum compat mode is set. 1180 */ 1181 error_report("Couldn't negotiate a suitable PVR during CAS"); 1182 return H_HARDWARE; 1183 } 1184 1185 /* Update CPUs */ 1186 if (cpu->compat_pvr != cas_pvr) { 1187 Error *local_err = NULL; 1188 1189 if (ppc_set_compat_all(cas_pvr, &local_err) < 0) { 1190 /* We fail to set compat mode (likely because running with KVM PR), 1191 * but maybe we can fallback to raw mode if the guest supports it. 1192 */ 1193 if (!raw_mode_supported) { 1194 error_report_err(local_err); 1195 return H_HARDWARE; 1196 } 1197 error_free(local_err); 1198 } 1199 } 1200 1201 /* For the future use: here @ov_table points to the first option vector */ 1202 ov_table = vec; 1203 1204 ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1205 if (!ov1_guest) { 1206 warn_report("guest didn't provide option vector 1"); 1207 return H_PARAMETER; 1208 } 1209 ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1210 if (!ov5_guest) { 1211 spapr_ovec_cleanup(ov1_guest); 1212 warn_report("guest didn't provide option vector 5"); 1213 return H_PARAMETER; 1214 } 1215 if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 1216 error_report("guest requested hash and radix MMU, which is invalid."); 1217 exit(EXIT_FAILURE); 1218 } 1219 if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { 1220 error_report("guest requested an invalid interrupt mode"); 1221 exit(EXIT_FAILURE); 1222 } 1223 1224 guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 1225 1226 guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); 1227 1228 /* 1229 * HPT resizing is a bit of a special case, because when enabled 1230 * we assume an HPT guest will support it until it says it 1231 * doesn't, instead of assuming it won't support it until it says 1232 * it does. Strictly speaking that approach could break for 1233 * guests which don't make a CAS call, but those are so old we 1234 * don't care about them. Without that assumption we'd have to 1235 * make at least a temporary allocation of an HPT sized for max 1236 * memory, which could be impossibly difficult under KVM HV if 1237 * maxram is large. 1238 */ 1239 if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 1240 int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1241 1242 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 1243 error_report( 1244 "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 1245 exit(1); 1246 } 1247 1248 if (spapr->htab_shift < maxshift) { 1249 /* Guest doesn't know about HPT resizing, so we 1250 * pre-emptively resize for the maximum permitted RAM. At 1251 * the point this is called, nothing should have been 1252 * entered into the existing HPT */ 1253 spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 1254 push_sregs_to_kvm_pr(spapr); 1255 } 1256 } 1257 1258 /* NOTE: there are actually a number of ov5 bits where input from the 1259 * guest is always zero, and the platform/QEMU enables them independently 1260 * of guest input. To model these properly we'd want some sort of mask, 1261 * but since they only currently apply to memory migration as defined 1262 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 1263 * to worry about this for now. 1264 */ 1265 1266 /* full range of negotiated ov5 capabilities */ 1267 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1268 spapr_ovec_cleanup(ov5_guest); 1269 1270 spapr_check_mmu_mode(guest_radix); 1271 1272 spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00); 1273 spapr_ovec_cleanup(ov1_guest); 1274 1275 /* 1276 * Check for NUMA affinity conditions now that we know which NUMA 1277 * affinity the guest will use. 1278 */ 1279 spapr_numa_associativity_check(spapr); 1280 1281 /* 1282 * Ensure the guest asks for an interrupt mode we support; 1283 * otherwise terminate the boot. 1284 */ 1285 if (guest_xive) { 1286 if (!spapr->irq->xive) { 1287 error_report( 1288 "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property"); 1289 exit(EXIT_FAILURE); 1290 } 1291 } else { 1292 if (!spapr->irq->xics) { 1293 error_report( 1294 "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual"); 1295 exit(EXIT_FAILURE); 1296 } 1297 } 1298 1299 spapr_irq_update_active_intc(spapr); 1300 1301 /* 1302 * Process all pending hot-plug/unplug requests now. An updated full 1303 * rendered FDT will be returned to the guest. 1304 */ 1305 spapr_drc_reset_all(spapr); 1306 spapr_clear_pending_hotplug_events(spapr); 1307 1308 /* 1309 * If spapr_machine_reset() did not set up a HPT but one is necessary 1310 * (because the guest isn't going to use radix) then set it up here. 1311 */ 1312 if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { 1313 /* legacy hash or new hash: */ 1314 spapr_setup_hpt(spapr); 1315 } 1316 1317 fdt = spapr_build_fdt(spapr, spapr->vof != NULL, fdt_bufsize); 1318 g_free(spapr->fdt_blob); 1319 spapr->fdt_size = fdt_totalsize(fdt); 1320 spapr->fdt_initial_size = spapr->fdt_size; 1321 spapr->fdt_blob = fdt; 1322 1323 /* 1324 * Set the machine->fdt pointer again since we just freed 1325 * it above (by freeing spapr->fdt_blob). We set this 1326 * pointer to enable support for the 'dumpdtb' QMP/HMP 1327 * command. 1328 */ 1329 MACHINE(spapr)->fdt = fdt; 1330 1331 return H_SUCCESS; 1332 } 1333 1334 static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1335 SpaprMachineState *spapr, 1336 target_ulong opcode, 1337 target_ulong *args) 1338 { 1339 target_ulong vec = ppc64_phys_to_real(args[0]); 1340 target_ulong fdt_buf = args[1]; 1341 target_ulong fdt_bufsize = args[2]; 1342 target_ulong ret; 1343 SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 1344 1345 if (fdt_bufsize < sizeof(hdr)) { 1346 error_report("SLOF provided insufficient CAS buffer " 1347 TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr)); 1348 exit(EXIT_FAILURE); 1349 } 1350 1351 fdt_bufsize -= sizeof(hdr); 1352 1353 ret = do_client_architecture_support(cpu, spapr, vec, fdt_bufsize); 1354 if (ret == H_SUCCESS) { 1355 _FDT((fdt_pack(spapr->fdt_blob))); 1356 spapr->fdt_size = fdt_totalsize(spapr->fdt_blob); 1357 spapr->fdt_initial_size = spapr->fdt_size; 1358 1359 cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr)); 1360 cpu_physical_memory_write(fdt_buf + sizeof(hdr), spapr->fdt_blob, 1361 spapr->fdt_size); 1362 trace_spapr_cas_continue(spapr->fdt_size + sizeof(hdr)); 1363 } 1364 1365 return ret; 1366 } 1367 1368 target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1369 CPUState *cs, 1370 target_ulong ovec_addr) 1371 { 1372 SpaprMachineState *spapr = SPAPR_MACHINE(ms); 1373 1374 target_ulong ret = do_client_architecture_support(POWERPC_CPU(cs), spapr, 1375 ovec_addr, FDT_MAX_SIZE); 1376 1377 /* 1378 * This adds stdout and generates phandles for boottime and CAS FDTs. 1379 * It is alright to update the FDT here as do_client_architecture_support() 1380 * does not pack it. 1381 */ 1382 spapr_vof_client_dt_finalize(spapr, spapr->fdt_blob); 1383 1384 return ret; 1385 } 1386 1387 static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1388 SpaprMachineState *spapr, 1389 target_ulong opcode, 1390 target_ulong *args) 1391 { 1392 uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1393 ~H_CPU_CHAR_THR_RECONF_TRIG; 1394 uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1395 uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1396 uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1397 uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 1398 uint8_t count_cache_flush_assist = spapr_get_cap(spapr, 1399 SPAPR_CAP_CCF_ASSIST); 1400 1401 switch (safe_cache) { 1402 case SPAPR_CAP_WORKAROUND: 1403 characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1404 characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1405 characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1406 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1407 break; 1408 case SPAPR_CAP_FIXED: 1409 behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY; 1410 behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS; 1411 break; 1412 default: /* broken */ 1413 assert(safe_cache == SPAPR_CAP_BROKEN); 1414 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1415 break; 1416 } 1417 1418 switch (safe_bounds_check) { 1419 case SPAPR_CAP_WORKAROUND: 1420 characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1421 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1422 break; 1423 case SPAPR_CAP_FIXED: 1424 break; 1425 default: /* broken */ 1426 assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1427 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1428 break; 1429 } 1430 1431 switch (safe_indirect_branch) { 1432 case SPAPR_CAP_FIXED_NA: 1433 break; 1434 case SPAPR_CAP_FIXED_CCD: 1435 characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; 1436 break; 1437 case SPAPR_CAP_FIXED_IBS: 1438 characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1439 break; 1440 case SPAPR_CAP_WORKAROUND: 1441 behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE; 1442 if (count_cache_flush_assist) { 1443 characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST; 1444 } 1445 break; 1446 default: /* broken */ 1447 assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1448 break; 1449 } 1450 1451 args[0] = characteristics; 1452 args[1] = behaviour; 1453 return H_SUCCESS; 1454 } 1455 1456 static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, 1457 target_ulong opcode, target_ulong *args) 1458 { 1459 target_ulong dt = ppc64_phys_to_real(args[0]); 1460 struct fdt_header hdr = { 0 }; 1461 unsigned cb; 1462 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1463 void *fdt; 1464 1465 cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); 1466 cb = fdt32_to_cpu(hdr.totalsize); 1467 1468 if (!smc->update_dt_enabled) { 1469 return H_SUCCESS; 1470 } 1471 1472 /* Check that the fdt did not grow out of proportion */ 1473 if (cb > spapr->fdt_initial_size * 2) { 1474 trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, 1475 fdt32_to_cpu(hdr.magic)); 1476 return H_PARAMETER; 1477 } 1478 1479 fdt = g_malloc0(cb); 1480 cpu_physical_memory_read(dt, fdt, cb); 1481 1482 /* Check the fdt consistency */ 1483 if (fdt_check_full(fdt, cb)) { 1484 trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, 1485 fdt32_to_cpu(hdr.magic)); 1486 return H_PARAMETER; 1487 } 1488 1489 g_free(spapr->fdt_blob); 1490 spapr->fdt_size = cb; 1491 spapr->fdt_blob = fdt; 1492 trace_spapr_update_dt(cb); 1493 1494 return H_SUCCESS; 1495 } 1496 1497 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 1498 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 1499 static spapr_hcall_fn svm_hypercall_table[(SVM_HCALL_MAX - SVM_HCALL_BASE) / 4 + 1]; 1500 1501 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 1502 { 1503 spapr_hcall_fn *slot; 1504 1505 if (opcode <= MAX_HCALL_OPCODE) { 1506 assert((opcode & 0x3) == 0); 1507 1508 slot = &papr_hypercall_table[opcode / 4]; 1509 } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { 1510 /* we only have SVM-related hcall numbers assigned in multiples of 4 */ 1511 assert((opcode & 0x3) == 0); 1512 1513 slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1514 } else { 1515 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1516 1517 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1518 } 1519 1520 assert(!(*slot)); 1521 *slot = fn; 1522 } 1523 1524 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 1525 target_ulong *args) 1526 { 1527 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1528 1529 if ((opcode <= MAX_HCALL_OPCODE) 1530 && ((opcode & 0x3) == 0)) { 1531 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 1532 1533 if (fn) { 1534 return fn(cpu, spapr, opcode, args); 1535 } 1536 } else if ((opcode >= SVM_HCALL_BASE) && 1537 (opcode <= SVM_HCALL_MAX)) { 1538 spapr_hcall_fn fn = svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1539 1540 if (fn) { 1541 return fn(cpu, spapr, opcode, args); 1542 } 1543 } else if ((opcode >= KVMPPC_HCALL_BASE) && 1544 (opcode <= KVMPPC_HCALL_MAX)) { 1545 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1546 1547 if (fn) { 1548 return fn(cpu, spapr, opcode, args); 1549 } 1550 } 1551 1552 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1553 opcode); 1554 return H_FUNCTION; 1555 } 1556 1557 #ifdef CONFIG_TCG 1558 static void hypercall_register_softmmu(void) 1559 { 1560 /* DO NOTHING */ 1561 } 1562 #else 1563 static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr, 1564 target_ulong opcode, target_ulong *args) 1565 { 1566 g_assert_not_reached(); 1567 } 1568 1569 static void hypercall_register_softmmu(void) 1570 { 1571 /* hcall-pft */ 1572 spapr_register_hypercall(H_ENTER, h_softmmu); 1573 spapr_register_hypercall(H_REMOVE, h_softmmu); 1574 spapr_register_hypercall(H_PROTECT, h_softmmu); 1575 spapr_register_hypercall(H_READ, h_softmmu); 1576 1577 /* hcall-bulk */ 1578 spapr_register_hypercall(H_BULK_REMOVE, h_softmmu); 1579 } 1580 #endif 1581 1582 static void hypercall_register_types(void) 1583 { 1584 hypercall_register_softmmu(); 1585 1586 /* hcall-hpt-resize */ 1587 spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 1588 spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 1589 1590 /* hcall-splpar */ 1591 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 1592 spapr_register_hypercall(H_CEDE, h_cede); 1593 spapr_register_hypercall(H_CONFER, h_confer); 1594 spapr_register_hypercall(H_PROD, h_prod); 1595 1596 /* hcall-join */ 1597 spapr_register_hypercall(H_JOIN, h_join); 1598 1599 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 1600 1601 /* processor register resource access h-calls */ 1602 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1603 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1604 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 1605 spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1606 spapr_register_hypercall(H_SET_MODE, h_set_mode); 1607 1608 /* In Memory Table MMU h-calls */ 1609 spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1610 spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1611 spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1612 1613 /* hcall-get-cpu-characteristics */ 1614 spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 1615 h_get_cpu_characteristics); 1616 1617 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differentiate 1618 * here between the "CI" and the "CACHE" variants, they will use whatever 1619 * mapping attributes qemu is using. When using KVM, the kernel will 1620 * enforce the attributes more strongly 1621 */ 1622 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 1623 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 1624 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 1625 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 1626 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 1627 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 1628 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 1629 1630 /* qemu/KVM-PPC specific hcalls */ 1631 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 1632 1633 /* ibm,client-architecture-support support */ 1634 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1635 1636 spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); 1637 1638 spapr_register_nested(); 1639 } 1640 1641 type_init(hypercall_register_types) 1642