1 #include "qemu/osdep.h" 2 #include "qapi/error.h" 3 #include "sysemu/hw_accel.h" 4 #include "sysemu/runstate.h" 5 #include "qemu/log.h" 6 #include "qemu/main-loop.h" 7 #include "qemu/module.h" 8 #include "qemu/error-report.h" 9 #include "cpu.h" 10 #include "exec/exec-all.h" 11 #include "helper_regs.h" 12 #include "hw/ppc/spapr.h" 13 #include "hw/ppc/spapr_cpu_core.h" 14 #include "mmu-hash64.h" 15 #include "cpu-models.h" 16 #include "trace.h" 17 #include "kvm_ppc.h" 18 #include "hw/ppc/spapr_ovec.h" 19 #include "mmu-book3s-v3.h" 20 #include "hw/mem/memory-device.h" 21 22 static bool has_spr(PowerPCCPU *cpu, int spr) 23 { 24 /* We can test whether the SPR is defined by checking for a valid name */ 25 return cpu->env.spr_cb[spr].name != NULL; 26 } 27 28 static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) 29 { 30 /* 31 * hash value/pteg group index is normalized by HPT mask 32 */ 33 if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { 34 return false; 35 } 36 return true; 37 } 38 39 static bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) 40 { 41 MachineState *machine = MACHINE(spapr); 42 DeviceMemoryState *dms = machine->device_memory; 43 44 if (addr < machine->ram_size) { 45 return true; 46 } 47 if ((addr >= dms->base) 48 && ((addr - dms->base) < memory_region_size(&dms->mr))) { 49 return true; 50 } 51 52 return false; 53 } 54 55 static target_ulong h_enter(PowerPCCPU *cpu, SpaprMachineState *spapr, 56 target_ulong opcode, target_ulong *args) 57 { 58 target_ulong flags = args[0]; 59 target_ulong ptex = args[1]; 60 target_ulong pteh = args[2]; 61 target_ulong ptel = args[3]; 62 unsigned apshift; 63 target_ulong raddr; 64 target_ulong slot; 65 const ppc_hash_pte64_t *hptes; 66 67 apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); 68 if (!apshift) { 69 /* Bad page size encoding */ 70 return H_PARAMETER; 71 } 72 73 raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); 74 75 if (is_ram_address(spapr, raddr)) { 76 /* Regular RAM - should have WIMG=0010 */ 77 if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 78 return H_PARAMETER; 79 } 80 } else { 81 target_ulong wimg_flags; 82 /* Looks like an IO address */ 83 /* FIXME: What WIMG combinations could be sensible for IO? 84 * For now we allow WIMG=010x, but are there others? */ 85 /* FIXME: Should we check against registered IO addresses? */ 86 wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); 87 88 if (wimg_flags != HPTE64_R_I && 89 wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { 90 return H_PARAMETER; 91 } 92 } 93 94 pteh &= ~0x60ULL; 95 96 if (!valid_ptex(cpu, ptex)) { 97 return H_PARAMETER; 98 } 99 100 slot = ptex & 7ULL; 101 ptex = ptex & ~7ULL; 102 103 if (likely((flags & H_EXACT) == 0)) { 104 hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 105 for (slot = 0; slot < 8; slot++) { 106 if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { 107 break; 108 } 109 } 110 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 111 if (slot == 8) { 112 return H_PTEG_FULL; 113 } 114 } else { 115 hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); 116 if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { 117 ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); 118 return H_PTEG_FULL; 119 } 120 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 121 } 122 123 spapr_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); 124 125 args[0] = ptex + slot; 126 return H_SUCCESS; 127 } 128 129 typedef enum { 130 REMOVE_SUCCESS = 0, 131 REMOVE_NOT_FOUND = 1, 132 REMOVE_PARM = 2, 133 REMOVE_HW = 3, 134 } RemoveResult; 135 136 static RemoveResult remove_hpte(PowerPCCPU *cpu 137 , target_ulong ptex, 138 target_ulong avpn, 139 target_ulong flags, 140 target_ulong *vp, target_ulong *rp) 141 { 142 const ppc_hash_pte64_t *hptes; 143 target_ulong v, r; 144 145 if (!valid_ptex(cpu, ptex)) { 146 return REMOVE_PARM; 147 } 148 149 hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 150 v = ppc_hash64_hpte0(cpu, hptes, 0); 151 r = ppc_hash64_hpte1(cpu, hptes, 0); 152 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 153 154 if ((v & HPTE64_V_VALID) == 0 || 155 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 156 ((flags & H_ANDCOND) && (v & avpn) != 0)) { 157 return REMOVE_NOT_FOUND; 158 } 159 *vp = v; 160 *rp = r; 161 spapr_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); 162 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 163 return REMOVE_SUCCESS; 164 } 165 166 static target_ulong h_remove(PowerPCCPU *cpu, SpaprMachineState *spapr, 167 target_ulong opcode, target_ulong *args) 168 { 169 CPUPPCState *env = &cpu->env; 170 target_ulong flags = args[0]; 171 target_ulong ptex = args[1]; 172 target_ulong avpn = args[2]; 173 RemoveResult ret; 174 175 ret = remove_hpte(cpu, ptex, avpn, flags, 176 &args[0], &args[1]); 177 178 switch (ret) { 179 case REMOVE_SUCCESS: 180 check_tlb_flush(env, true); 181 return H_SUCCESS; 182 183 case REMOVE_NOT_FOUND: 184 return H_NOT_FOUND; 185 186 case REMOVE_PARM: 187 return H_PARAMETER; 188 189 case REMOVE_HW: 190 return H_HARDWARE; 191 } 192 193 g_assert_not_reached(); 194 } 195 196 #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 197 #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 198 #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 199 #define H_BULK_REMOVE_END 0xc000000000000000ULL 200 #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 201 #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 202 #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 203 #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 204 #define H_BULK_REMOVE_HW 0x3000000000000000ULL 205 #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 206 #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 207 #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 208 #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 209 #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 210 #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 211 212 #define H_BULK_REMOVE_MAX_BATCH 4 213 214 static target_ulong h_bulk_remove(PowerPCCPU *cpu, SpaprMachineState *spapr, 215 target_ulong opcode, target_ulong *args) 216 { 217 CPUPPCState *env = &cpu->env; 218 int i; 219 target_ulong rc = H_SUCCESS; 220 221 for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 222 target_ulong *tsh = &args[i*2]; 223 target_ulong tsl = args[i*2 + 1]; 224 target_ulong v, r, ret; 225 226 if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 227 break; 228 } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 229 return H_PARAMETER; 230 } 231 232 *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 233 *tsh |= H_BULK_REMOVE_RESPONSE; 234 235 if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 236 *tsh |= H_BULK_REMOVE_PARM; 237 return H_PARAMETER; 238 } 239 240 ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, 241 (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 242 &v, &r); 243 244 *tsh |= ret << 60; 245 246 switch (ret) { 247 case REMOVE_SUCCESS: 248 *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 249 break; 250 251 case REMOVE_PARM: 252 rc = H_PARAMETER; 253 goto exit; 254 255 case REMOVE_HW: 256 rc = H_HARDWARE; 257 goto exit; 258 } 259 } 260 exit: 261 check_tlb_flush(env, true); 262 263 return rc; 264 } 265 266 static target_ulong h_protect(PowerPCCPU *cpu, SpaprMachineState *spapr, 267 target_ulong opcode, target_ulong *args) 268 { 269 CPUPPCState *env = &cpu->env; 270 target_ulong flags = args[0]; 271 target_ulong ptex = args[1]; 272 target_ulong avpn = args[2]; 273 const ppc_hash_pte64_t *hptes; 274 target_ulong v, r; 275 276 if (!valid_ptex(cpu, ptex)) { 277 return H_PARAMETER; 278 } 279 280 hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 281 v = ppc_hash64_hpte0(cpu, hptes, 0); 282 r = ppc_hash64_hpte1(cpu, hptes, 0); 283 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 284 285 if ((v & HPTE64_V_VALID) == 0 || 286 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 287 return H_NOT_FOUND; 288 } 289 290 r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 291 HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 292 r |= (flags << 55) & HPTE64_R_PP0; 293 r |= (flags << 48) & HPTE64_R_KEY_HI; 294 r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 295 spapr_store_hpte(cpu, ptex, 296 (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); 297 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 298 /* Flush the tlb */ 299 check_tlb_flush(env, true); 300 /* Don't need a memory barrier, due to qemu's global lock */ 301 spapr_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); 302 return H_SUCCESS; 303 } 304 305 static target_ulong h_read(PowerPCCPU *cpu, SpaprMachineState *spapr, 306 target_ulong opcode, target_ulong *args) 307 { 308 target_ulong flags = args[0]; 309 target_ulong ptex = args[1]; 310 int i, ridx, n_entries = 1; 311 const ppc_hash_pte64_t *hptes; 312 313 if (!valid_ptex(cpu, ptex)) { 314 return H_PARAMETER; 315 } 316 317 if (flags & H_READ_4) { 318 /* Clear the two low order bits */ 319 ptex &= ~(3ULL); 320 n_entries = 4; 321 } 322 323 hptes = ppc_hash64_map_hptes(cpu, ptex, n_entries); 324 for (i = 0, ridx = 0; i < n_entries; i++) { 325 args[ridx++] = ppc_hash64_hpte0(cpu, hptes, i); 326 args[ridx++] = ppc_hash64_hpte1(cpu, hptes, i); 327 } 328 ppc_hash64_unmap_hptes(cpu, hptes, ptex, n_entries); 329 330 return H_SUCCESS; 331 } 332 333 struct SpaprPendingHpt { 334 /* These fields are read-only after initialization */ 335 int shift; 336 QemuThread thread; 337 338 /* These fields are protected by the BQL */ 339 bool complete; 340 341 /* These fields are private to the preparation thread if 342 * !complete, otherwise protected by the BQL */ 343 int ret; 344 void *hpt; 345 }; 346 347 static void free_pending_hpt(SpaprPendingHpt *pending) 348 { 349 if (pending->hpt) { 350 qemu_vfree(pending->hpt); 351 } 352 353 g_free(pending); 354 } 355 356 static void *hpt_prepare_thread(void *opaque) 357 { 358 SpaprPendingHpt *pending = opaque; 359 size_t size = 1ULL << pending->shift; 360 361 pending->hpt = qemu_memalign(size, size); 362 if (pending->hpt) { 363 memset(pending->hpt, 0, size); 364 pending->ret = H_SUCCESS; 365 } else { 366 pending->ret = H_NO_MEM; 367 } 368 369 qemu_mutex_lock_iothread(); 370 371 if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) { 372 /* Ready to go */ 373 pending->complete = true; 374 } else { 375 /* We've been cancelled, clean ourselves up */ 376 free_pending_hpt(pending); 377 } 378 379 qemu_mutex_unlock_iothread(); 380 return NULL; 381 } 382 383 /* Must be called with BQL held */ 384 static void cancel_hpt_prepare(SpaprMachineState *spapr) 385 { 386 SpaprPendingHpt *pending = spapr->pending_hpt; 387 388 /* Let the thread know it's cancelled */ 389 spapr->pending_hpt = NULL; 390 391 if (!pending) { 392 /* Nothing to do */ 393 return; 394 } 395 396 if (!pending->complete) { 397 /* thread will clean itself up */ 398 return; 399 } 400 401 free_pending_hpt(pending); 402 } 403 404 /* Convert a return code from the KVM ioctl()s implementing resize HPT 405 * into a PAPR hypercall return code */ 406 static target_ulong resize_hpt_convert_rc(int ret) 407 { 408 if (ret >= 100000) { 409 return H_LONG_BUSY_ORDER_100_SEC; 410 } else if (ret >= 10000) { 411 return H_LONG_BUSY_ORDER_10_SEC; 412 } else if (ret >= 1000) { 413 return H_LONG_BUSY_ORDER_1_SEC; 414 } else if (ret >= 100) { 415 return H_LONG_BUSY_ORDER_100_MSEC; 416 } else if (ret >= 10) { 417 return H_LONG_BUSY_ORDER_10_MSEC; 418 } else if (ret > 0) { 419 return H_LONG_BUSY_ORDER_1_MSEC; 420 } 421 422 switch (ret) { 423 case 0: 424 return H_SUCCESS; 425 case -EPERM: 426 return H_AUTHORITY; 427 case -EINVAL: 428 return H_PARAMETER; 429 case -ENXIO: 430 return H_CLOSED; 431 case -ENOSPC: 432 return H_PTEG_FULL; 433 case -EBUSY: 434 return H_BUSY; 435 case -ENOMEM: 436 return H_NO_MEM; 437 default: 438 return H_HARDWARE; 439 } 440 } 441 442 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 443 SpaprMachineState *spapr, 444 target_ulong opcode, 445 target_ulong *args) 446 { 447 target_ulong flags = args[0]; 448 int shift = args[1]; 449 SpaprPendingHpt *pending = spapr->pending_hpt; 450 uint64_t current_ram_size; 451 int rc; 452 453 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 454 return H_AUTHORITY; 455 } 456 457 if (!spapr->htab_shift) { 458 /* Radix guest, no HPT */ 459 return H_NOT_AVAILABLE; 460 } 461 462 trace_spapr_h_resize_hpt_prepare(flags, shift); 463 464 if (flags != 0) { 465 return H_PARAMETER; 466 } 467 468 if (shift && ((shift < 18) || (shift > 46))) { 469 return H_PARAMETER; 470 } 471 472 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 473 474 /* We only allow the guest to allocate an HPT one order above what 475 * we'd normally give them (to stop a small guest claiming a huge 476 * chunk of resources in the HPT */ 477 if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 478 return H_RESOURCE; 479 } 480 481 rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 482 if (rc != -ENOSYS) { 483 return resize_hpt_convert_rc(rc); 484 } 485 486 if (pending) { 487 /* something already in progress */ 488 if (pending->shift == shift) { 489 /* and it's suitable */ 490 if (pending->complete) { 491 return pending->ret; 492 } else { 493 return H_LONG_BUSY_ORDER_100_MSEC; 494 } 495 } 496 497 /* not suitable, cancel and replace */ 498 cancel_hpt_prepare(spapr); 499 } 500 501 if (!shift) { 502 /* nothing to do */ 503 return H_SUCCESS; 504 } 505 506 /* start new prepare */ 507 508 pending = g_new0(SpaprPendingHpt, 1); 509 pending->shift = shift; 510 pending->ret = H_HARDWARE; 511 512 qemu_thread_create(&pending->thread, "sPAPR HPT prepare", 513 hpt_prepare_thread, pending, QEMU_THREAD_DETACHED); 514 515 spapr->pending_hpt = pending; 516 517 /* In theory we could estimate the time more accurately based on 518 * the new size, but there's not much point */ 519 return H_LONG_BUSY_ORDER_100_MSEC; 520 } 521 522 static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot) 523 { 524 uint8_t *addr = htab; 525 526 addr += pteg * HASH_PTEG_SIZE_64; 527 addr += slot * HASH_PTE_SIZE_64; 528 return ldq_p(addr); 529 } 530 531 static void new_hpte_store(void *htab, uint64_t pteg, int slot, 532 uint64_t pte0, uint64_t pte1) 533 { 534 uint8_t *addr = htab; 535 536 addr += pteg * HASH_PTEG_SIZE_64; 537 addr += slot * HASH_PTE_SIZE_64; 538 539 stq_p(addr, pte0); 540 stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1); 541 } 542 543 static int rehash_hpte(PowerPCCPU *cpu, 544 const ppc_hash_pte64_t *hptes, 545 void *old_hpt, uint64_t oldsize, 546 void *new_hpt, uint64_t newsize, 547 uint64_t pteg, int slot) 548 { 549 uint64_t old_hash_mask = (oldsize >> 7) - 1; 550 uint64_t new_hash_mask = (newsize >> 7) - 1; 551 target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot); 552 target_ulong pte1; 553 uint64_t avpn; 554 unsigned base_pg_shift; 555 uint64_t hash, new_pteg, replace_pte0; 556 557 if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) { 558 return H_SUCCESS; 559 } 560 561 pte1 = ppc_hash64_hpte1(cpu, hptes, slot); 562 563 base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1); 564 assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */ 565 avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23); 566 567 if (pte0 & HPTE64_V_SECONDARY) { 568 pteg = ~pteg; 569 } 570 571 if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) { 572 uint64_t offset, vsid; 573 574 /* We only have 28 - 23 bits of offset in avpn */ 575 offset = (avpn & 0x1f) << 23; 576 vsid = avpn >> 5; 577 /* We can find more bits from the pteg value */ 578 if (base_pg_shift < 23) { 579 offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift; 580 } 581 582 hash = vsid ^ (offset >> base_pg_shift); 583 } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) { 584 uint64_t offset, vsid; 585 586 /* We only have 40 - 23 bits of seg_off in avpn */ 587 offset = (avpn & 0x1ffff) << 23; 588 vsid = avpn >> 17; 589 if (base_pg_shift < 23) { 590 offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask) 591 << base_pg_shift; 592 } 593 594 hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift); 595 } else { 596 error_report("rehash_pte: Bad segment size in HPTE"); 597 return H_HARDWARE; 598 } 599 600 new_pteg = hash & new_hash_mask; 601 if (pte0 & HPTE64_V_SECONDARY) { 602 assert(~pteg == (hash & old_hash_mask)); 603 new_pteg = ~new_pteg; 604 } else { 605 assert(pteg == (hash & old_hash_mask)); 606 } 607 assert((oldsize != newsize) || (pteg == new_pteg)); 608 replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot); 609 /* 610 * Strictly speaking, we don't need all these tests, since we only 611 * ever rehash bolted HPTEs. We might in future handle non-bolted 612 * HPTEs, though so make the logic correct for those cases as 613 * well. 614 */ 615 if (replace_pte0 & HPTE64_V_VALID) { 616 assert(newsize < oldsize); 617 if (replace_pte0 & HPTE64_V_BOLTED) { 618 if (pte0 & HPTE64_V_BOLTED) { 619 /* Bolted collision, nothing we can do */ 620 return H_PTEG_FULL; 621 } else { 622 /* Discard this hpte */ 623 return H_SUCCESS; 624 } 625 } 626 } 627 628 new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1); 629 return H_SUCCESS; 630 } 631 632 static int rehash_hpt(PowerPCCPU *cpu, 633 void *old_hpt, uint64_t oldsize, 634 void *new_hpt, uint64_t newsize) 635 { 636 uint64_t n_ptegs = oldsize >> 7; 637 uint64_t pteg; 638 int slot; 639 int rc; 640 641 for (pteg = 0; pteg < n_ptegs; pteg++) { 642 hwaddr ptex = pteg * HPTES_PER_GROUP; 643 const ppc_hash_pte64_t *hptes 644 = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 645 646 if (!hptes) { 647 return H_HARDWARE; 648 } 649 650 for (slot = 0; slot < HPTES_PER_GROUP; slot++) { 651 rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize, 652 pteg, slot); 653 if (rc != H_SUCCESS) { 654 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 655 return rc; 656 } 657 } 658 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 659 } 660 661 return H_SUCCESS; 662 } 663 664 static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 665 { 666 int ret; 667 668 cpu_synchronize_state(cs); 669 670 ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 671 if (ret < 0) { 672 error_report("failed to push sregs to KVM: %s", strerror(-ret)); 673 exit(1); 674 } 675 } 676 677 static void push_sregs_to_kvm_pr(SpaprMachineState *spapr) 678 { 679 CPUState *cs; 680 681 /* 682 * This is a hack for the benefit of KVM PR - it abuses the SDR1 683 * slot in kvm_sregs to communicate the userspace address of the 684 * HPT 685 */ 686 if (!kvm_enabled() || !spapr->htab) { 687 return; 688 } 689 690 CPU_FOREACH(cs) { 691 run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 692 } 693 } 694 695 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 696 SpaprMachineState *spapr, 697 target_ulong opcode, 698 target_ulong *args) 699 { 700 target_ulong flags = args[0]; 701 target_ulong shift = args[1]; 702 SpaprPendingHpt *pending = spapr->pending_hpt; 703 int rc; 704 size_t newsize; 705 706 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 707 return H_AUTHORITY; 708 } 709 710 if (!spapr->htab_shift) { 711 /* Radix guest, no HPT */ 712 return H_NOT_AVAILABLE; 713 } 714 715 trace_spapr_h_resize_hpt_commit(flags, shift); 716 717 rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 718 if (rc != -ENOSYS) { 719 rc = resize_hpt_convert_rc(rc); 720 if (rc == H_SUCCESS) { 721 /* Need to set the new htab_shift in the machine state */ 722 spapr->htab_shift = shift; 723 } 724 return rc; 725 } 726 727 if (flags != 0) { 728 return H_PARAMETER; 729 } 730 731 if (!pending || (pending->shift != shift)) { 732 /* no matching prepare */ 733 return H_CLOSED; 734 } 735 736 if (!pending->complete) { 737 /* prepare has not completed */ 738 return H_BUSY; 739 } 740 741 /* Shouldn't have got past PREPARE without an HPT */ 742 g_assert(spapr->htab_shift); 743 744 newsize = 1ULL << pending->shift; 745 rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr), 746 pending->hpt, newsize); 747 if (rc == H_SUCCESS) { 748 qemu_vfree(spapr->htab); 749 spapr->htab = pending->hpt; 750 spapr->htab_shift = pending->shift; 751 752 push_sregs_to_kvm_pr(spapr); 753 754 pending->hpt = NULL; /* so it's not free()d */ 755 } 756 757 /* Clean up */ 758 spapr->pending_hpt = NULL; 759 free_pending_hpt(pending); 760 761 return rc; 762 } 763 764 static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, 765 target_ulong opcode, target_ulong *args) 766 { 767 cpu_synchronize_state(CPU(cpu)); 768 cpu->env.spr[SPR_SPRG0] = args[0]; 769 770 return H_SUCCESS; 771 } 772 773 static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 774 target_ulong opcode, target_ulong *args) 775 { 776 if (!has_spr(cpu, SPR_DABR)) { 777 return H_HARDWARE; /* DABR register not available */ 778 } 779 cpu_synchronize_state(CPU(cpu)); 780 781 if (has_spr(cpu, SPR_DABRX)) { 782 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 783 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 784 return H_RESERVED_DABR; 785 } 786 787 cpu->env.spr[SPR_DABR] = args[0]; 788 return H_SUCCESS; 789 } 790 791 static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 792 target_ulong opcode, target_ulong *args) 793 { 794 target_ulong dabrx = args[1]; 795 796 if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { 797 return H_HARDWARE; 798 } 799 800 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 801 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 802 return H_PARAMETER; 803 } 804 805 cpu_synchronize_state(CPU(cpu)); 806 cpu->env.spr[SPR_DABRX] = dabrx; 807 cpu->env.spr[SPR_DABR] = args[0]; 808 809 return H_SUCCESS; 810 } 811 812 static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, 813 target_ulong opcode, target_ulong *args) 814 { 815 target_ulong flags = args[0]; 816 hwaddr dst = args[1]; 817 hwaddr src = args[2]; 818 hwaddr len = TARGET_PAGE_SIZE; 819 uint8_t *pdst, *psrc; 820 target_long ret = H_SUCCESS; 821 822 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 823 | H_COPY_PAGE | H_ZERO_PAGE)) { 824 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 825 flags); 826 return H_PARAMETER; 827 } 828 829 /* Map-in destination */ 830 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 831 return H_PARAMETER; 832 } 833 pdst = cpu_physical_memory_map(dst, &len, 1); 834 if (!pdst || len != TARGET_PAGE_SIZE) { 835 return H_PARAMETER; 836 } 837 838 if (flags & H_COPY_PAGE) { 839 /* Map-in source, copy to destination, and unmap source again */ 840 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 841 ret = H_PARAMETER; 842 goto unmap_out; 843 } 844 psrc = cpu_physical_memory_map(src, &len, 0); 845 if (!psrc || len != TARGET_PAGE_SIZE) { 846 ret = H_PARAMETER; 847 goto unmap_out; 848 } 849 memcpy(pdst, psrc, len); 850 cpu_physical_memory_unmap(psrc, len, 0, len); 851 } else if (flags & H_ZERO_PAGE) { 852 memset(pdst, 0, len); /* Just clear the destination page */ 853 } 854 855 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 856 kvmppc_dcbst_range(cpu, pdst, len); 857 } 858 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 859 if (kvm_enabled()) { 860 kvmppc_icbi_range(cpu, pdst, len); 861 } else { 862 tb_flush(CPU(cpu)); 863 } 864 } 865 866 unmap_out: 867 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 868 return ret; 869 } 870 871 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 872 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 873 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 874 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 875 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 876 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 877 878 #define VPA_MIN_SIZE 640 879 #define VPA_SIZE_OFFSET 0x4 880 #define VPA_SHARED_PROC_OFFSET 0x9 881 #define VPA_SHARED_PROC_VAL 0x2 882 883 static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) 884 { 885 CPUState *cs = CPU(cpu); 886 CPUPPCState *env = &cpu->env; 887 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 888 uint16_t size; 889 uint8_t tmp; 890 891 if (vpa == 0) { 892 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 893 return H_HARDWARE; 894 } 895 896 if (vpa % env->dcache_line_size) { 897 return H_PARAMETER; 898 } 899 /* FIXME: bounds check the address */ 900 901 size = lduw_be_phys(cs->as, vpa + 0x4); 902 903 if (size < VPA_MIN_SIZE) { 904 return H_PARAMETER; 905 } 906 907 /* VPA is not allowed to cross a page boundary */ 908 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 909 return H_PARAMETER; 910 } 911 912 spapr_cpu->vpa_addr = vpa; 913 914 tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET); 915 tmp |= VPA_SHARED_PROC_VAL; 916 stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 917 918 return H_SUCCESS; 919 } 920 921 static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) 922 { 923 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 924 925 if (spapr_cpu->slb_shadow_addr) { 926 return H_RESOURCE; 927 } 928 929 if (spapr_cpu->dtl_addr) { 930 return H_RESOURCE; 931 } 932 933 spapr_cpu->vpa_addr = 0; 934 return H_SUCCESS; 935 } 936 937 static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 938 { 939 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 940 uint32_t size; 941 942 if (addr == 0) { 943 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 944 return H_HARDWARE; 945 } 946 947 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 948 if (size < 0x8) { 949 return H_PARAMETER; 950 } 951 952 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 953 return H_PARAMETER; 954 } 955 956 if (!spapr_cpu->vpa_addr) { 957 return H_RESOURCE; 958 } 959 960 spapr_cpu->slb_shadow_addr = addr; 961 spapr_cpu->slb_shadow_size = size; 962 963 return H_SUCCESS; 964 } 965 966 static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 967 { 968 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 969 970 spapr_cpu->slb_shadow_addr = 0; 971 spapr_cpu->slb_shadow_size = 0; 972 return H_SUCCESS; 973 } 974 975 static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) 976 { 977 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 978 uint32_t size; 979 980 if (addr == 0) { 981 hcall_dprintf("Can't cope with DTL at logical 0\n"); 982 return H_HARDWARE; 983 } 984 985 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 986 987 if (size < 48) { 988 return H_PARAMETER; 989 } 990 991 if (!spapr_cpu->vpa_addr) { 992 return H_RESOURCE; 993 } 994 995 spapr_cpu->dtl_addr = addr; 996 spapr_cpu->dtl_size = size; 997 998 return H_SUCCESS; 999 } 1000 1001 static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) 1002 { 1003 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1004 1005 spapr_cpu->dtl_addr = 0; 1006 spapr_cpu->dtl_size = 0; 1007 1008 return H_SUCCESS; 1009 } 1010 1011 static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr, 1012 target_ulong opcode, target_ulong *args) 1013 { 1014 target_ulong flags = args[0]; 1015 target_ulong procno = args[1]; 1016 target_ulong vpa = args[2]; 1017 target_ulong ret = H_PARAMETER; 1018 PowerPCCPU *tcpu; 1019 1020 tcpu = spapr_find_cpu(procno); 1021 if (!tcpu) { 1022 return H_PARAMETER; 1023 } 1024 1025 switch (flags) { 1026 case FLAGS_REGISTER_VPA: 1027 ret = register_vpa(tcpu, vpa); 1028 break; 1029 1030 case FLAGS_DEREGISTER_VPA: 1031 ret = deregister_vpa(tcpu, vpa); 1032 break; 1033 1034 case FLAGS_REGISTER_SLBSHADOW: 1035 ret = register_slb_shadow(tcpu, vpa); 1036 break; 1037 1038 case FLAGS_DEREGISTER_SLBSHADOW: 1039 ret = deregister_slb_shadow(tcpu, vpa); 1040 break; 1041 1042 case FLAGS_REGISTER_DTL: 1043 ret = register_dtl(tcpu, vpa); 1044 break; 1045 1046 case FLAGS_DEREGISTER_DTL: 1047 ret = deregister_dtl(tcpu, vpa); 1048 break; 1049 } 1050 1051 return ret; 1052 } 1053 1054 static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, 1055 target_ulong opcode, target_ulong *args) 1056 { 1057 CPUPPCState *env = &cpu->env; 1058 CPUState *cs = CPU(cpu); 1059 1060 env->msr |= (1ULL << MSR_EE); 1061 hreg_compute_hflags(env); 1062 if (!cpu_has_work(cs)) { 1063 cs->halted = 1; 1064 cs->exception_index = EXCP_HLT; 1065 cs->exit_request = 1; 1066 } 1067 return H_SUCCESS; 1068 } 1069 1070 static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, 1071 target_ulong opcode, target_ulong *args) 1072 { 1073 target_ulong rtas_r3 = args[0]; 1074 uint32_t token = rtas_ld(rtas_r3, 0); 1075 uint32_t nargs = rtas_ld(rtas_r3, 1); 1076 uint32_t nret = rtas_ld(rtas_r3, 2); 1077 1078 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 1079 nret, rtas_r3 + 12 + 4*nargs); 1080 } 1081 1082 static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr, 1083 target_ulong opcode, target_ulong *args) 1084 { 1085 CPUState *cs = CPU(cpu); 1086 target_ulong size = args[0]; 1087 target_ulong addr = args[1]; 1088 1089 switch (size) { 1090 case 1: 1091 args[0] = ldub_phys(cs->as, addr); 1092 return H_SUCCESS; 1093 case 2: 1094 args[0] = lduw_phys(cs->as, addr); 1095 return H_SUCCESS; 1096 case 4: 1097 args[0] = ldl_phys(cs->as, addr); 1098 return H_SUCCESS; 1099 case 8: 1100 args[0] = ldq_phys(cs->as, addr); 1101 return H_SUCCESS; 1102 } 1103 return H_PARAMETER; 1104 } 1105 1106 static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr, 1107 target_ulong opcode, target_ulong *args) 1108 { 1109 CPUState *cs = CPU(cpu); 1110 1111 target_ulong size = args[0]; 1112 target_ulong addr = args[1]; 1113 target_ulong val = args[2]; 1114 1115 switch (size) { 1116 case 1: 1117 stb_phys(cs->as, addr, val); 1118 return H_SUCCESS; 1119 case 2: 1120 stw_phys(cs->as, addr, val); 1121 return H_SUCCESS; 1122 case 4: 1123 stl_phys(cs->as, addr, val); 1124 return H_SUCCESS; 1125 case 8: 1126 stq_phys(cs->as, addr, val); 1127 return H_SUCCESS; 1128 } 1129 return H_PARAMETER; 1130 } 1131 1132 static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr, 1133 target_ulong opcode, target_ulong *args) 1134 { 1135 CPUState *cs = CPU(cpu); 1136 1137 target_ulong dst = args[0]; /* Destination address */ 1138 target_ulong src = args[1]; /* Source address */ 1139 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 1140 target_ulong count = args[3]; /* Element count */ 1141 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 1142 uint64_t tmp; 1143 unsigned int mask = (1 << esize) - 1; 1144 int step = 1 << esize; 1145 1146 if (count > 0x80000000) { 1147 return H_PARAMETER; 1148 } 1149 1150 if ((dst & mask) || (src & mask) || (op > 1)) { 1151 return H_PARAMETER; 1152 } 1153 1154 if (dst >= src && dst < (src + (count << esize))) { 1155 dst = dst + ((count - 1) << esize); 1156 src = src + ((count - 1) << esize); 1157 step = -step; 1158 } 1159 1160 while (count--) { 1161 switch (esize) { 1162 case 0: 1163 tmp = ldub_phys(cs->as, src); 1164 break; 1165 case 1: 1166 tmp = lduw_phys(cs->as, src); 1167 break; 1168 case 2: 1169 tmp = ldl_phys(cs->as, src); 1170 break; 1171 case 3: 1172 tmp = ldq_phys(cs->as, src); 1173 break; 1174 default: 1175 return H_PARAMETER; 1176 } 1177 if (op == 1) { 1178 tmp = ~tmp; 1179 } 1180 switch (esize) { 1181 case 0: 1182 stb_phys(cs->as, dst, tmp); 1183 break; 1184 case 1: 1185 stw_phys(cs->as, dst, tmp); 1186 break; 1187 case 2: 1188 stl_phys(cs->as, dst, tmp); 1189 break; 1190 case 3: 1191 stq_phys(cs->as, dst, tmp); 1192 break; 1193 } 1194 dst = dst + step; 1195 src = src + step; 1196 } 1197 1198 return H_SUCCESS; 1199 } 1200 1201 static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr, 1202 target_ulong opcode, target_ulong *args) 1203 { 1204 /* Nothing to do on emulation, KVM will trap this in the kernel */ 1205 return H_SUCCESS; 1206 } 1207 1208 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, 1209 target_ulong opcode, target_ulong *args) 1210 { 1211 /* Nothing to do on emulation, KVM will trap this in the kernel */ 1212 return H_SUCCESS; 1213 } 1214 1215 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 1216 target_ulong mflags, 1217 target_ulong value1, 1218 target_ulong value2) 1219 { 1220 if (value1) { 1221 return H_P3; 1222 } 1223 if (value2) { 1224 return H_P4; 1225 } 1226 1227 switch (mflags) { 1228 case H_SET_MODE_ENDIAN_BIG: 1229 spapr_set_all_lpcrs(0, LPCR_ILE); 1230 spapr_pci_switch_vga(true); 1231 return H_SUCCESS; 1232 1233 case H_SET_MODE_ENDIAN_LITTLE: 1234 spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); 1235 spapr_pci_switch_vga(false); 1236 return H_SUCCESS; 1237 } 1238 1239 return H_UNSUPPORTED_FLAG; 1240 } 1241 1242 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 1243 target_ulong mflags, 1244 target_ulong value1, 1245 target_ulong value2) 1246 { 1247 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 1248 1249 if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 1250 return H_P2; 1251 } 1252 if (value1) { 1253 return H_P3; 1254 } 1255 if (value2) { 1256 return H_P4; 1257 } 1258 1259 if (mflags == AIL_RESERVED) { 1260 return H_UNSUPPORTED_FLAG; 1261 } 1262 1263 spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); 1264 1265 return H_SUCCESS; 1266 } 1267 1268 static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, 1269 target_ulong opcode, target_ulong *args) 1270 { 1271 target_ulong resource = args[1]; 1272 target_ulong ret = H_P2; 1273 1274 switch (resource) { 1275 case H_SET_MODE_RESOURCE_LE: 1276 ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); 1277 break; 1278 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 1279 ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 1280 args[2], args[3]); 1281 break; 1282 } 1283 1284 return ret; 1285 } 1286 1287 static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, 1288 target_ulong opcode, target_ulong *args) 1289 { 1290 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1291 opcode, " (H_CLEAN_SLB)"); 1292 return H_FUNCTION; 1293 } 1294 1295 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr, 1296 target_ulong opcode, target_ulong *args) 1297 { 1298 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1299 opcode, " (H_INVALIDATE_PID)"); 1300 return H_FUNCTION; 1301 } 1302 1303 static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, 1304 uint64_t patbe_old, uint64_t patbe_new) 1305 { 1306 /* 1307 * We have 4 Options: 1308 * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 1309 * HASH->RADIX : Free HPT 1310 * RADIX->HASH : Allocate HPT 1311 * NOTHING->HASH : Allocate HPT 1312 * Note: NOTHING implies the case where we said the guest could choose 1313 * later and so assumed radix and now it's called H_REG_PROC_TBL 1314 */ 1315 1316 if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) { 1317 /* We assume RADIX, so this catches all the "Do Nothing" cases */ 1318 } else if (!(patbe_old & PATE1_GR)) { 1319 /* HASH->RADIX : Free HPT */ 1320 spapr_free_hpt(spapr); 1321 } else if (!(patbe_new & PATE1_GR)) { 1322 /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 1323 spapr_setup_hpt_and_vrma(spapr); 1324 } 1325 return; 1326 } 1327 1328 #define FLAGS_MASK 0x01FULL 1329 #define FLAG_MODIFY 0x10 1330 #define FLAG_REGISTER 0x08 1331 #define FLAG_RADIX 0x04 1332 #define FLAG_HASH_PROC_TBL 0x02 1333 #define FLAG_GTSE 0x01 1334 1335 static target_ulong h_register_process_table(PowerPCCPU *cpu, 1336 SpaprMachineState *spapr, 1337 target_ulong opcode, 1338 target_ulong *args) 1339 { 1340 target_ulong flags = args[0]; 1341 target_ulong proc_tbl = args[1]; 1342 target_ulong page_size = args[2]; 1343 target_ulong table_size = args[3]; 1344 target_ulong update_lpcr = 0; 1345 uint64_t cproc; 1346 1347 if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 1348 return H_PARAMETER; 1349 } 1350 if (flags & FLAG_MODIFY) { 1351 if (flags & FLAG_REGISTER) { 1352 if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 1353 if (proc_tbl & 0xfff || proc_tbl >> 60) { 1354 return H_P2; 1355 } else if (page_size) { 1356 return H_P3; 1357 } else if (table_size > 24) { 1358 return H_P4; 1359 } 1360 cproc = PATE1_GR | proc_tbl | table_size; 1361 } else { /* Register new HPT process table */ 1362 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 1363 /* TODO - Not Supported */ 1364 /* Technically caused by flag bits => H_PARAMETER */ 1365 return H_PARAMETER; 1366 } else { /* Hash with SLB */ 1367 if (proc_tbl >> 38) { 1368 return H_P2; 1369 } else if (page_size & ~0x7) { 1370 return H_P3; 1371 } else if (table_size > 24) { 1372 return H_P4; 1373 } 1374 } 1375 cproc = (proc_tbl << 25) | page_size << 5 | table_size; 1376 } 1377 1378 } else { /* Deregister current process table */ 1379 /* 1380 * Set to benign value: (current GR) | 0. This allows 1381 * deregistration in KVM to succeed even if the radix bit 1382 * in flags doesn't match the radix bit in the old PATE. 1383 */ 1384 cproc = spapr->patb_entry & PATE1_GR; 1385 } 1386 } else { /* Maintain current registration */ 1387 if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) { 1388 /* Technically caused by flag bits => H_PARAMETER */ 1389 return H_PARAMETER; /* Existing Process Table Mismatch */ 1390 } 1391 cproc = spapr->patb_entry; 1392 } 1393 1394 /* Check if we need to setup OR free the hpt */ 1395 spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 1396 1397 spapr->patb_entry = cproc; /* Save new process table */ 1398 1399 /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ 1400 if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */ 1401 update_lpcr |= (LPCR_UPRT | LPCR_HR); 1402 else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ 1403 update_lpcr |= LPCR_UPRT; 1404 if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ 1405 update_lpcr |= LPCR_GTSE; 1406 1407 spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); 1408 1409 if (kvm_enabled()) { 1410 return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1411 flags & FLAG_GTSE, cproc); 1412 } 1413 return H_SUCCESS; 1414 } 1415 1416 #define H_SIGNAL_SYS_RESET_ALL -1 1417 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 1418 1419 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1420 SpaprMachineState *spapr, 1421 target_ulong opcode, target_ulong *args) 1422 { 1423 target_long target = args[0]; 1424 CPUState *cs; 1425 1426 if (target < 0) { 1427 /* Broadcast */ 1428 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1429 return H_PARAMETER; 1430 } 1431 1432 CPU_FOREACH(cs) { 1433 PowerPCCPU *c = POWERPC_CPU(cs); 1434 1435 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1436 if (c == cpu) { 1437 continue; 1438 } 1439 } 1440 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1441 } 1442 return H_SUCCESS; 1443 1444 } else { 1445 /* Unicast */ 1446 cs = CPU(spapr_find_cpu(target)); 1447 if (cs) { 1448 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1449 return H_SUCCESS; 1450 } 1451 return H_PARAMETER; 1452 } 1453 } 1454 1455 static uint32_t cas_check_pvr(SpaprMachineState *spapr, PowerPCCPU *cpu, 1456 target_ulong *addr, bool *raw_mode_supported, 1457 Error **errp) 1458 { 1459 bool explicit_match = false; /* Matched the CPU's real PVR */ 1460 uint32_t max_compat = spapr->max_compat_pvr; 1461 uint32_t best_compat = 0; 1462 int i; 1463 1464 /* 1465 * We scan the supplied table of PVRs looking for two things 1466 * 1. Is our real CPU PVR in the list? 1467 * 2. What's the "best" listed logical PVR 1468 */ 1469 for (i = 0; i < 512; ++i) { 1470 uint32_t pvr, pvr_mask; 1471 1472 pvr_mask = ldl_be_phys(&address_space_memory, *addr); 1473 pvr = ldl_be_phys(&address_space_memory, *addr + 4); 1474 *addr += 8; 1475 1476 if (~pvr_mask & pvr) { 1477 break; /* Terminator record */ 1478 } 1479 1480 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1481 explicit_match = true; 1482 } else { 1483 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1484 best_compat = pvr; 1485 } 1486 } 1487 } 1488 1489 if ((best_compat == 0) && (!explicit_match || max_compat)) { 1490 /* We couldn't find a suitable compatibility mode, and either 1491 * the guest doesn't support "raw" mode for this CPU, or raw 1492 * mode is disabled because a maximum compat mode is set */ 1493 error_setg(errp, "Couldn't negotiate a suitable PVR during CAS"); 1494 return 0; 1495 } 1496 1497 *raw_mode_supported = explicit_match; 1498 1499 /* Parsing finished */ 1500 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 1501 1502 return best_compat; 1503 } 1504 1505 static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1506 SpaprMachineState *spapr, 1507 target_ulong opcode, 1508 target_ulong *args) 1509 { 1510 /* Working address in data buffer */ 1511 target_ulong addr = ppc64_phys_to_real(args[0]); 1512 target_ulong ov_table; 1513 uint32_t cas_pvr; 1514 SpaprOptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates; 1515 bool guest_radix; 1516 Error *local_err = NULL; 1517 bool raw_mode_supported = false; 1518 bool guest_xive; 1519 1520 cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err); 1521 if (local_err) { 1522 error_report_err(local_err); 1523 return H_HARDWARE; 1524 } 1525 1526 /* Update CPUs */ 1527 if (cpu->compat_pvr != cas_pvr) { 1528 ppc_set_compat_all(cas_pvr, &local_err); 1529 if (local_err) { 1530 /* We fail to set compat mode (likely because running with KVM PR), 1531 * but maybe we can fallback to raw mode if the guest supports it. 1532 */ 1533 if (!raw_mode_supported) { 1534 error_report_err(local_err); 1535 return H_HARDWARE; 1536 } 1537 error_free(local_err); 1538 local_err = NULL; 1539 } 1540 } 1541 1542 /* For the future use: here @ov_table points to the first option vector */ 1543 ov_table = addr; 1544 1545 ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1546 ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1547 if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 1548 error_report("guest requested hash and radix MMU, which is invalid."); 1549 exit(EXIT_FAILURE); 1550 } 1551 if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { 1552 error_report("guest requested an invalid interrupt mode"); 1553 exit(EXIT_FAILURE); 1554 } 1555 1556 /* The radix/hash bit in byte 24 requires special handling: */ 1557 guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 1558 spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300); 1559 1560 guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); 1561 1562 /* 1563 * HPT resizing is a bit of a special case, because when enabled 1564 * we assume an HPT guest will support it until it says it 1565 * doesn't, instead of assuming it won't support it until it says 1566 * it does. Strictly speaking that approach could break for 1567 * guests which don't make a CAS call, but those are so old we 1568 * don't care about them. Without that assumption we'd have to 1569 * make at least a temporary allocation of an HPT sized for max 1570 * memory, which could be impossibly difficult under KVM HV if 1571 * maxram is large. 1572 */ 1573 if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 1574 int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1575 1576 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 1577 error_report( 1578 "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 1579 exit(1); 1580 } 1581 1582 if (spapr->htab_shift < maxshift) { 1583 /* Guest doesn't know about HPT resizing, so we 1584 * pre-emptively resize for the maximum permitted RAM. At 1585 * the point this is called, nothing should have been 1586 * entered into the existing HPT */ 1587 spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 1588 push_sregs_to_kvm_pr(spapr); 1589 } 1590 } 1591 1592 /* NOTE: there are actually a number of ov5 bits where input from the 1593 * guest is always zero, and the platform/QEMU enables them independently 1594 * of guest input. To model these properly we'd want some sort of mask, 1595 * but since they only currently apply to memory migration as defined 1596 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 1597 * to worry about this for now. 1598 */ 1599 ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); 1600 1601 /* also clear the radix/hash bit from the current ov5_cas bits to 1602 * be in sync with the newly ov5 bits. Else the radix bit will be 1603 * seen as being removed and this will generate a reset loop 1604 */ 1605 spapr_ovec_clear(ov5_cas_old, OV5_MMU_RADIX_300); 1606 1607 /* full range of negotiated ov5 capabilities */ 1608 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1609 spapr_ovec_cleanup(ov5_guest); 1610 /* capabilities that have been added since CAS-generated guest reset. 1611 * if capabilities have since been removed, generate another reset 1612 */ 1613 ov5_updates = spapr_ovec_new(); 1614 spapr->cas_reboot = spapr_ovec_diff(ov5_updates, 1615 ov5_cas_old, spapr->ov5_cas); 1616 /* Now that processing is finished, set the radix/hash bit for the 1617 * guest if it requested a valid mode; otherwise terminate the boot. */ 1618 if (guest_radix) { 1619 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1620 error_report("Guest requested unavailable MMU mode (radix)."); 1621 exit(EXIT_FAILURE); 1622 } 1623 spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300); 1624 } else { 1625 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1626 && !kvmppc_has_cap_mmu_hash_v3()) { 1627 error_report("Guest requested unavailable MMU mode (hash)."); 1628 exit(EXIT_FAILURE); 1629 } 1630 } 1631 spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest, 1632 OV1_PPC_3_00); 1633 if (!spapr->cas_reboot) { 1634 /* If spapr_machine_reset() did not set up a HPT but one is necessary 1635 * (because the guest isn't going to use radix) then set it up here. */ 1636 if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { 1637 /* legacy hash or new hash: */ 1638 spapr_setup_hpt_and_vrma(spapr); 1639 } 1640 spapr->cas_reboot = 1641 (spapr_h_cas_compose_response(spapr, args[1], args[2], 1642 ov5_updates) != 0); 1643 } 1644 1645 /* 1646 * Ensure the guest asks for an interrupt mode we support; otherwise 1647 * terminate the boot. 1648 */ 1649 if (guest_xive) { 1650 if (spapr->irq->ov5 == SPAPR_OV5_XIVE_LEGACY) { 1651 error_report( 1652 "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property"); 1653 exit(EXIT_FAILURE); 1654 } 1655 } else { 1656 if (spapr->irq->ov5 == SPAPR_OV5_XIVE_EXPLOIT) { 1657 error_report( 1658 "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual"); 1659 exit(EXIT_FAILURE); 1660 } 1661 } 1662 1663 /* 1664 * Generate a machine reset when we have an update of the 1665 * interrupt mode. Only required when the machine supports both 1666 * modes. 1667 */ 1668 if (!spapr->cas_reboot) { 1669 spapr->cas_reboot = spapr_ovec_test(ov5_updates, OV5_XIVE_EXPLOIT) 1670 && spapr->irq->ov5 & SPAPR_OV5_XIVE_BOTH; 1671 } 1672 1673 spapr_ovec_cleanup(ov5_updates); 1674 1675 if (spapr->cas_reboot) { 1676 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1677 } 1678 1679 return H_SUCCESS; 1680 } 1681 1682 static target_ulong h_home_node_associativity(PowerPCCPU *cpu, 1683 SpaprMachineState *spapr, 1684 target_ulong opcode, 1685 target_ulong *args) 1686 { 1687 target_ulong flags = args[0]; 1688 target_ulong procno = args[1]; 1689 PowerPCCPU *tcpu; 1690 int idx; 1691 1692 /* only support procno from H_REGISTER_VPA */ 1693 if (flags != 0x1) { 1694 return H_FUNCTION; 1695 } 1696 1697 tcpu = spapr_find_cpu(procno); 1698 if (tcpu == NULL) { 1699 return H_P2; 1700 } 1701 1702 /* sequence is the same as in the "ibm,associativity" property */ 1703 1704 idx = 0; 1705 #define ASSOCIATIVITY(a, b) (((uint64_t)(a) << 32) | \ 1706 ((uint64_t)(b) & 0xffffffff)) 1707 args[idx++] = ASSOCIATIVITY(0, 0); 1708 args[idx++] = ASSOCIATIVITY(0, tcpu->node_id); 1709 args[idx++] = ASSOCIATIVITY(procno, -1); 1710 for ( ; idx < 6; idx++) { 1711 args[idx] = -1; 1712 } 1713 #undef ASSOCIATIVITY 1714 1715 return H_SUCCESS; 1716 } 1717 1718 static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1719 SpaprMachineState *spapr, 1720 target_ulong opcode, 1721 target_ulong *args) 1722 { 1723 uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1724 ~H_CPU_CHAR_THR_RECONF_TRIG; 1725 uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1726 uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1727 uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1728 uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 1729 uint8_t count_cache_flush_assist = spapr_get_cap(spapr, 1730 SPAPR_CAP_CCF_ASSIST); 1731 1732 switch (safe_cache) { 1733 case SPAPR_CAP_WORKAROUND: 1734 characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1735 characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1736 characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1737 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1738 break; 1739 case SPAPR_CAP_FIXED: 1740 break; 1741 default: /* broken */ 1742 assert(safe_cache == SPAPR_CAP_BROKEN); 1743 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1744 break; 1745 } 1746 1747 switch (safe_bounds_check) { 1748 case SPAPR_CAP_WORKAROUND: 1749 characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1750 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1751 break; 1752 case SPAPR_CAP_FIXED: 1753 break; 1754 default: /* broken */ 1755 assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1756 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1757 break; 1758 } 1759 1760 switch (safe_indirect_branch) { 1761 case SPAPR_CAP_FIXED_NA: 1762 break; 1763 case SPAPR_CAP_FIXED_CCD: 1764 characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; 1765 break; 1766 case SPAPR_CAP_FIXED_IBS: 1767 characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1768 break; 1769 case SPAPR_CAP_WORKAROUND: 1770 behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE; 1771 if (count_cache_flush_assist) { 1772 characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST; 1773 } 1774 break; 1775 default: /* broken */ 1776 assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1777 break; 1778 } 1779 1780 args[0] = characteristics; 1781 args[1] = behaviour; 1782 return H_SUCCESS; 1783 } 1784 1785 static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, 1786 target_ulong opcode, target_ulong *args) 1787 { 1788 target_ulong dt = ppc64_phys_to_real(args[0]); 1789 struct fdt_header hdr = { 0 }; 1790 unsigned cb; 1791 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1792 void *fdt; 1793 1794 cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); 1795 cb = fdt32_to_cpu(hdr.totalsize); 1796 1797 if (!smc->update_dt_enabled) { 1798 return H_SUCCESS; 1799 } 1800 1801 /* Check that the fdt did not grow out of proportion */ 1802 if (cb > spapr->fdt_initial_size * 2) { 1803 trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, 1804 fdt32_to_cpu(hdr.magic)); 1805 return H_PARAMETER; 1806 } 1807 1808 fdt = g_malloc0(cb); 1809 cpu_physical_memory_read(dt, fdt, cb); 1810 1811 /* Check the fdt consistency */ 1812 if (fdt_check_full(fdt, cb)) { 1813 trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, 1814 fdt32_to_cpu(hdr.magic)); 1815 return H_PARAMETER; 1816 } 1817 1818 g_free(spapr->fdt_blob); 1819 spapr->fdt_size = cb; 1820 spapr->fdt_blob = fdt; 1821 trace_spapr_update_dt(cb); 1822 1823 return H_SUCCESS; 1824 } 1825 1826 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 1827 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 1828 1829 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 1830 { 1831 spapr_hcall_fn *slot; 1832 1833 if (opcode <= MAX_HCALL_OPCODE) { 1834 assert((opcode & 0x3) == 0); 1835 1836 slot = &papr_hypercall_table[opcode / 4]; 1837 } else { 1838 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1839 1840 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1841 } 1842 1843 assert(!(*slot)); 1844 *slot = fn; 1845 } 1846 1847 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 1848 target_ulong *args) 1849 { 1850 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1851 1852 if ((opcode <= MAX_HCALL_OPCODE) 1853 && ((opcode & 0x3) == 0)) { 1854 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 1855 1856 if (fn) { 1857 return fn(cpu, spapr, opcode, args); 1858 } 1859 } else if ((opcode >= KVMPPC_HCALL_BASE) && 1860 (opcode <= KVMPPC_HCALL_MAX)) { 1861 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1862 1863 if (fn) { 1864 return fn(cpu, spapr, opcode, args); 1865 } 1866 } 1867 1868 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1869 opcode); 1870 return H_FUNCTION; 1871 } 1872 1873 static void hypercall_register_types(void) 1874 { 1875 /* hcall-pft */ 1876 spapr_register_hypercall(H_ENTER, h_enter); 1877 spapr_register_hypercall(H_REMOVE, h_remove); 1878 spapr_register_hypercall(H_PROTECT, h_protect); 1879 spapr_register_hypercall(H_READ, h_read); 1880 1881 /* hcall-bulk */ 1882 spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 1883 1884 /* hcall-hpt-resize */ 1885 spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 1886 spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 1887 1888 /* hcall-splpar */ 1889 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 1890 spapr_register_hypercall(H_CEDE, h_cede); 1891 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 1892 1893 /* processor register resource access h-calls */ 1894 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1895 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1896 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 1897 spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1898 spapr_register_hypercall(H_SET_MODE, h_set_mode); 1899 1900 /* In Memory Table MMU h-calls */ 1901 spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1902 spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1903 spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1904 1905 /* hcall-get-cpu-characteristics */ 1906 spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 1907 h_get_cpu_characteristics); 1908 1909 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 1910 * here between the "CI" and the "CACHE" variants, they will use whatever 1911 * mapping attributes qemu is using. When using KVM, the kernel will 1912 * enforce the attributes more strongly 1913 */ 1914 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 1915 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 1916 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 1917 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 1918 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 1919 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 1920 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 1921 1922 /* qemu/KVM-PPC specific hcalls */ 1923 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 1924 1925 /* ibm,client-architecture-support support */ 1926 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1927 1928 spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); 1929 1930 /* Virtual Processor Home Node */ 1931 spapr_register_hypercall(H_HOME_NODE_ASSOCIATIVITY, 1932 h_home_node_associativity); 1933 } 1934 1935 type_init(hypercall_register_types) 1936