1 #include "qemu/osdep.h" 2 #include "qapi/error.h" 3 #include "sysemu/hw_accel.h" 4 #include "sysemu/sysemu.h" 5 #include "qemu/log.h" 6 #include "qemu/error-report.h" 7 #include "cpu.h" 8 #include "exec/exec-all.h" 9 #include "helper_regs.h" 10 #include "hw/ppc/spapr.h" 11 #include "mmu-hash64.h" 12 #include "cpu-models.h" 13 #include "trace.h" 14 #include "kvm_ppc.h" 15 #include "hw/ppc/spapr_ovec.h" 16 #include "mmu-book3s-v3.h" 17 #include "hw/mem/memory-device.h" 18 19 struct LPCRSyncState { 20 target_ulong value; 21 target_ulong mask; 22 }; 23 24 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 25 { 26 struct LPCRSyncState *s = arg.host_ptr; 27 PowerPCCPU *cpu = POWERPC_CPU(cs); 28 CPUPPCState *env = &cpu->env; 29 target_ulong lpcr; 30 31 cpu_synchronize_state(cs); 32 lpcr = env->spr[SPR_LPCR]; 33 lpcr &= ~s->mask; 34 lpcr |= s->value; 35 ppc_store_lpcr(cpu, lpcr); 36 } 37 38 static void set_all_lpcrs(target_ulong value, target_ulong mask) 39 { 40 CPUState *cs; 41 struct LPCRSyncState s = { 42 .value = value, 43 .mask = mask 44 }; 45 CPU_FOREACH(cs) { 46 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 47 } 48 } 49 50 static bool has_spr(PowerPCCPU *cpu, int spr) 51 { 52 /* We can test whether the SPR is defined by checking for a valid name */ 53 return cpu->env.spr_cb[spr].name != NULL; 54 } 55 56 static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) 57 { 58 /* 59 * hash value/pteg group index is normalized by HPT mask 60 */ 61 if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { 62 return false; 63 } 64 return true; 65 } 66 67 static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr) 68 { 69 MachineState *machine = MACHINE(spapr); 70 DeviceMemoryState *dms = machine->device_memory; 71 72 if (addr < machine->ram_size) { 73 return true; 74 } 75 if ((addr >= dms->base) 76 && ((addr - dms->base) < memory_region_size(&dms->mr))) { 77 return true; 78 } 79 80 return false; 81 } 82 83 static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, 84 target_ulong opcode, target_ulong *args) 85 { 86 target_ulong flags = args[0]; 87 target_ulong ptex = args[1]; 88 target_ulong pteh = args[2]; 89 target_ulong ptel = args[3]; 90 unsigned apshift; 91 target_ulong raddr; 92 target_ulong slot; 93 const ppc_hash_pte64_t *hptes; 94 95 apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); 96 if (!apshift) { 97 /* Bad page size encoding */ 98 return H_PARAMETER; 99 } 100 101 raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); 102 103 if (is_ram_address(spapr, raddr)) { 104 /* Regular RAM - should have WIMG=0010 */ 105 if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 106 return H_PARAMETER; 107 } 108 } else { 109 target_ulong wimg_flags; 110 /* Looks like an IO address */ 111 /* FIXME: What WIMG combinations could be sensible for IO? 112 * For now we allow WIMG=010x, but are there others? */ 113 /* FIXME: Should we check against registered IO addresses? */ 114 wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); 115 116 if (wimg_flags != HPTE64_R_I && 117 wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { 118 return H_PARAMETER; 119 } 120 } 121 122 pteh &= ~0x60ULL; 123 124 if (!valid_ptex(cpu, ptex)) { 125 return H_PARAMETER; 126 } 127 128 slot = ptex & 7ULL; 129 ptex = ptex & ~7ULL; 130 131 if (likely((flags & H_EXACT) == 0)) { 132 hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 133 for (slot = 0; slot < 8; slot++) { 134 if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { 135 break; 136 } 137 } 138 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 139 if (slot == 8) { 140 return H_PTEG_FULL; 141 } 142 } else { 143 hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); 144 if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { 145 ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); 146 return H_PTEG_FULL; 147 } 148 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 149 } 150 151 ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); 152 153 args[0] = ptex + slot; 154 return H_SUCCESS; 155 } 156 157 typedef enum { 158 REMOVE_SUCCESS = 0, 159 REMOVE_NOT_FOUND = 1, 160 REMOVE_PARM = 2, 161 REMOVE_HW = 3, 162 } RemoveResult; 163 164 static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, 165 target_ulong avpn, 166 target_ulong flags, 167 target_ulong *vp, target_ulong *rp) 168 { 169 const ppc_hash_pte64_t *hptes; 170 target_ulong v, r; 171 172 if (!valid_ptex(cpu, ptex)) { 173 return REMOVE_PARM; 174 } 175 176 hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 177 v = ppc_hash64_hpte0(cpu, hptes, 0); 178 r = ppc_hash64_hpte1(cpu, hptes, 0); 179 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 180 181 if ((v & HPTE64_V_VALID) == 0 || 182 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 183 ((flags & H_ANDCOND) && (v & avpn) != 0)) { 184 return REMOVE_NOT_FOUND; 185 } 186 *vp = v; 187 *rp = r; 188 ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); 189 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 190 return REMOVE_SUCCESS; 191 } 192 193 static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 194 target_ulong opcode, target_ulong *args) 195 { 196 CPUPPCState *env = &cpu->env; 197 target_ulong flags = args[0]; 198 target_ulong ptex = args[1]; 199 target_ulong avpn = args[2]; 200 RemoveResult ret; 201 202 ret = remove_hpte(cpu, ptex, avpn, flags, 203 &args[0], &args[1]); 204 205 switch (ret) { 206 case REMOVE_SUCCESS: 207 check_tlb_flush(env, true); 208 return H_SUCCESS; 209 210 case REMOVE_NOT_FOUND: 211 return H_NOT_FOUND; 212 213 case REMOVE_PARM: 214 return H_PARAMETER; 215 216 case REMOVE_HW: 217 return H_HARDWARE; 218 } 219 220 g_assert_not_reached(); 221 } 222 223 #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 224 #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 225 #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 226 #define H_BULK_REMOVE_END 0xc000000000000000ULL 227 #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 228 #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 229 #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 230 #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 231 #define H_BULK_REMOVE_HW 0x3000000000000000ULL 232 #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 233 #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 234 #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 235 #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 236 #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 237 #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 238 239 #define H_BULK_REMOVE_MAX_BATCH 4 240 241 static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 242 target_ulong opcode, target_ulong *args) 243 { 244 CPUPPCState *env = &cpu->env; 245 int i; 246 target_ulong rc = H_SUCCESS; 247 248 for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 249 target_ulong *tsh = &args[i*2]; 250 target_ulong tsl = args[i*2 + 1]; 251 target_ulong v, r, ret; 252 253 if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 254 break; 255 } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 256 return H_PARAMETER; 257 } 258 259 *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 260 *tsh |= H_BULK_REMOVE_RESPONSE; 261 262 if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 263 *tsh |= H_BULK_REMOVE_PARM; 264 return H_PARAMETER; 265 } 266 267 ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, 268 (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 269 &v, &r); 270 271 *tsh |= ret << 60; 272 273 switch (ret) { 274 case REMOVE_SUCCESS: 275 *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 276 break; 277 278 case REMOVE_PARM: 279 rc = H_PARAMETER; 280 goto exit; 281 282 case REMOVE_HW: 283 rc = H_HARDWARE; 284 goto exit; 285 } 286 } 287 exit: 288 check_tlb_flush(env, true); 289 290 return rc; 291 } 292 293 static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr, 294 target_ulong opcode, target_ulong *args) 295 { 296 CPUPPCState *env = &cpu->env; 297 target_ulong flags = args[0]; 298 target_ulong ptex = args[1]; 299 target_ulong avpn = args[2]; 300 const ppc_hash_pte64_t *hptes; 301 target_ulong v, r; 302 303 if (!valid_ptex(cpu, ptex)) { 304 return H_PARAMETER; 305 } 306 307 hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 308 v = ppc_hash64_hpte0(cpu, hptes, 0); 309 r = ppc_hash64_hpte1(cpu, hptes, 0); 310 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 311 312 if ((v & HPTE64_V_VALID) == 0 || 313 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 314 return H_NOT_FOUND; 315 } 316 317 r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 318 HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 319 r |= (flags << 55) & HPTE64_R_PP0; 320 r |= (flags << 48) & HPTE64_R_KEY_HI; 321 r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 322 ppc_hash64_store_hpte(cpu, ptex, 323 (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); 324 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 325 /* Flush the tlb */ 326 check_tlb_flush(env, true); 327 /* Don't need a memory barrier, due to qemu's global lock */ 328 ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); 329 return H_SUCCESS; 330 } 331 332 static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr, 333 target_ulong opcode, target_ulong *args) 334 { 335 target_ulong flags = args[0]; 336 target_ulong ptex = args[1]; 337 uint8_t *hpte; 338 int i, ridx, n_entries = 1; 339 340 if (!valid_ptex(cpu, ptex)) { 341 return H_PARAMETER; 342 } 343 344 if (flags & H_READ_4) { 345 /* Clear the two low order bits */ 346 ptex &= ~(3ULL); 347 n_entries = 4; 348 } 349 350 hpte = spapr->htab + (ptex * HASH_PTE_SIZE_64); 351 352 for (i = 0, ridx = 0; i < n_entries; i++) { 353 args[ridx++] = ldq_p(hpte); 354 args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); 355 hpte += HASH_PTE_SIZE_64; 356 } 357 358 return H_SUCCESS; 359 } 360 361 struct sPAPRPendingHPT { 362 /* These fields are read-only after initialization */ 363 int shift; 364 QemuThread thread; 365 366 /* These fields are protected by the BQL */ 367 bool complete; 368 369 /* These fields are private to the preparation thread if 370 * !complete, otherwise protected by the BQL */ 371 int ret; 372 void *hpt; 373 }; 374 375 static void free_pending_hpt(sPAPRPendingHPT *pending) 376 { 377 if (pending->hpt) { 378 qemu_vfree(pending->hpt); 379 } 380 381 g_free(pending); 382 } 383 384 static void *hpt_prepare_thread(void *opaque) 385 { 386 sPAPRPendingHPT *pending = opaque; 387 size_t size = 1ULL << pending->shift; 388 389 pending->hpt = qemu_memalign(size, size); 390 if (pending->hpt) { 391 memset(pending->hpt, 0, size); 392 pending->ret = H_SUCCESS; 393 } else { 394 pending->ret = H_NO_MEM; 395 } 396 397 qemu_mutex_lock_iothread(); 398 399 if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) { 400 /* Ready to go */ 401 pending->complete = true; 402 } else { 403 /* We've been cancelled, clean ourselves up */ 404 free_pending_hpt(pending); 405 } 406 407 qemu_mutex_unlock_iothread(); 408 return NULL; 409 } 410 411 /* Must be called with BQL held */ 412 static void cancel_hpt_prepare(sPAPRMachineState *spapr) 413 { 414 sPAPRPendingHPT *pending = spapr->pending_hpt; 415 416 /* Let the thread know it's cancelled */ 417 spapr->pending_hpt = NULL; 418 419 if (!pending) { 420 /* Nothing to do */ 421 return; 422 } 423 424 if (!pending->complete) { 425 /* thread will clean itself up */ 426 return; 427 } 428 429 free_pending_hpt(pending); 430 } 431 432 /* Convert a return code from the KVM ioctl()s implementing resize HPT 433 * into a PAPR hypercall return code */ 434 static target_ulong resize_hpt_convert_rc(int ret) 435 { 436 if (ret >= 100000) { 437 return H_LONG_BUSY_ORDER_100_SEC; 438 } else if (ret >= 10000) { 439 return H_LONG_BUSY_ORDER_10_SEC; 440 } else if (ret >= 1000) { 441 return H_LONG_BUSY_ORDER_1_SEC; 442 } else if (ret >= 100) { 443 return H_LONG_BUSY_ORDER_100_MSEC; 444 } else if (ret >= 10) { 445 return H_LONG_BUSY_ORDER_10_MSEC; 446 } else if (ret > 0) { 447 return H_LONG_BUSY_ORDER_1_MSEC; 448 } 449 450 switch (ret) { 451 case 0: 452 return H_SUCCESS; 453 case -EPERM: 454 return H_AUTHORITY; 455 case -EINVAL: 456 return H_PARAMETER; 457 case -ENXIO: 458 return H_CLOSED; 459 case -ENOSPC: 460 return H_PTEG_FULL; 461 case -EBUSY: 462 return H_BUSY; 463 case -ENOMEM: 464 return H_NO_MEM; 465 default: 466 return H_HARDWARE; 467 } 468 } 469 470 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 471 sPAPRMachineState *spapr, 472 target_ulong opcode, 473 target_ulong *args) 474 { 475 target_ulong flags = args[0]; 476 int shift = args[1]; 477 sPAPRPendingHPT *pending = spapr->pending_hpt; 478 uint64_t current_ram_size; 479 int rc; 480 481 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 482 return H_AUTHORITY; 483 } 484 485 if (!spapr->htab_shift) { 486 /* Radix guest, no HPT */ 487 return H_NOT_AVAILABLE; 488 } 489 490 trace_spapr_h_resize_hpt_prepare(flags, shift); 491 492 if (flags != 0) { 493 return H_PARAMETER; 494 } 495 496 if (shift && ((shift < 18) || (shift > 46))) { 497 return H_PARAMETER; 498 } 499 500 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 501 502 /* We only allow the guest to allocate an HPT one order above what 503 * we'd normally give them (to stop a small guest claiming a huge 504 * chunk of resources in the HPT */ 505 if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 506 return H_RESOURCE; 507 } 508 509 rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 510 if (rc != -ENOSYS) { 511 return resize_hpt_convert_rc(rc); 512 } 513 514 if (pending) { 515 /* something already in progress */ 516 if (pending->shift == shift) { 517 /* and it's suitable */ 518 if (pending->complete) { 519 return pending->ret; 520 } else { 521 return H_LONG_BUSY_ORDER_100_MSEC; 522 } 523 } 524 525 /* not suitable, cancel and replace */ 526 cancel_hpt_prepare(spapr); 527 } 528 529 if (!shift) { 530 /* nothing to do */ 531 return H_SUCCESS; 532 } 533 534 /* start new prepare */ 535 536 pending = g_new0(sPAPRPendingHPT, 1); 537 pending->shift = shift; 538 pending->ret = H_HARDWARE; 539 540 qemu_thread_create(&pending->thread, "sPAPR HPT prepare", 541 hpt_prepare_thread, pending, QEMU_THREAD_DETACHED); 542 543 spapr->pending_hpt = pending; 544 545 /* In theory we could estimate the time more accurately based on 546 * the new size, but there's not much point */ 547 return H_LONG_BUSY_ORDER_100_MSEC; 548 } 549 550 static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot) 551 { 552 uint8_t *addr = htab; 553 554 addr += pteg * HASH_PTEG_SIZE_64; 555 addr += slot * HASH_PTE_SIZE_64; 556 return ldq_p(addr); 557 } 558 559 static void new_hpte_store(void *htab, uint64_t pteg, int slot, 560 uint64_t pte0, uint64_t pte1) 561 { 562 uint8_t *addr = htab; 563 564 addr += pteg * HASH_PTEG_SIZE_64; 565 addr += slot * HASH_PTE_SIZE_64; 566 567 stq_p(addr, pte0); 568 stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1); 569 } 570 571 static int rehash_hpte(PowerPCCPU *cpu, 572 const ppc_hash_pte64_t *hptes, 573 void *old_hpt, uint64_t oldsize, 574 void *new_hpt, uint64_t newsize, 575 uint64_t pteg, int slot) 576 { 577 uint64_t old_hash_mask = (oldsize >> 7) - 1; 578 uint64_t new_hash_mask = (newsize >> 7) - 1; 579 target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot); 580 target_ulong pte1; 581 uint64_t avpn; 582 unsigned base_pg_shift; 583 uint64_t hash, new_pteg, replace_pte0; 584 585 if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) { 586 return H_SUCCESS; 587 } 588 589 pte1 = ppc_hash64_hpte1(cpu, hptes, slot); 590 591 base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1); 592 assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */ 593 avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23); 594 595 if (pte0 & HPTE64_V_SECONDARY) { 596 pteg = ~pteg; 597 } 598 599 if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) { 600 uint64_t offset, vsid; 601 602 /* We only have 28 - 23 bits of offset in avpn */ 603 offset = (avpn & 0x1f) << 23; 604 vsid = avpn >> 5; 605 /* We can find more bits from the pteg value */ 606 if (base_pg_shift < 23) { 607 offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift; 608 } 609 610 hash = vsid ^ (offset >> base_pg_shift); 611 } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) { 612 uint64_t offset, vsid; 613 614 /* We only have 40 - 23 bits of seg_off in avpn */ 615 offset = (avpn & 0x1ffff) << 23; 616 vsid = avpn >> 17; 617 if (base_pg_shift < 23) { 618 offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask) 619 << base_pg_shift; 620 } 621 622 hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift); 623 } else { 624 error_report("rehash_pte: Bad segment size in HPTE"); 625 return H_HARDWARE; 626 } 627 628 new_pteg = hash & new_hash_mask; 629 if (pte0 & HPTE64_V_SECONDARY) { 630 assert(~pteg == (hash & old_hash_mask)); 631 new_pteg = ~new_pteg; 632 } else { 633 assert(pteg == (hash & old_hash_mask)); 634 } 635 assert((oldsize != newsize) || (pteg == new_pteg)); 636 replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot); 637 /* 638 * Strictly speaking, we don't need all these tests, since we only 639 * ever rehash bolted HPTEs. We might in future handle non-bolted 640 * HPTEs, though so make the logic correct for those cases as 641 * well. 642 */ 643 if (replace_pte0 & HPTE64_V_VALID) { 644 assert(newsize < oldsize); 645 if (replace_pte0 & HPTE64_V_BOLTED) { 646 if (pte0 & HPTE64_V_BOLTED) { 647 /* Bolted collision, nothing we can do */ 648 return H_PTEG_FULL; 649 } else { 650 /* Discard this hpte */ 651 return H_SUCCESS; 652 } 653 } 654 } 655 656 new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1); 657 return H_SUCCESS; 658 } 659 660 static int rehash_hpt(PowerPCCPU *cpu, 661 void *old_hpt, uint64_t oldsize, 662 void *new_hpt, uint64_t newsize) 663 { 664 uint64_t n_ptegs = oldsize >> 7; 665 uint64_t pteg; 666 int slot; 667 int rc; 668 669 for (pteg = 0; pteg < n_ptegs; pteg++) { 670 hwaddr ptex = pteg * HPTES_PER_GROUP; 671 const ppc_hash_pte64_t *hptes 672 = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 673 674 if (!hptes) { 675 return H_HARDWARE; 676 } 677 678 for (slot = 0; slot < HPTES_PER_GROUP; slot++) { 679 rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize, 680 pteg, slot); 681 if (rc != H_SUCCESS) { 682 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 683 return rc; 684 } 685 } 686 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 687 } 688 689 return H_SUCCESS; 690 } 691 692 static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 693 { 694 int ret; 695 696 cpu_synchronize_state(cs); 697 698 ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 699 if (ret < 0) { 700 error_report("failed to push sregs to KVM: %s", strerror(-ret)); 701 exit(1); 702 } 703 } 704 705 static void push_sregs_to_kvm_pr(sPAPRMachineState *spapr) 706 { 707 CPUState *cs; 708 709 /* 710 * This is a hack for the benefit of KVM PR - it abuses the SDR1 711 * slot in kvm_sregs to communicate the userspace address of the 712 * HPT 713 */ 714 if (!kvm_enabled() || !spapr->htab) { 715 return; 716 } 717 718 CPU_FOREACH(cs) { 719 run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 720 } 721 } 722 723 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 724 sPAPRMachineState *spapr, 725 target_ulong opcode, 726 target_ulong *args) 727 { 728 target_ulong flags = args[0]; 729 target_ulong shift = args[1]; 730 sPAPRPendingHPT *pending = spapr->pending_hpt; 731 int rc; 732 size_t newsize; 733 734 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 735 return H_AUTHORITY; 736 } 737 738 if (!spapr->htab_shift) { 739 /* Radix guest, no HPT */ 740 return H_NOT_AVAILABLE; 741 } 742 743 trace_spapr_h_resize_hpt_commit(flags, shift); 744 745 rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 746 if (rc != -ENOSYS) { 747 rc = resize_hpt_convert_rc(rc); 748 if (rc == H_SUCCESS) { 749 /* Need to set the new htab_shift in the machine state */ 750 spapr->htab_shift = shift; 751 } 752 return rc; 753 } 754 755 if (flags != 0) { 756 return H_PARAMETER; 757 } 758 759 if (!pending || (pending->shift != shift)) { 760 /* no matching prepare */ 761 return H_CLOSED; 762 } 763 764 if (!pending->complete) { 765 /* prepare has not completed */ 766 return H_BUSY; 767 } 768 769 /* Shouldn't have got past PREPARE without an HPT */ 770 g_assert(spapr->htab_shift); 771 772 newsize = 1ULL << pending->shift; 773 rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr), 774 pending->hpt, newsize); 775 if (rc == H_SUCCESS) { 776 qemu_vfree(spapr->htab); 777 spapr->htab = pending->hpt; 778 spapr->htab_shift = pending->shift; 779 780 push_sregs_to_kvm_pr(spapr); 781 782 pending->hpt = NULL; /* so it's not free()d */ 783 } 784 785 /* Clean up */ 786 spapr->pending_hpt = NULL; 787 free_pending_hpt(pending); 788 789 return rc; 790 } 791 792 static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr, 793 target_ulong opcode, target_ulong *args) 794 { 795 cpu_synchronize_state(CPU(cpu)); 796 cpu->env.spr[SPR_SPRG0] = args[0]; 797 798 return H_SUCCESS; 799 } 800 801 static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 802 target_ulong opcode, target_ulong *args) 803 { 804 if (!has_spr(cpu, SPR_DABR)) { 805 return H_HARDWARE; /* DABR register not available */ 806 } 807 cpu_synchronize_state(CPU(cpu)); 808 809 if (has_spr(cpu, SPR_DABRX)) { 810 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 811 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 812 return H_RESERVED_DABR; 813 } 814 815 cpu->env.spr[SPR_DABR] = args[0]; 816 return H_SUCCESS; 817 } 818 819 static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 820 target_ulong opcode, target_ulong *args) 821 { 822 target_ulong dabrx = args[1]; 823 824 if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { 825 return H_HARDWARE; 826 } 827 828 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 829 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 830 return H_PARAMETER; 831 } 832 833 cpu_synchronize_state(CPU(cpu)); 834 cpu->env.spr[SPR_DABRX] = dabrx; 835 cpu->env.spr[SPR_DABR] = args[0]; 836 837 return H_SUCCESS; 838 } 839 840 static target_ulong h_page_init(PowerPCCPU *cpu, sPAPRMachineState *spapr, 841 target_ulong opcode, target_ulong *args) 842 { 843 target_ulong flags = args[0]; 844 hwaddr dst = args[1]; 845 hwaddr src = args[2]; 846 hwaddr len = TARGET_PAGE_SIZE; 847 uint8_t *pdst, *psrc; 848 target_long ret = H_SUCCESS; 849 850 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 851 | H_COPY_PAGE | H_ZERO_PAGE)) { 852 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 853 flags); 854 return H_PARAMETER; 855 } 856 857 /* Map-in destination */ 858 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 859 return H_PARAMETER; 860 } 861 pdst = cpu_physical_memory_map(dst, &len, 1); 862 if (!pdst || len != TARGET_PAGE_SIZE) { 863 return H_PARAMETER; 864 } 865 866 if (flags & H_COPY_PAGE) { 867 /* Map-in source, copy to destination, and unmap source again */ 868 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 869 ret = H_PARAMETER; 870 goto unmap_out; 871 } 872 psrc = cpu_physical_memory_map(src, &len, 0); 873 if (!psrc || len != TARGET_PAGE_SIZE) { 874 ret = H_PARAMETER; 875 goto unmap_out; 876 } 877 memcpy(pdst, psrc, len); 878 cpu_physical_memory_unmap(psrc, len, 0, len); 879 } else if (flags & H_ZERO_PAGE) { 880 memset(pdst, 0, len); /* Just clear the destination page */ 881 } 882 883 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 884 kvmppc_dcbst_range(cpu, pdst, len); 885 } 886 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 887 if (kvm_enabled()) { 888 kvmppc_icbi_range(cpu, pdst, len); 889 } else { 890 tb_flush(CPU(cpu)); 891 } 892 } 893 894 unmap_out: 895 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 896 return ret; 897 } 898 899 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 900 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 901 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 902 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 903 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 904 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 905 906 #define VPA_MIN_SIZE 640 907 #define VPA_SIZE_OFFSET 0x4 908 #define VPA_SHARED_PROC_OFFSET 0x9 909 #define VPA_SHARED_PROC_VAL 0x2 910 911 static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) 912 { 913 CPUState *cs = CPU(ppc_env_get_cpu(env)); 914 uint16_t size; 915 uint8_t tmp; 916 917 if (vpa == 0) { 918 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 919 return H_HARDWARE; 920 } 921 922 if (vpa % env->dcache_line_size) { 923 return H_PARAMETER; 924 } 925 /* FIXME: bounds check the address */ 926 927 size = lduw_be_phys(cs->as, vpa + 0x4); 928 929 if (size < VPA_MIN_SIZE) { 930 return H_PARAMETER; 931 } 932 933 /* VPA is not allowed to cross a page boundary */ 934 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 935 return H_PARAMETER; 936 } 937 938 env->vpa_addr = vpa; 939 940 tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); 941 tmp |= VPA_SHARED_PROC_VAL; 942 stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 943 944 return H_SUCCESS; 945 } 946 947 static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) 948 { 949 if (env->slb_shadow_addr) { 950 return H_RESOURCE; 951 } 952 953 if (env->dtl_addr) { 954 return H_RESOURCE; 955 } 956 957 env->vpa_addr = 0; 958 return H_SUCCESS; 959 } 960 961 static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) 962 { 963 CPUState *cs = CPU(ppc_env_get_cpu(env)); 964 uint32_t size; 965 966 if (addr == 0) { 967 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 968 return H_HARDWARE; 969 } 970 971 size = ldl_be_phys(cs->as, addr + 0x4); 972 if (size < 0x8) { 973 return H_PARAMETER; 974 } 975 976 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 977 return H_PARAMETER; 978 } 979 980 if (!env->vpa_addr) { 981 return H_RESOURCE; 982 } 983 984 env->slb_shadow_addr = addr; 985 env->slb_shadow_size = size; 986 987 return H_SUCCESS; 988 } 989 990 static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) 991 { 992 env->slb_shadow_addr = 0; 993 env->slb_shadow_size = 0; 994 return H_SUCCESS; 995 } 996 997 static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) 998 { 999 CPUState *cs = CPU(ppc_env_get_cpu(env)); 1000 uint32_t size; 1001 1002 if (addr == 0) { 1003 hcall_dprintf("Can't cope with DTL at logical 0\n"); 1004 return H_HARDWARE; 1005 } 1006 1007 size = ldl_be_phys(cs->as, addr + 0x4); 1008 1009 if (size < 48) { 1010 return H_PARAMETER; 1011 } 1012 1013 if (!env->vpa_addr) { 1014 return H_RESOURCE; 1015 } 1016 1017 env->dtl_addr = addr; 1018 env->dtl_size = size; 1019 1020 return H_SUCCESS; 1021 } 1022 1023 static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) 1024 { 1025 env->dtl_addr = 0; 1026 env->dtl_size = 0; 1027 1028 return H_SUCCESS; 1029 } 1030 1031 static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1032 target_ulong opcode, target_ulong *args) 1033 { 1034 target_ulong flags = args[0]; 1035 target_ulong procno = args[1]; 1036 target_ulong vpa = args[2]; 1037 target_ulong ret = H_PARAMETER; 1038 CPUPPCState *tenv; 1039 PowerPCCPU *tcpu; 1040 1041 tcpu = spapr_find_cpu(procno); 1042 if (!tcpu) { 1043 return H_PARAMETER; 1044 } 1045 tenv = &tcpu->env; 1046 1047 switch (flags) { 1048 case FLAGS_REGISTER_VPA: 1049 ret = register_vpa(tenv, vpa); 1050 break; 1051 1052 case FLAGS_DEREGISTER_VPA: 1053 ret = deregister_vpa(tenv, vpa); 1054 break; 1055 1056 case FLAGS_REGISTER_SLBSHADOW: 1057 ret = register_slb_shadow(tenv, vpa); 1058 break; 1059 1060 case FLAGS_DEREGISTER_SLBSHADOW: 1061 ret = deregister_slb_shadow(tenv, vpa); 1062 break; 1063 1064 case FLAGS_REGISTER_DTL: 1065 ret = register_dtl(tenv, vpa); 1066 break; 1067 1068 case FLAGS_DEREGISTER_DTL: 1069 ret = deregister_dtl(tenv, vpa); 1070 break; 1071 } 1072 1073 return ret; 1074 } 1075 1076 static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1077 target_ulong opcode, target_ulong *args) 1078 { 1079 CPUPPCState *env = &cpu->env; 1080 CPUState *cs = CPU(cpu); 1081 1082 env->msr |= (1ULL << MSR_EE); 1083 hreg_compute_hflags(env); 1084 if (!cpu_has_work(cs)) { 1085 cs->halted = 1; 1086 cs->exception_index = EXCP_HLT; 1087 cs->exit_request = 1; 1088 } 1089 return H_SUCCESS; 1090 } 1091 1092 static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1093 target_ulong opcode, target_ulong *args) 1094 { 1095 target_ulong rtas_r3 = args[0]; 1096 uint32_t token = rtas_ld(rtas_r3, 0); 1097 uint32_t nargs = rtas_ld(rtas_r3, 1); 1098 uint32_t nret = rtas_ld(rtas_r3, 2); 1099 1100 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 1101 nret, rtas_r3 + 12 + 4*nargs); 1102 } 1103 1104 static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1105 target_ulong opcode, target_ulong *args) 1106 { 1107 CPUState *cs = CPU(cpu); 1108 target_ulong size = args[0]; 1109 target_ulong addr = args[1]; 1110 1111 switch (size) { 1112 case 1: 1113 args[0] = ldub_phys(cs->as, addr); 1114 return H_SUCCESS; 1115 case 2: 1116 args[0] = lduw_phys(cs->as, addr); 1117 return H_SUCCESS; 1118 case 4: 1119 args[0] = ldl_phys(cs->as, addr); 1120 return H_SUCCESS; 1121 case 8: 1122 args[0] = ldq_phys(cs->as, addr); 1123 return H_SUCCESS; 1124 } 1125 return H_PARAMETER; 1126 } 1127 1128 static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1129 target_ulong opcode, target_ulong *args) 1130 { 1131 CPUState *cs = CPU(cpu); 1132 1133 target_ulong size = args[0]; 1134 target_ulong addr = args[1]; 1135 target_ulong val = args[2]; 1136 1137 switch (size) { 1138 case 1: 1139 stb_phys(cs->as, addr, val); 1140 return H_SUCCESS; 1141 case 2: 1142 stw_phys(cs->as, addr, val); 1143 return H_SUCCESS; 1144 case 4: 1145 stl_phys(cs->as, addr, val); 1146 return H_SUCCESS; 1147 case 8: 1148 stq_phys(cs->as, addr, val); 1149 return H_SUCCESS; 1150 } 1151 return H_PARAMETER; 1152 } 1153 1154 static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1155 target_ulong opcode, target_ulong *args) 1156 { 1157 CPUState *cs = CPU(cpu); 1158 1159 target_ulong dst = args[0]; /* Destination address */ 1160 target_ulong src = args[1]; /* Source address */ 1161 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 1162 target_ulong count = args[3]; /* Element count */ 1163 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 1164 uint64_t tmp; 1165 unsigned int mask = (1 << esize) - 1; 1166 int step = 1 << esize; 1167 1168 if (count > 0x80000000) { 1169 return H_PARAMETER; 1170 } 1171 1172 if ((dst & mask) || (src & mask) || (op > 1)) { 1173 return H_PARAMETER; 1174 } 1175 1176 if (dst >= src && dst < (src + (count << esize))) { 1177 dst = dst + ((count - 1) << esize); 1178 src = src + ((count - 1) << esize); 1179 step = -step; 1180 } 1181 1182 while (count--) { 1183 switch (esize) { 1184 case 0: 1185 tmp = ldub_phys(cs->as, src); 1186 break; 1187 case 1: 1188 tmp = lduw_phys(cs->as, src); 1189 break; 1190 case 2: 1191 tmp = ldl_phys(cs->as, src); 1192 break; 1193 case 3: 1194 tmp = ldq_phys(cs->as, src); 1195 break; 1196 default: 1197 return H_PARAMETER; 1198 } 1199 if (op == 1) { 1200 tmp = ~tmp; 1201 } 1202 switch (esize) { 1203 case 0: 1204 stb_phys(cs->as, dst, tmp); 1205 break; 1206 case 1: 1207 stw_phys(cs->as, dst, tmp); 1208 break; 1209 case 2: 1210 stl_phys(cs->as, dst, tmp); 1211 break; 1212 case 3: 1213 stq_phys(cs->as, dst, tmp); 1214 break; 1215 } 1216 dst = dst + step; 1217 src = src + step; 1218 } 1219 1220 return H_SUCCESS; 1221 } 1222 1223 static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1224 target_ulong opcode, target_ulong *args) 1225 { 1226 /* Nothing to do on emulation, KVM will trap this in the kernel */ 1227 return H_SUCCESS; 1228 } 1229 1230 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1231 target_ulong opcode, target_ulong *args) 1232 { 1233 /* Nothing to do on emulation, KVM will trap this in the kernel */ 1234 return H_SUCCESS; 1235 } 1236 1237 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 1238 target_ulong mflags, 1239 target_ulong value1, 1240 target_ulong value2) 1241 { 1242 if (value1) { 1243 return H_P3; 1244 } 1245 if (value2) { 1246 return H_P4; 1247 } 1248 1249 switch (mflags) { 1250 case H_SET_MODE_ENDIAN_BIG: 1251 set_all_lpcrs(0, LPCR_ILE); 1252 spapr_pci_switch_vga(true); 1253 return H_SUCCESS; 1254 1255 case H_SET_MODE_ENDIAN_LITTLE: 1256 set_all_lpcrs(LPCR_ILE, LPCR_ILE); 1257 spapr_pci_switch_vga(false); 1258 return H_SUCCESS; 1259 } 1260 1261 return H_UNSUPPORTED_FLAG; 1262 } 1263 1264 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 1265 target_ulong mflags, 1266 target_ulong value1, 1267 target_ulong value2) 1268 { 1269 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 1270 1271 if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 1272 return H_P2; 1273 } 1274 if (value1) { 1275 return H_P3; 1276 } 1277 if (value2) { 1278 return H_P4; 1279 } 1280 1281 if (mflags == AIL_RESERVED) { 1282 return H_UNSUPPORTED_FLAG; 1283 } 1284 1285 set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); 1286 1287 return H_SUCCESS; 1288 } 1289 1290 static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1291 target_ulong opcode, target_ulong *args) 1292 { 1293 target_ulong resource = args[1]; 1294 target_ulong ret = H_P2; 1295 1296 switch (resource) { 1297 case H_SET_MODE_RESOURCE_LE: 1298 ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); 1299 break; 1300 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 1301 ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 1302 args[2], args[3]); 1303 break; 1304 } 1305 1306 return ret; 1307 } 1308 1309 static target_ulong h_clean_slb(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1310 target_ulong opcode, target_ulong *args) 1311 { 1312 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1313 opcode, " (H_CLEAN_SLB)"); 1314 return H_FUNCTION; 1315 } 1316 1317 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1318 target_ulong opcode, target_ulong *args) 1319 { 1320 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1321 opcode, " (H_INVALIDATE_PID)"); 1322 return H_FUNCTION; 1323 } 1324 1325 static void spapr_check_setup_free_hpt(sPAPRMachineState *spapr, 1326 uint64_t patbe_old, uint64_t patbe_new) 1327 { 1328 /* 1329 * We have 4 Options: 1330 * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 1331 * HASH->RADIX : Free HPT 1332 * RADIX->HASH : Allocate HPT 1333 * NOTHING->HASH : Allocate HPT 1334 * Note: NOTHING implies the case where we said the guest could choose 1335 * later and so assumed radix and now it's called H_REG_PROC_TBL 1336 */ 1337 1338 if ((patbe_old & PATBE1_GR) == (patbe_new & PATBE1_GR)) { 1339 /* We assume RADIX, so this catches all the "Do Nothing" cases */ 1340 } else if (!(patbe_old & PATBE1_GR)) { 1341 /* HASH->RADIX : Free HPT */ 1342 spapr_free_hpt(spapr); 1343 } else if (!(patbe_new & PATBE1_GR)) { 1344 /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 1345 spapr_setup_hpt_and_vrma(spapr); 1346 } 1347 return; 1348 } 1349 1350 #define FLAGS_MASK 0x01FULL 1351 #define FLAG_MODIFY 0x10 1352 #define FLAG_REGISTER 0x08 1353 #define FLAG_RADIX 0x04 1354 #define FLAG_HASH_PROC_TBL 0x02 1355 #define FLAG_GTSE 0x01 1356 1357 static target_ulong h_register_process_table(PowerPCCPU *cpu, 1358 sPAPRMachineState *spapr, 1359 target_ulong opcode, 1360 target_ulong *args) 1361 { 1362 target_ulong flags = args[0]; 1363 target_ulong proc_tbl = args[1]; 1364 target_ulong page_size = args[2]; 1365 target_ulong table_size = args[3]; 1366 uint64_t cproc; 1367 1368 if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 1369 return H_PARAMETER; 1370 } 1371 if (flags & FLAG_MODIFY) { 1372 if (flags & FLAG_REGISTER) { 1373 if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 1374 if (proc_tbl & 0xfff || proc_tbl >> 60) { 1375 return H_P2; 1376 } else if (page_size) { 1377 return H_P3; 1378 } else if (table_size > 24) { 1379 return H_P4; 1380 } 1381 cproc = PATBE1_GR | proc_tbl | table_size; 1382 } else { /* Register new HPT process table */ 1383 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 1384 /* TODO - Not Supported */ 1385 /* Technically caused by flag bits => H_PARAMETER */ 1386 return H_PARAMETER; 1387 } else { /* Hash with SLB */ 1388 if (proc_tbl >> 38) { 1389 return H_P2; 1390 } else if (page_size & ~0x7) { 1391 return H_P3; 1392 } else if (table_size > 24) { 1393 return H_P4; 1394 } 1395 } 1396 cproc = (proc_tbl << 25) | page_size << 5 | table_size; 1397 } 1398 1399 } else { /* Deregister current process table */ 1400 /* Set to benign value: (current GR) | 0. This allows 1401 * deregistration in KVM to succeed even if the radix bit in flags 1402 * doesn't match the radix bit in the old PATB. */ 1403 cproc = spapr->patb_entry & PATBE1_GR; 1404 } 1405 } else { /* Maintain current registration */ 1406 if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATBE1_GR)) { 1407 /* Technically caused by flag bits => H_PARAMETER */ 1408 return H_PARAMETER; /* Existing Process Table Mismatch */ 1409 } 1410 cproc = spapr->patb_entry; 1411 } 1412 1413 /* Check if we need to setup OR free the hpt */ 1414 spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 1415 1416 spapr->patb_entry = cproc; /* Save new process table */ 1417 1418 /* Update the UPRT and GTSE bits in the LPCR for all cpus */ 1419 set_all_lpcrs(((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT : 0) | 1420 ((flags & FLAG_GTSE) ? LPCR_GTSE : 0), 1421 LPCR_UPRT | LPCR_GTSE); 1422 1423 if (kvm_enabled()) { 1424 return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1425 flags & FLAG_GTSE, cproc); 1426 } 1427 return H_SUCCESS; 1428 } 1429 1430 #define H_SIGNAL_SYS_RESET_ALL -1 1431 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 1432 1433 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1434 sPAPRMachineState *spapr, 1435 target_ulong opcode, target_ulong *args) 1436 { 1437 target_long target = args[0]; 1438 CPUState *cs; 1439 1440 if (target < 0) { 1441 /* Broadcast */ 1442 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1443 return H_PARAMETER; 1444 } 1445 1446 CPU_FOREACH(cs) { 1447 PowerPCCPU *c = POWERPC_CPU(cs); 1448 1449 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1450 if (c == cpu) { 1451 continue; 1452 } 1453 } 1454 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1455 } 1456 return H_SUCCESS; 1457 1458 } else { 1459 /* Unicast */ 1460 cs = CPU(spapr_find_cpu(target)); 1461 if (cs) { 1462 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1463 return H_SUCCESS; 1464 } 1465 return H_PARAMETER; 1466 } 1467 } 1468 1469 static uint32_t cas_check_pvr(sPAPRMachineState *spapr, PowerPCCPU *cpu, 1470 target_ulong *addr, bool *raw_mode_supported, 1471 Error **errp) 1472 { 1473 bool explicit_match = false; /* Matched the CPU's real PVR */ 1474 uint32_t max_compat = spapr->max_compat_pvr; 1475 uint32_t best_compat = 0; 1476 int i; 1477 1478 /* 1479 * We scan the supplied table of PVRs looking for two things 1480 * 1. Is our real CPU PVR in the list? 1481 * 2. What's the "best" listed logical PVR 1482 */ 1483 for (i = 0; i < 512; ++i) { 1484 uint32_t pvr, pvr_mask; 1485 1486 pvr_mask = ldl_be_phys(&address_space_memory, *addr); 1487 pvr = ldl_be_phys(&address_space_memory, *addr + 4); 1488 *addr += 8; 1489 1490 if (~pvr_mask & pvr) { 1491 break; /* Terminator record */ 1492 } 1493 1494 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1495 explicit_match = true; 1496 } else { 1497 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1498 best_compat = pvr; 1499 } 1500 } 1501 } 1502 1503 if ((best_compat == 0) && (!explicit_match || max_compat)) { 1504 /* We couldn't find a suitable compatibility mode, and either 1505 * the guest doesn't support "raw" mode for this CPU, or raw 1506 * mode is disabled because a maximum compat mode is set */ 1507 error_setg(errp, "Couldn't negotiate a suitable PVR during CAS"); 1508 return 0; 1509 } 1510 1511 *raw_mode_supported = explicit_match; 1512 1513 /* Parsing finished */ 1514 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 1515 1516 return best_compat; 1517 } 1518 1519 static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1520 sPAPRMachineState *spapr, 1521 target_ulong opcode, 1522 target_ulong *args) 1523 { 1524 /* Working address in data buffer */ 1525 target_ulong addr = ppc64_phys_to_real(args[0]); 1526 target_ulong ov_table; 1527 uint32_t cas_pvr; 1528 sPAPROptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates; 1529 bool guest_radix; 1530 Error *local_err = NULL; 1531 bool raw_mode_supported = false; 1532 1533 cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err); 1534 if (local_err) { 1535 error_report_err(local_err); 1536 return H_HARDWARE; 1537 } 1538 1539 /* Update CPUs */ 1540 if (cpu->compat_pvr != cas_pvr) { 1541 ppc_set_compat_all(cas_pvr, &local_err); 1542 if (local_err) { 1543 /* We fail to set compat mode (likely because running with KVM PR), 1544 * but maybe we can fallback to raw mode if the guest supports it. 1545 */ 1546 if (!raw_mode_supported) { 1547 error_report_err(local_err); 1548 return H_HARDWARE; 1549 } 1550 local_err = NULL; 1551 } 1552 } 1553 1554 /* For the future use: here @ov_table points to the first option vector */ 1555 ov_table = addr; 1556 1557 ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1558 ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1559 if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 1560 error_report("guest requested hash and radix MMU, which is invalid."); 1561 exit(EXIT_FAILURE); 1562 } 1563 /* The radix/hash bit in byte 24 requires special handling: */ 1564 guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 1565 spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300); 1566 1567 /* 1568 * HPT resizing is a bit of a special case, because when enabled 1569 * we assume an HPT guest will support it until it says it 1570 * doesn't, instead of assuming it won't support it until it says 1571 * it does. Strictly speaking that approach could break for 1572 * guests which don't make a CAS call, but those are so old we 1573 * don't care about them. Without that assumption we'd have to 1574 * make at least a temporary allocation of an HPT sized for max 1575 * memory, which could be impossibly difficult under KVM HV if 1576 * maxram is large. 1577 */ 1578 if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 1579 int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1580 1581 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 1582 error_report( 1583 "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 1584 exit(1); 1585 } 1586 1587 if (spapr->htab_shift < maxshift) { 1588 /* Guest doesn't know about HPT resizing, so we 1589 * pre-emptively resize for the maximum permitted RAM. At 1590 * the point this is called, nothing should have been 1591 * entered into the existing HPT */ 1592 spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 1593 push_sregs_to_kvm_pr(spapr); 1594 } 1595 } 1596 1597 /* NOTE: there are actually a number of ov5 bits where input from the 1598 * guest is always zero, and the platform/QEMU enables them independently 1599 * of guest input. To model these properly we'd want some sort of mask, 1600 * but since they only currently apply to memory migration as defined 1601 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 1602 * to worry about this for now. 1603 */ 1604 ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); 1605 1606 /* also clear the radix/hash bit from the current ov5_cas bits to 1607 * be in sync with the newly ov5 bits. Else the radix bit will be 1608 * seen as being removed and this will generate a reset loop 1609 */ 1610 spapr_ovec_clear(ov5_cas_old, OV5_MMU_RADIX_300); 1611 1612 /* full range of negotiated ov5 capabilities */ 1613 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1614 spapr_ovec_cleanup(ov5_guest); 1615 /* capabilities that have been added since CAS-generated guest reset. 1616 * if capabilities have since been removed, generate another reset 1617 */ 1618 ov5_updates = spapr_ovec_new(); 1619 spapr->cas_reboot = spapr_ovec_diff(ov5_updates, 1620 ov5_cas_old, spapr->ov5_cas); 1621 /* Now that processing is finished, set the radix/hash bit for the 1622 * guest if it requested a valid mode; otherwise terminate the boot. */ 1623 if (guest_radix) { 1624 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1625 error_report("Guest requested unavailable MMU mode (radix)."); 1626 exit(EXIT_FAILURE); 1627 } 1628 spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300); 1629 } else { 1630 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1631 && !kvmppc_has_cap_mmu_hash_v3()) { 1632 error_report("Guest requested unavailable MMU mode (hash)."); 1633 exit(EXIT_FAILURE); 1634 } 1635 } 1636 spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest, 1637 OV1_PPC_3_00); 1638 if (!spapr->cas_reboot) { 1639 /* If spapr_machine_reset() did not set up a HPT but one is necessary 1640 * (because the guest isn't going to use radix) then set it up here. */ 1641 if ((spapr->patb_entry & PATBE1_GR) && !guest_radix) { 1642 /* legacy hash or new hash: */ 1643 spapr_setup_hpt_and_vrma(spapr); 1644 } 1645 spapr->cas_reboot = 1646 (spapr_h_cas_compose_response(spapr, args[1], args[2], 1647 ov5_updates) != 0); 1648 } 1649 spapr_ovec_cleanup(ov5_updates); 1650 1651 if (spapr->cas_reboot) { 1652 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1653 } 1654 1655 return H_SUCCESS; 1656 } 1657 1658 static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1659 sPAPRMachineState *spapr, 1660 target_ulong opcode, 1661 target_ulong *args) 1662 { 1663 uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1664 ~H_CPU_CHAR_THR_RECONF_TRIG; 1665 uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1666 uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1667 uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1668 uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 1669 1670 switch (safe_cache) { 1671 case SPAPR_CAP_WORKAROUND: 1672 characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1673 characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1674 characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1675 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1676 break; 1677 case SPAPR_CAP_FIXED: 1678 break; 1679 default: /* broken */ 1680 assert(safe_cache == SPAPR_CAP_BROKEN); 1681 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1682 break; 1683 } 1684 1685 switch (safe_bounds_check) { 1686 case SPAPR_CAP_WORKAROUND: 1687 characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1688 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1689 break; 1690 case SPAPR_CAP_FIXED: 1691 break; 1692 default: /* broken */ 1693 assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1694 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1695 break; 1696 } 1697 1698 switch (safe_indirect_branch) { 1699 case SPAPR_CAP_FIXED_CCD: 1700 characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; 1701 break; 1702 case SPAPR_CAP_FIXED_IBS: 1703 characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1704 break; 1705 default: /* broken */ 1706 assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1707 break; 1708 } 1709 1710 args[0] = characteristics; 1711 args[1] = behaviour; 1712 1713 return H_SUCCESS; 1714 } 1715 1716 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 1717 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 1718 1719 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 1720 { 1721 spapr_hcall_fn *slot; 1722 1723 if (opcode <= MAX_HCALL_OPCODE) { 1724 assert((opcode & 0x3) == 0); 1725 1726 slot = &papr_hypercall_table[opcode / 4]; 1727 } else { 1728 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1729 1730 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1731 } 1732 1733 assert(!(*slot)); 1734 *slot = fn; 1735 } 1736 1737 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 1738 target_ulong *args) 1739 { 1740 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1741 1742 if ((opcode <= MAX_HCALL_OPCODE) 1743 && ((opcode & 0x3) == 0)) { 1744 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 1745 1746 if (fn) { 1747 return fn(cpu, spapr, opcode, args); 1748 } 1749 } else if ((opcode >= KVMPPC_HCALL_BASE) && 1750 (opcode <= KVMPPC_HCALL_MAX)) { 1751 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1752 1753 if (fn) { 1754 return fn(cpu, spapr, opcode, args); 1755 } 1756 } 1757 1758 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1759 opcode); 1760 return H_FUNCTION; 1761 } 1762 1763 static void hypercall_register_types(void) 1764 { 1765 /* hcall-pft */ 1766 spapr_register_hypercall(H_ENTER, h_enter); 1767 spapr_register_hypercall(H_REMOVE, h_remove); 1768 spapr_register_hypercall(H_PROTECT, h_protect); 1769 spapr_register_hypercall(H_READ, h_read); 1770 1771 /* hcall-bulk */ 1772 spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 1773 1774 /* hcall-hpt-resize */ 1775 spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 1776 spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 1777 1778 /* hcall-splpar */ 1779 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 1780 spapr_register_hypercall(H_CEDE, h_cede); 1781 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 1782 1783 /* processor register resource access h-calls */ 1784 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1785 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1786 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 1787 spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1788 spapr_register_hypercall(H_SET_MODE, h_set_mode); 1789 1790 /* In Memory Table MMU h-calls */ 1791 spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1792 spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1793 spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1794 1795 /* hcall-get-cpu-characteristics */ 1796 spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 1797 h_get_cpu_characteristics); 1798 1799 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 1800 * here between the "CI" and the "CACHE" variants, they will use whatever 1801 * mapping attributes qemu is using. When using KVM, the kernel will 1802 * enforce the attributes more strongly 1803 */ 1804 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 1805 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 1806 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 1807 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 1808 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 1809 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 1810 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 1811 1812 /* qemu/KVM-PPC specific hcalls */ 1813 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 1814 1815 /* ibm,client-architecture-support support */ 1816 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1817 } 1818 1819 type_init(hypercall_register_types) 1820