1 #include "qemu/osdep.h" 2 #include "qemu/cutils.h" 3 #include "qapi/error.h" 4 #include "sysemu/hw_accel.h" 5 #include "sysemu/runstate.h" 6 #include "sysemu/tcg.h" 7 #include "qemu/log.h" 8 #include "qemu/main-loop.h" 9 #include "qemu/module.h" 10 #include "qemu/error-report.h" 11 #include "exec/tb-flush.h" 12 #include "helper_regs.h" 13 #include "hw/ppc/ppc.h" 14 #include "hw/ppc/spapr.h" 15 #include "hw/ppc/spapr_cpu_core.h" 16 #include "hw/ppc/spapr_nested.h" 17 #include "mmu-hash64.h" 18 #include "cpu-models.h" 19 #include "trace.h" 20 #include "kvm_ppc.h" 21 #include "hw/ppc/fdt.h" 22 #include "hw/ppc/spapr_ovec.h" 23 #include "hw/ppc/spapr_numa.h" 24 #include "mmu-book3s-v3.h" 25 #include "hw/mem/memory-device.h" 26 27 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) 28 { 29 MachineState *machine = MACHINE(spapr); 30 DeviceMemoryState *dms = machine->device_memory; 31 32 if (addr < machine->ram_size) { 33 return true; 34 } 35 if (dms && (addr >= dms->base) 36 && ((addr - dms->base) < memory_region_size(&dms->mr))) { 37 return true; 38 } 39 40 return false; 41 } 42 43 /* Convert a return code from the KVM ioctl()s implementing resize HPT 44 * into a PAPR hypercall return code */ 45 static target_ulong resize_hpt_convert_rc(int ret) 46 { 47 if (ret >= 100000) { 48 return H_LONG_BUSY_ORDER_100_SEC; 49 } else if (ret >= 10000) { 50 return H_LONG_BUSY_ORDER_10_SEC; 51 } else if (ret >= 1000) { 52 return H_LONG_BUSY_ORDER_1_SEC; 53 } else if (ret >= 100) { 54 return H_LONG_BUSY_ORDER_100_MSEC; 55 } else if (ret >= 10) { 56 return H_LONG_BUSY_ORDER_10_MSEC; 57 } else if (ret > 0) { 58 return H_LONG_BUSY_ORDER_1_MSEC; 59 } 60 61 switch (ret) { 62 case 0: 63 return H_SUCCESS; 64 case -EPERM: 65 return H_AUTHORITY; 66 case -EINVAL: 67 return H_PARAMETER; 68 case -ENXIO: 69 return H_CLOSED; 70 case -ENOSPC: 71 return H_PTEG_FULL; 72 case -EBUSY: 73 return H_BUSY; 74 case -ENOMEM: 75 return H_NO_MEM; 76 default: 77 return H_HARDWARE; 78 } 79 } 80 81 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 82 SpaprMachineState *spapr, 83 target_ulong opcode, 84 target_ulong *args) 85 { 86 target_ulong flags = args[0]; 87 int shift = args[1]; 88 uint64_t current_ram_size; 89 int rc; 90 91 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 92 return H_AUTHORITY; 93 } 94 95 if (!spapr->htab_shift) { 96 /* Radix guest, no HPT */ 97 return H_NOT_AVAILABLE; 98 } 99 100 trace_spapr_h_resize_hpt_prepare(flags, shift); 101 102 if (flags != 0) { 103 return H_PARAMETER; 104 } 105 106 if (shift && ((shift < 18) || (shift > 46))) { 107 return H_PARAMETER; 108 } 109 110 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 111 112 /* We only allow the guest to allocate an HPT one order above what 113 * we'd normally give them (to stop a small guest claiming a huge 114 * chunk of resources in the HPT */ 115 if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 116 return H_RESOURCE; 117 } 118 119 rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 120 if (rc != -ENOSYS) { 121 return resize_hpt_convert_rc(rc); 122 } 123 124 if (kvm_enabled()) { 125 return H_HARDWARE; 126 } else if (tcg_enabled()) { 127 return vhyp_mmu_resize_hpt_prepare(cpu, spapr, shift); 128 } else { 129 g_assert_not_reached(); 130 } 131 } 132 133 static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 134 { 135 int ret; 136 137 cpu_synchronize_state(cs); 138 139 ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 140 if (ret < 0) { 141 error_report("failed to push sregs to KVM: %s", strerror(-ret)); 142 exit(1); 143 } 144 } 145 146 void push_sregs_to_kvm_pr(SpaprMachineState *spapr) 147 { 148 CPUState *cs; 149 150 /* 151 * This is a hack for the benefit of KVM PR - it abuses the SDR1 152 * slot in kvm_sregs to communicate the userspace address of the 153 * HPT 154 */ 155 if (!kvm_enabled() || !spapr->htab) { 156 return; 157 } 158 159 CPU_FOREACH(cs) { 160 run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 161 } 162 } 163 164 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 165 SpaprMachineState *spapr, 166 target_ulong opcode, 167 target_ulong *args) 168 { 169 target_ulong flags = args[0]; 170 target_ulong shift = args[1]; 171 int rc; 172 173 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 174 return H_AUTHORITY; 175 } 176 177 if (!spapr->htab_shift) { 178 /* Radix guest, no HPT */ 179 return H_NOT_AVAILABLE; 180 } 181 182 trace_spapr_h_resize_hpt_commit(flags, shift); 183 184 rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 185 if (rc != -ENOSYS) { 186 rc = resize_hpt_convert_rc(rc); 187 if (rc == H_SUCCESS) { 188 /* Need to set the new htab_shift in the machine state */ 189 spapr->htab_shift = shift; 190 } 191 return rc; 192 } 193 194 if (kvm_enabled()) { 195 return H_HARDWARE; 196 } else if (tcg_enabled()) { 197 return vhyp_mmu_resize_hpt_commit(cpu, spapr, flags, shift); 198 } else { 199 g_assert_not_reached(); 200 } 201 } 202 203 204 205 static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, 206 target_ulong opcode, target_ulong *args) 207 { 208 cpu_synchronize_state(CPU(cpu)); 209 cpu->env.spr[SPR_SPRG0] = args[0]; 210 211 return H_SUCCESS; 212 } 213 214 static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 215 target_ulong opcode, target_ulong *args) 216 { 217 if (!ppc_has_spr(cpu, SPR_DABR)) { 218 return H_HARDWARE; /* DABR register not available */ 219 } 220 cpu_synchronize_state(CPU(cpu)); 221 222 if (ppc_has_spr(cpu, SPR_DABRX)) { 223 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 224 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 225 return H_RESERVED_DABR; 226 } 227 228 cpu->env.spr[SPR_DABR] = args[0]; 229 return H_SUCCESS; 230 } 231 232 static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 233 target_ulong opcode, target_ulong *args) 234 { 235 target_ulong dabrx = args[1]; 236 237 if (!ppc_has_spr(cpu, SPR_DABR) || !ppc_has_spr(cpu, SPR_DABRX)) { 238 return H_HARDWARE; 239 } 240 241 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 242 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 243 return H_PARAMETER; 244 } 245 246 cpu_synchronize_state(CPU(cpu)); 247 cpu->env.spr[SPR_DABRX] = dabrx; 248 cpu->env.spr[SPR_DABR] = args[0]; 249 250 return H_SUCCESS; 251 } 252 253 static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, 254 target_ulong opcode, target_ulong *args) 255 { 256 target_ulong flags = args[0]; 257 hwaddr dst = args[1]; 258 hwaddr src = args[2]; 259 hwaddr len = TARGET_PAGE_SIZE; 260 uint8_t *pdst, *psrc; 261 target_long ret = H_SUCCESS; 262 263 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 264 | H_COPY_PAGE | H_ZERO_PAGE)) { 265 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 266 flags); 267 return H_PARAMETER; 268 } 269 270 /* Map-in destination */ 271 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 272 return H_PARAMETER; 273 } 274 pdst = cpu_physical_memory_map(dst, &len, true); 275 if (!pdst || len != TARGET_PAGE_SIZE) { 276 return H_PARAMETER; 277 } 278 279 if (flags & H_COPY_PAGE) { 280 /* Map-in source, copy to destination, and unmap source again */ 281 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 282 ret = H_PARAMETER; 283 goto unmap_out; 284 } 285 psrc = cpu_physical_memory_map(src, &len, false); 286 if (!psrc || len != TARGET_PAGE_SIZE) { 287 ret = H_PARAMETER; 288 goto unmap_out; 289 } 290 memcpy(pdst, psrc, len); 291 cpu_physical_memory_unmap(psrc, len, 0, len); 292 } else if (flags & H_ZERO_PAGE) { 293 memset(pdst, 0, len); /* Just clear the destination page */ 294 } 295 296 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 297 kvmppc_dcbst_range(cpu, pdst, len); 298 } 299 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 300 if (kvm_enabled()) { 301 kvmppc_icbi_range(cpu, pdst, len); 302 } else { 303 tb_flush(CPU(cpu)); 304 } 305 } 306 307 unmap_out: 308 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 309 return ret; 310 } 311 312 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 313 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 314 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 315 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 316 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 317 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 318 319 static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) 320 { 321 CPUState *cs = CPU(cpu); 322 CPUPPCState *env = &cpu->env; 323 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 324 uint16_t size; 325 uint8_t tmp; 326 327 if (vpa == 0) { 328 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 329 return H_HARDWARE; 330 } 331 332 if (vpa % env->dcache_line_size) { 333 return H_PARAMETER; 334 } 335 /* FIXME: bounds check the address */ 336 337 size = lduw_be_phys(cs->as, vpa + 0x4); 338 339 if (size < VPA_MIN_SIZE) { 340 return H_PARAMETER; 341 } 342 343 /* VPA is not allowed to cross a page boundary */ 344 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 345 return H_PARAMETER; 346 } 347 348 spapr_cpu->vpa_addr = vpa; 349 350 tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET); 351 tmp |= VPA_SHARED_PROC_VAL; 352 stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 353 354 return H_SUCCESS; 355 } 356 357 static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) 358 { 359 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 360 361 if (spapr_cpu->slb_shadow_addr) { 362 return H_RESOURCE; 363 } 364 365 if (spapr_cpu->dtl_addr) { 366 return H_RESOURCE; 367 } 368 369 spapr_cpu->vpa_addr = 0; 370 return H_SUCCESS; 371 } 372 373 static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 374 { 375 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 376 uint32_t size; 377 378 if (addr == 0) { 379 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 380 return H_HARDWARE; 381 } 382 383 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 384 if (size < 0x8) { 385 return H_PARAMETER; 386 } 387 388 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 389 return H_PARAMETER; 390 } 391 392 if (!spapr_cpu->vpa_addr) { 393 return H_RESOURCE; 394 } 395 396 spapr_cpu->slb_shadow_addr = addr; 397 spapr_cpu->slb_shadow_size = size; 398 399 return H_SUCCESS; 400 } 401 402 static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 403 { 404 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 405 406 spapr_cpu->slb_shadow_addr = 0; 407 spapr_cpu->slb_shadow_size = 0; 408 return H_SUCCESS; 409 } 410 411 static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) 412 { 413 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 414 uint32_t size; 415 416 if (addr == 0) { 417 hcall_dprintf("Can't cope with DTL at logical 0\n"); 418 return H_HARDWARE; 419 } 420 421 size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 422 423 if (size < 48) { 424 return H_PARAMETER; 425 } 426 427 if (!spapr_cpu->vpa_addr) { 428 return H_RESOURCE; 429 } 430 431 spapr_cpu->dtl_addr = addr; 432 spapr_cpu->dtl_size = size; 433 434 return H_SUCCESS; 435 } 436 437 static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) 438 { 439 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 440 441 spapr_cpu->dtl_addr = 0; 442 spapr_cpu->dtl_size = 0; 443 444 return H_SUCCESS; 445 } 446 447 static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr, 448 target_ulong opcode, target_ulong *args) 449 { 450 target_ulong flags = args[0]; 451 target_ulong procno = args[1]; 452 target_ulong vpa = args[2]; 453 target_ulong ret = H_PARAMETER; 454 PowerPCCPU *tcpu; 455 456 tcpu = spapr_find_cpu(procno); 457 if (!tcpu) { 458 return H_PARAMETER; 459 } 460 461 switch (flags) { 462 case FLAGS_REGISTER_VPA: 463 ret = register_vpa(tcpu, vpa); 464 break; 465 466 case FLAGS_DEREGISTER_VPA: 467 ret = deregister_vpa(tcpu, vpa); 468 break; 469 470 case FLAGS_REGISTER_SLBSHADOW: 471 ret = register_slb_shadow(tcpu, vpa); 472 break; 473 474 case FLAGS_DEREGISTER_SLBSHADOW: 475 ret = deregister_slb_shadow(tcpu, vpa); 476 break; 477 478 case FLAGS_REGISTER_DTL: 479 ret = register_dtl(tcpu, vpa); 480 break; 481 482 case FLAGS_DEREGISTER_DTL: 483 ret = deregister_dtl(tcpu, vpa); 484 break; 485 } 486 487 return ret; 488 } 489 490 static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, 491 target_ulong opcode, target_ulong *args) 492 { 493 CPUPPCState *env = &cpu->env; 494 CPUState *cs = CPU(cpu); 495 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 496 497 env->msr |= (1ULL << MSR_EE); 498 hreg_compute_hflags(env); 499 ppc_maybe_interrupt(env); 500 501 if (spapr_cpu->prod) { 502 spapr_cpu->prod = false; 503 return H_SUCCESS; 504 } 505 506 if (!cpu_has_work(cs)) { 507 cs->halted = 1; 508 cs->exception_index = EXCP_HLT; 509 cs->exit_request = 1; 510 ppc_maybe_interrupt(env); 511 } 512 513 return H_SUCCESS; 514 } 515 516 /* 517 * Confer to self, aka join. Cede could use the same pattern as well, if 518 * EXCP_HLT can be changed to ECXP_HALTED. 519 */ 520 static target_ulong h_confer_self(PowerPCCPU *cpu) 521 { 522 CPUState *cs = CPU(cpu); 523 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 524 525 if (spapr_cpu->prod) { 526 spapr_cpu->prod = false; 527 return H_SUCCESS; 528 } 529 cs->halted = 1; 530 cs->exception_index = EXCP_HALTED; 531 cs->exit_request = 1; 532 ppc_maybe_interrupt(&cpu->env); 533 534 return H_SUCCESS; 535 } 536 537 static target_ulong h_join(PowerPCCPU *cpu, SpaprMachineState *spapr, 538 target_ulong opcode, target_ulong *args) 539 { 540 CPUPPCState *env = &cpu->env; 541 CPUState *cs; 542 bool last_unjoined = true; 543 544 if (env->msr & (1ULL << MSR_EE)) { 545 return H_BAD_MODE; 546 } 547 548 /* 549 * Must not join the last CPU running. Interestingly, no such restriction 550 * for H_CONFER-to-self, but that is probably not intended to be used 551 * when H_JOIN is available. 552 */ 553 CPU_FOREACH(cs) { 554 PowerPCCPU *c = POWERPC_CPU(cs); 555 CPUPPCState *e = &c->env; 556 if (c == cpu) { 557 continue; 558 } 559 560 /* Don't have a way to indicate joined, so use halted && MSR[EE]=0 */ 561 if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { 562 last_unjoined = false; 563 break; 564 } 565 } 566 if (last_unjoined) { 567 return H_CONTINUE; 568 } 569 570 return h_confer_self(cpu); 571 } 572 573 static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr, 574 target_ulong opcode, target_ulong *args) 575 { 576 target_long target = args[0]; 577 uint32_t dispatch = args[1]; 578 CPUState *cs = CPU(cpu); 579 SpaprCpuState *spapr_cpu; 580 581 /* 582 * -1 means confer to all other CPUs without dispatch counter check, 583 * otherwise it's a targeted confer. 584 */ 585 if (target != -1) { 586 PowerPCCPU *target_cpu = spapr_find_cpu(target); 587 uint32_t target_dispatch; 588 589 if (!target_cpu) { 590 return H_PARAMETER; 591 } 592 593 /* 594 * target == self is a special case, we wait until prodded, without 595 * dispatch counter check. 596 */ 597 if (cpu == target_cpu) { 598 return h_confer_self(cpu); 599 } 600 601 spapr_cpu = spapr_cpu_state(target_cpu); 602 if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) { 603 return H_SUCCESS; 604 } 605 606 target_dispatch = ldl_be_phys(cs->as, 607 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 608 if (target_dispatch != dispatch) { 609 return H_SUCCESS; 610 } 611 612 /* 613 * The targeted confer does not do anything special beyond yielding 614 * the current vCPU, but even this should be better than nothing. 615 * At least for single-threaded tcg, it gives the target a chance to 616 * run before we run again. Multi-threaded tcg does not really do 617 * anything with EXCP_YIELD yet. 618 */ 619 } 620 621 cs->exception_index = EXCP_YIELD; 622 cs->exit_request = 1; 623 cpu_loop_exit(cs); 624 625 return H_SUCCESS; 626 } 627 628 static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr, 629 target_ulong opcode, target_ulong *args) 630 { 631 target_long target = args[0]; 632 PowerPCCPU *tcpu; 633 CPUState *cs; 634 SpaprCpuState *spapr_cpu; 635 636 tcpu = spapr_find_cpu(target); 637 cs = CPU(tcpu); 638 if (!cs) { 639 return H_PARAMETER; 640 } 641 642 spapr_cpu = spapr_cpu_state(tcpu); 643 spapr_cpu->prod = true; 644 cs->halted = 0; 645 ppc_maybe_interrupt(&cpu->env); 646 qemu_cpu_kick(cs); 647 648 return H_SUCCESS; 649 } 650 651 static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, 652 target_ulong opcode, target_ulong *args) 653 { 654 target_ulong rtas_r3 = args[0]; 655 uint32_t token = rtas_ld(rtas_r3, 0); 656 uint32_t nargs = rtas_ld(rtas_r3, 1); 657 uint32_t nret = rtas_ld(rtas_r3, 2); 658 659 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 660 nret, rtas_r3 + 12 + 4*nargs); 661 } 662 663 static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr, 664 target_ulong opcode, target_ulong *args) 665 { 666 CPUState *cs = CPU(cpu); 667 target_ulong size = args[0]; 668 target_ulong addr = args[1]; 669 670 switch (size) { 671 case 1: 672 args[0] = ldub_phys(cs->as, addr); 673 return H_SUCCESS; 674 case 2: 675 args[0] = lduw_phys(cs->as, addr); 676 return H_SUCCESS; 677 case 4: 678 args[0] = ldl_phys(cs->as, addr); 679 return H_SUCCESS; 680 case 8: 681 args[0] = ldq_phys(cs->as, addr); 682 return H_SUCCESS; 683 } 684 return H_PARAMETER; 685 } 686 687 static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr, 688 target_ulong opcode, target_ulong *args) 689 { 690 CPUState *cs = CPU(cpu); 691 692 target_ulong size = args[0]; 693 target_ulong addr = args[1]; 694 target_ulong val = args[2]; 695 696 switch (size) { 697 case 1: 698 stb_phys(cs->as, addr, val); 699 return H_SUCCESS; 700 case 2: 701 stw_phys(cs->as, addr, val); 702 return H_SUCCESS; 703 case 4: 704 stl_phys(cs->as, addr, val); 705 return H_SUCCESS; 706 case 8: 707 stq_phys(cs->as, addr, val); 708 return H_SUCCESS; 709 } 710 return H_PARAMETER; 711 } 712 713 static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr, 714 target_ulong opcode, target_ulong *args) 715 { 716 CPUState *cs = CPU(cpu); 717 718 target_ulong dst = args[0]; /* Destination address */ 719 target_ulong src = args[1]; /* Source address */ 720 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 721 target_ulong count = args[3]; /* Element count */ 722 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 723 uint64_t tmp; 724 unsigned int mask = (1 << esize) - 1; 725 int step = 1 << esize; 726 727 if (count > 0x80000000) { 728 return H_PARAMETER; 729 } 730 731 if ((dst & mask) || (src & mask) || (op > 1)) { 732 return H_PARAMETER; 733 } 734 735 if (dst >= src && dst < (src + (count << esize))) { 736 dst = dst + ((count - 1) << esize); 737 src = src + ((count - 1) << esize); 738 step = -step; 739 } 740 741 while (count--) { 742 switch (esize) { 743 case 0: 744 tmp = ldub_phys(cs->as, src); 745 break; 746 case 1: 747 tmp = lduw_phys(cs->as, src); 748 break; 749 case 2: 750 tmp = ldl_phys(cs->as, src); 751 break; 752 case 3: 753 tmp = ldq_phys(cs->as, src); 754 break; 755 default: 756 return H_PARAMETER; 757 } 758 if (op == 1) { 759 tmp = ~tmp; 760 } 761 switch (esize) { 762 case 0: 763 stb_phys(cs->as, dst, tmp); 764 break; 765 case 1: 766 stw_phys(cs->as, dst, tmp); 767 break; 768 case 2: 769 stl_phys(cs->as, dst, tmp); 770 break; 771 case 3: 772 stq_phys(cs->as, dst, tmp); 773 break; 774 } 775 dst = dst + step; 776 src = src + step; 777 } 778 779 return H_SUCCESS; 780 } 781 782 static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr, 783 target_ulong opcode, target_ulong *args) 784 { 785 /* Nothing to do on emulation, KVM will trap this in the kernel */ 786 return H_SUCCESS; 787 } 788 789 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, 790 target_ulong opcode, target_ulong *args) 791 { 792 /* Nothing to do on emulation, KVM will trap this in the kernel */ 793 return H_SUCCESS; 794 } 795 796 static target_ulong h_set_mode_resource_set_ciabr(PowerPCCPU *cpu, 797 SpaprMachineState *spapr, 798 target_ulong mflags, 799 target_ulong value1, 800 target_ulong value2) 801 { 802 CPUPPCState *env = &cpu->env; 803 804 assert(tcg_enabled()); /* KVM will have handled this */ 805 806 if (mflags) { 807 return H_UNSUPPORTED_FLAG; 808 } 809 if (value2) { 810 return H_P4; 811 } 812 if ((value1 & PPC_BITMASK(62, 63)) == 0x3) { 813 return H_P3; 814 } 815 816 ppc_store_ciabr(env, value1); 817 818 return H_SUCCESS; 819 } 820 821 static target_ulong h_set_mode_resource_set_dawr0(PowerPCCPU *cpu, 822 SpaprMachineState *spapr, 823 target_ulong mflags, 824 target_ulong value1, 825 target_ulong value2) 826 { 827 CPUPPCState *env = &cpu->env; 828 829 assert(tcg_enabled()); /* KVM will have handled this */ 830 831 if (mflags) { 832 return H_UNSUPPORTED_FLAG; 833 } 834 if (value2 & PPC_BIT(61)) { 835 return H_P4; 836 } 837 838 ppc_store_dawr0(env, value1); 839 ppc_store_dawrx0(env, value2); 840 841 return H_SUCCESS; 842 } 843 844 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 845 SpaprMachineState *spapr, 846 target_ulong mflags, 847 target_ulong value1, 848 target_ulong value2) 849 { 850 if (value1) { 851 return H_P3; 852 } 853 if (value2) { 854 return H_P4; 855 } 856 857 switch (mflags) { 858 case H_SET_MODE_ENDIAN_BIG: 859 spapr_set_all_lpcrs(0, LPCR_ILE); 860 spapr_pci_switch_vga(spapr, true); 861 return H_SUCCESS; 862 863 case H_SET_MODE_ENDIAN_LITTLE: 864 spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); 865 spapr_pci_switch_vga(spapr, false); 866 return H_SUCCESS; 867 } 868 869 return H_UNSUPPORTED_FLAG; 870 } 871 872 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 873 SpaprMachineState *spapr, 874 target_ulong mflags, 875 target_ulong value1, 876 target_ulong value2) 877 { 878 if (value1) { 879 return H_P3; 880 } 881 882 if (value2) { 883 return H_P4; 884 } 885 886 /* 887 * AIL-1 is not architected, and AIL-2 is not supported by QEMU spapr. 888 * It is supported for faithful emulation of bare metal systems, but for 889 * compatibility concerns we leave it out of the pseries machine. 890 */ 891 if (mflags != 0 && mflags != 3) { 892 return H_UNSUPPORTED_FLAG; 893 } 894 895 if (mflags == 3) { 896 if (!spapr_get_cap(spapr, SPAPR_CAP_AIL_MODE_3)) { 897 return H_UNSUPPORTED_FLAG; 898 } 899 } 900 901 spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); 902 903 return H_SUCCESS; 904 } 905 906 static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, 907 target_ulong opcode, target_ulong *args) 908 { 909 target_ulong resource = args[1]; 910 target_ulong ret = H_P2; 911 912 switch (resource) { 913 case H_SET_MODE_RESOURCE_SET_CIABR: 914 ret = h_set_mode_resource_set_ciabr(cpu, spapr, args[0], args[2], 915 args[3]); 916 break; 917 case H_SET_MODE_RESOURCE_SET_DAWR0: 918 ret = h_set_mode_resource_set_dawr0(cpu, spapr, args[0], args[2], 919 args[3]); 920 break; 921 case H_SET_MODE_RESOURCE_LE: 922 ret = h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[3]); 923 break; 924 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 925 ret = h_set_mode_resource_addr_trans_mode(cpu, spapr, args[0], 926 args[2], args[3]); 927 break; 928 } 929 930 return ret; 931 } 932 933 static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, 934 target_ulong opcode, target_ulong *args) 935 { 936 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 937 opcode, " (H_CLEAN_SLB)"); 938 return H_FUNCTION; 939 } 940 941 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr, 942 target_ulong opcode, target_ulong *args) 943 { 944 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 945 opcode, " (H_INVALIDATE_PID)"); 946 return H_FUNCTION; 947 } 948 949 static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, 950 uint64_t patbe_old, uint64_t patbe_new) 951 { 952 /* 953 * We have 4 Options: 954 * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 955 * HASH->RADIX : Free HPT 956 * RADIX->HASH : Allocate HPT 957 * NOTHING->HASH : Allocate HPT 958 * Note: NOTHING implies the case where we said the guest could choose 959 * later and so assumed radix and now it's called H_REG_PROC_TBL 960 */ 961 962 if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) { 963 /* We assume RADIX, so this catches all the "Do Nothing" cases */ 964 } else if (!(patbe_old & PATE1_GR)) { 965 /* HASH->RADIX : Free HPT */ 966 spapr_free_hpt(spapr); 967 } else if (!(patbe_new & PATE1_GR)) { 968 /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 969 spapr_setup_hpt(spapr); 970 } 971 return; 972 } 973 974 #define FLAGS_MASK 0x01FULL 975 #define FLAG_MODIFY 0x10 976 #define FLAG_REGISTER 0x08 977 #define FLAG_RADIX 0x04 978 #define FLAG_HASH_PROC_TBL 0x02 979 #define FLAG_GTSE 0x01 980 981 static target_ulong h_register_process_table(PowerPCCPU *cpu, 982 SpaprMachineState *spapr, 983 target_ulong opcode, 984 target_ulong *args) 985 { 986 target_ulong flags = args[0]; 987 target_ulong proc_tbl = args[1]; 988 target_ulong page_size = args[2]; 989 target_ulong table_size = args[3]; 990 target_ulong update_lpcr = 0; 991 target_ulong table_byte_size; 992 uint64_t cproc; 993 994 if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 995 return H_PARAMETER; 996 } 997 if (flags & FLAG_MODIFY) { 998 if (flags & FLAG_REGISTER) { 999 /* Check process table alignment */ 1000 table_byte_size = 1ULL << (table_size + 12); 1001 if (proc_tbl & (table_byte_size - 1)) { 1002 qemu_log_mask(LOG_GUEST_ERROR, 1003 "%s: process table not properly aligned: proc_tbl 0x" 1004 TARGET_FMT_lx" proc_tbl_size 0x"TARGET_FMT_lx"\n", 1005 __func__, proc_tbl, table_byte_size); 1006 } 1007 if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 1008 if (proc_tbl & 0xfff || proc_tbl >> 60) { 1009 return H_P2; 1010 } else if (page_size) { 1011 return H_P3; 1012 } else if (table_size > 24) { 1013 return H_P4; 1014 } 1015 cproc = PATE1_GR | proc_tbl | table_size; 1016 } else { /* Register new HPT process table */ 1017 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 1018 /* TODO - Not Supported */ 1019 /* Technically caused by flag bits => H_PARAMETER */ 1020 return H_PARAMETER; 1021 } else { /* Hash with SLB */ 1022 if (proc_tbl >> 38) { 1023 return H_P2; 1024 } else if (page_size & ~0x7) { 1025 return H_P3; 1026 } else if (table_size > 24) { 1027 return H_P4; 1028 } 1029 } 1030 cproc = (proc_tbl << 25) | page_size << 5 | table_size; 1031 } 1032 1033 } else { /* Deregister current process table */ 1034 /* 1035 * Set to benign value: (current GR) | 0. This allows 1036 * deregistration in KVM to succeed even if the radix bit 1037 * in flags doesn't match the radix bit in the old PATE. 1038 */ 1039 cproc = spapr->patb_entry & PATE1_GR; 1040 } 1041 } else { /* Maintain current registration */ 1042 if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) { 1043 /* Technically caused by flag bits => H_PARAMETER */ 1044 return H_PARAMETER; /* Existing Process Table Mismatch */ 1045 } 1046 cproc = spapr->patb_entry; 1047 } 1048 1049 /* Check if we need to setup OR free the hpt */ 1050 spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 1051 1052 spapr->patb_entry = cproc; /* Save new process table */ 1053 1054 /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ 1055 if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */ 1056 update_lpcr |= (LPCR_UPRT | LPCR_HR); 1057 else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ 1058 update_lpcr |= LPCR_UPRT; 1059 if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ 1060 update_lpcr |= LPCR_GTSE; 1061 1062 spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); 1063 1064 if (kvm_enabled()) { 1065 return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1066 flags & FLAG_GTSE, cproc); 1067 } 1068 return H_SUCCESS; 1069 } 1070 1071 #define H_SIGNAL_SYS_RESET_ALL -1 1072 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 1073 1074 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1075 SpaprMachineState *spapr, 1076 target_ulong opcode, target_ulong *args) 1077 { 1078 target_long target = args[0]; 1079 CPUState *cs; 1080 1081 if (target < 0) { 1082 /* Broadcast */ 1083 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1084 return H_PARAMETER; 1085 } 1086 1087 CPU_FOREACH(cs) { 1088 PowerPCCPU *c = POWERPC_CPU(cs); 1089 1090 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1091 if (c == cpu) { 1092 continue; 1093 } 1094 } 1095 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1096 } 1097 return H_SUCCESS; 1098 1099 } else { 1100 /* Unicast */ 1101 cs = CPU(spapr_find_cpu(target)); 1102 if (cs) { 1103 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1104 return H_SUCCESS; 1105 } 1106 return H_PARAMETER; 1107 } 1108 } 1109 1110 /* Returns either a logical PVR or zero if none was found */ 1111 static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32_t max_compat, 1112 target_ulong *addr, bool *raw_mode_supported) 1113 { 1114 bool explicit_match = false; /* Matched the CPU's real PVR */ 1115 uint32_t best_compat = 0; 1116 int i; 1117 1118 /* 1119 * We scan the supplied table of PVRs looking for two things 1120 * 1. Is our real CPU PVR in the list? 1121 * 2. What's the "best" listed logical PVR 1122 */ 1123 for (i = 0; i < 512; ++i) { 1124 uint32_t pvr, pvr_mask; 1125 1126 pvr_mask = ldl_be_phys(&address_space_memory, *addr); 1127 pvr = ldl_be_phys(&address_space_memory, *addr + 4); 1128 *addr += 8; 1129 1130 if (~pvr_mask & pvr) { 1131 break; /* Terminator record */ 1132 } 1133 1134 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1135 explicit_match = true; 1136 } else { 1137 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1138 best_compat = pvr; 1139 } 1140 } 1141 } 1142 1143 *raw_mode_supported = explicit_match; 1144 1145 /* Parsing finished */ 1146 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 1147 1148 return best_compat; 1149 } 1150 1151 static 1152 target_ulong do_client_architecture_support(PowerPCCPU *cpu, 1153 SpaprMachineState *spapr, 1154 target_ulong vec, 1155 target_ulong fdt_bufsize) 1156 { 1157 target_ulong ov_table; /* Working address in data buffer */ 1158 uint32_t cas_pvr; 1159 SpaprOptionVector *ov1_guest, *ov5_guest; 1160 bool guest_radix; 1161 bool raw_mode_supported = false; 1162 bool guest_xive; 1163 CPUState *cs; 1164 void *fdt; 1165 uint32_t max_compat = spapr->max_compat_pvr; 1166 1167 /* CAS is supposed to be called early when only the boot vCPU is active. */ 1168 CPU_FOREACH(cs) { 1169 if (cs == CPU(cpu)) { 1170 continue; 1171 } 1172 if (!cs->halted) { 1173 warn_report("guest has multiple active vCPUs at CAS, which is not allowed"); 1174 return H_MULTI_THREADS_ACTIVE; 1175 } 1176 } 1177 1178 cas_pvr = cas_check_pvr(cpu, max_compat, &vec, &raw_mode_supported); 1179 if (!cas_pvr && (!raw_mode_supported || max_compat)) { 1180 /* 1181 * We couldn't find a suitable compatibility mode, and either 1182 * the guest doesn't support "raw" mode for this CPU, or "raw" 1183 * mode is disabled because a maximum compat mode is set. 1184 */ 1185 error_report("Couldn't negotiate a suitable PVR during CAS"); 1186 return H_HARDWARE; 1187 } 1188 1189 /* Update CPUs */ 1190 if (cpu->compat_pvr != cas_pvr) { 1191 Error *local_err = NULL; 1192 1193 if (ppc_set_compat_all(cas_pvr, &local_err) < 0) { 1194 /* We fail to set compat mode (likely because running with KVM PR), 1195 * but maybe we can fallback to raw mode if the guest supports it. 1196 */ 1197 if (!raw_mode_supported) { 1198 error_report_err(local_err); 1199 return H_HARDWARE; 1200 } 1201 error_free(local_err); 1202 } 1203 } 1204 1205 /* For the future use: here @ov_table points to the first option vector */ 1206 ov_table = vec; 1207 1208 ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1209 if (!ov1_guest) { 1210 warn_report("guest didn't provide option vector 1"); 1211 return H_PARAMETER; 1212 } 1213 ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1214 if (!ov5_guest) { 1215 spapr_ovec_cleanup(ov1_guest); 1216 warn_report("guest didn't provide option vector 5"); 1217 return H_PARAMETER; 1218 } 1219 if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 1220 error_report("guest requested hash and radix MMU, which is invalid."); 1221 exit(EXIT_FAILURE); 1222 } 1223 if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { 1224 error_report("guest requested an invalid interrupt mode"); 1225 exit(EXIT_FAILURE); 1226 } 1227 1228 guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 1229 1230 guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); 1231 1232 /* 1233 * HPT resizing is a bit of a special case, because when enabled 1234 * we assume an HPT guest will support it until it says it 1235 * doesn't, instead of assuming it won't support it until it says 1236 * it does. Strictly speaking that approach could break for 1237 * guests which don't make a CAS call, but those are so old we 1238 * don't care about them. Without that assumption we'd have to 1239 * make at least a temporary allocation of an HPT sized for max 1240 * memory, which could be impossibly difficult under KVM HV if 1241 * maxram is large. 1242 */ 1243 if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 1244 int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1245 1246 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 1247 error_report( 1248 "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 1249 exit(1); 1250 } 1251 1252 if (spapr->htab_shift < maxshift) { 1253 /* Guest doesn't know about HPT resizing, so we 1254 * pre-emptively resize for the maximum permitted RAM. At 1255 * the point this is called, nothing should have been 1256 * entered into the existing HPT */ 1257 spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 1258 push_sregs_to_kvm_pr(spapr); 1259 } 1260 } 1261 1262 /* NOTE: there are actually a number of ov5 bits where input from the 1263 * guest is always zero, and the platform/QEMU enables them independently 1264 * of guest input. To model these properly we'd want some sort of mask, 1265 * but since they only currently apply to memory migration as defined 1266 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 1267 * to worry about this for now. 1268 */ 1269 1270 /* full range of negotiated ov5 capabilities */ 1271 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1272 spapr_ovec_cleanup(ov5_guest); 1273 1274 spapr_check_mmu_mode(guest_radix); 1275 1276 spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00); 1277 spapr_ovec_cleanup(ov1_guest); 1278 1279 /* 1280 * Check for NUMA affinity conditions now that we know which NUMA 1281 * affinity the guest will use. 1282 */ 1283 spapr_numa_associativity_check(spapr); 1284 1285 /* 1286 * Ensure the guest asks for an interrupt mode we support; 1287 * otherwise terminate the boot. 1288 */ 1289 if (guest_xive) { 1290 if (!spapr->irq->xive) { 1291 error_report( 1292 "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property"); 1293 exit(EXIT_FAILURE); 1294 } 1295 } else { 1296 if (!spapr->irq->xics) { 1297 error_report( 1298 "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual"); 1299 exit(EXIT_FAILURE); 1300 } 1301 } 1302 1303 spapr_irq_update_active_intc(spapr); 1304 1305 /* 1306 * Process all pending hot-plug/unplug requests now. An updated full 1307 * rendered FDT will be returned to the guest. 1308 */ 1309 spapr_drc_reset_all(spapr); 1310 spapr_clear_pending_hotplug_events(spapr); 1311 1312 /* 1313 * If spapr_machine_reset() did not set up a HPT but one is necessary 1314 * (because the guest isn't going to use radix) then set it up here. 1315 */ 1316 if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { 1317 /* legacy hash or new hash: */ 1318 spapr_setup_hpt(spapr); 1319 } 1320 1321 fdt = spapr_build_fdt(spapr, spapr->vof != NULL, fdt_bufsize); 1322 g_free(spapr->fdt_blob); 1323 spapr->fdt_size = fdt_totalsize(fdt); 1324 spapr->fdt_initial_size = spapr->fdt_size; 1325 spapr->fdt_blob = fdt; 1326 1327 /* 1328 * Set the machine->fdt pointer again since we just freed 1329 * it above (by freeing spapr->fdt_blob). We set this 1330 * pointer to enable support for the 'dumpdtb' QMP/HMP 1331 * command. 1332 */ 1333 MACHINE(spapr)->fdt = fdt; 1334 1335 return H_SUCCESS; 1336 } 1337 1338 static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1339 SpaprMachineState *spapr, 1340 target_ulong opcode, 1341 target_ulong *args) 1342 { 1343 target_ulong vec = ppc64_phys_to_real(args[0]); 1344 target_ulong fdt_buf = args[1]; 1345 target_ulong fdt_bufsize = args[2]; 1346 target_ulong ret; 1347 SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 1348 1349 if (fdt_bufsize < sizeof(hdr)) { 1350 error_report("SLOF provided insufficient CAS buffer " 1351 TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr)); 1352 exit(EXIT_FAILURE); 1353 } 1354 1355 fdt_bufsize -= sizeof(hdr); 1356 1357 ret = do_client_architecture_support(cpu, spapr, vec, fdt_bufsize); 1358 if (ret == H_SUCCESS) { 1359 _FDT((fdt_pack(spapr->fdt_blob))); 1360 spapr->fdt_size = fdt_totalsize(spapr->fdt_blob); 1361 spapr->fdt_initial_size = spapr->fdt_size; 1362 1363 cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr)); 1364 cpu_physical_memory_write(fdt_buf + sizeof(hdr), spapr->fdt_blob, 1365 spapr->fdt_size); 1366 trace_spapr_cas_continue(spapr->fdt_size + sizeof(hdr)); 1367 } 1368 1369 return ret; 1370 } 1371 1372 target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1373 CPUState *cs, 1374 target_ulong ovec_addr) 1375 { 1376 SpaprMachineState *spapr = SPAPR_MACHINE(ms); 1377 1378 target_ulong ret = do_client_architecture_support(POWERPC_CPU(cs), spapr, 1379 ovec_addr, FDT_MAX_SIZE); 1380 1381 /* 1382 * This adds stdout and generates phandles for boottime and CAS FDTs. 1383 * It is alright to update the FDT here as do_client_architecture_support() 1384 * does not pack it. 1385 */ 1386 spapr_vof_client_dt_finalize(spapr, spapr->fdt_blob); 1387 1388 return ret; 1389 } 1390 1391 static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1392 SpaprMachineState *spapr, 1393 target_ulong opcode, 1394 target_ulong *args) 1395 { 1396 uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1397 ~H_CPU_CHAR_THR_RECONF_TRIG; 1398 uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1399 uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1400 uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1401 uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 1402 uint8_t count_cache_flush_assist = spapr_get_cap(spapr, 1403 SPAPR_CAP_CCF_ASSIST); 1404 1405 switch (safe_cache) { 1406 case SPAPR_CAP_WORKAROUND: 1407 characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1408 characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1409 characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1410 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1411 break; 1412 case SPAPR_CAP_FIXED: 1413 behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY; 1414 behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS; 1415 break; 1416 default: /* broken */ 1417 assert(safe_cache == SPAPR_CAP_BROKEN); 1418 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1419 break; 1420 } 1421 1422 switch (safe_bounds_check) { 1423 case SPAPR_CAP_WORKAROUND: 1424 characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1425 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1426 break; 1427 case SPAPR_CAP_FIXED: 1428 break; 1429 default: /* broken */ 1430 assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1431 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1432 break; 1433 } 1434 1435 switch (safe_indirect_branch) { 1436 case SPAPR_CAP_FIXED_NA: 1437 break; 1438 case SPAPR_CAP_FIXED_CCD: 1439 characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; 1440 break; 1441 case SPAPR_CAP_FIXED_IBS: 1442 characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1443 break; 1444 case SPAPR_CAP_WORKAROUND: 1445 behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE; 1446 if (count_cache_flush_assist) { 1447 characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST; 1448 } 1449 break; 1450 default: /* broken */ 1451 assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1452 break; 1453 } 1454 1455 args[0] = characteristics; 1456 args[1] = behaviour; 1457 return H_SUCCESS; 1458 } 1459 1460 static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, 1461 target_ulong opcode, target_ulong *args) 1462 { 1463 target_ulong dt = ppc64_phys_to_real(args[0]); 1464 struct fdt_header hdr = { 0 }; 1465 unsigned cb; 1466 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1467 void *fdt; 1468 1469 cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); 1470 cb = fdt32_to_cpu(hdr.totalsize); 1471 1472 if (!smc->update_dt_enabled) { 1473 return H_SUCCESS; 1474 } 1475 1476 /* Check that the fdt did not grow out of proportion */ 1477 if (cb > spapr->fdt_initial_size * 2) { 1478 trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, 1479 fdt32_to_cpu(hdr.magic)); 1480 return H_PARAMETER; 1481 } 1482 1483 fdt = g_malloc0(cb); 1484 cpu_physical_memory_read(dt, fdt, cb); 1485 1486 /* Check the fdt consistency */ 1487 if (fdt_check_full(fdt, cb)) { 1488 trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, 1489 fdt32_to_cpu(hdr.magic)); 1490 return H_PARAMETER; 1491 } 1492 1493 g_free(spapr->fdt_blob); 1494 spapr->fdt_size = cb; 1495 spapr->fdt_blob = fdt; 1496 trace_spapr_update_dt(cb); 1497 1498 return H_SUCCESS; 1499 } 1500 1501 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 1502 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 1503 static spapr_hcall_fn svm_hypercall_table[(SVM_HCALL_MAX - SVM_HCALL_BASE) / 4 + 1]; 1504 1505 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 1506 { 1507 spapr_hcall_fn *slot; 1508 1509 if (opcode <= MAX_HCALL_OPCODE) { 1510 assert((opcode & 0x3) == 0); 1511 1512 slot = &papr_hypercall_table[opcode / 4]; 1513 } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { 1514 /* we only have SVM-related hcall numbers assigned in multiples of 4 */ 1515 assert((opcode & 0x3) == 0); 1516 1517 slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1518 } else { 1519 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1520 1521 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1522 } 1523 1524 assert(!(*slot)); 1525 *slot = fn; 1526 } 1527 1528 void spapr_unregister_hypercall(target_ulong opcode) 1529 { 1530 spapr_hcall_fn *slot; 1531 1532 if (opcode <= MAX_HCALL_OPCODE) { 1533 assert((opcode & 0x3) == 0); 1534 1535 slot = &papr_hypercall_table[opcode / 4]; 1536 } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { 1537 /* we only have SVM-related hcall numbers assigned in multiples of 4 */ 1538 assert((opcode & 0x3) == 0); 1539 1540 slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1541 } else { 1542 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1543 1544 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1545 } 1546 1547 *slot = NULL; 1548 } 1549 1550 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 1551 target_ulong *args) 1552 { 1553 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1554 1555 if ((opcode <= MAX_HCALL_OPCODE) 1556 && ((opcode & 0x3) == 0)) { 1557 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 1558 1559 if (fn) { 1560 return fn(cpu, spapr, opcode, args); 1561 } 1562 } else if ((opcode >= SVM_HCALL_BASE) && 1563 (opcode <= SVM_HCALL_MAX)) { 1564 spapr_hcall_fn fn = svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 1565 1566 if (fn) { 1567 return fn(cpu, spapr, opcode, args); 1568 } 1569 } else if ((opcode >= KVMPPC_HCALL_BASE) && 1570 (opcode <= KVMPPC_HCALL_MAX)) { 1571 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1572 1573 if (fn) { 1574 return fn(cpu, spapr, opcode, args); 1575 } 1576 } 1577 1578 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1579 opcode); 1580 return H_FUNCTION; 1581 } 1582 1583 #ifdef CONFIG_TCG 1584 static void hypercall_register_softmmu(void) 1585 { 1586 /* DO NOTHING */ 1587 } 1588 #else 1589 static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr, 1590 target_ulong opcode, target_ulong *args) 1591 { 1592 g_assert_not_reached(); 1593 } 1594 1595 static void hypercall_register_softmmu(void) 1596 { 1597 /* hcall-pft */ 1598 spapr_register_hypercall(H_ENTER, h_softmmu); 1599 spapr_register_hypercall(H_REMOVE, h_softmmu); 1600 spapr_register_hypercall(H_PROTECT, h_softmmu); 1601 spapr_register_hypercall(H_READ, h_softmmu); 1602 1603 /* hcall-bulk */ 1604 spapr_register_hypercall(H_BULK_REMOVE, h_softmmu); 1605 } 1606 #endif 1607 1608 static void hypercall_register_types(void) 1609 { 1610 hypercall_register_softmmu(); 1611 1612 /* hcall-hpt-resize */ 1613 spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 1614 spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 1615 1616 /* hcall-splpar */ 1617 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 1618 spapr_register_hypercall(H_CEDE, h_cede); 1619 spapr_register_hypercall(H_CONFER, h_confer); 1620 spapr_register_hypercall(H_PROD, h_prod); 1621 1622 /* hcall-join */ 1623 spapr_register_hypercall(H_JOIN, h_join); 1624 1625 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 1626 1627 /* processor register resource access h-calls */ 1628 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1629 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1630 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 1631 spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1632 spapr_register_hypercall(H_SET_MODE, h_set_mode); 1633 1634 /* In Memory Table MMU h-calls */ 1635 spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1636 spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1637 spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1638 1639 /* hcall-get-cpu-characteristics */ 1640 spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 1641 h_get_cpu_characteristics); 1642 1643 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differentiate 1644 * here between the "CI" and the "CACHE" variants, they will use whatever 1645 * mapping attributes qemu is using. When using KVM, the kernel will 1646 * enforce the attributes more strongly 1647 */ 1648 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 1649 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 1650 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 1651 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 1652 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 1653 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 1654 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 1655 1656 /* qemu/KVM-PPC specific hcalls */ 1657 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 1658 1659 /* ibm,client-architecture-support support */ 1660 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1661 1662 spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); 1663 } 1664 1665 type_init(hypercall_register_types) 1666