10d75590dSPeter Maydell #include "qemu/osdep.h" 2da34e65cSMarkus Armbruster #include "qapi/error.h" 3b3946626SVincent Palatin #include "sysemu/hw_accel.h" 454d31236SMarkus Armbruster #include "sysemu/runstate.h" 503dd024fSPaolo Bonzini #include "qemu/log.h" 6db725815SMarkus Armbruster #include "qemu/main-loop.h" 70b8fa32fSMarkus Armbruster #include "qemu/module.h" 80b0b8310SDavid Gibson #include "qemu/error-report.h" 99f64bd8aSPaolo Bonzini #include "cpu.h" 1063c91552SPaolo Bonzini #include "exec/exec-all.h" 119f64bd8aSPaolo Bonzini #include "helper_regs.h" 120d09e41aSPaolo Bonzini #include "hw/ppc/spapr.h" 137388efafSDavid Gibson #include "hw/ppc/spapr_cpu_core.h" 14d5aea6f3SDavid Gibson #include "mmu-hash64.h" 153794d548SAlexey Kardashevskiy #include "cpu-models.h" 163794d548SAlexey Kardashevskiy #include "trace.h" 173794d548SAlexey Kardashevskiy #include "kvm_ppc.h" 18facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 19b4db5413SSuraj Jitindar Singh #include "mmu-book3s-v3.h" 202cc0e2e8SDavid Hildenbrand #include "hw/mem/memory-device.h" 219f64bd8aSPaolo Bonzini 22af08a58fSThomas Huth static bool has_spr(PowerPCCPU *cpu, int spr) 23af08a58fSThomas Huth { 24af08a58fSThomas Huth /* We can test whether the SPR is defined by checking for a valid name */ 25af08a58fSThomas Huth return cpu->env.spr_cb[spr].name != NULL; 26af08a58fSThomas Huth } 27af08a58fSThomas Huth 28c6404adeSDavid Gibson static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) 29f3c75d42SAneesh Kumar K.V { 30f3c75d42SAneesh Kumar K.V /* 3136778660SDavid Gibson * hash value/pteg group index is normalized by HPT mask 32f3c75d42SAneesh Kumar K.V */ 3336778660SDavid Gibson if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { 34f3c75d42SAneesh Kumar K.V return false; 35f3c75d42SAneesh Kumar K.V } 36f3c75d42SAneesh Kumar K.V return true; 37f3c75d42SAneesh Kumar K.V } 38f3c75d42SAneesh Kumar K.V 39ce2918cbSDavid Gibson static bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) 40ecbc25faSDavid Gibson { 41ecbc25faSDavid Gibson MachineState *machine = MACHINE(spapr); 42e017da37SDavid Hildenbrand DeviceMemoryState *dms = machine->device_memory; 43ecbc25faSDavid Gibson 44ecbc25faSDavid Gibson if (addr < machine->ram_size) { 45ecbc25faSDavid Gibson return true; 46ecbc25faSDavid Gibson } 47e017da37SDavid Hildenbrand if ((addr >= dms->base) 48e017da37SDavid Hildenbrand && ((addr - dms->base) < memory_region_size(&dms->mr))) { 49ecbc25faSDavid Gibson return true; 50ecbc25faSDavid Gibson } 51ecbc25faSDavid Gibson 52ecbc25faSDavid Gibson return false; 53ecbc25faSDavid Gibson } 54ecbc25faSDavid Gibson 55ce2918cbSDavid Gibson static target_ulong h_enter(PowerPCCPU *cpu, SpaprMachineState *spapr, 569f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 579f64bd8aSPaolo Bonzini { 589f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 59c6404adeSDavid Gibson target_ulong ptex = args[1]; 609f64bd8aSPaolo Bonzini target_ulong pteh = args[2]; 619f64bd8aSPaolo Bonzini target_ulong ptel = args[3]; 621f0252e6SCédric Le Goater unsigned apshift; 639f64bd8aSPaolo Bonzini target_ulong raddr; 64c6404adeSDavid Gibson target_ulong slot; 657222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 669f64bd8aSPaolo Bonzini 671f0252e6SCédric Le Goater apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); 681114e712SDavid Gibson if (!apshift) { 691114e712SDavid Gibson /* Bad page size encoding */ 709f64bd8aSPaolo Bonzini return H_PARAMETER; 719f64bd8aSPaolo Bonzini } 729f64bd8aSPaolo Bonzini 731114e712SDavid Gibson raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); 749f64bd8aSPaolo Bonzini 75ecbc25faSDavid Gibson if (is_ram_address(spapr, raddr)) { 769f64bd8aSPaolo Bonzini /* Regular RAM - should have WIMG=0010 */ 77d5aea6f3SDavid Gibson if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 789f64bd8aSPaolo Bonzini return H_PARAMETER; 799f64bd8aSPaolo Bonzini } 809f64bd8aSPaolo Bonzini } else { 81c1175907SAneesh Kumar K.V target_ulong wimg_flags; 829f64bd8aSPaolo Bonzini /* Looks like an IO address */ 839f64bd8aSPaolo Bonzini /* FIXME: What WIMG combinations could be sensible for IO? 849f64bd8aSPaolo Bonzini * For now we allow WIMG=010x, but are there others? */ 859f64bd8aSPaolo Bonzini /* FIXME: Should we check against registered IO addresses? */ 86c1175907SAneesh Kumar K.V wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); 87c1175907SAneesh Kumar K.V 88c1175907SAneesh Kumar K.V if (wimg_flags != HPTE64_R_I && 89c1175907SAneesh Kumar K.V wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { 909f64bd8aSPaolo Bonzini return H_PARAMETER; 919f64bd8aSPaolo Bonzini } 929f64bd8aSPaolo Bonzini } 939f64bd8aSPaolo Bonzini 949f64bd8aSPaolo Bonzini pteh &= ~0x60ULL; 959f64bd8aSPaolo Bonzini 96c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 979f64bd8aSPaolo Bonzini return H_PARAMETER; 989f64bd8aSPaolo Bonzini } 997c43bca0SAneesh Kumar K.V 100c6404adeSDavid Gibson slot = ptex & 7ULL; 101c6404adeSDavid Gibson ptex = ptex & ~7ULL; 102c6404adeSDavid Gibson 1039f64bd8aSPaolo Bonzini if (likely((flags & H_EXACT) == 0)) { 1047222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 105c6404adeSDavid Gibson for (slot = 0; slot < 8; slot++) { 1067222b94aSDavid Gibson if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { 1079f64bd8aSPaolo Bonzini break; 1089f64bd8aSPaolo Bonzini } 1097aaf4957SAneesh Kumar K.V } 1107222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 111c6404adeSDavid Gibson if (slot == 8) { 1127aaf4957SAneesh Kumar K.V return H_PTEG_FULL; 1137aaf4957SAneesh Kumar K.V } 1149f64bd8aSPaolo Bonzini } else { 1157222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); 1167222b94aSDavid Gibson if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { 1177222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); 1189f64bd8aSPaolo Bonzini return H_PTEG_FULL; 1199f64bd8aSPaolo Bonzini } 1207222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 1219f64bd8aSPaolo Bonzini } 1227c43bca0SAneesh Kumar K.V 123a2dd4e83SBenjamin Herrenschmidt spapr_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); 1249f64bd8aSPaolo Bonzini 125c6404adeSDavid Gibson args[0] = ptex + slot; 1269f64bd8aSPaolo Bonzini return H_SUCCESS; 1279f64bd8aSPaolo Bonzini } 1289f64bd8aSPaolo Bonzini 129a3801402SStefan Weil typedef enum { 1309f64bd8aSPaolo Bonzini REMOVE_SUCCESS = 0, 1319f64bd8aSPaolo Bonzini REMOVE_NOT_FOUND = 1, 1329f64bd8aSPaolo Bonzini REMOVE_PARM = 2, 1339f64bd8aSPaolo Bonzini REMOVE_HW = 3, 134a3801402SStefan Weil } RemoveResult; 1359f64bd8aSPaolo Bonzini 136a2dd4e83SBenjamin Herrenschmidt static RemoveResult remove_hpte(PowerPCCPU *cpu 137a2dd4e83SBenjamin Herrenschmidt , target_ulong ptex, 1389f64bd8aSPaolo Bonzini target_ulong avpn, 1399f64bd8aSPaolo Bonzini target_ulong flags, 1409f64bd8aSPaolo Bonzini target_ulong *vp, target_ulong *rp) 1419f64bd8aSPaolo Bonzini { 1427222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 14361a36c9bSDavid Gibson target_ulong v, r; 1449f64bd8aSPaolo Bonzini 145c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 1469f64bd8aSPaolo Bonzini return REMOVE_PARM; 1479f64bd8aSPaolo Bonzini } 1489f64bd8aSPaolo Bonzini 1497222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 1507222b94aSDavid Gibson v = ppc_hash64_hpte0(cpu, hptes, 0); 1517222b94aSDavid Gibson r = ppc_hash64_hpte1(cpu, hptes, 0); 1527222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 1539f64bd8aSPaolo Bonzini 154d5aea6f3SDavid Gibson if ((v & HPTE64_V_VALID) == 0 || 1559f64bd8aSPaolo Bonzini ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 1569f64bd8aSPaolo Bonzini ((flags & H_ANDCOND) && (v & avpn) != 0)) { 1579f64bd8aSPaolo Bonzini return REMOVE_NOT_FOUND; 1589f64bd8aSPaolo Bonzini } 1599f64bd8aSPaolo Bonzini *vp = v; 1609f64bd8aSPaolo Bonzini *rp = r; 161a2dd4e83SBenjamin Herrenschmidt spapr_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); 16261a36c9bSDavid Gibson ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 1639f64bd8aSPaolo Bonzini return REMOVE_SUCCESS; 1649f64bd8aSPaolo Bonzini } 1659f64bd8aSPaolo Bonzini 166ce2918cbSDavid Gibson static target_ulong h_remove(PowerPCCPU *cpu, SpaprMachineState *spapr, 1679f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 1689f64bd8aSPaolo Bonzini { 169cd0c6f47SBenjamin Herrenschmidt CPUPPCState *env = &cpu->env; 1709f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 171c6404adeSDavid Gibson target_ulong ptex = args[1]; 1729f64bd8aSPaolo Bonzini target_ulong avpn = args[2]; 173a3801402SStefan Weil RemoveResult ret; 1749f64bd8aSPaolo Bonzini 175c6404adeSDavid Gibson ret = remove_hpte(cpu, ptex, avpn, flags, 1769f64bd8aSPaolo Bonzini &args[0], &args[1]); 1779f64bd8aSPaolo Bonzini 1789f64bd8aSPaolo Bonzini switch (ret) { 1799f64bd8aSPaolo Bonzini case REMOVE_SUCCESS: 180e3cffe6fSNikunj A Dadhania check_tlb_flush(env, true); 1819f64bd8aSPaolo Bonzini return H_SUCCESS; 1829f64bd8aSPaolo Bonzini 1839f64bd8aSPaolo Bonzini case REMOVE_NOT_FOUND: 1849f64bd8aSPaolo Bonzini return H_NOT_FOUND; 1859f64bd8aSPaolo Bonzini 1869f64bd8aSPaolo Bonzini case REMOVE_PARM: 1879f64bd8aSPaolo Bonzini return H_PARAMETER; 1889f64bd8aSPaolo Bonzini 1899f64bd8aSPaolo Bonzini case REMOVE_HW: 1909f64bd8aSPaolo Bonzini return H_HARDWARE; 1919f64bd8aSPaolo Bonzini } 1929f64bd8aSPaolo Bonzini 1939a39970dSStefan Weil g_assert_not_reached(); 1949f64bd8aSPaolo Bonzini } 1959f64bd8aSPaolo Bonzini 1969f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 1979f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 1989f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 1999f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_END 0xc000000000000000ULL 2009f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 2019f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 2029f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 2039f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 2049f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_HW 0x3000000000000000ULL 2059f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 2069f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 2079f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 2089f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 2099f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 2109f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 2119f64bd8aSPaolo Bonzini 2129f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_MAX_BATCH 4 2139f64bd8aSPaolo Bonzini 214ce2918cbSDavid Gibson static target_ulong h_bulk_remove(PowerPCCPU *cpu, SpaprMachineState *spapr, 2159f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 2169f64bd8aSPaolo Bonzini { 217cd0c6f47SBenjamin Herrenschmidt CPUPPCState *env = &cpu->env; 2189f64bd8aSPaolo Bonzini int i; 219cd0c6f47SBenjamin Herrenschmidt target_ulong rc = H_SUCCESS; 2209f64bd8aSPaolo Bonzini 2219f64bd8aSPaolo Bonzini for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 2229f64bd8aSPaolo Bonzini target_ulong *tsh = &args[i*2]; 2239f64bd8aSPaolo Bonzini target_ulong tsl = args[i*2 + 1]; 2249f64bd8aSPaolo Bonzini target_ulong v, r, ret; 2259f64bd8aSPaolo Bonzini 2269f64bd8aSPaolo Bonzini if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 2279f64bd8aSPaolo Bonzini break; 2289f64bd8aSPaolo Bonzini } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 2299f64bd8aSPaolo Bonzini return H_PARAMETER; 2309f64bd8aSPaolo Bonzini } 2319f64bd8aSPaolo Bonzini 2329f64bd8aSPaolo Bonzini *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 2339f64bd8aSPaolo Bonzini *tsh |= H_BULK_REMOVE_RESPONSE; 2349f64bd8aSPaolo Bonzini 2359f64bd8aSPaolo Bonzini if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 2369f64bd8aSPaolo Bonzini *tsh |= H_BULK_REMOVE_PARM; 2379f64bd8aSPaolo Bonzini return H_PARAMETER; 2389f64bd8aSPaolo Bonzini } 2399f64bd8aSPaolo Bonzini 2407ef23068SDavid Gibson ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, 2419f64bd8aSPaolo Bonzini (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 2429f64bd8aSPaolo Bonzini &v, &r); 2439f64bd8aSPaolo Bonzini 2449f64bd8aSPaolo Bonzini *tsh |= ret << 60; 2459f64bd8aSPaolo Bonzini 2469f64bd8aSPaolo Bonzini switch (ret) { 2479f64bd8aSPaolo Bonzini case REMOVE_SUCCESS: 248d5aea6f3SDavid Gibson *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 2499f64bd8aSPaolo Bonzini break; 2509f64bd8aSPaolo Bonzini 2519f64bd8aSPaolo Bonzini case REMOVE_PARM: 252cd0c6f47SBenjamin Herrenschmidt rc = H_PARAMETER; 253cd0c6f47SBenjamin Herrenschmidt goto exit; 2549f64bd8aSPaolo Bonzini 2559f64bd8aSPaolo Bonzini case REMOVE_HW: 256cd0c6f47SBenjamin Herrenschmidt rc = H_HARDWARE; 257cd0c6f47SBenjamin Herrenschmidt goto exit; 2589f64bd8aSPaolo Bonzini } 2599f64bd8aSPaolo Bonzini } 260cd0c6f47SBenjamin Herrenschmidt exit: 261e3cffe6fSNikunj A Dadhania check_tlb_flush(env, true); 2629f64bd8aSPaolo Bonzini 263cd0c6f47SBenjamin Herrenschmidt return rc; 2649f64bd8aSPaolo Bonzini } 2659f64bd8aSPaolo Bonzini 266ce2918cbSDavid Gibson static target_ulong h_protect(PowerPCCPU *cpu, SpaprMachineState *spapr, 2679f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 2689f64bd8aSPaolo Bonzini { 2699f64bd8aSPaolo Bonzini CPUPPCState *env = &cpu->env; 2709f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 271c6404adeSDavid Gibson target_ulong ptex = args[1]; 2729f64bd8aSPaolo Bonzini target_ulong avpn = args[2]; 2737222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 27461a36c9bSDavid Gibson target_ulong v, r; 2759f64bd8aSPaolo Bonzini 276c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 2779f64bd8aSPaolo Bonzini return H_PARAMETER; 2789f64bd8aSPaolo Bonzini } 2799f64bd8aSPaolo Bonzini 2807222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 2817222b94aSDavid Gibson v = ppc_hash64_hpte0(cpu, hptes, 0); 2827222b94aSDavid Gibson r = ppc_hash64_hpte1(cpu, hptes, 0); 2837222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 2849f64bd8aSPaolo Bonzini 285d5aea6f3SDavid Gibson if ((v & HPTE64_V_VALID) == 0 || 2869f64bd8aSPaolo Bonzini ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 2879f64bd8aSPaolo Bonzini return H_NOT_FOUND; 2889f64bd8aSPaolo Bonzini } 2899f64bd8aSPaolo Bonzini 290d5aea6f3SDavid Gibson r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 291d5aea6f3SDavid Gibson HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 292d5aea6f3SDavid Gibson r |= (flags << 55) & HPTE64_R_PP0; 293d5aea6f3SDavid Gibson r |= (flags << 48) & HPTE64_R_KEY_HI; 294d5aea6f3SDavid Gibson r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 295a2dd4e83SBenjamin Herrenschmidt spapr_store_hpte(cpu, ptex, 2963f94170bSAneesh Kumar K.V (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); 297c6404adeSDavid Gibson ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 298d76ab5e1SNikunj A Dadhania /* Flush the tlb */ 299d76ab5e1SNikunj A Dadhania check_tlb_flush(env, true); 3009f64bd8aSPaolo Bonzini /* Don't need a memory barrier, due to qemu's global lock */ 301a2dd4e83SBenjamin Herrenschmidt spapr_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); 3029f64bd8aSPaolo Bonzini return H_SUCCESS; 3039f64bd8aSPaolo Bonzini } 3049f64bd8aSPaolo Bonzini 305ce2918cbSDavid Gibson static target_ulong h_read(PowerPCCPU *cpu, SpaprMachineState *spapr, 306fa388916SAnthony Liguori target_ulong opcode, target_ulong *args) 307fa388916SAnthony Liguori { 308fa388916SAnthony Liguori target_ulong flags = args[0]; 309c6404adeSDavid Gibson target_ulong ptex = args[1]; 310fa388916SAnthony Liguori int i, ridx, n_entries = 1; 311993aaf0cSBenjamin Herrenschmidt const ppc_hash_pte64_t *hptes; 312fa388916SAnthony Liguori 313c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 314fa388916SAnthony Liguori return H_PARAMETER; 315fa388916SAnthony Liguori } 316fa388916SAnthony Liguori 317fa388916SAnthony Liguori if (flags & H_READ_4) { 318fa388916SAnthony Liguori /* Clear the two low order bits */ 319c6404adeSDavid Gibson ptex &= ~(3ULL); 320fa388916SAnthony Liguori n_entries = 4; 321fa388916SAnthony Liguori } 322fa388916SAnthony Liguori 323993aaf0cSBenjamin Herrenschmidt hptes = ppc_hash64_map_hptes(cpu, ptex, n_entries); 324fa388916SAnthony Liguori for (i = 0, ridx = 0; i < n_entries; i++) { 325993aaf0cSBenjamin Herrenschmidt args[ridx++] = ppc_hash64_hpte0(cpu, hptes, i); 326993aaf0cSBenjamin Herrenschmidt args[ridx++] = ppc_hash64_hpte1(cpu, hptes, i); 327fa388916SAnthony Liguori } 328993aaf0cSBenjamin Herrenschmidt ppc_hash64_unmap_hptes(cpu, hptes, ptex, n_entries); 329fa388916SAnthony Liguori 330fa388916SAnthony Liguori return H_SUCCESS; 331fa388916SAnthony Liguori } 332fa388916SAnthony Liguori 333ce2918cbSDavid Gibson struct SpaprPendingHpt { 3340b0b8310SDavid Gibson /* These fields are read-only after initialization */ 3350b0b8310SDavid Gibson int shift; 3360b0b8310SDavid Gibson QemuThread thread; 3370b0b8310SDavid Gibson 3380b0b8310SDavid Gibson /* These fields are protected by the BQL */ 3390b0b8310SDavid Gibson bool complete; 3400b0b8310SDavid Gibson 3410b0b8310SDavid Gibson /* These fields are private to the preparation thread if 3420b0b8310SDavid Gibson * !complete, otherwise protected by the BQL */ 3430b0b8310SDavid Gibson int ret; 3440b0b8310SDavid Gibson void *hpt; 3450b0b8310SDavid Gibson }; 3460b0b8310SDavid Gibson 347ce2918cbSDavid Gibson static void free_pending_hpt(SpaprPendingHpt *pending) 3480b0b8310SDavid Gibson { 3490b0b8310SDavid Gibson if (pending->hpt) { 3500b0b8310SDavid Gibson qemu_vfree(pending->hpt); 3510b0b8310SDavid Gibson } 3520b0b8310SDavid Gibson 3530b0b8310SDavid Gibson g_free(pending); 3540b0b8310SDavid Gibson } 3550b0b8310SDavid Gibson 3560b0b8310SDavid Gibson static void *hpt_prepare_thread(void *opaque) 3570b0b8310SDavid Gibson { 358ce2918cbSDavid Gibson SpaprPendingHpt *pending = opaque; 3590b0b8310SDavid Gibson size_t size = 1ULL << pending->shift; 3600b0b8310SDavid Gibson 3610b0b8310SDavid Gibson pending->hpt = qemu_memalign(size, size); 3620b0b8310SDavid Gibson if (pending->hpt) { 3630b0b8310SDavid Gibson memset(pending->hpt, 0, size); 3640b0b8310SDavid Gibson pending->ret = H_SUCCESS; 3650b0b8310SDavid Gibson } else { 3660b0b8310SDavid Gibson pending->ret = H_NO_MEM; 3670b0b8310SDavid Gibson } 3680b0b8310SDavid Gibson 3690b0b8310SDavid Gibson qemu_mutex_lock_iothread(); 3700b0b8310SDavid Gibson 3710b0b8310SDavid Gibson if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) { 3720b0b8310SDavid Gibson /* Ready to go */ 3730b0b8310SDavid Gibson pending->complete = true; 3740b0b8310SDavid Gibson } else { 3750b0b8310SDavid Gibson /* We've been cancelled, clean ourselves up */ 3760b0b8310SDavid Gibson free_pending_hpt(pending); 3770b0b8310SDavid Gibson } 3780b0b8310SDavid Gibson 3790b0b8310SDavid Gibson qemu_mutex_unlock_iothread(); 3800b0b8310SDavid Gibson return NULL; 3810b0b8310SDavid Gibson } 3820b0b8310SDavid Gibson 3830b0b8310SDavid Gibson /* Must be called with BQL held */ 384ce2918cbSDavid Gibson static void cancel_hpt_prepare(SpaprMachineState *spapr) 3850b0b8310SDavid Gibson { 386ce2918cbSDavid Gibson SpaprPendingHpt *pending = spapr->pending_hpt; 3870b0b8310SDavid Gibson 3880b0b8310SDavid Gibson /* Let the thread know it's cancelled */ 3890b0b8310SDavid Gibson spapr->pending_hpt = NULL; 3900b0b8310SDavid Gibson 3910b0b8310SDavid Gibson if (!pending) { 3920b0b8310SDavid Gibson /* Nothing to do */ 3930b0b8310SDavid Gibson return; 3940b0b8310SDavid Gibson } 3950b0b8310SDavid Gibson 3960b0b8310SDavid Gibson if (!pending->complete) { 3970b0b8310SDavid Gibson /* thread will clean itself up */ 3980b0b8310SDavid Gibson return; 3990b0b8310SDavid Gibson } 4000b0b8310SDavid Gibson 4010b0b8310SDavid Gibson free_pending_hpt(pending); 4020b0b8310SDavid Gibson } 4030b0b8310SDavid Gibson 404b55d295eSDavid Gibson /* Convert a return code from the KVM ioctl()s implementing resize HPT 405b55d295eSDavid Gibson * into a PAPR hypercall return code */ 406b55d295eSDavid Gibson static target_ulong resize_hpt_convert_rc(int ret) 407b55d295eSDavid Gibson { 408b55d295eSDavid Gibson if (ret >= 100000) { 409b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_100_SEC; 410b55d295eSDavid Gibson } else if (ret >= 10000) { 411b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_10_SEC; 412b55d295eSDavid Gibson } else if (ret >= 1000) { 413b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_1_SEC; 414b55d295eSDavid Gibson } else if (ret >= 100) { 415b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 416b55d295eSDavid Gibson } else if (ret >= 10) { 417b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_10_MSEC; 418b55d295eSDavid Gibson } else if (ret > 0) { 419b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_1_MSEC; 420b55d295eSDavid Gibson } 421b55d295eSDavid Gibson 422b55d295eSDavid Gibson switch (ret) { 423b55d295eSDavid Gibson case 0: 424b55d295eSDavid Gibson return H_SUCCESS; 425b55d295eSDavid Gibson case -EPERM: 426b55d295eSDavid Gibson return H_AUTHORITY; 427b55d295eSDavid Gibson case -EINVAL: 428b55d295eSDavid Gibson return H_PARAMETER; 429b55d295eSDavid Gibson case -ENXIO: 430b55d295eSDavid Gibson return H_CLOSED; 431b55d295eSDavid Gibson case -ENOSPC: 432b55d295eSDavid Gibson return H_PTEG_FULL; 433b55d295eSDavid Gibson case -EBUSY: 434b55d295eSDavid Gibson return H_BUSY; 435b55d295eSDavid Gibson case -ENOMEM: 436b55d295eSDavid Gibson return H_NO_MEM; 437b55d295eSDavid Gibson default: 438b55d295eSDavid Gibson return H_HARDWARE; 439b55d295eSDavid Gibson } 440b55d295eSDavid Gibson } 441b55d295eSDavid Gibson 44230f4b05bSDavid Gibson static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 443ce2918cbSDavid Gibson SpaprMachineState *spapr, 44430f4b05bSDavid Gibson target_ulong opcode, 44530f4b05bSDavid Gibson target_ulong *args) 44630f4b05bSDavid Gibson { 44730f4b05bSDavid Gibson target_ulong flags = args[0]; 4480b0b8310SDavid Gibson int shift = args[1]; 449ce2918cbSDavid Gibson SpaprPendingHpt *pending = spapr->pending_hpt; 450db50f280SDavid Gibson uint64_t current_ram_size; 451b55d295eSDavid Gibson int rc; 45230f4b05bSDavid Gibson 45330f4b05bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 45430f4b05bSDavid Gibson return H_AUTHORITY; 45530f4b05bSDavid Gibson } 45630f4b05bSDavid Gibson 4570b0b8310SDavid Gibson if (!spapr->htab_shift) { 4580b0b8310SDavid Gibson /* Radix guest, no HPT */ 4590b0b8310SDavid Gibson return H_NOT_AVAILABLE; 4600b0b8310SDavid Gibson } 4610b0b8310SDavid Gibson 46230f4b05bSDavid Gibson trace_spapr_h_resize_hpt_prepare(flags, shift); 4630b0b8310SDavid Gibson 4640b0b8310SDavid Gibson if (flags != 0) { 4650b0b8310SDavid Gibson return H_PARAMETER; 4660b0b8310SDavid Gibson } 4670b0b8310SDavid Gibson 4680b0b8310SDavid Gibson if (shift && ((shift < 18) || (shift > 46))) { 4690b0b8310SDavid Gibson return H_PARAMETER; 4700b0b8310SDavid Gibson } 4710b0b8310SDavid Gibson 472db50f280SDavid Gibson current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 4730b0b8310SDavid Gibson 4740b0b8310SDavid Gibson /* We only allow the guest to allocate an HPT one order above what 4750b0b8310SDavid Gibson * we'd normally give them (to stop a small guest claiming a huge 4760b0b8310SDavid Gibson * chunk of resources in the HPT */ 4770b0b8310SDavid Gibson if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 4780b0b8310SDavid Gibson return H_RESOURCE; 4790b0b8310SDavid Gibson } 4800b0b8310SDavid Gibson 481b55d295eSDavid Gibson rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 482b55d295eSDavid Gibson if (rc != -ENOSYS) { 483b55d295eSDavid Gibson return resize_hpt_convert_rc(rc); 484b55d295eSDavid Gibson } 485b55d295eSDavid Gibson 4860b0b8310SDavid Gibson if (pending) { 4870b0b8310SDavid Gibson /* something already in progress */ 4880b0b8310SDavid Gibson if (pending->shift == shift) { 4890b0b8310SDavid Gibson /* and it's suitable */ 4900b0b8310SDavid Gibson if (pending->complete) { 4910b0b8310SDavid Gibson return pending->ret; 4920b0b8310SDavid Gibson } else { 4930b0b8310SDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 4940b0b8310SDavid Gibson } 4950b0b8310SDavid Gibson } 4960b0b8310SDavid Gibson 4970b0b8310SDavid Gibson /* not suitable, cancel and replace */ 4980b0b8310SDavid Gibson cancel_hpt_prepare(spapr); 4990b0b8310SDavid Gibson } 5000b0b8310SDavid Gibson 5010b0b8310SDavid Gibson if (!shift) { 5020b0b8310SDavid Gibson /* nothing to do */ 5030b0b8310SDavid Gibson return H_SUCCESS; 5040b0b8310SDavid Gibson } 5050b0b8310SDavid Gibson 5060b0b8310SDavid Gibson /* start new prepare */ 5070b0b8310SDavid Gibson 508ce2918cbSDavid Gibson pending = g_new0(SpaprPendingHpt, 1); 5090b0b8310SDavid Gibson pending->shift = shift; 5100b0b8310SDavid Gibson pending->ret = H_HARDWARE; 5110b0b8310SDavid Gibson 5120b0b8310SDavid Gibson qemu_thread_create(&pending->thread, "sPAPR HPT prepare", 5130b0b8310SDavid Gibson hpt_prepare_thread, pending, QEMU_THREAD_DETACHED); 5140b0b8310SDavid Gibson 5150b0b8310SDavid Gibson spapr->pending_hpt = pending; 5160b0b8310SDavid Gibson 5170b0b8310SDavid Gibson /* In theory we could estimate the time more accurately based on 5180b0b8310SDavid Gibson * the new size, but there's not much point */ 5190b0b8310SDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 5200b0b8310SDavid Gibson } 5210b0b8310SDavid Gibson 5220b0b8310SDavid Gibson static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot) 5230b0b8310SDavid Gibson { 5240b0b8310SDavid Gibson uint8_t *addr = htab; 5250b0b8310SDavid Gibson 5260b0b8310SDavid Gibson addr += pteg * HASH_PTEG_SIZE_64; 5270b0b8310SDavid Gibson addr += slot * HASH_PTE_SIZE_64; 5280b0b8310SDavid Gibson return ldq_p(addr); 5290b0b8310SDavid Gibson } 5300b0b8310SDavid Gibson 5310b0b8310SDavid Gibson static void new_hpte_store(void *htab, uint64_t pteg, int slot, 5320b0b8310SDavid Gibson uint64_t pte0, uint64_t pte1) 5330b0b8310SDavid Gibson { 5340b0b8310SDavid Gibson uint8_t *addr = htab; 5350b0b8310SDavid Gibson 5360b0b8310SDavid Gibson addr += pteg * HASH_PTEG_SIZE_64; 5370b0b8310SDavid Gibson addr += slot * HASH_PTE_SIZE_64; 5380b0b8310SDavid Gibson 5390b0b8310SDavid Gibson stq_p(addr, pte0); 5400b0b8310SDavid Gibson stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1); 5410b0b8310SDavid Gibson } 5420b0b8310SDavid Gibson 5430b0b8310SDavid Gibson static int rehash_hpte(PowerPCCPU *cpu, 5440b0b8310SDavid Gibson const ppc_hash_pte64_t *hptes, 5450b0b8310SDavid Gibson void *old_hpt, uint64_t oldsize, 5460b0b8310SDavid Gibson void *new_hpt, uint64_t newsize, 5470b0b8310SDavid Gibson uint64_t pteg, int slot) 5480b0b8310SDavid Gibson { 5490b0b8310SDavid Gibson uint64_t old_hash_mask = (oldsize >> 7) - 1; 5500b0b8310SDavid Gibson uint64_t new_hash_mask = (newsize >> 7) - 1; 5510b0b8310SDavid Gibson target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot); 5520b0b8310SDavid Gibson target_ulong pte1; 5530b0b8310SDavid Gibson uint64_t avpn; 5540b0b8310SDavid Gibson unsigned base_pg_shift; 5550b0b8310SDavid Gibson uint64_t hash, new_pteg, replace_pte0; 5560b0b8310SDavid Gibson 5570b0b8310SDavid Gibson if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) { 5580b0b8310SDavid Gibson return H_SUCCESS; 5590b0b8310SDavid Gibson } 5600b0b8310SDavid Gibson 5610b0b8310SDavid Gibson pte1 = ppc_hash64_hpte1(cpu, hptes, slot); 5620b0b8310SDavid Gibson 5630b0b8310SDavid Gibson base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1); 5640b0b8310SDavid Gibson assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */ 5650b0b8310SDavid Gibson avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23); 5660b0b8310SDavid Gibson 5670b0b8310SDavid Gibson if (pte0 & HPTE64_V_SECONDARY) { 5680b0b8310SDavid Gibson pteg = ~pteg; 5690b0b8310SDavid Gibson } 5700b0b8310SDavid Gibson 5710b0b8310SDavid Gibson if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) { 5720b0b8310SDavid Gibson uint64_t offset, vsid; 5730b0b8310SDavid Gibson 5740b0b8310SDavid Gibson /* We only have 28 - 23 bits of offset in avpn */ 5750b0b8310SDavid Gibson offset = (avpn & 0x1f) << 23; 5760b0b8310SDavid Gibson vsid = avpn >> 5; 5770b0b8310SDavid Gibson /* We can find more bits from the pteg value */ 5780b0b8310SDavid Gibson if (base_pg_shift < 23) { 5790b0b8310SDavid Gibson offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift; 5800b0b8310SDavid Gibson } 5810b0b8310SDavid Gibson 5820b0b8310SDavid Gibson hash = vsid ^ (offset >> base_pg_shift); 5830b0b8310SDavid Gibson } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) { 5840b0b8310SDavid Gibson uint64_t offset, vsid; 5850b0b8310SDavid Gibson 5860b0b8310SDavid Gibson /* We only have 40 - 23 bits of seg_off in avpn */ 5870b0b8310SDavid Gibson offset = (avpn & 0x1ffff) << 23; 5880b0b8310SDavid Gibson vsid = avpn >> 17; 5890b0b8310SDavid Gibson if (base_pg_shift < 23) { 5900b0b8310SDavid Gibson offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask) 5910b0b8310SDavid Gibson << base_pg_shift; 5920b0b8310SDavid Gibson } 5930b0b8310SDavid Gibson 5940b0b8310SDavid Gibson hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift); 5950b0b8310SDavid Gibson } else { 5960b0b8310SDavid Gibson error_report("rehash_pte: Bad segment size in HPTE"); 59730f4b05bSDavid Gibson return H_HARDWARE; 59830f4b05bSDavid Gibson } 59930f4b05bSDavid Gibson 6000b0b8310SDavid Gibson new_pteg = hash & new_hash_mask; 6010b0b8310SDavid Gibson if (pte0 & HPTE64_V_SECONDARY) { 6020b0b8310SDavid Gibson assert(~pteg == (hash & old_hash_mask)); 6030b0b8310SDavid Gibson new_pteg = ~new_pteg; 6040b0b8310SDavid Gibson } else { 6050b0b8310SDavid Gibson assert(pteg == (hash & old_hash_mask)); 6060b0b8310SDavid Gibson } 6070b0b8310SDavid Gibson assert((oldsize != newsize) || (pteg == new_pteg)); 6080b0b8310SDavid Gibson replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot); 6090b0b8310SDavid Gibson /* 6100b0b8310SDavid Gibson * Strictly speaking, we don't need all these tests, since we only 6110b0b8310SDavid Gibson * ever rehash bolted HPTEs. We might in future handle non-bolted 6120b0b8310SDavid Gibson * HPTEs, though so make the logic correct for those cases as 6130b0b8310SDavid Gibson * well. 6140b0b8310SDavid Gibson */ 6150b0b8310SDavid Gibson if (replace_pte0 & HPTE64_V_VALID) { 6160b0b8310SDavid Gibson assert(newsize < oldsize); 6170b0b8310SDavid Gibson if (replace_pte0 & HPTE64_V_BOLTED) { 6180b0b8310SDavid Gibson if (pte0 & HPTE64_V_BOLTED) { 6190b0b8310SDavid Gibson /* Bolted collision, nothing we can do */ 6200b0b8310SDavid Gibson return H_PTEG_FULL; 6210b0b8310SDavid Gibson } else { 6220b0b8310SDavid Gibson /* Discard this hpte */ 6230b0b8310SDavid Gibson return H_SUCCESS; 6240b0b8310SDavid Gibson } 6250b0b8310SDavid Gibson } 6260b0b8310SDavid Gibson } 6270b0b8310SDavid Gibson 6280b0b8310SDavid Gibson new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1); 6290b0b8310SDavid Gibson return H_SUCCESS; 6300b0b8310SDavid Gibson } 6310b0b8310SDavid Gibson 6320b0b8310SDavid Gibson static int rehash_hpt(PowerPCCPU *cpu, 6330b0b8310SDavid Gibson void *old_hpt, uint64_t oldsize, 6340b0b8310SDavid Gibson void *new_hpt, uint64_t newsize) 6350b0b8310SDavid Gibson { 6360b0b8310SDavid Gibson uint64_t n_ptegs = oldsize >> 7; 6370b0b8310SDavid Gibson uint64_t pteg; 6380b0b8310SDavid Gibson int slot; 6390b0b8310SDavid Gibson int rc; 6400b0b8310SDavid Gibson 6410b0b8310SDavid Gibson for (pteg = 0; pteg < n_ptegs; pteg++) { 6420b0b8310SDavid Gibson hwaddr ptex = pteg * HPTES_PER_GROUP; 6430b0b8310SDavid Gibson const ppc_hash_pte64_t *hptes 6440b0b8310SDavid Gibson = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 6450b0b8310SDavid Gibson 6460b0b8310SDavid Gibson if (!hptes) { 6470b0b8310SDavid Gibson return H_HARDWARE; 6480b0b8310SDavid Gibson } 6490b0b8310SDavid Gibson 6500b0b8310SDavid Gibson for (slot = 0; slot < HPTES_PER_GROUP; slot++) { 6510b0b8310SDavid Gibson rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize, 6520b0b8310SDavid Gibson pteg, slot); 6530b0b8310SDavid Gibson if (rc != H_SUCCESS) { 6540b0b8310SDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 6550b0b8310SDavid Gibson return rc; 6560b0b8310SDavid Gibson } 6570b0b8310SDavid Gibson } 6580b0b8310SDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 6590b0b8310SDavid Gibson } 6600b0b8310SDavid Gibson 6610b0b8310SDavid Gibson return H_SUCCESS; 6620b0b8310SDavid Gibson } 6630b0b8310SDavid Gibson 6641ec26c75SGreg Kurz static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 6651ec26c75SGreg Kurz { 6661ec26c75SGreg Kurz int ret; 6671ec26c75SGreg Kurz 6681ec26c75SGreg Kurz cpu_synchronize_state(cs); 6691ec26c75SGreg Kurz 6701ec26c75SGreg Kurz ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 6711ec26c75SGreg Kurz if (ret < 0) { 6721ec26c75SGreg Kurz error_report("failed to push sregs to KVM: %s", strerror(-ret)); 6731ec26c75SGreg Kurz exit(1); 6741ec26c75SGreg Kurz } 6751ec26c75SGreg Kurz } 6761ec26c75SGreg Kurz 677ce2918cbSDavid Gibson static void push_sregs_to_kvm_pr(SpaprMachineState *spapr) 6781ec26c75SGreg Kurz { 6791ec26c75SGreg Kurz CPUState *cs; 6801ec26c75SGreg Kurz 6811ec26c75SGreg Kurz /* 6821ec26c75SGreg Kurz * This is a hack for the benefit of KVM PR - it abuses the SDR1 6831ec26c75SGreg Kurz * slot in kvm_sregs to communicate the userspace address of the 6841ec26c75SGreg Kurz * HPT 6851ec26c75SGreg Kurz */ 6861ec26c75SGreg Kurz if (!kvm_enabled() || !spapr->htab) { 6871ec26c75SGreg Kurz return; 6881ec26c75SGreg Kurz } 6891ec26c75SGreg Kurz 6901ec26c75SGreg Kurz CPU_FOREACH(cs) { 6911ec26c75SGreg Kurz run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 6921ec26c75SGreg Kurz } 6931ec26c75SGreg Kurz } 6941ec26c75SGreg Kurz 69530f4b05bSDavid Gibson static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 696ce2918cbSDavid Gibson SpaprMachineState *spapr, 69730f4b05bSDavid Gibson target_ulong opcode, 69830f4b05bSDavid Gibson target_ulong *args) 69930f4b05bSDavid Gibson { 70030f4b05bSDavid Gibson target_ulong flags = args[0]; 70130f4b05bSDavid Gibson target_ulong shift = args[1]; 702ce2918cbSDavid Gibson SpaprPendingHpt *pending = spapr->pending_hpt; 7030b0b8310SDavid Gibson int rc; 7040b0b8310SDavid Gibson size_t newsize; 70530f4b05bSDavid Gibson 70630f4b05bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 70730f4b05bSDavid Gibson return H_AUTHORITY; 70830f4b05bSDavid Gibson } 70930f4b05bSDavid Gibson 71094789567SDaniel Henrique Barboza if (!spapr->htab_shift) { 71194789567SDaniel Henrique Barboza /* Radix guest, no HPT */ 71294789567SDaniel Henrique Barboza return H_NOT_AVAILABLE; 71394789567SDaniel Henrique Barboza } 71494789567SDaniel Henrique Barboza 71530f4b05bSDavid Gibson trace_spapr_h_resize_hpt_commit(flags, shift); 7160b0b8310SDavid Gibson 717b55d295eSDavid Gibson rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 718b55d295eSDavid Gibson if (rc != -ENOSYS) { 71994789567SDaniel Henrique Barboza rc = resize_hpt_convert_rc(rc); 72094789567SDaniel Henrique Barboza if (rc == H_SUCCESS) { 72194789567SDaniel Henrique Barboza /* Need to set the new htab_shift in the machine state */ 72294789567SDaniel Henrique Barboza spapr->htab_shift = shift; 72394789567SDaniel Henrique Barboza } 72494789567SDaniel Henrique Barboza return rc; 725b55d295eSDavid Gibson } 726b55d295eSDavid Gibson 7270b0b8310SDavid Gibson if (flags != 0) { 7280b0b8310SDavid Gibson return H_PARAMETER; 7290b0b8310SDavid Gibson } 7300b0b8310SDavid Gibson 7310b0b8310SDavid Gibson if (!pending || (pending->shift != shift)) { 7320b0b8310SDavid Gibson /* no matching prepare */ 7330b0b8310SDavid Gibson return H_CLOSED; 7340b0b8310SDavid Gibson } 7350b0b8310SDavid Gibson 7360b0b8310SDavid Gibson if (!pending->complete) { 7370b0b8310SDavid Gibson /* prepare has not completed */ 7380b0b8310SDavid Gibson return H_BUSY; 7390b0b8310SDavid Gibson } 7400b0b8310SDavid Gibson 7410b0b8310SDavid Gibson /* Shouldn't have got past PREPARE without an HPT */ 7420b0b8310SDavid Gibson g_assert(spapr->htab_shift); 7430b0b8310SDavid Gibson 7440b0b8310SDavid Gibson newsize = 1ULL << pending->shift; 7450b0b8310SDavid Gibson rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr), 7460b0b8310SDavid Gibson pending->hpt, newsize); 7470b0b8310SDavid Gibson if (rc == H_SUCCESS) { 7480b0b8310SDavid Gibson qemu_vfree(spapr->htab); 7490b0b8310SDavid Gibson spapr->htab = pending->hpt; 7500b0b8310SDavid Gibson spapr->htab_shift = pending->shift; 7510b0b8310SDavid Gibson 7521ec26c75SGreg Kurz push_sregs_to_kvm_pr(spapr); 753b55d295eSDavid Gibson 7540b0b8310SDavid Gibson pending->hpt = NULL; /* so it's not free()d */ 7550b0b8310SDavid Gibson } 7560b0b8310SDavid Gibson 7570b0b8310SDavid Gibson /* Clean up */ 7580b0b8310SDavid Gibson spapr->pending_hpt = NULL; 7590b0b8310SDavid Gibson free_pending_hpt(pending); 7600b0b8310SDavid Gibson 7610b0b8310SDavid Gibson return rc; 76230f4b05bSDavid Gibson } 76330f4b05bSDavid Gibson 764ce2918cbSDavid Gibson static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, 765423576f7SThomas Huth target_ulong opcode, target_ulong *args) 766423576f7SThomas Huth { 767423576f7SThomas Huth cpu_synchronize_state(CPU(cpu)); 768423576f7SThomas Huth cpu->env.spr[SPR_SPRG0] = args[0]; 769423576f7SThomas Huth 770423576f7SThomas Huth return H_SUCCESS; 771423576f7SThomas Huth } 772423576f7SThomas Huth 773ce2918cbSDavid Gibson static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 7749f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 7759f64bd8aSPaolo Bonzini { 776af08a58fSThomas Huth if (!has_spr(cpu, SPR_DABR)) { 777af08a58fSThomas Huth return H_HARDWARE; /* DABR register not available */ 778af08a58fSThomas Huth } 779af08a58fSThomas Huth cpu_synchronize_state(CPU(cpu)); 780af08a58fSThomas Huth 781af08a58fSThomas Huth if (has_spr(cpu, SPR_DABRX)) { 782af08a58fSThomas Huth cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 783af08a58fSThomas Huth } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 784af08a58fSThomas Huth return H_RESERVED_DABR; 785af08a58fSThomas Huth } 786af08a58fSThomas Huth 787af08a58fSThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 788af08a58fSThomas Huth return H_SUCCESS; 7899f64bd8aSPaolo Bonzini } 7909f64bd8aSPaolo Bonzini 791ce2918cbSDavid Gibson static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 792e49ff266SThomas Huth target_ulong opcode, target_ulong *args) 793e49ff266SThomas Huth { 794e49ff266SThomas Huth target_ulong dabrx = args[1]; 795e49ff266SThomas Huth 796e49ff266SThomas Huth if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { 797e49ff266SThomas Huth return H_HARDWARE; 798e49ff266SThomas Huth } 799e49ff266SThomas Huth 800e49ff266SThomas Huth if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 801e49ff266SThomas Huth || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 802e49ff266SThomas Huth return H_PARAMETER; 803e49ff266SThomas Huth } 804e49ff266SThomas Huth 805e49ff266SThomas Huth cpu_synchronize_state(CPU(cpu)); 806e49ff266SThomas Huth cpu->env.spr[SPR_DABRX] = dabrx; 807e49ff266SThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 808e49ff266SThomas Huth 809e49ff266SThomas Huth return H_SUCCESS; 810e49ff266SThomas Huth } 811e49ff266SThomas Huth 812ce2918cbSDavid Gibson static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, 8133240dd9aSThomas Huth target_ulong opcode, target_ulong *args) 8143240dd9aSThomas Huth { 8153240dd9aSThomas Huth target_ulong flags = args[0]; 8163240dd9aSThomas Huth hwaddr dst = args[1]; 8173240dd9aSThomas Huth hwaddr src = args[2]; 8183240dd9aSThomas Huth hwaddr len = TARGET_PAGE_SIZE; 8193240dd9aSThomas Huth uint8_t *pdst, *psrc; 8203240dd9aSThomas Huth target_long ret = H_SUCCESS; 8213240dd9aSThomas Huth 8223240dd9aSThomas Huth if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 8233240dd9aSThomas Huth | H_COPY_PAGE | H_ZERO_PAGE)) { 8243240dd9aSThomas Huth qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 8253240dd9aSThomas Huth flags); 8263240dd9aSThomas Huth return H_PARAMETER; 8273240dd9aSThomas Huth } 8283240dd9aSThomas Huth 8293240dd9aSThomas Huth /* Map-in destination */ 8303240dd9aSThomas Huth if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 8313240dd9aSThomas Huth return H_PARAMETER; 8323240dd9aSThomas Huth } 8333240dd9aSThomas Huth pdst = cpu_physical_memory_map(dst, &len, 1); 8343240dd9aSThomas Huth if (!pdst || len != TARGET_PAGE_SIZE) { 8353240dd9aSThomas Huth return H_PARAMETER; 8363240dd9aSThomas Huth } 8373240dd9aSThomas Huth 8383240dd9aSThomas Huth if (flags & H_COPY_PAGE) { 8393240dd9aSThomas Huth /* Map-in source, copy to destination, and unmap source again */ 8403240dd9aSThomas Huth if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 8413240dd9aSThomas Huth ret = H_PARAMETER; 8423240dd9aSThomas Huth goto unmap_out; 8433240dd9aSThomas Huth } 8443240dd9aSThomas Huth psrc = cpu_physical_memory_map(src, &len, 0); 8453240dd9aSThomas Huth if (!psrc || len != TARGET_PAGE_SIZE) { 8463240dd9aSThomas Huth ret = H_PARAMETER; 8473240dd9aSThomas Huth goto unmap_out; 8483240dd9aSThomas Huth } 8493240dd9aSThomas Huth memcpy(pdst, psrc, len); 8503240dd9aSThomas Huth cpu_physical_memory_unmap(psrc, len, 0, len); 8513240dd9aSThomas Huth } else if (flags & H_ZERO_PAGE) { 8523240dd9aSThomas Huth memset(pdst, 0, len); /* Just clear the destination page */ 8533240dd9aSThomas Huth } 8543240dd9aSThomas Huth 8553240dd9aSThomas Huth if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 8563240dd9aSThomas Huth kvmppc_dcbst_range(cpu, pdst, len); 8573240dd9aSThomas Huth } 8583240dd9aSThomas Huth if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 8593240dd9aSThomas Huth if (kvm_enabled()) { 8603240dd9aSThomas Huth kvmppc_icbi_range(cpu, pdst, len); 8613240dd9aSThomas Huth } else { 8623240dd9aSThomas Huth tb_flush(CPU(cpu)); 8633240dd9aSThomas Huth } 8643240dd9aSThomas Huth } 8653240dd9aSThomas Huth 8663240dd9aSThomas Huth unmap_out: 8673240dd9aSThomas Huth cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 8683240dd9aSThomas Huth return ret; 8693240dd9aSThomas Huth } 8703240dd9aSThomas Huth 8719f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 8729f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 8739f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 8749f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 8759f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 8769f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 8779f64bd8aSPaolo Bonzini 8787388efafSDavid Gibson static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) 8799f64bd8aSPaolo Bonzini { 8807388efafSDavid Gibson CPUState *cs = CPU(cpu); 8817388efafSDavid Gibson CPUPPCState *env = &cpu->env; 882ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 8839f64bd8aSPaolo Bonzini uint16_t size; 8849f64bd8aSPaolo Bonzini uint8_t tmp; 8859f64bd8aSPaolo Bonzini 8869f64bd8aSPaolo Bonzini if (vpa == 0) { 8879f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 8889f64bd8aSPaolo Bonzini return H_HARDWARE; 8899f64bd8aSPaolo Bonzini } 8909f64bd8aSPaolo Bonzini 8919f64bd8aSPaolo Bonzini if (vpa % env->dcache_line_size) { 8929f64bd8aSPaolo Bonzini return H_PARAMETER; 8939f64bd8aSPaolo Bonzini } 8949f64bd8aSPaolo Bonzini /* FIXME: bounds check the address */ 8959f64bd8aSPaolo Bonzini 89641701aa4SEdgar E. Iglesias size = lduw_be_phys(cs->as, vpa + 0x4); 8979f64bd8aSPaolo Bonzini 8989f64bd8aSPaolo Bonzini if (size < VPA_MIN_SIZE) { 8999f64bd8aSPaolo Bonzini return H_PARAMETER; 9009f64bd8aSPaolo Bonzini } 9019f64bd8aSPaolo Bonzini 9029f64bd8aSPaolo Bonzini /* VPA is not allowed to cross a page boundary */ 9039f64bd8aSPaolo Bonzini if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 9049f64bd8aSPaolo Bonzini return H_PARAMETER; 9059f64bd8aSPaolo Bonzini } 9069f64bd8aSPaolo Bonzini 9077388efafSDavid Gibson spapr_cpu->vpa_addr = vpa; 9089f64bd8aSPaolo Bonzini 9097388efafSDavid Gibson tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET); 9109f64bd8aSPaolo Bonzini tmp |= VPA_SHARED_PROC_VAL; 9117388efafSDavid Gibson stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 9129f64bd8aSPaolo Bonzini 9139f64bd8aSPaolo Bonzini return H_SUCCESS; 9149f64bd8aSPaolo Bonzini } 9159f64bd8aSPaolo Bonzini 9167388efafSDavid Gibson static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) 9179f64bd8aSPaolo Bonzini { 918ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 9197388efafSDavid Gibson 9207388efafSDavid Gibson if (spapr_cpu->slb_shadow_addr) { 9219f64bd8aSPaolo Bonzini return H_RESOURCE; 9229f64bd8aSPaolo Bonzini } 9239f64bd8aSPaolo Bonzini 9247388efafSDavid Gibson if (spapr_cpu->dtl_addr) { 9259f64bd8aSPaolo Bonzini return H_RESOURCE; 9269f64bd8aSPaolo Bonzini } 9279f64bd8aSPaolo Bonzini 9287388efafSDavid Gibson spapr_cpu->vpa_addr = 0; 9299f64bd8aSPaolo Bonzini return H_SUCCESS; 9309f64bd8aSPaolo Bonzini } 9319f64bd8aSPaolo Bonzini 9327388efafSDavid Gibson static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 9339f64bd8aSPaolo Bonzini { 934ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 9359f64bd8aSPaolo Bonzini uint32_t size; 9369f64bd8aSPaolo Bonzini 9379f64bd8aSPaolo Bonzini if (addr == 0) { 9389f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 9399f64bd8aSPaolo Bonzini return H_HARDWARE; 9409f64bd8aSPaolo Bonzini } 9419f64bd8aSPaolo Bonzini 9427388efafSDavid Gibson size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 9439f64bd8aSPaolo Bonzini if (size < 0x8) { 9449f64bd8aSPaolo Bonzini return H_PARAMETER; 9459f64bd8aSPaolo Bonzini } 9469f64bd8aSPaolo Bonzini 9479f64bd8aSPaolo Bonzini if ((addr / 4096) != ((addr + size - 1) / 4096)) { 9489f64bd8aSPaolo Bonzini return H_PARAMETER; 9499f64bd8aSPaolo Bonzini } 9509f64bd8aSPaolo Bonzini 9517388efafSDavid Gibson if (!spapr_cpu->vpa_addr) { 9529f64bd8aSPaolo Bonzini return H_RESOURCE; 9539f64bd8aSPaolo Bonzini } 9549f64bd8aSPaolo Bonzini 9557388efafSDavid Gibson spapr_cpu->slb_shadow_addr = addr; 9567388efafSDavid Gibson spapr_cpu->slb_shadow_size = size; 9579f64bd8aSPaolo Bonzini 9589f64bd8aSPaolo Bonzini return H_SUCCESS; 9599f64bd8aSPaolo Bonzini } 9609f64bd8aSPaolo Bonzini 9617388efafSDavid Gibson static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 9629f64bd8aSPaolo Bonzini { 963ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 9647388efafSDavid Gibson 9657388efafSDavid Gibson spapr_cpu->slb_shadow_addr = 0; 9667388efafSDavid Gibson spapr_cpu->slb_shadow_size = 0; 9679f64bd8aSPaolo Bonzini return H_SUCCESS; 9689f64bd8aSPaolo Bonzini } 9699f64bd8aSPaolo Bonzini 9707388efafSDavid Gibson static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) 9719f64bd8aSPaolo Bonzini { 972ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 9739f64bd8aSPaolo Bonzini uint32_t size; 9749f64bd8aSPaolo Bonzini 9759f64bd8aSPaolo Bonzini if (addr == 0) { 9769f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with DTL at logical 0\n"); 9779f64bd8aSPaolo Bonzini return H_HARDWARE; 9789f64bd8aSPaolo Bonzini } 9799f64bd8aSPaolo Bonzini 9807388efafSDavid Gibson size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 9819f64bd8aSPaolo Bonzini 9829f64bd8aSPaolo Bonzini if (size < 48) { 9839f64bd8aSPaolo Bonzini return H_PARAMETER; 9849f64bd8aSPaolo Bonzini } 9859f64bd8aSPaolo Bonzini 9867388efafSDavid Gibson if (!spapr_cpu->vpa_addr) { 9879f64bd8aSPaolo Bonzini return H_RESOURCE; 9889f64bd8aSPaolo Bonzini } 9899f64bd8aSPaolo Bonzini 9907388efafSDavid Gibson spapr_cpu->dtl_addr = addr; 9917388efafSDavid Gibson spapr_cpu->dtl_size = size; 9929f64bd8aSPaolo Bonzini 9939f64bd8aSPaolo Bonzini return H_SUCCESS; 9949f64bd8aSPaolo Bonzini } 9959f64bd8aSPaolo Bonzini 9967388efafSDavid Gibson static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) 9979f64bd8aSPaolo Bonzini { 998ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 9997388efafSDavid Gibson 10007388efafSDavid Gibson spapr_cpu->dtl_addr = 0; 10017388efafSDavid Gibson spapr_cpu->dtl_size = 0; 10029f64bd8aSPaolo Bonzini 10039f64bd8aSPaolo Bonzini return H_SUCCESS; 10049f64bd8aSPaolo Bonzini } 10059f64bd8aSPaolo Bonzini 1006ce2918cbSDavid Gibson static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr, 10079f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 10089f64bd8aSPaolo Bonzini { 10099f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 10109f64bd8aSPaolo Bonzini target_ulong procno = args[1]; 10119f64bd8aSPaolo Bonzini target_ulong vpa = args[2]; 10129f64bd8aSPaolo Bonzini target_ulong ret = H_PARAMETER; 10130f20ba62SAlexey Kardashevskiy PowerPCCPU *tcpu; 10149f64bd8aSPaolo Bonzini 10152e886fb3SSam Bobroff tcpu = spapr_find_cpu(procno); 10169f64bd8aSPaolo Bonzini if (!tcpu) { 10179f64bd8aSPaolo Bonzini return H_PARAMETER; 10189f64bd8aSPaolo Bonzini } 10199f64bd8aSPaolo Bonzini 10209f64bd8aSPaolo Bonzini switch (flags) { 10219f64bd8aSPaolo Bonzini case FLAGS_REGISTER_VPA: 10227388efafSDavid Gibson ret = register_vpa(tcpu, vpa); 10239f64bd8aSPaolo Bonzini break; 10249f64bd8aSPaolo Bonzini 10259f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_VPA: 10267388efafSDavid Gibson ret = deregister_vpa(tcpu, vpa); 10279f64bd8aSPaolo Bonzini break; 10289f64bd8aSPaolo Bonzini 10299f64bd8aSPaolo Bonzini case FLAGS_REGISTER_SLBSHADOW: 10307388efafSDavid Gibson ret = register_slb_shadow(tcpu, vpa); 10319f64bd8aSPaolo Bonzini break; 10329f64bd8aSPaolo Bonzini 10339f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_SLBSHADOW: 10347388efafSDavid Gibson ret = deregister_slb_shadow(tcpu, vpa); 10359f64bd8aSPaolo Bonzini break; 10369f64bd8aSPaolo Bonzini 10379f64bd8aSPaolo Bonzini case FLAGS_REGISTER_DTL: 10387388efafSDavid Gibson ret = register_dtl(tcpu, vpa); 10399f64bd8aSPaolo Bonzini break; 10409f64bd8aSPaolo Bonzini 10419f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_DTL: 10427388efafSDavid Gibson ret = deregister_dtl(tcpu, vpa); 10439f64bd8aSPaolo Bonzini break; 10449f64bd8aSPaolo Bonzini } 10459f64bd8aSPaolo Bonzini 10469f64bd8aSPaolo Bonzini return ret; 10479f64bd8aSPaolo Bonzini } 10489f64bd8aSPaolo Bonzini 1049ce2918cbSDavid Gibson static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, 10509f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 10519f64bd8aSPaolo Bonzini { 10529f64bd8aSPaolo Bonzini CPUPPCState *env = &cpu->env; 10539f64bd8aSPaolo Bonzini CPUState *cs = CPU(cpu); 10543a6e6224SNicholas Piggin SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 10559f64bd8aSPaolo Bonzini 10569f64bd8aSPaolo Bonzini env->msr |= (1ULL << MSR_EE); 10579f64bd8aSPaolo Bonzini hreg_compute_hflags(env); 10583a6e6224SNicholas Piggin 10593a6e6224SNicholas Piggin if (spapr_cpu->prod) { 10603a6e6224SNicholas Piggin spapr_cpu->prod = false; 10613a6e6224SNicholas Piggin return H_SUCCESS; 10623a6e6224SNicholas Piggin } 10633a6e6224SNicholas Piggin 10649f64bd8aSPaolo Bonzini if (!cpu_has_work(cs)) { 1065259186a7SAndreas Färber cs->halted = 1; 106627103424SAndreas Färber cs->exception_index = EXCP_HLT; 10679f64bd8aSPaolo Bonzini cs->exit_request = 1; 10689f64bd8aSPaolo Bonzini } 10693a6e6224SNicholas Piggin 10703a6e6224SNicholas Piggin return H_SUCCESS; 10713a6e6224SNicholas Piggin } 10723a6e6224SNicholas Piggin 1073*e8ce0e40SNicholas Piggin static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr, 1074*e8ce0e40SNicholas Piggin target_ulong opcode, target_ulong *args) 1075*e8ce0e40SNicholas Piggin { 1076*e8ce0e40SNicholas Piggin target_long target = args[0]; 1077*e8ce0e40SNicholas Piggin uint32_t dispatch = args[1]; 1078*e8ce0e40SNicholas Piggin CPUState *cs = CPU(cpu); 1079*e8ce0e40SNicholas Piggin SpaprCpuState *spapr_cpu; 1080*e8ce0e40SNicholas Piggin 1081*e8ce0e40SNicholas Piggin /* 1082*e8ce0e40SNicholas Piggin * -1 means confer to all other CPUs without dispatch counter check, 1083*e8ce0e40SNicholas Piggin * otherwise it's a targeted confer. 1084*e8ce0e40SNicholas Piggin */ 1085*e8ce0e40SNicholas Piggin if (target != -1) { 1086*e8ce0e40SNicholas Piggin PowerPCCPU *target_cpu = spapr_find_cpu(target); 1087*e8ce0e40SNicholas Piggin uint32_t target_dispatch; 1088*e8ce0e40SNicholas Piggin 1089*e8ce0e40SNicholas Piggin if (!target_cpu) { 1090*e8ce0e40SNicholas Piggin return H_PARAMETER; 1091*e8ce0e40SNicholas Piggin } 1092*e8ce0e40SNicholas Piggin 1093*e8ce0e40SNicholas Piggin spapr_cpu = spapr_cpu_state(target_cpu); 1094*e8ce0e40SNicholas Piggin 1095*e8ce0e40SNicholas Piggin /* 1096*e8ce0e40SNicholas Piggin * target == self is a special case, we wait until prodded, without 1097*e8ce0e40SNicholas Piggin * dispatch counter check. 1098*e8ce0e40SNicholas Piggin */ 1099*e8ce0e40SNicholas Piggin if (cpu == target_cpu) { 1100*e8ce0e40SNicholas Piggin if (spapr_cpu->prod) { 1101*e8ce0e40SNicholas Piggin spapr_cpu->prod = false; 1102*e8ce0e40SNicholas Piggin 1103*e8ce0e40SNicholas Piggin return H_SUCCESS; 1104*e8ce0e40SNicholas Piggin } 1105*e8ce0e40SNicholas Piggin 1106*e8ce0e40SNicholas Piggin cs->halted = 1; 1107*e8ce0e40SNicholas Piggin cs->exception_index = EXCP_HALTED; 1108*e8ce0e40SNicholas Piggin cs->exit_request = 1; 1109*e8ce0e40SNicholas Piggin 1110*e8ce0e40SNicholas Piggin return H_SUCCESS; 1111*e8ce0e40SNicholas Piggin } 1112*e8ce0e40SNicholas Piggin 1113*e8ce0e40SNicholas Piggin if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) { 1114*e8ce0e40SNicholas Piggin return H_SUCCESS; 1115*e8ce0e40SNicholas Piggin } 1116*e8ce0e40SNicholas Piggin 1117*e8ce0e40SNicholas Piggin target_dispatch = ldl_be_phys(cs->as, 1118*e8ce0e40SNicholas Piggin spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 1119*e8ce0e40SNicholas Piggin if (target_dispatch != dispatch) { 1120*e8ce0e40SNicholas Piggin return H_SUCCESS; 1121*e8ce0e40SNicholas Piggin } 1122*e8ce0e40SNicholas Piggin 1123*e8ce0e40SNicholas Piggin /* 1124*e8ce0e40SNicholas Piggin * The targeted confer does not do anything special beyond yielding 1125*e8ce0e40SNicholas Piggin * the current vCPU, but even this should be better than nothing. 1126*e8ce0e40SNicholas Piggin * At least for single-threaded tcg, it gives the target a chance to 1127*e8ce0e40SNicholas Piggin * run before we run again. Multi-threaded tcg does not really do 1128*e8ce0e40SNicholas Piggin * anything with EXCP_YIELD yet. 1129*e8ce0e40SNicholas Piggin */ 1130*e8ce0e40SNicholas Piggin } 1131*e8ce0e40SNicholas Piggin 1132*e8ce0e40SNicholas Piggin cs->exception_index = EXCP_YIELD; 1133*e8ce0e40SNicholas Piggin cs->exit_request = 1; 1134*e8ce0e40SNicholas Piggin cpu_loop_exit(cs); 1135*e8ce0e40SNicholas Piggin 1136*e8ce0e40SNicholas Piggin return H_SUCCESS; 1137*e8ce0e40SNicholas Piggin } 1138*e8ce0e40SNicholas Piggin 11393a6e6224SNicholas Piggin static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr, 11403a6e6224SNicholas Piggin target_ulong opcode, target_ulong *args) 11413a6e6224SNicholas Piggin { 11423a6e6224SNicholas Piggin target_long target = args[0]; 11433a6e6224SNicholas Piggin PowerPCCPU *tcpu; 11443a6e6224SNicholas Piggin CPUState *cs; 11453a6e6224SNicholas Piggin SpaprCpuState *spapr_cpu; 11463a6e6224SNicholas Piggin 11473a6e6224SNicholas Piggin tcpu = spapr_find_cpu(target); 11483a6e6224SNicholas Piggin cs = CPU(tcpu); 11493a6e6224SNicholas Piggin if (!cs) { 11503a6e6224SNicholas Piggin return H_PARAMETER; 11513a6e6224SNicholas Piggin } 11523a6e6224SNicholas Piggin 11533a6e6224SNicholas Piggin spapr_cpu = spapr_cpu_state(tcpu); 11543a6e6224SNicholas Piggin spapr_cpu->prod = true; 11553a6e6224SNicholas Piggin cs->halted = 0; 11563a6e6224SNicholas Piggin qemu_cpu_kick(cs); 11573a6e6224SNicholas Piggin 11589f64bd8aSPaolo Bonzini return H_SUCCESS; 11599f64bd8aSPaolo Bonzini } 11609f64bd8aSPaolo Bonzini 1161ce2918cbSDavid Gibson static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, 11629f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 11639f64bd8aSPaolo Bonzini { 11649f64bd8aSPaolo Bonzini target_ulong rtas_r3 = args[0]; 11654fe822e0SAlexey Kardashevskiy uint32_t token = rtas_ld(rtas_r3, 0); 11664fe822e0SAlexey Kardashevskiy uint32_t nargs = rtas_ld(rtas_r3, 1); 11674fe822e0SAlexey Kardashevskiy uint32_t nret = rtas_ld(rtas_r3, 2); 11689f64bd8aSPaolo Bonzini 1169210b580bSAnthony Liguori return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 11709f64bd8aSPaolo Bonzini nret, rtas_r3 + 12 + 4*nargs); 11719f64bd8aSPaolo Bonzini } 11729f64bd8aSPaolo Bonzini 1173ce2918cbSDavid Gibson static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr, 11749f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 11759f64bd8aSPaolo Bonzini { 1176fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 11779f64bd8aSPaolo Bonzini target_ulong size = args[0]; 11789f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 11799f64bd8aSPaolo Bonzini 11809f64bd8aSPaolo Bonzini switch (size) { 11819f64bd8aSPaolo Bonzini case 1: 11822c17449bSEdgar E. Iglesias args[0] = ldub_phys(cs->as, addr); 11839f64bd8aSPaolo Bonzini return H_SUCCESS; 11849f64bd8aSPaolo Bonzini case 2: 118541701aa4SEdgar E. Iglesias args[0] = lduw_phys(cs->as, addr); 11869f64bd8aSPaolo Bonzini return H_SUCCESS; 11879f64bd8aSPaolo Bonzini case 4: 1188fdfba1a2SEdgar E. Iglesias args[0] = ldl_phys(cs->as, addr); 11899f64bd8aSPaolo Bonzini return H_SUCCESS; 11909f64bd8aSPaolo Bonzini case 8: 11912c17449bSEdgar E. Iglesias args[0] = ldq_phys(cs->as, addr); 11929f64bd8aSPaolo Bonzini return H_SUCCESS; 11939f64bd8aSPaolo Bonzini } 11949f64bd8aSPaolo Bonzini return H_PARAMETER; 11959f64bd8aSPaolo Bonzini } 11969f64bd8aSPaolo Bonzini 1197ce2918cbSDavid Gibson static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr, 11989f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 11999f64bd8aSPaolo Bonzini { 1200f606604fSEdgar E. Iglesias CPUState *cs = CPU(cpu); 1201f606604fSEdgar E. Iglesias 12029f64bd8aSPaolo Bonzini target_ulong size = args[0]; 12039f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 12049f64bd8aSPaolo Bonzini target_ulong val = args[2]; 12059f64bd8aSPaolo Bonzini 12069f64bd8aSPaolo Bonzini switch (size) { 12079f64bd8aSPaolo Bonzini case 1: 1208db3be60dSEdgar E. Iglesias stb_phys(cs->as, addr, val); 12099f64bd8aSPaolo Bonzini return H_SUCCESS; 12109f64bd8aSPaolo Bonzini case 2: 12115ce5944dSEdgar E. Iglesias stw_phys(cs->as, addr, val); 12129f64bd8aSPaolo Bonzini return H_SUCCESS; 12139f64bd8aSPaolo Bonzini case 4: 1214ab1da857SEdgar E. Iglesias stl_phys(cs->as, addr, val); 12159f64bd8aSPaolo Bonzini return H_SUCCESS; 12169f64bd8aSPaolo Bonzini case 8: 1217f606604fSEdgar E. Iglesias stq_phys(cs->as, addr, val); 12189f64bd8aSPaolo Bonzini return H_SUCCESS; 12199f64bd8aSPaolo Bonzini } 12209f64bd8aSPaolo Bonzini return H_PARAMETER; 12219f64bd8aSPaolo Bonzini } 12229f64bd8aSPaolo Bonzini 1223ce2918cbSDavid Gibson static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr, 12249f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 12259f64bd8aSPaolo Bonzini { 1226fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 1227fdfba1a2SEdgar E. Iglesias 12289f64bd8aSPaolo Bonzini target_ulong dst = args[0]; /* Destination address */ 12299f64bd8aSPaolo Bonzini target_ulong src = args[1]; /* Source address */ 12309f64bd8aSPaolo Bonzini target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 12319f64bd8aSPaolo Bonzini target_ulong count = args[3]; /* Element count */ 12329f64bd8aSPaolo Bonzini target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 12339f64bd8aSPaolo Bonzini uint64_t tmp; 12349f64bd8aSPaolo Bonzini unsigned int mask = (1 << esize) - 1; 12359f64bd8aSPaolo Bonzini int step = 1 << esize; 12369f64bd8aSPaolo Bonzini 12379f64bd8aSPaolo Bonzini if (count > 0x80000000) { 12389f64bd8aSPaolo Bonzini return H_PARAMETER; 12399f64bd8aSPaolo Bonzini } 12409f64bd8aSPaolo Bonzini 12419f64bd8aSPaolo Bonzini if ((dst & mask) || (src & mask) || (op > 1)) { 12429f64bd8aSPaolo Bonzini return H_PARAMETER; 12439f64bd8aSPaolo Bonzini } 12449f64bd8aSPaolo Bonzini 12459f64bd8aSPaolo Bonzini if (dst >= src && dst < (src + (count << esize))) { 12469f64bd8aSPaolo Bonzini dst = dst + ((count - 1) << esize); 12479f64bd8aSPaolo Bonzini src = src + ((count - 1) << esize); 12489f64bd8aSPaolo Bonzini step = -step; 12499f64bd8aSPaolo Bonzini } 12509f64bd8aSPaolo Bonzini 12519f64bd8aSPaolo Bonzini while (count--) { 12529f64bd8aSPaolo Bonzini switch (esize) { 12539f64bd8aSPaolo Bonzini case 0: 12542c17449bSEdgar E. Iglesias tmp = ldub_phys(cs->as, src); 12559f64bd8aSPaolo Bonzini break; 12569f64bd8aSPaolo Bonzini case 1: 125741701aa4SEdgar E. Iglesias tmp = lduw_phys(cs->as, src); 12589f64bd8aSPaolo Bonzini break; 12599f64bd8aSPaolo Bonzini case 2: 1260fdfba1a2SEdgar E. Iglesias tmp = ldl_phys(cs->as, src); 12619f64bd8aSPaolo Bonzini break; 12629f64bd8aSPaolo Bonzini case 3: 12632c17449bSEdgar E. Iglesias tmp = ldq_phys(cs->as, src); 12649f64bd8aSPaolo Bonzini break; 12659f64bd8aSPaolo Bonzini default: 12669f64bd8aSPaolo Bonzini return H_PARAMETER; 12679f64bd8aSPaolo Bonzini } 12689f64bd8aSPaolo Bonzini if (op == 1) { 12699f64bd8aSPaolo Bonzini tmp = ~tmp; 12709f64bd8aSPaolo Bonzini } 12719f64bd8aSPaolo Bonzini switch (esize) { 12729f64bd8aSPaolo Bonzini case 0: 1273db3be60dSEdgar E. Iglesias stb_phys(cs->as, dst, tmp); 12749f64bd8aSPaolo Bonzini break; 12759f64bd8aSPaolo Bonzini case 1: 12765ce5944dSEdgar E. Iglesias stw_phys(cs->as, dst, tmp); 12779f64bd8aSPaolo Bonzini break; 12789f64bd8aSPaolo Bonzini case 2: 1279ab1da857SEdgar E. Iglesias stl_phys(cs->as, dst, tmp); 12809f64bd8aSPaolo Bonzini break; 12819f64bd8aSPaolo Bonzini case 3: 1282f606604fSEdgar E. Iglesias stq_phys(cs->as, dst, tmp); 12839f64bd8aSPaolo Bonzini break; 12849f64bd8aSPaolo Bonzini } 12859f64bd8aSPaolo Bonzini dst = dst + step; 12869f64bd8aSPaolo Bonzini src = src + step; 12879f64bd8aSPaolo Bonzini } 12889f64bd8aSPaolo Bonzini 12899f64bd8aSPaolo Bonzini return H_SUCCESS; 12909f64bd8aSPaolo Bonzini } 12919f64bd8aSPaolo Bonzini 1292ce2918cbSDavid Gibson static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr, 12939f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 12949f64bd8aSPaolo Bonzini { 12959f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 12969f64bd8aSPaolo Bonzini return H_SUCCESS; 12979f64bd8aSPaolo Bonzini } 12989f64bd8aSPaolo Bonzini 1299ce2918cbSDavid Gibson static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, 13009f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 13019f64bd8aSPaolo Bonzini { 13029f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 13039f64bd8aSPaolo Bonzini return H_SUCCESS; 13049f64bd8aSPaolo Bonzini } 13059f64bd8aSPaolo Bonzini 13067d0cd464SPeter Maydell static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 1307c4015bbdSAlexey Kardashevskiy target_ulong mflags, 1308c4015bbdSAlexey Kardashevskiy target_ulong value1, 1309c4015bbdSAlexey Kardashevskiy target_ulong value2) 131042561bf2SAnton Blanchard { 131142561bf2SAnton Blanchard if (value1) { 1312c4015bbdSAlexey Kardashevskiy return H_P3; 131342561bf2SAnton Blanchard } 131442561bf2SAnton Blanchard if (value2) { 1315c4015bbdSAlexey Kardashevskiy return H_P4; 131642561bf2SAnton Blanchard } 1317c4015bbdSAlexey Kardashevskiy 131842561bf2SAnton Blanchard switch (mflags) { 131942561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_BIG: 132000fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(0, LPCR_ILE); 1321eefaccc0SDavid Gibson spapr_pci_switch_vga(true); 1322c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 132342561bf2SAnton Blanchard 132442561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_LITTLE: 132500fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); 1326eefaccc0SDavid Gibson spapr_pci_switch_vga(false); 1327c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 1328c4015bbdSAlexey Kardashevskiy } 1329c4015bbdSAlexey Kardashevskiy 1330c4015bbdSAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 1331c4015bbdSAlexey Kardashevskiy } 1332c4015bbdSAlexey Kardashevskiy 13337d0cd464SPeter Maydell static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 1334d5ac4f54SAlexey Kardashevskiy target_ulong mflags, 1335d5ac4f54SAlexey Kardashevskiy target_ulong value1, 1336d5ac4f54SAlexey Kardashevskiy target_ulong value2) 1337d5ac4f54SAlexey Kardashevskiy { 1338d5ac4f54SAlexey Kardashevskiy PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 1339d5ac4f54SAlexey Kardashevskiy 1340d5ac4f54SAlexey Kardashevskiy if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 1341d5ac4f54SAlexey Kardashevskiy return H_P2; 1342d5ac4f54SAlexey Kardashevskiy } 1343d5ac4f54SAlexey Kardashevskiy if (value1) { 1344d5ac4f54SAlexey Kardashevskiy return H_P3; 1345d5ac4f54SAlexey Kardashevskiy } 1346d5ac4f54SAlexey Kardashevskiy if (value2) { 1347d5ac4f54SAlexey Kardashevskiy return H_P4; 1348d5ac4f54SAlexey Kardashevskiy } 1349d5ac4f54SAlexey Kardashevskiy 13505c94b2a5SCédric Le Goater if (mflags == AIL_RESERVED) { 1351d5ac4f54SAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 1352d5ac4f54SAlexey Kardashevskiy } 1353d5ac4f54SAlexey Kardashevskiy 135400fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); 1355d5ac4f54SAlexey Kardashevskiy 1356d5ac4f54SAlexey Kardashevskiy return H_SUCCESS; 1357d5ac4f54SAlexey Kardashevskiy } 1358d5ac4f54SAlexey Kardashevskiy 1359ce2918cbSDavid Gibson static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, 1360c4015bbdSAlexey Kardashevskiy target_ulong opcode, target_ulong *args) 1361c4015bbdSAlexey Kardashevskiy { 1362c4015bbdSAlexey Kardashevskiy target_ulong resource = args[1]; 1363c4015bbdSAlexey Kardashevskiy target_ulong ret = H_P2; 1364c4015bbdSAlexey Kardashevskiy 1365c4015bbdSAlexey Kardashevskiy switch (resource) { 1366c4015bbdSAlexey Kardashevskiy case H_SET_MODE_RESOURCE_LE: 13677d0cd464SPeter Maydell ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); 136842561bf2SAnton Blanchard break; 1369d5ac4f54SAlexey Kardashevskiy case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 13707d0cd464SPeter Maydell ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 1371d5ac4f54SAlexey Kardashevskiy args[2], args[3]); 1372d5ac4f54SAlexey Kardashevskiy break; 137342561bf2SAnton Blanchard } 137442561bf2SAnton Blanchard 137542561bf2SAnton Blanchard return ret; 137642561bf2SAnton Blanchard } 137742561bf2SAnton Blanchard 1378ce2918cbSDavid Gibson static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, 1379d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 1380d77a98b0SSuraj Jitindar Singh { 1381d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1382d77a98b0SSuraj Jitindar Singh opcode, " (H_CLEAN_SLB)"); 1383d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 1384d77a98b0SSuraj Jitindar Singh } 1385d77a98b0SSuraj Jitindar Singh 1386ce2918cbSDavid Gibson static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr, 1387d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 1388d77a98b0SSuraj Jitindar Singh { 1389d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1390d77a98b0SSuraj Jitindar Singh opcode, " (H_INVALIDATE_PID)"); 1391d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 1392d77a98b0SSuraj Jitindar Singh } 1393d77a98b0SSuraj Jitindar Singh 1394ce2918cbSDavid Gibson static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, 1395b4db5413SSuraj Jitindar Singh uint64_t patbe_old, uint64_t patbe_new) 1396b4db5413SSuraj Jitindar Singh { 1397b4db5413SSuraj Jitindar Singh /* 1398b4db5413SSuraj Jitindar Singh * We have 4 Options: 1399b4db5413SSuraj Jitindar Singh * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 1400b4db5413SSuraj Jitindar Singh * HASH->RADIX : Free HPT 1401b4db5413SSuraj Jitindar Singh * RADIX->HASH : Allocate HPT 1402b4db5413SSuraj Jitindar Singh * NOTHING->HASH : Allocate HPT 1403b4db5413SSuraj Jitindar Singh * Note: NOTHING implies the case where we said the guest could choose 1404b4db5413SSuraj Jitindar Singh * later and so assumed radix and now it's called H_REG_PROC_TBL 1405b4db5413SSuraj Jitindar Singh */ 1406b4db5413SSuraj Jitindar Singh 140779825f4dSBenjamin Herrenschmidt if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) { 1408b4db5413SSuraj Jitindar Singh /* We assume RADIX, so this catches all the "Do Nothing" cases */ 140979825f4dSBenjamin Herrenschmidt } else if (!(patbe_old & PATE1_GR)) { 1410b4db5413SSuraj Jitindar Singh /* HASH->RADIX : Free HPT */ 141106ec79e8SBharata B Rao spapr_free_hpt(spapr); 141279825f4dSBenjamin Herrenschmidt } else if (!(patbe_new & PATE1_GR)) { 1413b4db5413SSuraj Jitindar Singh /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 1414b4db5413SSuraj Jitindar Singh spapr_setup_hpt_and_vrma(spapr); 1415b4db5413SSuraj Jitindar Singh } 1416b4db5413SSuraj Jitindar Singh return; 1417b4db5413SSuraj Jitindar Singh } 1418b4db5413SSuraj Jitindar Singh 1419b4db5413SSuraj Jitindar Singh #define FLAGS_MASK 0x01FULL 1420b4db5413SSuraj Jitindar Singh #define FLAG_MODIFY 0x10 1421b4db5413SSuraj Jitindar Singh #define FLAG_REGISTER 0x08 1422b4db5413SSuraj Jitindar Singh #define FLAG_RADIX 0x04 1423b4db5413SSuraj Jitindar Singh #define FLAG_HASH_PROC_TBL 0x02 1424b4db5413SSuraj Jitindar Singh #define FLAG_GTSE 0x01 1425b4db5413SSuraj Jitindar Singh 1426d77a98b0SSuraj Jitindar Singh static target_ulong h_register_process_table(PowerPCCPU *cpu, 1427ce2918cbSDavid Gibson SpaprMachineState *spapr, 1428d77a98b0SSuraj Jitindar Singh target_ulong opcode, 1429d77a98b0SSuraj Jitindar Singh target_ulong *args) 1430d77a98b0SSuraj Jitindar Singh { 1431b4db5413SSuraj Jitindar Singh target_ulong flags = args[0]; 1432b4db5413SSuraj Jitindar Singh target_ulong proc_tbl = args[1]; 1433b4db5413SSuraj Jitindar Singh target_ulong page_size = args[2]; 1434b4db5413SSuraj Jitindar Singh target_ulong table_size = args[3]; 1435176dcceeSSuraj Jitindar Singh target_ulong update_lpcr = 0; 1436b4db5413SSuraj Jitindar Singh uint64_t cproc; 1437b4db5413SSuraj Jitindar Singh 1438b4db5413SSuraj Jitindar Singh if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 1439b4db5413SSuraj Jitindar Singh return H_PARAMETER; 1440b4db5413SSuraj Jitindar Singh } 1441b4db5413SSuraj Jitindar Singh if (flags & FLAG_MODIFY) { 1442b4db5413SSuraj Jitindar Singh if (flags & FLAG_REGISTER) { 1443b4db5413SSuraj Jitindar Singh if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 1444b4db5413SSuraj Jitindar Singh if (proc_tbl & 0xfff || proc_tbl >> 60) { 1445b4db5413SSuraj Jitindar Singh return H_P2; 1446b4db5413SSuraj Jitindar Singh } else if (page_size) { 1447b4db5413SSuraj Jitindar Singh return H_P3; 1448b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 1449b4db5413SSuraj Jitindar Singh return H_P4; 1450b4db5413SSuraj Jitindar Singh } 145179825f4dSBenjamin Herrenschmidt cproc = PATE1_GR | proc_tbl | table_size; 1452b4db5413SSuraj Jitindar Singh } else { /* Register new HPT process table */ 1453b4db5413SSuraj Jitindar Singh if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 1454b4db5413SSuraj Jitindar Singh /* TODO - Not Supported */ 1455b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 1456b4db5413SSuraj Jitindar Singh return H_PARAMETER; 1457b4db5413SSuraj Jitindar Singh } else { /* Hash with SLB */ 1458b4db5413SSuraj Jitindar Singh if (proc_tbl >> 38) { 1459b4db5413SSuraj Jitindar Singh return H_P2; 1460b4db5413SSuraj Jitindar Singh } else if (page_size & ~0x7) { 1461b4db5413SSuraj Jitindar Singh return H_P3; 1462b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 1463b4db5413SSuraj Jitindar Singh return H_P4; 1464b4db5413SSuraj Jitindar Singh } 1465b4db5413SSuraj Jitindar Singh } 1466b4db5413SSuraj Jitindar Singh cproc = (proc_tbl << 25) | page_size << 5 | table_size; 1467b4db5413SSuraj Jitindar Singh } 1468b4db5413SSuraj Jitindar Singh 1469b4db5413SSuraj Jitindar Singh } else { /* Deregister current process table */ 147079825f4dSBenjamin Herrenschmidt /* 147179825f4dSBenjamin Herrenschmidt * Set to benign value: (current GR) | 0. This allows 147279825f4dSBenjamin Herrenschmidt * deregistration in KVM to succeed even if the radix bit 147379825f4dSBenjamin Herrenschmidt * in flags doesn't match the radix bit in the old PATE. 147479825f4dSBenjamin Herrenschmidt */ 147579825f4dSBenjamin Herrenschmidt cproc = spapr->patb_entry & PATE1_GR; 1476b4db5413SSuraj Jitindar Singh } 1477b4db5413SSuraj Jitindar Singh } else { /* Maintain current registration */ 147879825f4dSBenjamin Herrenschmidt if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) { 1479b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 1480b4db5413SSuraj Jitindar Singh return H_PARAMETER; /* Existing Process Table Mismatch */ 1481b4db5413SSuraj Jitindar Singh } 1482b4db5413SSuraj Jitindar Singh cproc = spapr->patb_entry; 1483b4db5413SSuraj Jitindar Singh } 1484b4db5413SSuraj Jitindar Singh 1485b4db5413SSuraj Jitindar Singh /* Check if we need to setup OR free the hpt */ 1486b4db5413SSuraj Jitindar Singh spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 1487b4db5413SSuraj Jitindar Singh 1488b4db5413SSuraj Jitindar Singh spapr->patb_entry = cproc; /* Save new process table */ 14896de83307SSuraj Jitindar Singh 149000fd075eSBenjamin Herrenschmidt /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ 1491176dcceeSSuraj Jitindar Singh if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */ 1492176dcceeSSuraj Jitindar Singh update_lpcr |= (LPCR_UPRT | LPCR_HR); 1493176dcceeSSuraj Jitindar Singh else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ 1494176dcceeSSuraj Jitindar Singh update_lpcr |= LPCR_UPRT; 1495176dcceeSSuraj Jitindar Singh if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ 149649e9fdd7SDavid Gibson update_lpcr |= LPCR_GTSE; 149749e9fdd7SDavid Gibson 1498176dcceeSSuraj Jitindar Singh spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); 1499b4db5413SSuraj Jitindar Singh 1500b4db5413SSuraj Jitindar Singh if (kvm_enabled()) { 1501b4db5413SSuraj Jitindar Singh return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1502b4db5413SSuraj Jitindar Singh flags & FLAG_GTSE, cproc); 1503b4db5413SSuraj Jitindar Singh } 1504b4db5413SSuraj Jitindar Singh return H_SUCCESS; 1505d77a98b0SSuraj Jitindar Singh } 1506d77a98b0SSuraj Jitindar Singh 15071c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALL -1 15081c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 15091c7ad77eSNicholas Piggin 15101c7ad77eSNicholas Piggin static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1511ce2918cbSDavid Gibson SpaprMachineState *spapr, 15121c7ad77eSNicholas Piggin target_ulong opcode, target_ulong *args) 15131c7ad77eSNicholas Piggin { 15141c7ad77eSNicholas Piggin target_long target = args[0]; 15151c7ad77eSNicholas Piggin CPUState *cs; 15161c7ad77eSNicholas Piggin 15171c7ad77eSNicholas Piggin if (target < 0) { 15181c7ad77eSNicholas Piggin /* Broadcast */ 15191c7ad77eSNicholas Piggin if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 15201c7ad77eSNicholas Piggin return H_PARAMETER; 15211c7ad77eSNicholas Piggin } 15221c7ad77eSNicholas Piggin 15231c7ad77eSNicholas Piggin CPU_FOREACH(cs) { 15241c7ad77eSNicholas Piggin PowerPCCPU *c = POWERPC_CPU(cs); 15251c7ad77eSNicholas Piggin 15261c7ad77eSNicholas Piggin if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 15271c7ad77eSNicholas Piggin if (c == cpu) { 15281c7ad77eSNicholas Piggin continue; 15291c7ad77eSNicholas Piggin } 15301c7ad77eSNicholas Piggin } 15311c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 15321c7ad77eSNicholas Piggin } 15331c7ad77eSNicholas Piggin return H_SUCCESS; 15341c7ad77eSNicholas Piggin 15351c7ad77eSNicholas Piggin } else { 15361c7ad77eSNicholas Piggin /* Unicast */ 15372e886fb3SSam Bobroff cs = CPU(spapr_find_cpu(target)); 1538f57467e3SSam Bobroff if (cs) { 15391c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 15401c7ad77eSNicholas Piggin return H_SUCCESS; 15411c7ad77eSNicholas Piggin } 15421c7ad77eSNicholas Piggin return H_PARAMETER; 15431c7ad77eSNicholas Piggin } 15441c7ad77eSNicholas Piggin } 15451c7ad77eSNicholas Piggin 1546ce2918cbSDavid Gibson static uint32_t cas_check_pvr(SpaprMachineState *spapr, PowerPCCPU *cpu, 1547cc7b35b1SGreg Kurz target_ulong *addr, bool *raw_mode_supported, 1548cc7b35b1SGreg Kurz Error **errp) 15492a6593cbSAlexey Kardashevskiy { 1550152ef803SDavid Gibson bool explicit_match = false; /* Matched the CPU's real PVR */ 15517843c0d6SDavid Gibson uint32_t max_compat = spapr->max_compat_pvr; 1552152ef803SDavid Gibson uint32_t best_compat = 0; 1553152ef803SDavid Gibson int i; 15543794d548SAlexey Kardashevskiy 1555152ef803SDavid Gibson /* 1556152ef803SDavid Gibson * We scan the supplied table of PVRs looking for two things 1557152ef803SDavid Gibson * 1. Is our real CPU PVR in the list? 1558152ef803SDavid Gibson * 2. What's the "best" listed logical PVR 1559152ef803SDavid Gibson */ 1560152ef803SDavid Gibson for (i = 0; i < 512; ++i) { 15613794d548SAlexey Kardashevskiy uint32_t pvr, pvr_mask; 15623794d548SAlexey Kardashevskiy 156380c33d34SDavid Gibson pvr_mask = ldl_be_phys(&address_space_memory, *addr); 156480c33d34SDavid Gibson pvr = ldl_be_phys(&address_space_memory, *addr + 4); 156580c33d34SDavid Gibson *addr += 8; 15663794d548SAlexey Kardashevskiy 15673794d548SAlexey Kardashevskiy if (~pvr_mask & pvr) { 1568152ef803SDavid Gibson break; /* Terminator record */ 15693794d548SAlexey Kardashevskiy } 1570152ef803SDavid Gibson 1571152ef803SDavid Gibson if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1572152ef803SDavid Gibson explicit_match = true; 1573152ef803SDavid Gibson } else { 1574152ef803SDavid Gibson if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1575152ef803SDavid Gibson best_compat = pvr; 1576152ef803SDavid Gibson } 1577152ef803SDavid Gibson } 1578152ef803SDavid Gibson } 1579152ef803SDavid Gibson 1580152ef803SDavid Gibson if ((best_compat == 0) && (!explicit_match || max_compat)) { 1581152ef803SDavid Gibson /* We couldn't find a suitable compatibility mode, and either 1582152ef803SDavid Gibson * the guest doesn't support "raw" mode for this CPU, or raw 1583152ef803SDavid Gibson * mode is disabled because a maximum compat mode is set */ 158480c33d34SDavid Gibson error_setg(errp, "Couldn't negotiate a suitable PVR during CAS"); 158580c33d34SDavid Gibson return 0; 15863794d548SAlexey Kardashevskiy } 15873794d548SAlexey Kardashevskiy 1588cc7b35b1SGreg Kurz *raw_mode_supported = explicit_match; 1589cc7b35b1SGreg Kurz 15903794d548SAlexey Kardashevskiy /* Parsing finished */ 1591152ef803SDavid Gibson trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 15923794d548SAlexey Kardashevskiy 159380c33d34SDavid Gibson return best_compat; 159480c33d34SDavid Gibson } 159580c33d34SDavid Gibson 159680c33d34SDavid Gibson static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1597ce2918cbSDavid Gibson SpaprMachineState *spapr, 159880c33d34SDavid Gibson target_ulong opcode, 159980c33d34SDavid Gibson target_ulong *args) 160080c33d34SDavid Gibson { 160180c33d34SDavid Gibson /* Working address in data buffer */ 160280c33d34SDavid Gibson target_ulong addr = ppc64_phys_to_real(args[0]); 160380c33d34SDavid Gibson target_ulong ov_table; 160480c33d34SDavid Gibson uint32_t cas_pvr; 1605ce2918cbSDavid Gibson SpaprOptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates; 160680c33d34SDavid Gibson bool guest_radix; 1607f6f242c7SDavid Gibson Error *local_err = NULL; 1608cc7b35b1SGreg Kurz bool raw_mode_supported = false; 1609e7f78db9SGreg Kurz bool guest_xive; 16103794d548SAlexey Kardashevskiy 1611cc7b35b1SGreg Kurz cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err); 161280c33d34SDavid Gibson if (local_err) { 161380c33d34SDavid Gibson error_report_err(local_err); 161480c33d34SDavid Gibson return H_HARDWARE; 161580c33d34SDavid Gibson } 161680c33d34SDavid Gibson 161780c33d34SDavid Gibson /* Update CPUs */ 161880c33d34SDavid Gibson if (cpu->compat_pvr != cas_pvr) { 161980c33d34SDavid Gibson ppc_set_compat_all(cas_pvr, &local_err); 1620f6f242c7SDavid Gibson if (local_err) { 1621cc7b35b1SGreg Kurz /* We fail to set compat mode (likely because running with KVM PR), 1622cc7b35b1SGreg Kurz * but maybe we can fallback to raw mode if the guest supports it. 1623cc7b35b1SGreg Kurz */ 1624cc7b35b1SGreg Kurz if (!raw_mode_supported) { 1625f6f242c7SDavid Gibson error_report_err(local_err); 16263794d548SAlexey Kardashevskiy return H_HARDWARE; 16273794d548SAlexey Kardashevskiy } 16282c9dfdacSGreg Kurz error_free(local_err); 1629cc7b35b1SGreg Kurz local_err = NULL; 1630cc7b35b1SGreg Kurz } 16313794d548SAlexey Kardashevskiy } 16323794d548SAlexey Kardashevskiy 163303d196b7SBharata B Rao /* For the future use: here @ov_table points to the first option vector */ 163480c33d34SDavid Gibson ov_table = addr; 163503d196b7SBharata B Rao 1636e957f6a9SSam Bobroff ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1637facdb8b6SMichael Roth ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 16389fb4541fSSam Bobroff if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 16399fb4541fSSam Bobroff error_report("guest requested hash and radix MMU, which is invalid."); 16409fb4541fSSam Bobroff exit(EXIT_FAILURE); 16419fb4541fSSam Bobroff } 1642e7f78db9SGreg Kurz if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { 1643e7f78db9SGreg Kurz error_report("guest requested an invalid interrupt mode"); 1644e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1645e7f78db9SGreg Kurz } 1646e7f78db9SGreg Kurz 16479fb4541fSSam Bobroff /* The radix/hash bit in byte 24 requires special handling: */ 16489fb4541fSSam Bobroff guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 16499fb4541fSSam Bobroff spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300); 16502a6593cbSAlexey Kardashevskiy 1651e7f78db9SGreg Kurz guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); 1652e7f78db9SGreg Kurz 16532772cf6bSDavid Gibson /* 16542772cf6bSDavid Gibson * HPT resizing is a bit of a special case, because when enabled 16552772cf6bSDavid Gibson * we assume an HPT guest will support it until it says it 16562772cf6bSDavid Gibson * doesn't, instead of assuming it won't support it until it says 16572772cf6bSDavid Gibson * it does. Strictly speaking that approach could break for 16582772cf6bSDavid Gibson * guests which don't make a CAS call, but those are so old we 16592772cf6bSDavid Gibson * don't care about them. Without that assumption we'd have to 16602772cf6bSDavid Gibson * make at least a temporary allocation of an HPT sized for max 16612772cf6bSDavid Gibson * memory, which could be impossibly difficult under KVM HV if 16622772cf6bSDavid Gibson * maxram is large. 16632772cf6bSDavid Gibson */ 16642772cf6bSDavid Gibson if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 16652772cf6bSDavid Gibson int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 16662772cf6bSDavid Gibson 16672772cf6bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 16682772cf6bSDavid Gibson error_report( 16692772cf6bSDavid Gibson "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 16702772cf6bSDavid Gibson exit(1); 16712772cf6bSDavid Gibson } 16722772cf6bSDavid Gibson 16732772cf6bSDavid Gibson if (spapr->htab_shift < maxshift) { 16742772cf6bSDavid Gibson /* Guest doesn't know about HPT resizing, so we 16752772cf6bSDavid Gibson * pre-emptively resize for the maximum permitted RAM. At 16762772cf6bSDavid Gibson * the point this is called, nothing should have been 16772772cf6bSDavid Gibson * entered into the existing HPT */ 16782772cf6bSDavid Gibson spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 16791ec26c75SGreg Kurz push_sregs_to_kvm_pr(spapr); 1680b55d295eSDavid Gibson } 16812772cf6bSDavid Gibson } 16822772cf6bSDavid Gibson 1683facdb8b6SMichael Roth /* NOTE: there are actually a number of ov5 bits where input from the 1684facdb8b6SMichael Roth * guest is always zero, and the platform/QEMU enables them independently 1685facdb8b6SMichael Roth * of guest input. To model these properly we'd want some sort of mask, 1686facdb8b6SMichael Roth * but since they only currently apply to memory migration as defined 1687facdb8b6SMichael Roth * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 16886787d27bSMichael Roth * to worry about this for now. 1689facdb8b6SMichael Roth */ 16906787d27bSMichael Roth ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); 169130bf9ed1SCédric Le Goater 169230bf9ed1SCédric Le Goater /* also clear the radix/hash bit from the current ov5_cas bits to 169330bf9ed1SCédric Le Goater * be in sync with the newly ov5 bits. Else the radix bit will be 169430bf9ed1SCédric Le Goater * seen as being removed and this will generate a reset loop 169530bf9ed1SCédric Le Goater */ 169630bf9ed1SCédric Le Goater spapr_ovec_clear(ov5_cas_old, OV5_MMU_RADIX_300); 169730bf9ed1SCédric Le Goater 16986787d27bSMichael Roth /* full range of negotiated ov5 capabilities */ 1699facdb8b6SMichael Roth spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1700facdb8b6SMichael Roth spapr_ovec_cleanup(ov5_guest); 17016787d27bSMichael Roth /* capabilities that have been added since CAS-generated guest reset. 17026787d27bSMichael Roth * if capabilities have since been removed, generate another reset 17036787d27bSMichael Roth */ 17046787d27bSMichael Roth ov5_updates = spapr_ovec_new(); 17056787d27bSMichael Roth spapr->cas_reboot = spapr_ovec_diff(ov5_updates, 17066787d27bSMichael Roth ov5_cas_old, spapr->ov5_cas); 170700005f22SShivaprasad G Bhat spapr_ovec_cleanup(ov5_cas_old); 17089fb4541fSSam Bobroff /* Now that processing is finished, set the radix/hash bit for the 17099fb4541fSSam Bobroff * guest if it requested a valid mode; otherwise terminate the boot. */ 17109fb4541fSSam Bobroff if (guest_radix) { 17119fb4541fSSam Bobroff if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 17129fb4541fSSam Bobroff error_report("Guest requested unavailable MMU mode (radix)."); 17139fb4541fSSam Bobroff exit(EXIT_FAILURE); 17149fb4541fSSam Bobroff } 17159fb4541fSSam Bobroff spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300); 17169fb4541fSSam Bobroff } else { 17179fb4541fSSam Bobroff if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 17189fb4541fSSam Bobroff && !kvmppc_has_cap_mmu_hash_v3()) { 17199fb4541fSSam Bobroff error_report("Guest requested unavailable MMU mode (hash)."); 17209fb4541fSSam Bobroff exit(EXIT_FAILURE); 17219fb4541fSSam Bobroff } 17229fb4541fSSam Bobroff } 1723e957f6a9SSam Bobroff spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest, 1724e957f6a9SSam Bobroff OV1_PPC_3_00); 172500005f22SShivaprasad G Bhat spapr_ovec_cleanup(ov1_guest); 17266787d27bSMichael Roth if (!spapr->cas_reboot) { 1727b472b1a7SDaniel Henrique Barboza /* If spapr_machine_reset() did not set up a HPT but one is necessary 1728e05fba50SSam Bobroff * (because the guest isn't going to use radix) then set it up here. */ 172979825f4dSBenjamin Herrenschmidt if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { 1730e05fba50SSam Bobroff /* legacy hash or new hash: */ 1731e05fba50SSam Bobroff spapr_setup_hpt_and_vrma(spapr); 1732e05fba50SSam Bobroff } 17336787d27bSMichael Roth spapr->cas_reboot = 17345b120785SDavid Gibson (spapr_h_cas_compose_response(spapr, args[1], args[2], 17356787d27bSMichael Roth ov5_updates) != 0); 17366787d27bSMichael Roth } 173713db0cd9SCédric Le Goater 173813db0cd9SCédric Le Goater /* 1739e7f78db9SGreg Kurz * Ensure the guest asks for an interrupt mode we support; otherwise 1740e7f78db9SGreg Kurz * terminate the boot. 1741e7f78db9SGreg Kurz */ 1742e7f78db9SGreg Kurz if (guest_xive) { 1743e7f78db9SGreg Kurz if (spapr->irq->ov5 == SPAPR_OV5_XIVE_LEGACY) { 174475de5941SGreg Kurz error_report( 174575de5941SGreg Kurz "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property"); 1746e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1747e7f78db9SGreg Kurz } 1748e7f78db9SGreg Kurz } else { 1749e7f78db9SGreg Kurz if (spapr->irq->ov5 == SPAPR_OV5_XIVE_EXPLOIT) { 175075de5941SGreg Kurz error_report( 175175de5941SGreg Kurz "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual"); 1752e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1753e7f78db9SGreg Kurz } 1754e7f78db9SGreg Kurz } 1755e7f78db9SGreg Kurz 1756e7f78db9SGreg Kurz /* 175713db0cd9SCédric Le Goater * Generate a machine reset when we have an update of the 175813db0cd9SCédric Le Goater * interrupt mode. Only required when the machine supports both 175913db0cd9SCédric Le Goater * modes. 176013db0cd9SCédric Le Goater */ 176113db0cd9SCédric Le Goater if (!spapr->cas_reboot) { 176213db0cd9SCédric Le Goater spapr->cas_reboot = spapr_ovec_test(ov5_updates, OV5_XIVE_EXPLOIT) 176313db0cd9SCédric Le Goater && spapr->irq->ov5 & SPAPR_OV5_XIVE_BOTH; 176413db0cd9SCédric Le Goater } 176513db0cd9SCédric Le Goater 17666787d27bSMichael Roth spapr_ovec_cleanup(ov5_updates); 17676787d27bSMichael Roth 17686787d27bSMichael Roth if (spapr->cas_reboot) { 1769cf83f140SEric Blake qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 17702a6593cbSAlexey Kardashevskiy } 17712a6593cbSAlexey Kardashevskiy 17722a6593cbSAlexey Kardashevskiy return H_SUCCESS; 17732a6593cbSAlexey Kardashevskiy } 17742a6593cbSAlexey Kardashevskiy 1775c24ba3d0SLaurent Vivier static target_ulong h_home_node_associativity(PowerPCCPU *cpu, 1776ce2918cbSDavid Gibson SpaprMachineState *spapr, 1777c24ba3d0SLaurent Vivier target_ulong opcode, 1778c24ba3d0SLaurent Vivier target_ulong *args) 1779c24ba3d0SLaurent Vivier { 1780c24ba3d0SLaurent Vivier target_ulong flags = args[0]; 1781c24ba3d0SLaurent Vivier target_ulong procno = args[1]; 1782c24ba3d0SLaurent Vivier PowerPCCPU *tcpu; 1783c24ba3d0SLaurent Vivier int idx; 1784c24ba3d0SLaurent Vivier 1785c24ba3d0SLaurent Vivier /* only support procno from H_REGISTER_VPA */ 1786c24ba3d0SLaurent Vivier if (flags != 0x1) { 1787c24ba3d0SLaurent Vivier return H_FUNCTION; 1788c24ba3d0SLaurent Vivier } 1789c24ba3d0SLaurent Vivier 1790c24ba3d0SLaurent Vivier tcpu = spapr_find_cpu(procno); 1791c24ba3d0SLaurent Vivier if (tcpu == NULL) { 1792c24ba3d0SLaurent Vivier return H_P2; 1793c24ba3d0SLaurent Vivier } 1794c24ba3d0SLaurent Vivier 1795c24ba3d0SLaurent Vivier /* sequence is the same as in the "ibm,associativity" property */ 1796c24ba3d0SLaurent Vivier 1797c24ba3d0SLaurent Vivier idx = 0; 1798c24ba3d0SLaurent Vivier #define ASSOCIATIVITY(a, b) (((uint64_t)(a) << 32) | \ 1799c24ba3d0SLaurent Vivier ((uint64_t)(b) & 0xffffffff)) 1800c24ba3d0SLaurent Vivier args[idx++] = ASSOCIATIVITY(0, 0); 1801c24ba3d0SLaurent Vivier args[idx++] = ASSOCIATIVITY(0, tcpu->node_id); 1802c24ba3d0SLaurent Vivier args[idx++] = ASSOCIATIVITY(procno, -1); 1803c24ba3d0SLaurent Vivier for ( ; idx < 6; idx++) { 1804c24ba3d0SLaurent Vivier args[idx] = -1; 1805c24ba3d0SLaurent Vivier } 1806c24ba3d0SLaurent Vivier #undef ASSOCIATIVITY 1807c24ba3d0SLaurent Vivier 1808c24ba3d0SLaurent Vivier return H_SUCCESS; 1809c24ba3d0SLaurent Vivier } 1810c24ba3d0SLaurent Vivier 1811c59704b2SSuraj Jitindar Singh static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1812ce2918cbSDavid Gibson SpaprMachineState *spapr, 1813c59704b2SSuraj Jitindar Singh target_ulong opcode, 1814c59704b2SSuraj Jitindar Singh target_ulong *args) 1815c59704b2SSuraj Jitindar Singh { 1816c59704b2SSuraj Jitindar Singh uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1817c59704b2SSuraj Jitindar Singh ~H_CPU_CHAR_THR_RECONF_TRIG; 1818c59704b2SSuraj Jitindar Singh uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1819c59704b2SSuraj Jitindar Singh uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1820c59704b2SSuraj Jitindar Singh uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1821c59704b2SSuraj Jitindar Singh uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 18228ff43ee4SSuraj Jitindar Singh uint8_t count_cache_flush_assist = spapr_get_cap(spapr, 18238ff43ee4SSuraj Jitindar Singh SPAPR_CAP_CCF_ASSIST); 1824c59704b2SSuraj Jitindar Singh 1825c59704b2SSuraj Jitindar Singh switch (safe_cache) { 1826c59704b2SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1827c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1828c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1829c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1830c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1831c59704b2SSuraj Jitindar Singh break; 1832c59704b2SSuraj Jitindar Singh case SPAPR_CAP_FIXED: 1833c59704b2SSuraj Jitindar Singh break; 1834c59704b2SSuraj Jitindar Singh default: /* broken */ 1835c59704b2SSuraj Jitindar Singh assert(safe_cache == SPAPR_CAP_BROKEN); 1836c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1837c59704b2SSuraj Jitindar Singh break; 1838c59704b2SSuraj Jitindar Singh } 1839c59704b2SSuraj Jitindar Singh 1840c59704b2SSuraj Jitindar Singh switch (safe_bounds_check) { 1841c59704b2SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1842c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1843c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1844c59704b2SSuraj Jitindar Singh break; 1845c59704b2SSuraj Jitindar Singh case SPAPR_CAP_FIXED: 1846c59704b2SSuraj Jitindar Singh break; 1847c59704b2SSuraj Jitindar Singh default: /* broken */ 1848c59704b2SSuraj Jitindar Singh assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1849c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1850c59704b2SSuraj Jitindar Singh break; 1851c59704b2SSuraj Jitindar Singh } 1852c59704b2SSuraj Jitindar Singh 1853c59704b2SSuraj Jitindar Singh switch (safe_indirect_branch) { 1854399b2896SSuraj Jitindar Singh case SPAPR_CAP_FIXED_NA: 1855399b2896SSuraj Jitindar Singh break; 1856c76c0d30SSuraj Jitindar Singh case SPAPR_CAP_FIXED_CCD: 1857c76c0d30SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; 1858c76c0d30SSuraj Jitindar Singh break; 1859c76c0d30SSuraj Jitindar Singh case SPAPR_CAP_FIXED_IBS: 1860c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1861fa86f592SGreg Kurz break; 1862399b2896SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1863399b2896SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE; 18648ff43ee4SSuraj Jitindar Singh if (count_cache_flush_assist) { 18658ff43ee4SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST; 18668ff43ee4SSuraj Jitindar Singh } 1867399b2896SSuraj Jitindar Singh break; 1868c59704b2SSuraj Jitindar Singh default: /* broken */ 1869c59704b2SSuraj Jitindar Singh assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1870c59704b2SSuraj Jitindar Singh break; 1871c59704b2SSuraj Jitindar Singh } 1872c59704b2SSuraj Jitindar Singh 1873c59704b2SSuraj Jitindar Singh args[0] = characteristics; 1874c59704b2SSuraj Jitindar Singh args[1] = behaviour; 1875fea35ca4SAlexey Kardashevskiy return H_SUCCESS; 1876fea35ca4SAlexey Kardashevskiy } 1877fea35ca4SAlexey Kardashevskiy 1878ce2918cbSDavid Gibson static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, 1879fea35ca4SAlexey Kardashevskiy target_ulong opcode, target_ulong *args) 1880fea35ca4SAlexey Kardashevskiy { 1881fea35ca4SAlexey Kardashevskiy target_ulong dt = ppc64_phys_to_real(args[0]); 1882fea35ca4SAlexey Kardashevskiy struct fdt_header hdr = { 0 }; 1883fea35ca4SAlexey Kardashevskiy unsigned cb; 1884ce2918cbSDavid Gibson SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1885fea35ca4SAlexey Kardashevskiy void *fdt; 1886fea35ca4SAlexey Kardashevskiy 1887fea35ca4SAlexey Kardashevskiy cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); 1888fea35ca4SAlexey Kardashevskiy cb = fdt32_to_cpu(hdr.totalsize); 1889fea35ca4SAlexey Kardashevskiy 1890fea35ca4SAlexey Kardashevskiy if (!smc->update_dt_enabled) { 1891fea35ca4SAlexey Kardashevskiy return H_SUCCESS; 1892fea35ca4SAlexey Kardashevskiy } 1893fea35ca4SAlexey Kardashevskiy 1894fea35ca4SAlexey Kardashevskiy /* Check that the fdt did not grow out of proportion */ 1895fea35ca4SAlexey Kardashevskiy if (cb > spapr->fdt_initial_size * 2) { 1896fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, 1897fea35ca4SAlexey Kardashevskiy fdt32_to_cpu(hdr.magic)); 1898fea35ca4SAlexey Kardashevskiy return H_PARAMETER; 1899fea35ca4SAlexey Kardashevskiy } 1900fea35ca4SAlexey Kardashevskiy 1901fea35ca4SAlexey Kardashevskiy fdt = g_malloc0(cb); 1902fea35ca4SAlexey Kardashevskiy cpu_physical_memory_read(dt, fdt, cb); 1903fea35ca4SAlexey Kardashevskiy 1904fea35ca4SAlexey Kardashevskiy /* Check the fdt consistency */ 1905fea35ca4SAlexey Kardashevskiy if (fdt_check_full(fdt, cb)) { 1906fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, 1907fea35ca4SAlexey Kardashevskiy fdt32_to_cpu(hdr.magic)); 1908fea35ca4SAlexey Kardashevskiy return H_PARAMETER; 1909fea35ca4SAlexey Kardashevskiy } 1910fea35ca4SAlexey Kardashevskiy 1911fea35ca4SAlexey Kardashevskiy g_free(spapr->fdt_blob); 1912fea35ca4SAlexey Kardashevskiy spapr->fdt_size = cb; 1913fea35ca4SAlexey Kardashevskiy spapr->fdt_blob = fdt; 1914fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt(cb); 1915c59704b2SSuraj Jitindar Singh 1916c59704b2SSuraj Jitindar Singh return H_SUCCESS; 1917c59704b2SSuraj Jitindar Singh } 1918c59704b2SSuraj Jitindar Singh 19199f64bd8aSPaolo Bonzini static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 19209f64bd8aSPaolo Bonzini static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 19219f64bd8aSPaolo Bonzini 19229f64bd8aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 19239f64bd8aSPaolo Bonzini { 19249f64bd8aSPaolo Bonzini spapr_hcall_fn *slot; 19259f64bd8aSPaolo Bonzini 19269f64bd8aSPaolo Bonzini if (opcode <= MAX_HCALL_OPCODE) { 19279f64bd8aSPaolo Bonzini assert((opcode & 0x3) == 0); 19289f64bd8aSPaolo Bonzini 19299f64bd8aSPaolo Bonzini slot = &papr_hypercall_table[opcode / 4]; 19309f64bd8aSPaolo Bonzini } else { 19319f64bd8aSPaolo Bonzini assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 19329f64bd8aSPaolo Bonzini 19339f64bd8aSPaolo Bonzini slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 19349f64bd8aSPaolo Bonzini } 19359f64bd8aSPaolo Bonzini 19369f64bd8aSPaolo Bonzini assert(!(*slot)); 19379f64bd8aSPaolo Bonzini *slot = fn; 19389f64bd8aSPaolo Bonzini } 19399f64bd8aSPaolo Bonzini 19409f64bd8aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 19419f64bd8aSPaolo Bonzini target_ulong *args) 19429f64bd8aSPaolo Bonzini { 1943ce2918cbSDavid Gibson SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 194428e02042SDavid Gibson 19459f64bd8aSPaolo Bonzini if ((opcode <= MAX_HCALL_OPCODE) 19469f64bd8aSPaolo Bonzini && ((opcode & 0x3) == 0)) { 19479f64bd8aSPaolo Bonzini spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 19489f64bd8aSPaolo Bonzini 19499f64bd8aSPaolo Bonzini if (fn) { 19509f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 19519f64bd8aSPaolo Bonzini } 19529f64bd8aSPaolo Bonzini } else if ((opcode >= KVMPPC_HCALL_BASE) && 19539f64bd8aSPaolo Bonzini (opcode <= KVMPPC_HCALL_MAX)) { 19549f64bd8aSPaolo Bonzini spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 19559f64bd8aSPaolo Bonzini 19569f64bd8aSPaolo Bonzini if (fn) { 19579f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 19589f64bd8aSPaolo Bonzini } 19599f64bd8aSPaolo Bonzini } 19609f64bd8aSPaolo Bonzini 1961aaf87c66SThomas Huth qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1962aaf87c66SThomas Huth opcode); 19639f64bd8aSPaolo Bonzini return H_FUNCTION; 19649f64bd8aSPaolo Bonzini } 19659f64bd8aSPaolo Bonzini 19669f64bd8aSPaolo Bonzini static void hypercall_register_types(void) 19679f64bd8aSPaolo Bonzini { 19689f64bd8aSPaolo Bonzini /* hcall-pft */ 19699f64bd8aSPaolo Bonzini spapr_register_hypercall(H_ENTER, h_enter); 19709f64bd8aSPaolo Bonzini spapr_register_hypercall(H_REMOVE, h_remove); 19719f64bd8aSPaolo Bonzini spapr_register_hypercall(H_PROTECT, h_protect); 1972fa388916SAnthony Liguori spapr_register_hypercall(H_READ, h_read); 19739f64bd8aSPaolo Bonzini 19749f64bd8aSPaolo Bonzini /* hcall-bulk */ 19759f64bd8aSPaolo Bonzini spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 19769f64bd8aSPaolo Bonzini 197730f4b05bSDavid Gibson /* hcall-hpt-resize */ 197830f4b05bSDavid Gibson spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 197930f4b05bSDavid Gibson spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 198030f4b05bSDavid Gibson 19819f64bd8aSPaolo Bonzini /* hcall-splpar */ 19829f64bd8aSPaolo Bonzini spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 19839f64bd8aSPaolo Bonzini spapr_register_hypercall(H_CEDE, h_cede); 1984*e8ce0e40SNicholas Piggin spapr_register_hypercall(H_CONFER, h_confer); 19853a6e6224SNicholas Piggin spapr_register_hypercall(H_PROD, h_prod); 19863a6e6224SNicholas Piggin 19871c7ad77eSNicholas Piggin spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 19889f64bd8aSPaolo Bonzini 1989423576f7SThomas Huth /* processor register resource access h-calls */ 1990423576f7SThomas Huth spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1991af08a58fSThomas Huth spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1992e49ff266SThomas Huth spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 19933240dd9aSThomas Huth spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1994423576f7SThomas Huth spapr_register_hypercall(H_SET_MODE, h_set_mode); 1995423576f7SThomas Huth 1996d77a98b0SSuraj Jitindar Singh /* In Memory Table MMU h-calls */ 1997d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1998d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1999d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 2000d77a98b0SSuraj Jitindar Singh 2001c59704b2SSuraj Jitindar Singh /* hcall-get-cpu-characteristics */ 2002c59704b2SSuraj Jitindar Singh spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 2003c59704b2SSuraj Jitindar Singh h_get_cpu_characteristics); 2004c59704b2SSuraj Jitindar Singh 20059f64bd8aSPaolo Bonzini /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 20069f64bd8aSPaolo Bonzini * here between the "CI" and the "CACHE" variants, they will use whatever 20079f64bd8aSPaolo Bonzini * mapping attributes qemu is using. When using KVM, the kernel will 20089f64bd8aSPaolo Bonzini * enforce the attributes more strongly 20099f64bd8aSPaolo Bonzini */ 20109f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 20119f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 20129f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 20139f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 20149f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 20159f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 20169f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 20179f64bd8aSPaolo Bonzini 20189f64bd8aSPaolo Bonzini /* qemu/KVM-PPC specific hcalls */ 20199f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 202042561bf2SAnton Blanchard 20212a6593cbSAlexey Kardashevskiy /* ibm,client-architecture-support support */ 20222a6593cbSAlexey Kardashevskiy spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 2023c24ba3d0SLaurent Vivier 2024fea35ca4SAlexey Kardashevskiy spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); 2025fea35ca4SAlexey Kardashevskiy 2026c24ba3d0SLaurent Vivier /* Virtual Processor Home Node */ 2027c24ba3d0SLaurent Vivier spapr_register_hypercall(H_HOME_NODE_ASSOCIATIVITY, 2028c24ba3d0SLaurent Vivier h_home_node_associativity); 20299f64bd8aSPaolo Bonzini } 20309f64bd8aSPaolo Bonzini 20319f64bd8aSPaolo Bonzini type_init(hypercall_register_types) 2032