10d75590dSPeter Maydell #include "qemu/osdep.h" 2da34e65cSMarkus Armbruster #include "qapi/error.h" 3b3946626SVincent Palatin #include "sysemu/hw_accel.h" 49f64bd8aSPaolo Bonzini #include "sysemu/sysemu.h" 503dd024fSPaolo Bonzini #include "qemu/log.h" 60b0b8310SDavid Gibson #include "qemu/error-report.h" 79f64bd8aSPaolo Bonzini #include "cpu.h" 863c91552SPaolo Bonzini #include "exec/exec-all.h" 99f64bd8aSPaolo Bonzini #include "helper_regs.h" 100d09e41aSPaolo Bonzini #include "hw/ppc/spapr.h" 117388efafSDavid Gibson #include "hw/ppc/spapr_cpu_core.h" 12d5aea6f3SDavid Gibson #include "mmu-hash64.h" 133794d548SAlexey Kardashevskiy #include "cpu-models.h" 143794d548SAlexey Kardashevskiy #include "trace.h" 153794d548SAlexey Kardashevskiy #include "kvm_ppc.h" 16facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 17b4db5413SSuraj Jitindar Singh #include "mmu-book3s-v3.h" 182cc0e2e8SDavid Hildenbrand #include "hw/mem/memory-device.h" 199f64bd8aSPaolo Bonzini 20af08a58fSThomas Huth static bool has_spr(PowerPCCPU *cpu, int spr) 21af08a58fSThomas Huth { 22af08a58fSThomas Huth /* We can test whether the SPR is defined by checking for a valid name */ 23af08a58fSThomas Huth return cpu->env.spr_cb[spr].name != NULL; 24af08a58fSThomas Huth } 25af08a58fSThomas Huth 26c6404adeSDavid Gibson static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) 27f3c75d42SAneesh Kumar K.V { 28f3c75d42SAneesh Kumar K.V /* 2936778660SDavid Gibson * hash value/pteg group index is normalized by HPT mask 30f3c75d42SAneesh Kumar K.V */ 3136778660SDavid Gibson if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { 32f3c75d42SAneesh Kumar K.V return false; 33f3c75d42SAneesh Kumar K.V } 34f3c75d42SAneesh Kumar K.V return true; 35f3c75d42SAneesh Kumar K.V } 36f3c75d42SAneesh Kumar K.V 37ce2918cbSDavid Gibson static bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) 38ecbc25faSDavid Gibson { 39ecbc25faSDavid Gibson MachineState *machine = MACHINE(spapr); 40e017da37SDavid Hildenbrand DeviceMemoryState *dms = machine->device_memory; 41ecbc25faSDavid Gibson 42ecbc25faSDavid Gibson if (addr < machine->ram_size) { 43ecbc25faSDavid Gibson return true; 44ecbc25faSDavid Gibson } 45e017da37SDavid Hildenbrand if ((addr >= dms->base) 46e017da37SDavid Hildenbrand && ((addr - dms->base) < memory_region_size(&dms->mr))) { 47ecbc25faSDavid Gibson return true; 48ecbc25faSDavid Gibson } 49ecbc25faSDavid Gibson 50ecbc25faSDavid Gibson return false; 51ecbc25faSDavid Gibson } 52ecbc25faSDavid Gibson 53ce2918cbSDavid Gibson static target_ulong h_enter(PowerPCCPU *cpu, SpaprMachineState *spapr, 549f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 559f64bd8aSPaolo Bonzini { 569f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 57c6404adeSDavid Gibson target_ulong ptex = args[1]; 589f64bd8aSPaolo Bonzini target_ulong pteh = args[2]; 599f64bd8aSPaolo Bonzini target_ulong ptel = args[3]; 601f0252e6SCédric Le Goater unsigned apshift; 619f64bd8aSPaolo Bonzini target_ulong raddr; 62c6404adeSDavid Gibson target_ulong slot; 637222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 649f64bd8aSPaolo Bonzini 651f0252e6SCédric Le Goater apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); 661114e712SDavid Gibson if (!apshift) { 671114e712SDavid Gibson /* Bad page size encoding */ 689f64bd8aSPaolo Bonzini return H_PARAMETER; 699f64bd8aSPaolo Bonzini } 709f64bd8aSPaolo Bonzini 711114e712SDavid Gibson raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); 729f64bd8aSPaolo Bonzini 73ecbc25faSDavid Gibson if (is_ram_address(spapr, raddr)) { 749f64bd8aSPaolo Bonzini /* Regular RAM - should have WIMG=0010 */ 75d5aea6f3SDavid Gibson if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 769f64bd8aSPaolo Bonzini return H_PARAMETER; 779f64bd8aSPaolo Bonzini } 789f64bd8aSPaolo Bonzini } else { 79c1175907SAneesh Kumar K.V target_ulong wimg_flags; 809f64bd8aSPaolo Bonzini /* Looks like an IO address */ 819f64bd8aSPaolo Bonzini /* FIXME: What WIMG combinations could be sensible for IO? 829f64bd8aSPaolo Bonzini * For now we allow WIMG=010x, but are there others? */ 839f64bd8aSPaolo Bonzini /* FIXME: Should we check against registered IO addresses? */ 84c1175907SAneesh Kumar K.V wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); 85c1175907SAneesh Kumar K.V 86c1175907SAneesh Kumar K.V if (wimg_flags != HPTE64_R_I && 87c1175907SAneesh Kumar K.V wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { 889f64bd8aSPaolo Bonzini return H_PARAMETER; 899f64bd8aSPaolo Bonzini } 909f64bd8aSPaolo Bonzini } 919f64bd8aSPaolo Bonzini 929f64bd8aSPaolo Bonzini pteh &= ~0x60ULL; 939f64bd8aSPaolo Bonzini 94c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 959f64bd8aSPaolo Bonzini return H_PARAMETER; 969f64bd8aSPaolo Bonzini } 977c43bca0SAneesh Kumar K.V 98c6404adeSDavid Gibson slot = ptex & 7ULL; 99c6404adeSDavid Gibson ptex = ptex & ~7ULL; 100c6404adeSDavid Gibson 1019f64bd8aSPaolo Bonzini if (likely((flags & H_EXACT) == 0)) { 1027222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 103c6404adeSDavid Gibson for (slot = 0; slot < 8; slot++) { 1047222b94aSDavid Gibson if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { 1059f64bd8aSPaolo Bonzini break; 1069f64bd8aSPaolo Bonzini } 1077aaf4957SAneesh Kumar K.V } 1087222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 109c6404adeSDavid Gibson if (slot == 8) { 1107aaf4957SAneesh Kumar K.V return H_PTEG_FULL; 1117aaf4957SAneesh Kumar K.V } 1129f64bd8aSPaolo Bonzini } else { 1137222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); 1147222b94aSDavid Gibson if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { 1157222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); 1169f64bd8aSPaolo Bonzini return H_PTEG_FULL; 1179f64bd8aSPaolo Bonzini } 1187222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 1199f64bd8aSPaolo Bonzini } 1207c43bca0SAneesh Kumar K.V 121a2dd4e83SBenjamin Herrenschmidt spapr_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); 1229f64bd8aSPaolo Bonzini 123c6404adeSDavid Gibson args[0] = ptex + slot; 1249f64bd8aSPaolo Bonzini return H_SUCCESS; 1259f64bd8aSPaolo Bonzini } 1269f64bd8aSPaolo Bonzini 127a3801402SStefan Weil typedef enum { 1289f64bd8aSPaolo Bonzini REMOVE_SUCCESS = 0, 1299f64bd8aSPaolo Bonzini REMOVE_NOT_FOUND = 1, 1309f64bd8aSPaolo Bonzini REMOVE_PARM = 2, 1319f64bd8aSPaolo Bonzini REMOVE_HW = 3, 132a3801402SStefan Weil } RemoveResult; 1339f64bd8aSPaolo Bonzini 134a2dd4e83SBenjamin Herrenschmidt static RemoveResult remove_hpte(PowerPCCPU *cpu 135a2dd4e83SBenjamin Herrenschmidt , target_ulong ptex, 1369f64bd8aSPaolo Bonzini target_ulong avpn, 1379f64bd8aSPaolo Bonzini target_ulong flags, 1389f64bd8aSPaolo Bonzini target_ulong *vp, target_ulong *rp) 1399f64bd8aSPaolo Bonzini { 1407222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 14161a36c9bSDavid Gibson target_ulong v, r; 1429f64bd8aSPaolo Bonzini 143c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 1449f64bd8aSPaolo Bonzini return REMOVE_PARM; 1459f64bd8aSPaolo Bonzini } 1469f64bd8aSPaolo Bonzini 1477222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 1487222b94aSDavid Gibson v = ppc_hash64_hpte0(cpu, hptes, 0); 1497222b94aSDavid Gibson r = ppc_hash64_hpte1(cpu, hptes, 0); 1507222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 1519f64bd8aSPaolo Bonzini 152d5aea6f3SDavid Gibson if ((v & HPTE64_V_VALID) == 0 || 1539f64bd8aSPaolo Bonzini ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 1549f64bd8aSPaolo Bonzini ((flags & H_ANDCOND) && (v & avpn) != 0)) { 1559f64bd8aSPaolo Bonzini return REMOVE_NOT_FOUND; 1569f64bd8aSPaolo Bonzini } 1579f64bd8aSPaolo Bonzini *vp = v; 1589f64bd8aSPaolo Bonzini *rp = r; 159a2dd4e83SBenjamin Herrenschmidt spapr_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); 16061a36c9bSDavid Gibson ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 1619f64bd8aSPaolo Bonzini return REMOVE_SUCCESS; 1629f64bd8aSPaolo Bonzini } 1639f64bd8aSPaolo Bonzini 164ce2918cbSDavid Gibson static target_ulong h_remove(PowerPCCPU *cpu, SpaprMachineState *spapr, 1659f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 1669f64bd8aSPaolo Bonzini { 167cd0c6f47SBenjamin Herrenschmidt CPUPPCState *env = &cpu->env; 1689f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 169c6404adeSDavid Gibson target_ulong ptex = args[1]; 1709f64bd8aSPaolo Bonzini target_ulong avpn = args[2]; 171a3801402SStefan Weil RemoveResult ret; 1729f64bd8aSPaolo Bonzini 173c6404adeSDavid Gibson ret = remove_hpte(cpu, ptex, avpn, flags, 1749f64bd8aSPaolo Bonzini &args[0], &args[1]); 1759f64bd8aSPaolo Bonzini 1769f64bd8aSPaolo Bonzini switch (ret) { 1779f64bd8aSPaolo Bonzini case REMOVE_SUCCESS: 178e3cffe6fSNikunj A Dadhania check_tlb_flush(env, true); 1799f64bd8aSPaolo Bonzini return H_SUCCESS; 1809f64bd8aSPaolo Bonzini 1819f64bd8aSPaolo Bonzini case REMOVE_NOT_FOUND: 1829f64bd8aSPaolo Bonzini return H_NOT_FOUND; 1839f64bd8aSPaolo Bonzini 1849f64bd8aSPaolo Bonzini case REMOVE_PARM: 1859f64bd8aSPaolo Bonzini return H_PARAMETER; 1869f64bd8aSPaolo Bonzini 1879f64bd8aSPaolo Bonzini case REMOVE_HW: 1889f64bd8aSPaolo Bonzini return H_HARDWARE; 1899f64bd8aSPaolo Bonzini } 1909f64bd8aSPaolo Bonzini 1919a39970dSStefan Weil g_assert_not_reached(); 1929f64bd8aSPaolo Bonzini } 1939f64bd8aSPaolo Bonzini 1949f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 1959f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 1969f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 1979f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_END 0xc000000000000000ULL 1989f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 1999f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 2009f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 2019f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 2029f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_HW 0x3000000000000000ULL 2039f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 2049f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 2059f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 2069f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 2079f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 2089f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 2099f64bd8aSPaolo Bonzini 2109f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_MAX_BATCH 4 2119f64bd8aSPaolo Bonzini 212ce2918cbSDavid Gibson static target_ulong h_bulk_remove(PowerPCCPU *cpu, SpaprMachineState *spapr, 2139f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 2149f64bd8aSPaolo Bonzini { 215cd0c6f47SBenjamin Herrenschmidt CPUPPCState *env = &cpu->env; 2169f64bd8aSPaolo Bonzini int i; 217cd0c6f47SBenjamin Herrenschmidt target_ulong rc = H_SUCCESS; 2189f64bd8aSPaolo Bonzini 2199f64bd8aSPaolo Bonzini for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 2209f64bd8aSPaolo Bonzini target_ulong *tsh = &args[i*2]; 2219f64bd8aSPaolo Bonzini target_ulong tsl = args[i*2 + 1]; 2229f64bd8aSPaolo Bonzini target_ulong v, r, ret; 2239f64bd8aSPaolo Bonzini 2249f64bd8aSPaolo Bonzini if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 2259f64bd8aSPaolo Bonzini break; 2269f64bd8aSPaolo Bonzini } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 2279f64bd8aSPaolo Bonzini return H_PARAMETER; 2289f64bd8aSPaolo Bonzini } 2299f64bd8aSPaolo Bonzini 2309f64bd8aSPaolo Bonzini *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 2319f64bd8aSPaolo Bonzini *tsh |= H_BULK_REMOVE_RESPONSE; 2329f64bd8aSPaolo Bonzini 2339f64bd8aSPaolo Bonzini if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 2349f64bd8aSPaolo Bonzini *tsh |= H_BULK_REMOVE_PARM; 2359f64bd8aSPaolo Bonzini return H_PARAMETER; 2369f64bd8aSPaolo Bonzini } 2379f64bd8aSPaolo Bonzini 2387ef23068SDavid Gibson ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, 2399f64bd8aSPaolo Bonzini (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 2409f64bd8aSPaolo Bonzini &v, &r); 2419f64bd8aSPaolo Bonzini 2429f64bd8aSPaolo Bonzini *tsh |= ret << 60; 2439f64bd8aSPaolo Bonzini 2449f64bd8aSPaolo Bonzini switch (ret) { 2459f64bd8aSPaolo Bonzini case REMOVE_SUCCESS: 246d5aea6f3SDavid Gibson *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 2479f64bd8aSPaolo Bonzini break; 2489f64bd8aSPaolo Bonzini 2499f64bd8aSPaolo Bonzini case REMOVE_PARM: 250cd0c6f47SBenjamin Herrenschmidt rc = H_PARAMETER; 251cd0c6f47SBenjamin Herrenschmidt goto exit; 2529f64bd8aSPaolo Bonzini 2539f64bd8aSPaolo Bonzini case REMOVE_HW: 254cd0c6f47SBenjamin Herrenschmidt rc = H_HARDWARE; 255cd0c6f47SBenjamin Herrenschmidt goto exit; 2569f64bd8aSPaolo Bonzini } 2579f64bd8aSPaolo Bonzini } 258cd0c6f47SBenjamin Herrenschmidt exit: 259e3cffe6fSNikunj A Dadhania check_tlb_flush(env, true); 2609f64bd8aSPaolo Bonzini 261cd0c6f47SBenjamin Herrenschmidt return rc; 2629f64bd8aSPaolo Bonzini } 2639f64bd8aSPaolo Bonzini 264ce2918cbSDavid Gibson static target_ulong h_protect(PowerPCCPU *cpu, SpaprMachineState *spapr, 2659f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 2669f64bd8aSPaolo Bonzini { 2679f64bd8aSPaolo Bonzini CPUPPCState *env = &cpu->env; 2689f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 269c6404adeSDavid Gibson target_ulong ptex = args[1]; 2709f64bd8aSPaolo Bonzini target_ulong avpn = args[2]; 2717222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 27261a36c9bSDavid Gibson target_ulong v, r; 2739f64bd8aSPaolo Bonzini 274c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 2759f64bd8aSPaolo Bonzini return H_PARAMETER; 2769f64bd8aSPaolo Bonzini } 2779f64bd8aSPaolo Bonzini 2787222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 2797222b94aSDavid Gibson v = ppc_hash64_hpte0(cpu, hptes, 0); 2807222b94aSDavid Gibson r = ppc_hash64_hpte1(cpu, hptes, 0); 2817222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 2829f64bd8aSPaolo Bonzini 283d5aea6f3SDavid Gibson if ((v & HPTE64_V_VALID) == 0 || 2849f64bd8aSPaolo Bonzini ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 2859f64bd8aSPaolo Bonzini return H_NOT_FOUND; 2869f64bd8aSPaolo Bonzini } 2879f64bd8aSPaolo Bonzini 288d5aea6f3SDavid Gibson r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 289d5aea6f3SDavid Gibson HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 290d5aea6f3SDavid Gibson r |= (flags << 55) & HPTE64_R_PP0; 291d5aea6f3SDavid Gibson r |= (flags << 48) & HPTE64_R_KEY_HI; 292d5aea6f3SDavid Gibson r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 293a2dd4e83SBenjamin Herrenschmidt spapr_store_hpte(cpu, ptex, 2943f94170bSAneesh Kumar K.V (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); 295c6404adeSDavid Gibson ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 296d76ab5e1SNikunj A Dadhania /* Flush the tlb */ 297d76ab5e1SNikunj A Dadhania check_tlb_flush(env, true); 2989f64bd8aSPaolo Bonzini /* Don't need a memory barrier, due to qemu's global lock */ 299a2dd4e83SBenjamin Herrenschmidt spapr_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); 3009f64bd8aSPaolo Bonzini return H_SUCCESS; 3019f64bd8aSPaolo Bonzini } 3029f64bd8aSPaolo Bonzini 303ce2918cbSDavid Gibson static target_ulong h_read(PowerPCCPU *cpu, SpaprMachineState *spapr, 304fa388916SAnthony Liguori target_ulong opcode, target_ulong *args) 305fa388916SAnthony Liguori { 306fa388916SAnthony Liguori target_ulong flags = args[0]; 307c6404adeSDavid Gibson target_ulong ptex = args[1]; 308fa388916SAnthony Liguori int i, ridx, n_entries = 1; 309993aaf0cSBenjamin Herrenschmidt const ppc_hash_pte64_t *hptes; 310fa388916SAnthony Liguori 311c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 312fa388916SAnthony Liguori return H_PARAMETER; 313fa388916SAnthony Liguori } 314fa388916SAnthony Liguori 315fa388916SAnthony Liguori if (flags & H_READ_4) { 316fa388916SAnthony Liguori /* Clear the two low order bits */ 317c6404adeSDavid Gibson ptex &= ~(3ULL); 318fa388916SAnthony Liguori n_entries = 4; 319fa388916SAnthony Liguori } 320fa388916SAnthony Liguori 321993aaf0cSBenjamin Herrenschmidt hptes = ppc_hash64_map_hptes(cpu, ptex, n_entries); 322fa388916SAnthony Liguori for (i = 0, ridx = 0; i < n_entries; i++) { 323993aaf0cSBenjamin Herrenschmidt args[ridx++] = ppc_hash64_hpte0(cpu, hptes, i); 324993aaf0cSBenjamin Herrenschmidt args[ridx++] = ppc_hash64_hpte1(cpu, hptes, i); 325fa388916SAnthony Liguori } 326993aaf0cSBenjamin Herrenschmidt ppc_hash64_unmap_hptes(cpu, hptes, ptex, n_entries); 327fa388916SAnthony Liguori 328fa388916SAnthony Liguori return H_SUCCESS; 329fa388916SAnthony Liguori } 330fa388916SAnthony Liguori 331ce2918cbSDavid Gibson struct SpaprPendingHpt { 3320b0b8310SDavid Gibson /* These fields are read-only after initialization */ 3330b0b8310SDavid Gibson int shift; 3340b0b8310SDavid Gibson QemuThread thread; 3350b0b8310SDavid Gibson 3360b0b8310SDavid Gibson /* These fields are protected by the BQL */ 3370b0b8310SDavid Gibson bool complete; 3380b0b8310SDavid Gibson 3390b0b8310SDavid Gibson /* These fields are private to the preparation thread if 3400b0b8310SDavid Gibson * !complete, otherwise protected by the BQL */ 3410b0b8310SDavid Gibson int ret; 3420b0b8310SDavid Gibson void *hpt; 3430b0b8310SDavid Gibson }; 3440b0b8310SDavid Gibson 345ce2918cbSDavid Gibson static void free_pending_hpt(SpaprPendingHpt *pending) 3460b0b8310SDavid Gibson { 3470b0b8310SDavid Gibson if (pending->hpt) { 3480b0b8310SDavid Gibson qemu_vfree(pending->hpt); 3490b0b8310SDavid Gibson } 3500b0b8310SDavid Gibson 3510b0b8310SDavid Gibson g_free(pending); 3520b0b8310SDavid Gibson } 3530b0b8310SDavid Gibson 3540b0b8310SDavid Gibson static void *hpt_prepare_thread(void *opaque) 3550b0b8310SDavid Gibson { 356ce2918cbSDavid Gibson SpaprPendingHpt *pending = opaque; 3570b0b8310SDavid Gibson size_t size = 1ULL << pending->shift; 3580b0b8310SDavid Gibson 3590b0b8310SDavid Gibson pending->hpt = qemu_memalign(size, size); 3600b0b8310SDavid Gibson if (pending->hpt) { 3610b0b8310SDavid Gibson memset(pending->hpt, 0, size); 3620b0b8310SDavid Gibson pending->ret = H_SUCCESS; 3630b0b8310SDavid Gibson } else { 3640b0b8310SDavid Gibson pending->ret = H_NO_MEM; 3650b0b8310SDavid Gibson } 3660b0b8310SDavid Gibson 3670b0b8310SDavid Gibson qemu_mutex_lock_iothread(); 3680b0b8310SDavid Gibson 3690b0b8310SDavid Gibson if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) { 3700b0b8310SDavid Gibson /* Ready to go */ 3710b0b8310SDavid Gibson pending->complete = true; 3720b0b8310SDavid Gibson } else { 3730b0b8310SDavid Gibson /* We've been cancelled, clean ourselves up */ 3740b0b8310SDavid Gibson free_pending_hpt(pending); 3750b0b8310SDavid Gibson } 3760b0b8310SDavid Gibson 3770b0b8310SDavid Gibson qemu_mutex_unlock_iothread(); 3780b0b8310SDavid Gibson return NULL; 3790b0b8310SDavid Gibson } 3800b0b8310SDavid Gibson 3810b0b8310SDavid Gibson /* Must be called with BQL held */ 382ce2918cbSDavid Gibson static void cancel_hpt_prepare(SpaprMachineState *spapr) 3830b0b8310SDavid Gibson { 384ce2918cbSDavid Gibson SpaprPendingHpt *pending = spapr->pending_hpt; 3850b0b8310SDavid Gibson 3860b0b8310SDavid Gibson /* Let the thread know it's cancelled */ 3870b0b8310SDavid Gibson spapr->pending_hpt = NULL; 3880b0b8310SDavid Gibson 3890b0b8310SDavid Gibson if (!pending) { 3900b0b8310SDavid Gibson /* Nothing to do */ 3910b0b8310SDavid Gibson return; 3920b0b8310SDavid Gibson } 3930b0b8310SDavid Gibson 3940b0b8310SDavid Gibson if (!pending->complete) { 3950b0b8310SDavid Gibson /* thread will clean itself up */ 3960b0b8310SDavid Gibson return; 3970b0b8310SDavid Gibson } 3980b0b8310SDavid Gibson 3990b0b8310SDavid Gibson free_pending_hpt(pending); 4000b0b8310SDavid Gibson } 4010b0b8310SDavid Gibson 402b55d295eSDavid Gibson /* Convert a return code from the KVM ioctl()s implementing resize HPT 403b55d295eSDavid Gibson * into a PAPR hypercall return code */ 404b55d295eSDavid Gibson static target_ulong resize_hpt_convert_rc(int ret) 405b55d295eSDavid Gibson { 406b55d295eSDavid Gibson if (ret >= 100000) { 407b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_100_SEC; 408b55d295eSDavid Gibson } else if (ret >= 10000) { 409b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_10_SEC; 410b55d295eSDavid Gibson } else if (ret >= 1000) { 411b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_1_SEC; 412b55d295eSDavid Gibson } else if (ret >= 100) { 413b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 414b55d295eSDavid Gibson } else if (ret >= 10) { 415b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_10_MSEC; 416b55d295eSDavid Gibson } else if (ret > 0) { 417b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_1_MSEC; 418b55d295eSDavid Gibson } 419b55d295eSDavid Gibson 420b55d295eSDavid Gibson switch (ret) { 421b55d295eSDavid Gibson case 0: 422b55d295eSDavid Gibson return H_SUCCESS; 423b55d295eSDavid Gibson case -EPERM: 424b55d295eSDavid Gibson return H_AUTHORITY; 425b55d295eSDavid Gibson case -EINVAL: 426b55d295eSDavid Gibson return H_PARAMETER; 427b55d295eSDavid Gibson case -ENXIO: 428b55d295eSDavid Gibson return H_CLOSED; 429b55d295eSDavid Gibson case -ENOSPC: 430b55d295eSDavid Gibson return H_PTEG_FULL; 431b55d295eSDavid Gibson case -EBUSY: 432b55d295eSDavid Gibson return H_BUSY; 433b55d295eSDavid Gibson case -ENOMEM: 434b55d295eSDavid Gibson return H_NO_MEM; 435b55d295eSDavid Gibson default: 436b55d295eSDavid Gibson return H_HARDWARE; 437b55d295eSDavid Gibson } 438b55d295eSDavid Gibson } 439b55d295eSDavid Gibson 44030f4b05bSDavid Gibson static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 441ce2918cbSDavid Gibson SpaprMachineState *spapr, 44230f4b05bSDavid Gibson target_ulong opcode, 44330f4b05bSDavid Gibson target_ulong *args) 44430f4b05bSDavid Gibson { 44530f4b05bSDavid Gibson target_ulong flags = args[0]; 4460b0b8310SDavid Gibson int shift = args[1]; 447ce2918cbSDavid Gibson SpaprPendingHpt *pending = spapr->pending_hpt; 448db50f280SDavid Gibson uint64_t current_ram_size; 449b55d295eSDavid Gibson int rc; 45030f4b05bSDavid Gibson 45130f4b05bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 45230f4b05bSDavid Gibson return H_AUTHORITY; 45330f4b05bSDavid Gibson } 45430f4b05bSDavid Gibson 4550b0b8310SDavid Gibson if (!spapr->htab_shift) { 4560b0b8310SDavid Gibson /* Radix guest, no HPT */ 4570b0b8310SDavid Gibson return H_NOT_AVAILABLE; 4580b0b8310SDavid Gibson } 4590b0b8310SDavid Gibson 46030f4b05bSDavid Gibson trace_spapr_h_resize_hpt_prepare(flags, shift); 4610b0b8310SDavid Gibson 4620b0b8310SDavid Gibson if (flags != 0) { 4630b0b8310SDavid Gibson return H_PARAMETER; 4640b0b8310SDavid Gibson } 4650b0b8310SDavid Gibson 4660b0b8310SDavid Gibson if (shift && ((shift < 18) || (shift > 46))) { 4670b0b8310SDavid Gibson return H_PARAMETER; 4680b0b8310SDavid Gibson } 4690b0b8310SDavid Gibson 470db50f280SDavid Gibson current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 4710b0b8310SDavid Gibson 4720b0b8310SDavid Gibson /* We only allow the guest to allocate an HPT one order above what 4730b0b8310SDavid Gibson * we'd normally give them (to stop a small guest claiming a huge 4740b0b8310SDavid Gibson * chunk of resources in the HPT */ 4750b0b8310SDavid Gibson if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 4760b0b8310SDavid Gibson return H_RESOURCE; 4770b0b8310SDavid Gibson } 4780b0b8310SDavid Gibson 479b55d295eSDavid Gibson rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 480b55d295eSDavid Gibson if (rc != -ENOSYS) { 481b55d295eSDavid Gibson return resize_hpt_convert_rc(rc); 482b55d295eSDavid Gibson } 483b55d295eSDavid Gibson 4840b0b8310SDavid Gibson if (pending) { 4850b0b8310SDavid Gibson /* something already in progress */ 4860b0b8310SDavid Gibson if (pending->shift == shift) { 4870b0b8310SDavid Gibson /* and it's suitable */ 4880b0b8310SDavid Gibson if (pending->complete) { 4890b0b8310SDavid Gibson return pending->ret; 4900b0b8310SDavid Gibson } else { 4910b0b8310SDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 4920b0b8310SDavid Gibson } 4930b0b8310SDavid Gibson } 4940b0b8310SDavid Gibson 4950b0b8310SDavid Gibson /* not suitable, cancel and replace */ 4960b0b8310SDavid Gibson cancel_hpt_prepare(spapr); 4970b0b8310SDavid Gibson } 4980b0b8310SDavid Gibson 4990b0b8310SDavid Gibson if (!shift) { 5000b0b8310SDavid Gibson /* nothing to do */ 5010b0b8310SDavid Gibson return H_SUCCESS; 5020b0b8310SDavid Gibson } 5030b0b8310SDavid Gibson 5040b0b8310SDavid Gibson /* start new prepare */ 5050b0b8310SDavid Gibson 506ce2918cbSDavid Gibson pending = g_new0(SpaprPendingHpt, 1); 5070b0b8310SDavid Gibson pending->shift = shift; 5080b0b8310SDavid Gibson pending->ret = H_HARDWARE; 5090b0b8310SDavid Gibson 5100b0b8310SDavid Gibson qemu_thread_create(&pending->thread, "sPAPR HPT prepare", 5110b0b8310SDavid Gibson hpt_prepare_thread, pending, QEMU_THREAD_DETACHED); 5120b0b8310SDavid Gibson 5130b0b8310SDavid Gibson spapr->pending_hpt = pending; 5140b0b8310SDavid Gibson 5150b0b8310SDavid Gibson /* In theory we could estimate the time more accurately based on 5160b0b8310SDavid Gibson * the new size, but there's not much point */ 5170b0b8310SDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 5180b0b8310SDavid Gibson } 5190b0b8310SDavid Gibson 5200b0b8310SDavid Gibson static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot) 5210b0b8310SDavid Gibson { 5220b0b8310SDavid Gibson uint8_t *addr = htab; 5230b0b8310SDavid Gibson 5240b0b8310SDavid Gibson addr += pteg * HASH_PTEG_SIZE_64; 5250b0b8310SDavid Gibson addr += slot * HASH_PTE_SIZE_64; 5260b0b8310SDavid Gibson return ldq_p(addr); 5270b0b8310SDavid Gibson } 5280b0b8310SDavid Gibson 5290b0b8310SDavid Gibson static void new_hpte_store(void *htab, uint64_t pteg, int slot, 5300b0b8310SDavid Gibson uint64_t pte0, uint64_t pte1) 5310b0b8310SDavid Gibson { 5320b0b8310SDavid Gibson uint8_t *addr = htab; 5330b0b8310SDavid Gibson 5340b0b8310SDavid Gibson addr += pteg * HASH_PTEG_SIZE_64; 5350b0b8310SDavid Gibson addr += slot * HASH_PTE_SIZE_64; 5360b0b8310SDavid Gibson 5370b0b8310SDavid Gibson stq_p(addr, pte0); 5380b0b8310SDavid Gibson stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1); 5390b0b8310SDavid Gibson } 5400b0b8310SDavid Gibson 5410b0b8310SDavid Gibson static int rehash_hpte(PowerPCCPU *cpu, 5420b0b8310SDavid Gibson const ppc_hash_pte64_t *hptes, 5430b0b8310SDavid Gibson void *old_hpt, uint64_t oldsize, 5440b0b8310SDavid Gibson void *new_hpt, uint64_t newsize, 5450b0b8310SDavid Gibson uint64_t pteg, int slot) 5460b0b8310SDavid Gibson { 5470b0b8310SDavid Gibson uint64_t old_hash_mask = (oldsize >> 7) - 1; 5480b0b8310SDavid Gibson uint64_t new_hash_mask = (newsize >> 7) - 1; 5490b0b8310SDavid Gibson target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot); 5500b0b8310SDavid Gibson target_ulong pte1; 5510b0b8310SDavid Gibson uint64_t avpn; 5520b0b8310SDavid Gibson unsigned base_pg_shift; 5530b0b8310SDavid Gibson uint64_t hash, new_pteg, replace_pte0; 5540b0b8310SDavid Gibson 5550b0b8310SDavid Gibson if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) { 5560b0b8310SDavid Gibson return H_SUCCESS; 5570b0b8310SDavid Gibson } 5580b0b8310SDavid Gibson 5590b0b8310SDavid Gibson pte1 = ppc_hash64_hpte1(cpu, hptes, slot); 5600b0b8310SDavid Gibson 5610b0b8310SDavid Gibson base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1); 5620b0b8310SDavid Gibson assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */ 5630b0b8310SDavid Gibson avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23); 5640b0b8310SDavid Gibson 5650b0b8310SDavid Gibson if (pte0 & HPTE64_V_SECONDARY) { 5660b0b8310SDavid Gibson pteg = ~pteg; 5670b0b8310SDavid Gibson } 5680b0b8310SDavid Gibson 5690b0b8310SDavid Gibson if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) { 5700b0b8310SDavid Gibson uint64_t offset, vsid; 5710b0b8310SDavid Gibson 5720b0b8310SDavid Gibson /* We only have 28 - 23 bits of offset in avpn */ 5730b0b8310SDavid Gibson offset = (avpn & 0x1f) << 23; 5740b0b8310SDavid Gibson vsid = avpn >> 5; 5750b0b8310SDavid Gibson /* We can find more bits from the pteg value */ 5760b0b8310SDavid Gibson if (base_pg_shift < 23) { 5770b0b8310SDavid Gibson offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift; 5780b0b8310SDavid Gibson } 5790b0b8310SDavid Gibson 5800b0b8310SDavid Gibson hash = vsid ^ (offset >> base_pg_shift); 5810b0b8310SDavid Gibson } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) { 5820b0b8310SDavid Gibson uint64_t offset, vsid; 5830b0b8310SDavid Gibson 5840b0b8310SDavid Gibson /* We only have 40 - 23 bits of seg_off in avpn */ 5850b0b8310SDavid Gibson offset = (avpn & 0x1ffff) << 23; 5860b0b8310SDavid Gibson vsid = avpn >> 17; 5870b0b8310SDavid Gibson if (base_pg_shift < 23) { 5880b0b8310SDavid Gibson offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask) 5890b0b8310SDavid Gibson << base_pg_shift; 5900b0b8310SDavid Gibson } 5910b0b8310SDavid Gibson 5920b0b8310SDavid Gibson hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift); 5930b0b8310SDavid Gibson } else { 5940b0b8310SDavid Gibson error_report("rehash_pte: Bad segment size in HPTE"); 59530f4b05bSDavid Gibson return H_HARDWARE; 59630f4b05bSDavid Gibson } 59730f4b05bSDavid Gibson 5980b0b8310SDavid Gibson new_pteg = hash & new_hash_mask; 5990b0b8310SDavid Gibson if (pte0 & HPTE64_V_SECONDARY) { 6000b0b8310SDavid Gibson assert(~pteg == (hash & old_hash_mask)); 6010b0b8310SDavid Gibson new_pteg = ~new_pteg; 6020b0b8310SDavid Gibson } else { 6030b0b8310SDavid Gibson assert(pteg == (hash & old_hash_mask)); 6040b0b8310SDavid Gibson } 6050b0b8310SDavid Gibson assert((oldsize != newsize) || (pteg == new_pteg)); 6060b0b8310SDavid Gibson replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot); 6070b0b8310SDavid Gibson /* 6080b0b8310SDavid Gibson * Strictly speaking, we don't need all these tests, since we only 6090b0b8310SDavid Gibson * ever rehash bolted HPTEs. We might in future handle non-bolted 6100b0b8310SDavid Gibson * HPTEs, though so make the logic correct for those cases as 6110b0b8310SDavid Gibson * well. 6120b0b8310SDavid Gibson */ 6130b0b8310SDavid Gibson if (replace_pte0 & HPTE64_V_VALID) { 6140b0b8310SDavid Gibson assert(newsize < oldsize); 6150b0b8310SDavid Gibson if (replace_pte0 & HPTE64_V_BOLTED) { 6160b0b8310SDavid Gibson if (pte0 & HPTE64_V_BOLTED) { 6170b0b8310SDavid Gibson /* Bolted collision, nothing we can do */ 6180b0b8310SDavid Gibson return H_PTEG_FULL; 6190b0b8310SDavid Gibson } else { 6200b0b8310SDavid Gibson /* Discard this hpte */ 6210b0b8310SDavid Gibson return H_SUCCESS; 6220b0b8310SDavid Gibson } 6230b0b8310SDavid Gibson } 6240b0b8310SDavid Gibson } 6250b0b8310SDavid Gibson 6260b0b8310SDavid Gibson new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1); 6270b0b8310SDavid Gibson return H_SUCCESS; 6280b0b8310SDavid Gibson } 6290b0b8310SDavid Gibson 6300b0b8310SDavid Gibson static int rehash_hpt(PowerPCCPU *cpu, 6310b0b8310SDavid Gibson void *old_hpt, uint64_t oldsize, 6320b0b8310SDavid Gibson void *new_hpt, uint64_t newsize) 6330b0b8310SDavid Gibson { 6340b0b8310SDavid Gibson uint64_t n_ptegs = oldsize >> 7; 6350b0b8310SDavid Gibson uint64_t pteg; 6360b0b8310SDavid Gibson int slot; 6370b0b8310SDavid Gibson int rc; 6380b0b8310SDavid Gibson 6390b0b8310SDavid Gibson for (pteg = 0; pteg < n_ptegs; pteg++) { 6400b0b8310SDavid Gibson hwaddr ptex = pteg * HPTES_PER_GROUP; 6410b0b8310SDavid Gibson const ppc_hash_pte64_t *hptes 6420b0b8310SDavid Gibson = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 6430b0b8310SDavid Gibson 6440b0b8310SDavid Gibson if (!hptes) { 6450b0b8310SDavid Gibson return H_HARDWARE; 6460b0b8310SDavid Gibson } 6470b0b8310SDavid Gibson 6480b0b8310SDavid Gibson for (slot = 0; slot < HPTES_PER_GROUP; slot++) { 6490b0b8310SDavid Gibson rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize, 6500b0b8310SDavid Gibson pteg, slot); 6510b0b8310SDavid Gibson if (rc != H_SUCCESS) { 6520b0b8310SDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 6530b0b8310SDavid Gibson return rc; 6540b0b8310SDavid Gibson } 6550b0b8310SDavid Gibson } 6560b0b8310SDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 6570b0b8310SDavid Gibson } 6580b0b8310SDavid Gibson 6590b0b8310SDavid Gibson return H_SUCCESS; 6600b0b8310SDavid Gibson } 6610b0b8310SDavid Gibson 6621ec26c75SGreg Kurz static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 6631ec26c75SGreg Kurz { 6641ec26c75SGreg Kurz int ret; 6651ec26c75SGreg Kurz 6661ec26c75SGreg Kurz cpu_synchronize_state(cs); 6671ec26c75SGreg Kurz 6681ec26c75SGreg Kurz ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 6691ec26c75SGreg Kurz if (ret < 0) { 6701ec26c75SGreg Kurz error_report("failed to push sregs to KVM: %s", strerror(-ret)); 6711ec26c75SGreg Kurz exit(1); 6721ec26c75SGreg Kurz } 6731ec26c75SGreg Kurz } 6741ec26c75SGreg Kurz 675ce2918cbSDavid Gibson static void push_sregs_to_kvm_pr(SpaprMachineState *spapr) 6761ec26c75SGreg Kurz { 6771ec26c75SGreg Kurz CPUState *cs; 6781ec26c75SGreg Kurz 6791ec26c75SGreg Kurz /* 6801ec26c75SGreg Kurz * This is a hack for the benefit of KVM PR - it abuses the SDR1 6811ec26c75SGreg Kurz * slot in kvm_sregs to communicate the userspace address of the 6821ec26c75SGreg Kurz * HPT 6831ec26c75SGreg Kurz */ 6841ec26c75SGreg Kurz if (!kvm_enabled() || !spapr->htab) { 6851ec26c75SGreg Kurz return; 6861ec26c75SGreg Kurz } 6871ec26c75SGreg Kurz 6881ec26c75SGreg Kurz CPU_FOREACH(cs) { 6891ec26c75SGreg Kurz run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 6901ec26c75SGreg Kurz } 6911ec26c75SGreg Kurz } 6921ec26c75SGreg Kurz 69330f4b05bSDavid Gibson static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 694ce2918cbSDavid Gibson SpaprMachineState *spapr, 69530f4b05bSDavid Gibson target_ulong opcode, 69630f4b05bSDavid Gibson target_ulong *args) 69730f4b05bSDavid Gibson { 69830f4b05bSDavid Gibson target_ulong flags = args[0]; 69930f4b05bSDavid Gibson target_ulong shift = args[1]; 700ce2918cbSDavid Gibson SpaprPendingHpt *pending = spapr->pending_hpt; 7010b0b8310SDavid Gibson int rc; 7020b0b8310SDavid Gibson size_t newsize; 70330f4b05bSDavid Gibson 70430f4b05bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 70530f4b05bSDavid Gibson return H_AUTHORITY; 70630f4b05bSDavid Gibson } 70730f4b05bSDavid Gibson 70894789567SDaniel Henrique Barboza if (!spapr->htab_shift) { 70994789567SDaniel Henrique Barboza /* Radix guest, no HPT */ 71094789567SDaniel Henrique Barboza return H_NOT_AVAILABLE; 71194789567SDaniel Henrique Barboza } 71294789567SDaniel Henrique Barboza 71330f4b05bSDavid Gibson trace_spapr_h_resize_hpt_commit(flags, shift); 7140b0b8310SDavid Gibson 715b55d295eSDavid Gibson rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 716b55d295eSDavid Gibson if (rc != -ENOSYS) { 71794789567SDaniel Henrique Barboza rc = resize_hpt_convert_rc(rc); 71894789567SDaniel Henrique Barboza if (rc == H_SUCCESS) { 71994789567SDaniel Henrique Barboza /* Need to set the new htab_shift in the machine state */ 72094789567SDaniel Henrique Barboza spapr->htab_shift = shift; 72194789567SDaniel Henrique Barboza } 72294789567SDaniel Henrique Barboza return rc; 723b55d295eSDavid Gibson } 724b55d295eSDavid Gibson 7250b0b8310SDavid Gibson if (flags != 0) { 7260b0b8310SDavid Gibson return H_PARAMETER; 7270b0b8310SDavid Gibson } 7280b0b8310SDavid Gibson 7290b0b8310SDavid Gibson if (!pending || (pending->shift != shift)) { 7300b0b8310SDavid Gibson /* no matching prepare */ 7310b0b8310SDavid Gibson return H_CLOSED; 7320b0b8310SDavid Gibson } 7330b0b8310SDavid Gibson 7340b0b8310SDavid Gibson if (!pending->complete) { 7350b0b8310SDavid Gibson /* prepare has not completed */ 7360b0b8310SDavid Gibson return H_BUSY; 7370b0b8310SDavid Gibson } 7380b0b8310SDavid Gibson 7390b0b8310SDavid Gibson /* Shouldn't have got past PREPARE without an HPT */ 7400b0b8310SDavid Gibson g_assert(spapr->htab_shift); 7410b0b8310SDavid Gibson 7420b0b8310SDavid Gibson newsize = 1ULL << pending->shift; 7430b0b8310SDavid Gibson rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr), 7440b0b8310SDavid Gibson pending->hpt, newsize); 7450b0b8310SDavid Gibson if (rc == H_SUCCESS) { 7460b0b8310SDavid Gibson qemu_vfree(spapr->htab); 7470b0b8310SDavid Gibson spapr->htab = pending->hpt; 7480b0b8310SDavid Gibson spapr->htab_shift = pending->shift; 7490b0b8310SDavid Gibson 7501ec26c75SGreg Kurz push_sregs_to_kvm_pr(spapr); 751b55d295eSDavid Gibson 7520b0b8310SDavid Gibson pending->hpt = NULL; /* so it's not free()d */ 7530b0b8310SDavid Gibson } 7540b0b8310SDavid Gibson 7550b0b8310SDavid Gibson /* Clean up */ 7560b0b8310SDavid Gibson spapr->pending_hpt = NULL; 7570b0b8310SDavid Gibson free_pending_hpt(pending); 7580b0b8310SDavid Gibson 7590b0b8310SDavid Gibson return rc; 76030f4b05bSDavid Gibson } 76130f4b05bSDavid Gibson 762ce2918cbSDavid Gibson static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, 763423576f7SThomas Huth target_ulong opcode, target_ulong *args) 764423576f7SThomas Huth { 765423576f7SThomas Huth cpu_synchronize_state(CPU(cpu)); 766423576f7SThomas Huth cpu->env.spr[SPR_SPRG0] = args[0]; 767423576f7SThomas Huth 768423576f7SThomas Huth return H_SUCCESS; 769423576f7SThomas Huth } 770423576f7SThomas Huth 771ce2918cbSDavid Gibson static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 7729f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 7739f64bd8aSPaolo Bonzini { 774af08a58fSThomas Huth if (!has_spr(cpu, SPR_DABR)) { 775af08a58fSThomas Huth return H_HARDWARE; /* DABR register not available */ 776af08a58fSThomas Huth } 777af08a58fSThomas Huth cpu_synchronize_state(CPU(cpu)); 778af08a58fSThomas Huth 779af08a58fSThomas Huth if (has_spr(cpu, SPR_DABRX)) { 780af08a58fSThomas Huth cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 781af08a58fSThomas Huth } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 782af08a58fSThomas Huth return H_RESERVED_DABR; 783af08a58fSThomas Huth } 784af08a58fSThomas Huth 785af08a58fSThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 786af08a58fSThomas Huth return H_SUCCESS; 7879f64bd8aSPaolo Bonzini } 7889f64bd8aSPaolo Bonzini 789ce2918cbSDavid Gibson static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 790e49ff266SThomas Huth target_ulong opcode, target_ulong *args) 791e49ff266SThomas Huth { 792e49ff266SThomas Huth target_ulong dabrx = args[1]; 793e49ff266SThomas Huth 794e49ff266SThomas Huth if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { 795e49ff266SThomas Huth return H_HARDWARE; 796e49ff266SThomas Huth } 797e49ff266SThomas Huth 798e49ff266SThomas Huth if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 799e49ff266SThomas Huth || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 800e49ff266SThomas Huth return H_PARAMETER; 801e49ff266SThomas Huth } 802e49ff266SThomas Huth 803e49ff266SThomas Huth cpu_synchronize_state(CPU(cpu)); 804e49ff266SThomas Huth cpu->env.spr[SPR_DABRX] = dabrx; 805e49ff266SThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 806e49ff266SThomas Huth 807e49ff266SThomas Huth return H_SUCCESS; 808e49ff266SThomas Huth } 809e49ff266SThomas Huth 810ce2918cbSDavid Gibson static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, 8113240dd9aSThomas Huth target_ulong opcode, target_ulong *args) 8123240dd9aSThomas Huth { 8133240dd9aSThomas Huth target_ulong flags = args[0]; 8143240dd9aSThomas Huth hwaddr dst = args[1]; 8153240dd9aSThomas Huth hwaddr src = args[2]; 8163240dd9aSThomas Huth hwaddr len = TARGET_PAGE_SIZE; 8173240dd9aSThomas Huth uint8_t *pdst, *psrc; 8183240dd9aSThomas Huth target_long ret = H_SUCCESS; 8193240dd9aSThomas Huth 8203240dd9aSThomas Huth if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 8213240dd9aSThomas Huth | H_COPY_PAGE | H_ZERO_PAGE)) { 8223240dd9aSThomas Huth qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 8233240dd9aSThomas Huth flags); 8243240dd9aSThomas Huth return H_PARAMETER; 8253240dd9aSThomas Huth } 8263240dd9aSThomas Huth 8273240dd9aSThomas Huth /* Map-in destination */ 8283240dd9aSThomas Huth if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 8293240dd9aSThomas Huth return H_PARAMETER; 8303240dd9aSThomas Huth } 8313240dd9aSThomas Huth pdst = cpu_physical_memory_map(dst, &len, 1); 8323240dd9aSThomas Huth if (!pdst || len != TARGET_PAGE_SIZE) { 8333240dd9aSThomas Huth return H_PARAMETER; 8343240dd9aSThomas Huth } 8353240dd9aSThomas Huth 8363240dd9aSThomas Huth if (flags & H_COPY_PAGE) { 8373240dd9aSThomas Huth /* Map-in source, copy to destination, and unmap source again */ 8383240dd9aSThomas Huth if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 8393240dd9aSThomas Huth ret = H_PARAMETER; 8403240dd9aSThomas Huth goto unmap_out; 8413240dd9aSThomas Huth } 8423240dd9aSThomas Huth psrc = cpu_physical_memory_map(src, &len, 0); 8433240dd9aSThomas Huth if (!psrc || len != TARGET_PAGE_SIZE) { 8443240dd9aSThomas Huth ret = H_PARAMETER; 8453240dd9aSThomas Huth goto unmap_out; 8463240dd9aSThomas Huth } 8473240dd9aSThomas Huth memcpy(pdst, psrc, len); 8483240dd9aSThomas Huth cpu_physical_memory_unmap(psrc, len, 0, len); 8493240dd9aSThomas Huth } else if (flags & H_ZERO_PAGE) { 8503240dd9aSThomas Huth memset(pdst, 0, len); /* Just clear the destination page */ 8513240dd9aSThomas Huth } 8523240dd9aSThomas Huth 8533240dd9aSThomas Huth if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 8543240dd9aSThomas Huth kvmppc_dcbst_range(cpu, pdst, len); 8553240dd9aSThomas Huth } 8563240dd9aSThomas Huth if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 8573240dd9aSThomas Huth if (kvm_enabled()) { 8583240dd9aSThomas Huth kvmppc_icbi_range(cpu, pdst, len); 8593240dd9aSThomas Huth } else { 8603240dd9aSThomas Huth tb_flush(CPU(cpu)); 8613240dd9aSThomas Huth } 8623240dd9aSThomas Huth } 8633240dd9aSThomas Huth 8643240dd9aSThomas Huth unmap_out: 8653240dd9aSThomas Huth cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 8663240dd9aSThomas Huth return ret; 8673240dd9aSThomas Huth } 8683240dd9aSThomas Huth 8699f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 8709f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 8719f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 8729f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 8739f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 8749f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 8759f64bd8aSPaolo Bonzini 8769f64bd8aSPaolo Bonzini #define VPA_MIN_SIZE 640 8779f64bd8aSPaolo Bonzini #define VPA_SIZE_OFFSET 0x4 8789f64bd8aSPaolo Bonzini #define VPA_SHARED_PROC_OFFSET 0x9 8799f64bd8aSPaolo Bonzini #define VPA_SHARED_PROC_VAL 0x2 8809f64bd8aSPaolo Bonzini 8817388efafSDavid Gibson static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) 8829f64bd8aSPaolo Bonzini { 8837388efafSDavid Gibson CPUState *cs = CPU(cpu); 8847388efafSDavid Gibson CPUPPCState *env = &cpu->env; 885ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 8869f64bd8aSPaolo Bonzini uint16_t size; 8879f64bd8aSPaolo Bonzini uint8_t tmp; 8889f64bd8aSPaolo Bonzini 8899f64bd8aSPaolo Bonzini if (vpa == 0) { 8909f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 8919f64bd8aSPaolo Bonzini return H_HARDWARE; 8929f64bd8aSPaolo Bonzini } 8939f64bd8aSPaolo Bonzini 8949f64bd8aSPaolo Bonzini if (vpa % env->dcache_line_size) { 8959f64bd8aSPaolo Bonzini return H_PARAMETER; 8969f64bd8aSPaolo Bonzini } 8979f64bd8aSPaolo Bonzini /* FIXME: bounds check the address */ 8989f64bd8aSPaolo Bonzini 89941701aa4SEdgar E. Iglesias size = lduw_be_phys(cs->as, vpa + 0x4); 9009f64bd8aSPaolo Bonzini 9019f64bd8aSPaolo Bonzini if (size < VPA_MIN_SIZE) { 9029f64bd8aSPaolo Bonzini return H_PARAMETER; 9039f64bd8aSPaolo Bonzini } 9049f64bd8aSPaolo Bonzini 9059f64bd8aSPaolo Bonzini /* VPA is not allowed to cross a page boundary */ 9069f64bd8aSPaolo Bonzini if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 9079f64bd8aSPaolo Bonzini return H_PARAMETER; 9089f64bd8aSPaolo Bonzini } 9099f64bd8aSPaolo Bonzini 9107388efafSDavid Gibson spapr_cpu->vpa_addr = vpa; 9119f64bd8aSPaolo Bonzini 9127388efafSDavid Gibson tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET); 9139f64bd8aSPaolo Bonzini tmp |= VPA_SHARED_PROC_VAL; 9147388efafSDavid Gibson stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 9159f64bd8aSPaolo Bonzini 9169f64bd8aSPaolo Bonzini return H_SUCCESS; 9179f64bd8aSPaolo Bonzini } 9189f64bd8aSPaolo Bonzini 9197388efafSDavid Gibson static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) 9209f64bd8aSPaolo Bonzini { 921ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 9227388efafSDavid Gibson 9237388efafSDavid Gibson if (spapr_cpu->slb_shadow_addr) { 9249f64bd8aSPaolo Bonzini return H_RESOURCE; 9259f64bd8aSPaolo Bonzini } 9269f64bd8aSPaolo Bonzini 9277388efafSDavid Gibson if (spapr_cpu->dtl_addr) { 9289f64bd8aSPaolo Bonzini return H_RESOURCE; 9299f64bd8aSPaolo Bonzini } 9309f64bd8aSPaolo Bonzini 9317388efafSDavid Gibson spapr_cpu->vpa_addr = 0; 9329f64bd8aSPaolo Bonzini return H_SUCCESS; 9339f64bd8aSPaolo Bonzini } 9349f64bd8aSPaolo Bonzini 9357388efafSDavid Gibson static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 9369f64bd8aSPaolo Bonzini { 937ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 9389f64bd8aSPaolo Bonzini uint32_t size; 9399f64bd8aSPaolo Bonzini 9409f64bd8aSPaolo Bonzini if (addr == 0) { 9419f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 9429f64bd8aSPaolo Bonzini return H_HARDWARE; 9439f64bd8aSPaolo Bonzini } 9449f64bd8aSPaolo Bonzini 9457388efafSDavid Gibson size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 9469f64bd8aSPaolo Bonzini if (size < 0x8) { 9479f64bd8aSPaolo Bonzini return H_PARAMETER; 9489f64bd8aSPaolo Bonzini } 9499f64bd8aSPaolo Bonzini 9509f64bd8aSPaolo Bonzini if ((addr / 4096) != ((addr + size - 1) / 4096)) { 9519f64bd8aSPaolo Bonzini return H_PARAMETER; 9529f64bd8aSPaolo Bonzini } 9539f64bd8aSPaolo Bonzini 9547388efafSDavid Gibson if (!spapr_cpu->vpa_addr) { 9559f64bd8aSPaolo Bonzini return H_RESOURCE; 9569f64bd8aSPaolo Bonzini } 9579f64bd8aSPaolo Bonzini 9587388efafSDavid Gibson spapr_cpu->slb_shadow_addr = addr; 9597388efafSDavid Gibson spapr_cpu->slb_shadow_size = size; 9609f64bd8aSPaolo Bonzini 9619f64bd8aSPaolo Bonzini return H_SUCCESS; 9629f64bd8aSPaolo Bonzini } 9639f64bd8aSPaolo Bonzini 9647388efafSDavid Gibson static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 9659f64bd8aSPaolo Bonzini { 966ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 9677388efafSDavid Gibson 9687388efafSDavid Gibson spapr_cpu->slb_shadow_addr = 0; 9697388efafSDavid Gibson spapr_cpu->slb_shadow_size = 0; 9709f64bd8aSPaolo Bonzini return H_SUCCESS; 9719f64bd8aSPaolo Bonzini } 9729f64bd8aSPaolo Bonzini 9737388efafSDavid Gibson static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) 9749f64bd8aSPaolo Bonzini { 975ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 9769f64bd8aSPaolo Bonzini uint32_t size; 9779f64bd8aSPaolo Bonzini 9789f64bd8aSPaolo Bonzini if (addr == 0) { 9799f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with DTL at logical 0\n"); 9809f64bd8aSPaolo Bonzini return H_HARDWARE; 9819f64bd8aSPaolo Bonzini } 9829f64bd8aSPaolo Bonzini 9837388efafSDavid Gibson size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 9849f64bd8aSPaolo Bonzini 9859f64bd8aSPaolo Bonzini if (size < 48) { 9869f64bd8aSPaolo Bonzini return H_PARAMETER; 9879f64bd8aSPaolo Bonzini } 9889f64bd8aSPaolo Bonzini 9897388efafSDavid Gibson if (!spapr_cpu->vpa_addr) { 9909f64bd8aSPaolo Bonzini return H_RESOURCE; 9919f64bd8aSPaolo Bonzini } 9929f64bd8aSPaolo Bonzini 9937388efafSDavid Gibson spapr_cpu->dtl_addr = addr; 9947388efafSDavid Gibson spapr_cpu->dtl_size = size; 9959f64bd8aSPaolo Bonzini 9969f64bd8aSPaolo Bonzini return H_SUCCESS; 9979f64bd8aSPaolo Bonzini } 9989f64bd8aSPaolo Bonzini 9997388efafSDavid Gibson static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) 10009f64bd8aSPaolo Bonzini { 1001ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 10027388efafSDavid Gibson 10037388efafSDavid Gibson spapr_cpu->dtl_addr = 0; 10047388efafSDavid Gibson spapr_cpu->dtl_size = 0; 10059f64bd8aSPaolo Bonzini 10069f64bd8aSPaolo Bonzini return H_SUCCESS; 10079f64bd8aSPaolo Bonzini } 10089f64bd8aSPaolo Bonzini 1009ce2918cbSDavid Gibson static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr, 10109f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 10119f64bd8aSPaolo Bonzini { 10129f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 10139f64bd8aSPaolo Bonzini target_ulong procno = args[1]; 10149f64bd8aSPaolo Bonzini target_ulong vpa = args[2]; 10159f64bd8aSPaolo Bonzini target_ulong ret = H_PARAMETER; 10160f20ba62SAlexey Kardashevskiy PowerPCCPU *tcpu; 10179f64bd8aSPaolo Bonzini 10182e886fb3SSam Bobroff tcpu = spapr_find_cpu(procno); 10199f64bd8aSPaolo Bonzini if (!tcpu) { 10209f64bd8aSPaolo Bonzini return H_PARAMETER; 10219f64bd8aSPaolo Bonzini } 10229f64bd8aSPaolo Bonzini 10239f64bd8aSPaolo Bonzini switch (flags) { 10249f64bd8aSPaolo Bonzini case FLAGS_REGISTER_VPA: 10257388efafSDavid Gibson ret = register_vpa(tcpu, vpa); 10269f64bd8aSPaolo Bonzini break; 10279f64bd8aSPaolo Bonzini 10289f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_VPA: 10297388efafSDavid Gibson ret = deregister_vpa(tcpu, vpa); 10309f64bd8aSPaolo Bonzini break; 10319f64bd8aSPaolo Bonzini 10329f64bd8aSPaolo Bonzini case FLAGS_REGISTER_SLBSHADOW: 10337388efafSDavid Gibson ret = register_slb_shadow(tcpu, vpa); 10349f64bd8aSPaolo Bonzini break; 10359f64bd8aSPaolo Bonzini 10369f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_SLBSHADOW: 10377388efafSDavid Gibson ret = deregister_slb_shadow(tcpu, vpa); 10389f64bd8aSPaolo Bonzini break; 10399f64bd8aSPaolo Bonzini 10409f64bd8aSPaolo Bonzini case FLAGS_REGISTER_DTL: 10417388efafSDavid Gibson ret = register_dtl(tcpu, vpa); 10429f64bd8aSPaolo Bonzini break; 10439f64bd8aSPaolo Bonzini 10449f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_DTL: 10457388efafSDavid Gibson ret = deregister_dtl(tcpu, vpa); 10469f64bd8aSPaolo Bonzini break; 10479f64bd8aSPaolo Bonzini } 10489f64bd8aSPaolo Bonzini 10499f64bd8aSPaolo Bonzini return ret; 10509f64bd8aSPaolo Bonzini } 10519f64bd8aSPaolo Bonzini 1052ce2918cbSDavid Gibson static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, 10539f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 10549f64bd8aSPaolo Bonzini { 10559f64bd8aSPaolo Bonzini CPUPPCState *env = &cpu->env; 10569f64bd8aSPaolo Bonzini CPUState *cs = CPU(cpu); 10579f64bd8aSPaolo Bonzini 10589f64bd8aSPaolo Bonzini env->msr |= (1ULL << MSR_EE); 10599f64bd8aSPaolo Bonzini hreg_compute_hflags(env); 10609f64bd8aSPaolo Bonzini if (!cpu_has_work(cs)) { 1061259186a7SAndreas Färber cs->halted = 1; 106227103424SAndreas Färber cs->exception_index = EXCP_HLT; 10639f64bd8aSPaolo Bonzini cs->exit_request = 1; 10649f64bd8aSPaolo Bonzini } 10659f64bd8aSPaolo Bonzini return H_SUCCESS; 10669f64bd8aSPaolo Bonzini } 10679f64bd8aSPaolo Bonzini 1068ce2918cbSDavid Gibson static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, 10699f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 10709f64bd8aSPaolo Bonzini { 10719f64bd8aSPaolo Bonzini target_ulong rtas_r3 = args[0]; 10724fe822e0SAlexey Kardashevskiy uint32_t token = rtas_ld(rtas_r3, 0); 10734fe822e0SAlexey Kardashevskiy uint32_t nargs = rtas_ld(rtas_r3, 1); 10744fe822e0SAlexey Kardashevskiy uint32_t nret = rtas_ld(rtas_r3, 2); 10759f64bd8aSPaolo Bonzini 1076210b580bSAnthony Liguori return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 10779f64bd8aSPaolo Bonzini nret, rtas_r3 + 12 + 4*nargs); 10789f64bd8aSPaolo Bonzini } 10799f64bd8aSPaolo Bonzini 1080ce2918cbSDavid Gibson static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr, 10819f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 10829f64bd8aSPaolo Bonzini { 1083fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 10849f64bd8aSPaolo Bonzini target_ulong size = args[0]; 10859f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 10869f64bd8aSPaolo Bonzini 10879f64bd8aSPaolo Bonzini switch (size) { 10889f64bd8aSPaolo Bonzini case 1: 10892c17449bSEdgar E. Iglesias args[0] = ldub_phys(cs->as, addr); 10909f64bd8aSPaolo Bonzini return H_SUCCESS; 10919f64bd8aSPaolo Bonzini case 2: 109241701aa4SEdgar E. Iglesias args[0] = lduw_phys(cs->as, addr); 10939f64bd8aSPaolo Bonzini return H_SUCCESS; 10949f64bd8aSPaolo Bonzini case 4: 1095fdfba1a2SEdgar E. Iglesias args[0] = ldl_phys(cs->as, addr); 10969f64bd8aSPaolo Bonzini return H_SUCCESS; 10979f64bd8aSPaolo Bonzini case 8: 10982c17449bSEdgar E. Iglesias args[0] = ldq_phys(cs->as, addr); 10999f64bd8aSPaolo Bonzini return H_SUCCESS; 11009f64bd8aSPaolo Bonzini } 11019f64bd8aSPaolo Bonzini return H_PARAMETER; 11029f64bd8aSPaolo Bonzini } 11039f64bd8aSPaolo Bonzini 1104ce2918cbSDavid Gibson static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr, 11059f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 11069f64bd8aSPaolo Bonzini { 1107f606604fSEdgar E. Iglesias CPUState *cs = CPU(cpu); 1108f606604fSEdgar E. Iglesias 11099f64bd8aSPaolo Bonzini target_ulong size = args[0]; 11109f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 11119f64bd8aSPaolo Bonzini target_ulong val = args[2]; 11129f64bd8aSPaolo Bonzini 11139f64bd8aSPaolo Bonzini switch (size) { 11149f64bd8aSPaolo Bonzini case 1: 1115db3be60dSEdgar E. Iglesias stb_phys(cs->as, addr, val); 11169f64bd8aSPaolo Bonzini return H_SUCCESS; 11179f64bd8aSPaolo Bonzini case 2: 11185ce5944dSEdgar E. Iglesias stw_phys(cs->as, addr, val); 11199f64bd8aSPaolo Bonzini return H_SUCCESS; 11209f64bd8aSPaolo Bonzini case 4: 1121ab1da857SEdgar E. Iglesias stl_phys(cs->as, addr, val); 11229f64bd8aSPaolo Bonzini return H_SUCCESS; 11239f64bd8aSPaolo Bonzini case 8: 1124f606604fSEdgar E. Iglesias stq_phys(cs->as, addr, val); 11259f64bd8aSPaolo Bonzini return H_SUCCESS; 11269f64bd8aSPaolo Bonzini } 11279f64bd8aSPaolo Bonzini return H_PARAMETER; 11289f64bd8aSPaolo Bonzini } 11299f64bd8aSPaolo Bonzini 1130ce2918cbSDavid Gibson static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr, 11319f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 11329f64bd8aSPaolo Bonzini { 1133fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 1134fdfba1a2SEdgar E. Iglesias 11359f64bd8aSPaolo Bonzini target_ulong dst = args[0]; /* Destination address */ 11369f64bd8aSPaolo Bonzini target_ulong src = args[1]; /* Source address */ 11379f64bd8aSPaolo Bonzini target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 11389f64bd8aSPaolo Bonzini target_ulong count = args[3]; /* Element count */ 11399f64bd8aSPaolo Bonzini target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 11409f64bd8aSPaolo Bonzini uint64_t tmp; 11419f64bd8aSPaolo Bonzini unsigned int mask = (1 << esize) - 1; 11429f64bd8aSPaolo Bonzini int step = 1 << esize; 11439f64bd8aSPaolo Bonzini 11449f64bd8aSPaolo Bonzini if (count > 0x80000000) { 11459f64bd8aSPaolo Bonzini return H_PARAMETER; 11469f64bd8aSPaolo Bonzini } 11479f64bd8aSPaolo Bonzini 11489f64bd8aSPaolo Bonzini if ((dst & mask) || (src & mask) || (op > 1)) { 11499f64bd8aSPaolo Bonzini return H_PARAMETER; 11509f64bd8aSPaolo Bonzini } 11519f64bd8aSPaolo Bonzini 11529f64bd8aSPaolo Bonzini if (dst >= src && dst < (src + (count << esize))) { 11539f64bd8aSPaolo Bonzini dst = dst + ((count - 1) << esize); 11549f64bd8aSPaolo Bonzini src = src + ((count - 1) << esize); 11559f64bd8aSPaolo Bonzini step = -step; 11569f64bd8aSPaolo Bonzini } 11579f64bd8aSPaolo Bonzini 11589f64bd8aSPaolo Bonzini while (count--) { 11599f64bd8aSPaolo Bonzini switch (esize) { 11609f64bd8aSPaolo Bonzini case 0: 11612c17449bSEdgar E. Iglesias tmp = ldub_phys(cs->as, src); 11629f64bd8aSPaolo Bonzini break; 11639f64bd8aSPaolo Bonzini case 1: 116441701aa4SEdgar E. Iglesias tmp = lduw_phys(cs->as, src); 11659f64bd8aSPaolo Bonzini break; 11669f64bd8aSPaolo Bonzini case 2: 1167fdfba1a2SEdgar E. Iglesias tmp = ldl_phys(cs->as, src); 11689f64bd8aSPaolo Bonzini break; 11699f64bd8aSPaolo Bonzini case 3: 11702c17449bSEdgar E. Iglesias tmp = ldq_phys(cs->as, src); 11719f64bd8aSPaolo Bonzini break; 11729f64bd8aSPaolo Bonzini default: 11739f64bd8aSPaolo Bonzini return H_PARAMETER; 11749f64bd8aSPaolo Bonzini } 11759f64bd8aSPaolo Bonzini if (op == 1) { 11769f64bd8aSPaolo Bonzini tmp = ~tmp; 11779f64bd8aSPaolo Bonzini } 11789f64bd8aSPaolo Bonzini switch (esize) { 11799f64bd8aSPaolo Bonzini case 0: 1180db3be60dSEdgar E. Iglesias stb_phys(cs->as, dst, tmp); 11819f64bd8aSPaolo Bonzini break; 11829f64bd8aSPaolo Bonzini case 1: 11835ce5944dSEdgar E. Iglesias stw_phys(cs->as, dst, tmp); 11849f64bd8aSPaolo Bonzini break; 11859f64bd8aSPaolo Bonzini case 2: 1186ab1da857SEdgar E. Iglesias stl_phys(cs->as, dst, tmp); 11879f64bd8aSPaolo Bonzini break; 11889f64bd8aSPaolo Bonzini case 3: 1189f606604fSEdgar E. Iglesias stq_phys(cs->as, dst, tmp); 11909f64bd8aSPaolo Bonzini break; 11919f64bd8aSPaolo Bonzini } 11929f64bd8aSPaolo Bonzini dst = dst + step; 11939f64bd8aSPaolo Bonzini src = src + step; 11949f64bd8aSPaolo Bonzini } 11959f64bd8aSPaolo Bonzini 11969f64bd8aSPaolo Bonzini return H_SUCCESS; 11979f64bd8aSPaolo Bonzini } 11989f64bd8aSPaolo Bonzini 1199ce2918cbSDavid Gibson static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr, 12009f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 12019f64bd8aSPaolo Bonzini { 12029f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 12039f64bd8aSPaolo Bonzini return H_SUCCESS; 12049f64bd8aSPaolo Bonzini } 12059f64bd8aSPaolo Bonzini 1206ce2918cbSDavid Gibson static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, 12079f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 12089f64bd8aSPaolo Bonzini { 12099f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 12109f64bd8aSPaolo Bonzini return H_SUCCESS; 12119f64bd8aSPaolo Bonzini } 12129f64bd8aSPaolo Bonzini 12137d0cd464SPeter Maydell static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 1214c4015bbdSAlexey Kardashevskiy target_ulong mflags, 1215c4015bbdSAlexey Kardashevskiy target_ulong value1, 1216c4015bbdSAlexey Kardashevskiy target_ulong value2) 121742561bf2SAnton Blanchard { 121842561bf2SAnton Blanchard if (value1) { 1219c4015bbdSAlexey Kardashevskiy return H_P3; 122042561bf2SAnton Blanchard } 122142561bf2SAnton Blanchard if (value2) { 1222c4015bbdSAlexey Kardashevskiy return H_P4; 122342561bf2SAnton Blanchard } 1224c4015bbdSAlexey Kardashevskiy 122542561bf2SAnton Blanchard switch (mflags) { 122642561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_BIG: 122700fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(0, LPCR_ILE); 1228eefaccc0SDavid Gibson spapr_pci_switch_vga(true); 1229c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 123042561bf2SAnton Blanchard 123142561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_LITTLE: 123200fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); 1233eefaccc0SDavid Gibson spapr_pci_switch_vga(false); 1234c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 1235c4015bbdSAlexey Kardashevskiy } 1236c4015bbdSAlexey Kardashevskiy 1237c4015bbdSAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 1238c4015bbdSAlexey Kardashevskiy } 1239c4015bbdSAlexey Kardashevskiy 12407d0cd464SPeter Maydell static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 1241d5ac4f54SAlexey Kardashevskiy target_ulong mflags, 1242d5ac4f54SAlexey Kardashevskiy target_ulong value1, 1243d5ac4f54SAlexey Kardashevskiy target_ulong value2) 1244d5ac4f54SAlexey Kardashevskiy { 1245d5ac4f54SAlexey Kardashevskiy PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 1246d5ac4f54SAlexey Kardashevskiy 1247d5ac4f54SAlexey Kardashevskiy if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 1248d5ac4f54SAlexey Kardashevskiy return H_P2; 1249d5ac4f54SAlexey Kardashevskiy } 1250d5ac4f54SAlexey Kardashevskiy if (value1) { 1251d5ac4f54SAlexey Kardashevskiy return H_P3; 1252d5ac4f54SAlexey Kardashevskiy } 1253d5ac4f54SAlexey Kardashevskiy if (value2) { 1254d5ac4f54SAlexey Kardashevskiy return H_P4; 1255d5ac4f54SAlexey Kardashevskiy } 1256d5ac4f54SAlexey Kardashevskiy 12575c94b2a5SCédric Le Goater if (mflags == AIL_RESERVED) { 1258d5ac4f54SAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 1259d5ac4f54SAlexey Kardashevskiy } 1260d5ac4f54SAlexey Kardashevskiy 126100fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); 1262d5ac4f54SAlexey Kardashevskiy 1263d5ac4f54SAlexey Kardashevskiy return H_SUCCESS; 1264d5ac4f54SAlexey Kardashevskiy } 1265d5ac4f54SAlexey Kardashevskiy 1266ce2918cbSDavid Gibson static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, 1267c4015bbdSAlexey Kardashevskiy target_ulong opcode, target_ulong *args) 1268c4015bbdSAlexey Kardashevskiy { 1269c4015bbdSAlexey Kardashevskiy target_ulong resource = args[1]; 1270c4015bbdSAlexey Kardashevskiy target_ulong ret = H_P2; 1271c4015bbdSAlexey Kardashevskiy 1272c4015bbdSAlexey Kardashevskiy switch (resource) { 1273c4015bbdSAlexey Kardashevskiy case H_SET_MODE_RESOURCE_LE: 12747d0cd464SPeter Maydell ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); 127542561bf2SAnton Blanchard break; 1276d5ac4f54SAlexey Kardashevskiy case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 12777d0cd464SPeter Maydell ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 1278d5ac4f54SAlexey Kardashevskiy args[2], args[3]); 1279d5ac4f54SAlexey Kardashevskiy break; 128042561bf2SAnton Blanchard } 128142561bf2SAnton Blanchard 128242561bf2SAnton Blanchard return ret; 128342561bf2SAnton Blanchard } 128442561bf2SAnton Blanchard 1285ce2918cbSDavid Gibson static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, 1286d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 1287d77a98b0SSuraj Jitindar Singh { 1288d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1289d77a98b0SSuraj Jitindar Singh opcode, " (H_CLEAN_SLB)"); 1290d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 1291d77a98b0SSuraj Jitindar Singh } 1292d77a98b0SSuraj Jitindar Singh 1293ce2918cbSDavid Gibson static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr, 1294d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 1295d77a98b0SSuraj Jitindar Singh { 1296d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1297d77a98b0SSuraj Jitindar Singh opcode, " (H_INVALIDATE_PID)"); 1298d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 1299d77a98b0SSuraj Jitindar Singh } 1300d77a98b0SSuraj Jitindar Singh 1301ce2918cbSDavid Gibson static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, 1302b4db5413SSuraj Jitindar Singh uint64_t patbe_old, uint64_t patbe_new) 1303b4db5413SSuraj Jitindar Singh { 1304b4db5413SSuraj Jitindar Singh /* 1305b4db5413SSuraj Jitindar Singh * We have 4 Options: 1306b4db5413SSuraj Jitindar Singh * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 1307b4db5413SSuraj Jitindar Singh * HASH->RADIX : Free HPT 1308b4db5413SSuraj Jitindar Singh * RADIX->HASH : Allocate HPT 1309b4db5413SSuraj Jitindar Singh * NOTHING->HASH : Allocate HPT 1310b4db5413SSuraj Jitindar Singh * Note: NOTHING implies the case where we said the guest could choose 1311b4db5413SSuraj Jitindar Singh * later and so assumed radix and now it's called H_REG_PROC_TBL 1312b4db5413SSuraj Jitindar Singh */ 1313b4db5413SSuraj Jitindar Singh 131479825f4dSBenjamin Herrenschmidt if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) { 1315b4db5413SSuraj Jitindar Singh /* We assume RADIX, so this catches all the "Do Nothing" cases */ 131679825f4dSBenjamin Herrenschmidt } else if (!(patbe_old & PATE1_GR)) { 1317b4db5413SSuraj Jitindar Singh /* HASH->RADIX : Free HPT */ 131806ec79e8SBharata B Rao spapr_free_hpt(spapr); 131979825f4dSBenjamin Herrenschmidt } else if (!(patbe_new & PATE1_GR)) { 1320b4db5413SSuraj Jitindar Singh /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 1321b4db5413SSuraj Jitindar Singh spapr_setup_hpt_and_vrma(spapr); 1322b4db5413SSuraj Jitindar Singh } 1323b4db5413SSuraj Jitindar Singh return; 1324b4db5413SSuraj Jitindar Singh } 1325b4db5413SSuraj Jitindar Singh 1326b4db5413SSuraj Jitindar Singh #define FLAGS_MASK 0x01FULL 1327b4db5413SSuraj Jitindar Singh #define FLAG_MODIFY 0x10 1328b4db5413SSuraj Jitindar Singh #define FLAG_REGISTER 0x08 1329b4db5413SSuraj Jitindar Singh #define FLAG_RADIX 0x04 1330b4db5413SSuraj Jitindar Singh #define FLAG_HASH_PROC_TBL 0x02 1331b4db5413SSuraj Jitindar Singh #define FLAG_GTSE 0x01 1332b4db5413SSuraj Jitindar Singh 1333d77a98b0SSuraj Jitindar Singh static target_ulong h_register_process_table(PowerPCCPU *cpu, 1334ce2918cbSDavid Gibson SpaprMachineState *spapr, 1335d77a98b0SSuraj Jitindar Singh target_ulong opcode, 1336d77a98b0SSuraj Jitindar Singh target_ulong *args) 1337d77a98b0SSuraj Jitindar Singh { 1338b4db5413SSuraj Jitindar Singh target_ulong flags = args[0]; 1339b4db5413SSuraj Jitindar Singh target_ulong proc_tbl = args[1]; 1340b4db5413SSuraj Jitindar Singh target_ulong page_size = args[2]; 1341b4db5413SSuraj Jitindar Singh target_ulong table_size = args[3]; 1342176dcceeSSuraj Jitindar Singh target_ulong update_lpcr = 0; 1343b4db5413SSuraj Jitindar Singh uint64_t cproc; 1344b4db5413SSuraj Jitindar Singh 1345b4db5413SSuraj Jitindar Singh if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 1346b4db5413SSuraj Jitindar Singh return H_PARAMETER; 1347b4db5413SSuraj Jitindar Singh } 1348b4db5413SSuraj Jitindar Singh if (flags & FLAG_MODIFY) { 1349b4db5413SSuraj Jitindar Singh if (flags & FLAG_REGISTER) { 1350b4db5413SSuraj Jitindar Singh if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 1351b4db5413SSuraj Jitindar Singh if (proc_tbl & 0xfff || proc_tbl >> 60) { 1352b4db5413SSuraj Jitindar Singh return H_P2; 1353b4db5413SSuraj Jitindar Singh } else if (page_size) { 1354b4db5413SSuraj Jitindar Singh return H_P3; 1355b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 1356b4db5413SSuraj Jitindar Singh return H_P4; 1357b4db5413SSuraj Jitindar Singh } 135879825f4dSBenjamin Herrenschmidt cproc = PATE1_GR | proc_tbl | table_size; 1359b4db5413SSuraj Jitindar Singh } else { /* Register new HPT process table */ 1360b4db5413SSuraj Jitindar Singh if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 1361b4db5413SSuraj Jitindar Singh /* TODO - Not Supported */ 1362b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 1363b4db5413SSuraj Jitindar Singh return H_PARAMETER; 1364b4db5413SSuraj Jitindar Singh } else { /* Hash with SLB */ 1365b4db5413SSuraj Jitindar Singh if (proc_tbl >> 38) { 1366b4db5413SSuraj Jitindar Singh return H_P2; 1367b4db5413SSuraj Jitindar Singh } else if (page_size & ~0x7) { 1368b4db5413SSuraj Jitindar Singh return H_P3; 1369b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 1370b4db5413SSuraj Jitindar Singh return H_P4; 1371b4db5413SSuraj Jitindar Singh } 1372b4db5413SSuraj Jitindar Singh } 1373b4db5413SSuraj Jitindar Singh cproc = (proc_tbl << 25) | page_size << 5 | table_size; 1374b4db5413SSuraj Jitindar Singh } 1375b4db5413SSuraj Jitindar Singh 1376b4db5413SSuraj Jitindar Singh } else { /* Deregister current process table */ 137779825f4dSBenjamin Herrenschmidt /* 137879825f4dSBenjamin Herrenschmidt * Set to benign value: (current GR) | 0. This allows 137979825f4dSBenjamin Herrenschmidt * deregistration in KVM to succeed even if the radix bit 138079825f4dSBenjamin Herrenschmidt * in flags doesn't match the radix bit in the old PATE. 138179825f4dSBenjamin Herrenschmidt */ 138279825f4dSBenjamin Herrenschmidt cproc = spapr->patb_entry & PATE1_GR; 1383b4db5413SSuraj Jitindar Singh } 1384b4db5413SSuraj Jitindar Singh } else { /* Maintain current registration */ 138579825f4dSBenjamin Herrenschmidt if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) { 1386b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 1387b4db5413SSuraj Jitindar Singh return H_PARAMETER; /* Existing Process Table Mismatch */ 1388b4db5413SSuraj Jitindar Singh } 1389b4db5413SSuraj Jitindar Singh cproc = spapr->patb_entry; 1390b4db5413SSuraj Jitindar Singh } 1391b4db5413SSuraj Jitindar Singh 1392b4db5413SSuraj Jitindar Singh /* Check if we need to setup OR free the hpt */ 1393b4db5413SSuraj Jitindar Singh spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 1394b4db5413SSuraj Jitindar Singh 1395b4db5413SSuraj Jitindar Singh spapr->patb_entry = cproc; /* Save new process table */ 13966de83307SSuraj Jitindar Singh 139700fd075eSBenjamin Herrenschmidt /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ 1398176dcceeSSuraj Jitindar Singh if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */ 1399176dcceeSSuraj Jitindar Singh update_lpcr |= (LPCR_UPRT | LPCR_HR); 1400176dcceeSSuraj Jitindar Singh else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ 1401176dcceeSSuraj Jitindar Singh update_lpcr |= LPCR_UPRT; 1402176dcceeSSuraj Jitindar Singh if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ 140349e9fdd7SDavid Gibson update_lpcr |= LPCR_GTSE; 140449e9fdd7SDavid Gibson 1405176dcceeSSuraj Jitindar Singh spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); 1406b4db5413SSuraj Jitindar Singh 1407b4db5413SSuraj Jitindar Singh if (kvm_enabled()) { 1408b4db5413SSuraj Jitindar Singh return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1409b4db5413SSuraj Jitindar Singh flags & FLAG_GTSE, cproc); 1410b4db5413SSuraj Jitindar Singh } 1411b4db5413SSuraj Jitindar Singh return H_SUCCESS; 1412d77a98b0SSuraj Jitindar Singh } 1413d77a98b0SSuraj Jitindar Singh 14141c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALL -1 14151c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 14161c7ad77eSNicholas Piggin 14171c7ad77eSNicholas Piggin static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1418ce2918cbSDavid Gibson SpaprMachineState *spapr, 14191c7ad77eSNicholas Piggin target_ulong opcode, target_ulong *args) 14201c7ad77eSNicholas Piggin { 14211c7ad77eSNicholas Piggin target_long target = args[0]; 14221c7ad77eSNicholas Piggin CPUState *cs; 14231c7ad77eSNicholas Piggin 14241c7ad77eSNicholas Piggin if (target < 0) { 14251c7ad77eSNicholas Piggin /* Broadcast */ 14261c7ad77eSNicholas Piggin if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 14271c7ad77eSNicholas Piggin return H_PARAMETER; 14281c7ad77eSNicholas Piggin } 14291c7ad77eSNicholas Piggin 14301c7ad77eSNicholas Piggin CPU_FOREACH(cs) { 14311c7ad77eSNicholas Piggin PowerPCCPU *c = POWERPC_CPU(cs); 14321c7ad77eSNicholas Piggin 14331c7ad77eSNicholas Piggin if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 14341c7ad77eSNicholas Piggin if (c == cpu) { 14351c7ad77eSNicholas Piggin continue; 14361c7ad77eSNicholas Piggin } 14371c7ad77eSNicholas Piggin } 14381c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 14391c7ad77eSNicholas Piggin } 14401c7ad77eSNicholas Piggin return H_SUCCESS; 14411c7ad77eSNicholas Piggin 14421c7ad77eSNicholas Piggin } else { 14431c7ad77eSNicholas Piggin /* Unicast */ 14442e886fb3SSam Bobroff cs = CPU(spapr_find_cpu(target)); 1445f57467e3SSam Bobroff if (cs) { 14461c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 14471c7ad77eSNicholas Piggin return H_SUCCESS; 14481c7ad77eSNicholas Piggin } 14491c7ad77eSNicholas Piggin return H_PARAMETER; 14501c7ad77eSNicholas Piggin } 14511c7ad77eSNicholas Piggin } 14521c7ad77eSNicholas Piggin 1453ce2918cbSDavid Gibson static uint32_t cas_check_pvr(SpaprMachineState *spapr, PowerPCCPU *cpu, 1454cc7b35b1SGreg Kurz target_ulong *addr, bool *raw_mode_supported, 1455cc7b35b1SGreg Kurz Error **errp) 14562a6593cbSAlexey Kardashevskiy { 1457152ef803SDavid Gibson bool explicit_match = false; /* Matched the CPU's real PVR */ 14587843c0d6SDavid Gibson uint32_t max_compat = spapr->max_compat_pvr; 1459152ef803SDavid Gibson uint32_t best_compat = 0; 1460152ef803SDavid Gibson int i; 14613794d548SAlexey Kardashevskiy 1462152ef803SDavid Gibson /* 1463152ef803SDavid Gibson * We scan the supplied table of PVRs looking for two things 1464152ef803SDavid Gibson * 1. Is our real CPU PVR in the list? 1465152ef803SDavid Gibson * 2. What's the "best" listed logical PVR 1466152ef803SDavid Gibson */ 1467152ef803SDavid Gibson for (i = 0; i < 512; ++i) { 14683794d548SAlexey Kardashevskiy uint32_t pvr, pvr_mask; 14693794d548SAlexey Kardashevskiy 147080c33d34SDavid Gibson pvr_mask = ldl_be_phys(&address_space_memory, *addr); 147180c33d34SDavid Gibson pvr = ldl_be_phys(&address_space_memory, *addr + 4); 147280c33d34SDavid Gibson *addr += 8; 14733794d548SAlexey Kardashevskiy 14743794d548SAlexey Kardashevskiy if (~pvr_mask & pvr) { 1475152ef803SDavid Gibson break; /* Terminator record */ 14763794d548SAlexey Kardashevskiy } 1477152ef803SDavid Gibson 1478152ef803SDavid Gibson if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1479152ef803SDavid Gibson explicit_match = true; 1480152ef803SDavid Gibson } else { 1481152ef803SDavid Gibson if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1482152ef803SDavid Gibson best_compat = pvr; 1483152ef803SDavid Gibson } 1484152ef803SDavid Gibson } 1485152ef803SDavid Gibson } 1486152ef803SDavid Gibson 1487152ef803SDavid Gibson if ((best_compat == 0) && (!explicit_match || max_compat)) { 1488152ef803SDavid Gibson /* We couldn't find a suitable compatibility mode, and either 1489152ef803SDavid Gibson * the guest doesn't support "raw" mode for this CPU, or raw 1490152ef803SDavid Gibson * mode is disabled because a maximum compat mode is set */ 149180c33d34SDavid Gibson error_setg(errp, "Couldn't negotiate a suitable PVR during CAS"); 149280c33d34SDavid Gibson return 0; 14933794d548SAlexey Kardashevskiy } 14943794d548SAlexey Kardashevskiy 1495cc7b35b1SGreg Kurz *raw_mode_supported = explicit_match; 1496cc7b35b1SGreg Kurz 14973794d548SAlexey Kardashevskiy /* Parsing finished */ 1498152ef803SDavid Gibson trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 14993794d548SAlexey Kardashevskiy 150080c33d34SDavid Gibson return best_compat; 150180c33d34SDavid Gibson } 150280c33d34SDavid Gibson 150380c33d34SDavid Gibson static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1504ce2918cbSDavid Gibson SpaprMachineState *spapr, 150580c33d34SDavid Gibson target_ulong opcode, 150680c33d34SDavid Gibson target_ulong *args) 150780c33d34SDavid Gibson { 150880c33d34SDavid Gibson /* Working address in data buffer */ 150980c33d34SDavid Gibson target_ulong addr = ppc64_phys_to_real(args[0]); 151080c33d34SDavid Gibson target_ulong ov_table; 151180c33d34SDavid Gibson uint32_t cas_pvr; 1512ce2918cbSDavid Gibson SpaprOptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates; 151380c33d34SDavid Gibson bool guest_radix; 1514f6f242c7SDavid Gibson Error *local_err = NULL; 1515cc7b35b1SGreg Kurz bool raw_mode_supported = false; 1516*e7f78db9SGreg Kurz bool guest_xive; 15173794d548SAlexey Kardashevskiy 1518cc7b35b1SGreg Kurz cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err); 151980c33d34SDavid Gibson if (local_err) { 152080c33d34SDavid Gibson error_report_err(local_err); 152180c33d34SDavid Gibson return H_HARDWARE; 152280c33d34SDavid Gibson } 152380c33d34SDavid Gibson 152480c33d34SDavid Gibson /* Update CPUs */ 152580c33d34SDavid Gibson if (cpu->compat_pvr != cas_pvr) { 152680c33d34SDavid Gibson ppc_set_compat_all(cas_pvr, &local_err); 1527f6f242c7SDavid Gibson if (local_err) { 1528cc7b35b1SGreg Kurz /* We fail to set compat mode (likely because running with KVM PR), 1529cc7b35b1SGreg Kurz * but maybe we can fallback to raw mode if the guest supports it. 1530cc7b35b1SGreg Kurz */ 1531cc7b35b1SGreg Kurz if (!raw_mode_supported) { 1532f6f242c7SDavid Gibson error_report_err(local_err); 15333794d548SAlexey Kardashevskiy return H_HARDWARE; 15343794d548SAlexey Kardashevskiy } 15352c9dfdacSGreg Kurz error_free(local_err); 1536cc7b35b1SGreg Kurz local_err = NULL; 1537cc7b35b1SGreg Kurz } 15383794d548SAlexey Kardashevskiy } 15393794d548SAlexey Kardashevskiy 154003d196b7SBharata B Rao /* For the future use: here @ov_table points to the first option vector */ 154180c33d34SDavid Gibson ov_table = addr; 154203d196b7SBharata B Rao 1543e957f6a9SSam Bobroff ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1544facdb8b6SMichael Roth ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 15459fb4541fSSam Bobroff if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 15469fb4541fSSam Bobroff error_report("guest requested hash and radix MMU, which is invalid."); 15479fb4541fSSam Bobroff exit(EXIT_FAILURE); 15489fb4541fSSam Bobroff } 1549*e7f78db9SGreg Kurz if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { 1550*e7f78db9SGreg Kurz error_report("guest requested an invalid interrupt mode"); 1551*e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1552*e7f78db9SGreg Kurz } 1553*e7f78db9SGreg Kurz 15549fb4541fSSam Bobroff /* The radix/hash bit in byte 24 requires special handling: */ 15559fb4541fSSam Bobroff guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 15569fb4541fSSam Bobroff spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300); 15572a6593cbSAlexey Kardashevskiy 1558*e7f78db9SGreg Kurz guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); 1559*e7f78db9SGreg Kurz 15602772cf6bSDavid Gibson /* 15612772cf6bSDavid Gibson * HPT resizing is a bit of a special case, because when enabled 15622772cf6bSDavid Gibson * we assume an HPT guest will support it until it says it 15632772cf6bSDavid Gibson * doesn't, instead of assuming it won't support it until it says 15642772cf6bSDavid Gibson * it does. Strictly speaking that approach could break for 15652772cf6bSDavid Gibson * guests which don't make a CAS call, but those are so old we 15662772cf6bSDavid Gibson * don't care about them. Without that assumption we'd have to 15672772cf6bSDavid Gibson * make at least a temporary allocation of an HPT sized for max 15682772cf6bSDavid Gibson * memory, which could be impossibly difficult under KVM HV if 15692772cf6bSDavid Gibson * maxram is large. 15702772cf6bSDavid Gibson */ 15712772cf6bSDavid Gibson if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 15722772cf6bSDavid Gibson int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 15732772cf6bSDavid Gibson 15742772cf6bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 15752772cf6bSDavid Gibson error_report( 15762772cf6bSDavid Gibson "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 15772772cf6bSDavid Gibson exit(1); 15782772cf6bSDavid Gibson } 15792772cf6bSDavid Gibson 15802772cf6bSDavid Gibson if (spapr->htab_shift < maxshift) { 15812772cf6bSDavid Gibson /* Guest doesn't know about HPT resizing, so we 15822772cf6bSDavid Gibson * pre-emptively resize for the maximum permitted RAM. At 15832772cf6bSDavid Gibson * the point this is called, nothing should have been 15842772cf6bSDavid Gibson * entered into the existing HPT */ 15852772cf6bSDavid Gibson spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 15861ec26c75SGreg Kurz push_sregs_to_kvm_pr(spapr); 1587b55d295eSDavid Gibson } 15882772cf6bSDavid Gibson } 15892772cf6bSDavid Gibson 1590facdb8b6SMichael Roth /* NOTE: there are actually a number of ov5 bits where input from the 1591facdb8b6SMichael Roth * guest is always zero, and the platform/QEMU enables them independently 1592facdb8b6SMichael Roth * of guest input. To model these properly we'd want some sort of mask, 1593facdb8b6SMichael Roth * but since they only currently apply to memory migration as defined 1594facdb8b6SMichael Roth * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 15956787d27bSMichael Roth * to worry about this for now. 1596facdb8b6SMichael Roth */ 15976787d27bSMichael Roth ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); 159830bf9ed1SCédric Le Goater 159930bf9ed1SCédric Le Goater /* also clear the radix/hash bit from the current ov5_cas bits to 160030bf9ed1SCédric Le Goater * be in sync with the newly ov5 bits. Else the radix bit will be 160130bf9ed1SCédric Le Goater * seen as being removed and this will generate a reset loop 160230bf9ed1SCédric Le Goater */ 160330bf9ed1SCédric Le Goater spapr_ovec_clear(ov5_cas_old, OV5_MMU_RADIX_300); 160430bf9ed1SCédric Le Goater 16056787d27bSMichael Roth /* full range of negotiated ov5 capabilities */ 1606facdb8b6SMichael Roth spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1607facdb8b6SMichael Roth spapr_ovec_cleanup(ov5_guest); 16086787d27bSMichael Roth /* capabilities that have been added since CAS-generated guest reset. 16096787d27bSMichael Roth * if capabilities have since been removed, generate another reset 16106787d27bSMichael Roth */ 16116787d27bSMichael Roth ov5_updates = spapr_ovec_new(); 16126787d27bSMichael Roth spapr->cas_reboot = spapr_ovec_diff(ov5_updates, 16136787d27bSMichael Roth ov5_cas_old, spapr->ov5_cas); 16149fb4541fSSam Bobroff /* Now that processing is finished, set the radix/hash bit for the 16159fb4541fSSam Bobroff * guest if it requested a valid mode; otherwise terminate the boot. */ 16169fb4541fSSam Bobroff if (guest_radix) { 16179fb4541fSSam Bobroff if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 16189fb4541fSSam Bobroff error_report("Guest requested unavailable MMU mode (radix)."); 16199fb4541fSSam Bobroff exit(EXIT_FAILURE); 16209fb4541fSSam Bobroff } 16219fb4541fSSam Bobroff spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300); 16229fb4541fSSam Bobroff } else { 16239fb4541fSSam Bobroff if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 16249fb4541fSSam Bobroff && !kvmppc_has_cap_mmu_hash_v3()) { 16259fb4541fSSam Bobroff error_report("Guest requested unavailable MMU mode (hash)."); 16269fb4541fSSam Bobroff exit(EXIT_FAILURE); 16279fb4541fSSam Bobroff } 16289fb4541fSSam Bobroff } 1629e957f6a9SSam Bobroff spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest, 1630e957f6a9SSam Bobroff OV1_PPC_3_00); 16316787d27bSMichael Roth if (!spapr->cas_reboot) { 1632b472b1a7SDaniel Henrique Barboza /* If spapr_machine_reset() did not set up a HPT but one is necessary 1633e05fba50SSam Bobroff * (because the guest isn't going to use radix) then set it up here. */ 163479825f4dSBenjamin Herrenschmidt if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { 1635e05fba50SSam Bobroff /* legacy hash or new hash: */ 1636e05fba50SSam Bobroff spapr_setup_hpt_and_vrma(spapr); 1637e05fba50SSam Bobroff } 16386787d27bSMichael Roth spapr->cas_reboot = 16395b120785SDavid Gibson (spapr_h_cas_compose_response(spapr, args[1], args[2], 16406787d27bSMichael Roth ov5_updates) != 0); 16416787d27bSMichael Roth } 164213db0cd9SCédric Le Goater 164313db0cd9SCédric Le Goater /* 1644*e7f78db9SGreg Kurz * Ensure the guest asks for an interrupt mode we support; otherwise 1645*e7f78db9SGreg Kurz * terminate the boot. 1646*e7f78db9SGreg Kurz */ 1647*e7f78db9SGreg Kurz if (guest_xive) { 1648*e7f78db9SGreg Kurz if (spapr->irq->ov5 == SPAPR_OV5_XIVE_LEGACY) { 1649*e7f78db9SGreg Kurz error_report("Guest requested unavailable interrupt mode (XIVE)"); 1650*e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1651*e7f78db9SGreg Kurz } 1652*e7f78db9SGreg Kurz } else { 1653*e7f78db9SGreg Kurz if (spapr->irq->ov5 == SPAPR_OV5_XIVE_EXPLOIT) { 1654*e7f78db9SGreg Kurz error_report("Guest requested unavailable interrupt mode (XICS)"); 1655*e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1656*e7f78db9SGreg Kurz } 1657*e7f78db9SGreg Kurz } 1658*e7f78db9SGreg Kurz 1659*e7f78db9SGreg Kurz /* 166013db0cd9SCédric Le Goater * Generate a machine reset when we have an update of the 166113db0cd9SCédric Le Goater * interrupt mode. Only required when the machine supports both 166213db0cd9SCédric Le Goater * modes. 166313db0cd9SCédric Le Goater */ 166413db0cd9SCédric Le Goater if (!spapr->cas_reboot) { 166513db0cd9SCédric Le Goater spapr->cas_reboot = spapr_ovec_test(ov5_updates, OV5_XIVE_EXPLOIT) 166613db0cd9SCédric Le Goater && spapr->irq->ov5 & SPAPR_OV5_XIVE_BOTH; 166713db0cd9SCédric Le Goater } 166813db0cd9SCédric Le Goater 16696787d27bSMichael Roth spapr_ovec_cleanup(ov5_updates); 16706787d27bSMichael Roth 16716787d27bSMichael Roth if (spapr->cas_reboot) { 1672cf83f140SEric Blake qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 16732a6593cbSAlexey Kardashevskiy } 16742a6593cbSAlexey Kardashevskiy 16752a6593cbSAlexey Kardashevskiy return H_SUCCESS; 16762a6593cbSAlexey Kardashevskiy } 16772a6593cbSAlexey Kardashevskiy 1678c24ba3d0SLaurent Vivier static target_ulong h_home_node_associativity(PowerPCCPU *cpu, 1679ce2918cbSDavid Gibson SpaprMachineState *spapr, 1680c24ba3d0SLaurent Vivier target_ulong opcode, 1681c24ba3d0SLaurent Vivier target_ulong *args) 1682c24ba3d0SLaurent Vivier { 1683c24ba3d0SLaurent Vivier target_ulong flags = args[0]; 1684c24ba3d0SLaurent Vivier target_ulong procno = args[1]; 1685c24ba3d0SLaurent Vivier PowerPCCPU *tcpu; 1686c24ba3d0SLaurent Vivier int idx; 1687c24ba3d0SLaurent Vivier 1688c24ba3d0SLaurent Vivier /* only support procno from H_REGISTER_VPA */ 1689c24ba3d0SLaurent Vivier if (flags != 0x1) { 1690c24ba3d0SLaurent Vivier return H_FUNCTION; 1691c24ba3d0SLaurent Vivier } 1692c24ba3d0SLaurent Vivier 1693c24ba3d0SLaurent Vivier tcpu = spapr_find_cpu(procno); 1694c24ba3d0SLaurent Vivier if (tcpu == NULL) { 1695c24ba3d0SLaurent Vivier return H_P2; 1696c24ba3d0SLaurent Vivier } 1697c24ba3d0SLaurent Vivier 1698c24ba3d0SLaurent Vivier /* sequence is the same as in the "ibm,associativity" property */ 1699c24ba3d0SLaurent Vivier 1700c24ba3d0SLaurent Vivier idx = 0; 1701c24ba3d0SLaurent Vivier #define ASSOCIATIVITY(a, b) (((uint64_t)(a) << 32) | \ 1702c24ba3d0SLaurent Vivier ((uint64_t)(b) & 0xffffffff)) 1703c24ba3d0SLaurent Vivier args[idx++] = ASSOCIATIVITY(0, 0); 1704c24ba3d0SLaurent Vivier args[idx++] = ASSOCIATIVITY(0, tcpu->node_id); 1705c24ba3d0SLaurent Vivier args[idx++] = ASSOCIATIVITY(procno, -1); 1706c24ba3d0SLaurent Vivier for ( ; idx < 6; idx++) { 1707c24ba3d0SLaurent Vivier args[idx] = -1; 1708c24ba3d0SLaurent Vivier } 1709c24ba3d0SLaurent Vivier #undef ASSOCIATIVITY 1710c24ba3d0SLaurent Vivier 1711c24ba3d0SLaurent Vivier return H_SUCCESS; 1712c24ba3d0SLaurent Vivier } 1713c24ba3d0SLaurent Vivier 1714c59704b2SSuraj Jitindar Singh static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1715ce2918cbSDavid Gibson SpaprMachineState *spapr, 1716c59704b2SSuraj Jitindar Singh target_ulong opcode, 1717c59704b2SSuraj Jitindar Singh target_ulong *args) 1718c59704b2SSuraj Jitindar Singh { 1719c59704b2SSuraj Jitindar Singh uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1720c59704b2SSuraj Jitindar Singh ~H_CPU_CHAR_THR_RECONF_TRIG; 1721c59704b2SSuraj Jitindar Singh uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1722c59704b2SSuraj Jitindar Singh uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1723c59704b2SSuraj Jitindar Singh uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1724c59704b2SSuraj Jitindar Singh uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 17258ff43ee4SSuraj Jitindar Singh uint8_t count_cache_flush_assist = spapr_get_cap(spapr, 17268ff43ee4SSuraj Jitindar Singh SPAPR_CAP_CCF_ASSIST); 1727c59704b2SSuraj Jitindar Singh 1728c59704b2SSuraj Jitindar Singh switch (safe_cache) { 1729c59704b2SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1730c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1731c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1732c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1733c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1734c59704b2SSuraj Jitindar Singh break; 1735c59704b2SSuraj Jitindar Singh case SPAPR_CAP_FIXED: 1736c59704b2SSuraj Jitindar Singh break; 1737c59704b2SSuraj Jitindar Singh default: /* broken */ 1738c59704b2SSuraj Jitindar Singh assert(safe_cache == SPAPR_CAP_BROKEN); 1739c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1740c59704b2SSuraj Jitindar Singh break; 1741c59704b2SSuraj Jitindar Singh } 1742c59704b2SSuraj Jitindar Singh 1743c59704b2SSuraj Jitindar Singh switch (safe_bounds_check) { 1744c59704b2SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1745c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1746c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1747c59704b2SSuraj Jitindar Singh break; 1748c59704b2SSuraj Jitindar Singh case SPAPR_CAP_FIXED: 1749c59704b2SSuraj Jitindar Singh break; 1750c59704b2SSuraj Jitindar Singh default: /* broken */ 1751c59704b2SSuraj Jitindar Singh assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1752c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1753c59704b2SSuraj Jitindar Singh break; 1754c59704b2SSuraj Jitindar Singh } 1755c59704b2SSuraj Jitindar Singh 1756c59704b2SSuraj Jitindar Singh switch (safe_indirect_branch) { 1757399b2896SSuraj Jitindar Singh case SPAPR_CAP_FIXED_NA: 1758399b2896SSuraj Jitindar Singh break; 1759c76c0d30SSuraj Jitindar Singh case SPAPR_CAP_FIXED_CCD: 1760c76c0d30SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; 1761c76c0d30SSuraj Jitindar Singh break; 1762c76c0d30SSuraj Jitindar Singh case SPAPR_CAP_FIXED_IBS: 1763c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1764fa86f592SGreg Kurz break; 1765399b2896SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1766399b2896SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE; 17678ff43ee4SSuraj Jitindar Singh if (count_cache_flush_assist) { 17688ff43ee4SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST; 17698ff43ee4SSuraj Jitindar Singh } 1770399b2896SSuraj Jitindar Singh break; 1771c59704b2SSuraj Jitindar Singh default: /* broken */ 1772c59704b2SSuraj Jitindar Singh assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1773c59704b2SSuraj Jitindar Singh break; 1774c59704b2SSuraj Jitindar Singh } 1775c59704b2SSuraj Jitindar Singh 1776c59704b2SSuraj Jitindar Singh args[0] = characteristics; 1777c59704b2SSuraj Jitindar Singh args[1] = behaviour; 1778fea35ca4SAlexey Kardashevskiy return H_SUCCESS; 1779fea35ca4SAlexey Kardashevskiy } 1780fea35ca4SAlexey Kardashevskiy 1781ce2918cbSDavid Gibson static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, 1782fea35ca4SAlexey Kardashevskiy target_ulong opcode, target_ulong *args) 1783fea35ca4SAlexey Kardashevskiy { 1784fea35ca4SAlexey Kardashevskiy target_ulong dt = ppc64_phys_to_real(args[0]); 1785fea35ca4SAlexey Kardashevskiy struct fdt_header hdr = { 0 }; 1786fea35ca4SAlexey Kardashevskiy unsigned cb; 1787ce2918cbSDavid Gibson SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1788fea35ca4SAlexey Kardashevskiy void *fdt; 1789fea35ca4SAlexey Kardashevskiy 1790fea35ca4SAlexey Kardashevskiy cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); 1791fea35ca4SAlexey Kardashevskiy cb = fdt32_to_cpu(hdr.totalsize); 1792fea35ca4SAlexey Kardashevskiy 1793fea35ca4SAlexey Kardashevskiy if (!smc->update_dt_enabled) { 1794fea35ca4SAlexey Kardashevskiy return H_SUCCESS; 1795fea35ca4SAlexey Kardashevskiy } 1796fea35ca4SAlexey Kardashevskiy 1797fea35ca4SAlexey Kardashevskiy /* Check that the fdt did not grow out of proportion */ 1798fea35ca4SAlexey Kardashevskiy if (cb > spapr->fdt_initial_size * 2) { 1799fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, 1800fea35ca4SAlexey Kardashevskiy fdt32_to_cpu(hdr.magic)); 1801fea35ca4SAlexey Kardashevskiy return H_PARAMETER; 1802fea35ca4SAlexey Kardashevskiy } 1803fea35ca4SAlexey Kardashevskiy 1804fea35ca4SAlexey Kardashevskiy fdt = g_malloc0(cb); 1805fea35ca4SAlexey Kardashevskiy cpu_physical_memory_read(dt, fdt, cb); 1806fea35ca4SAlexey Kardashevskiy 1807fea35ca4SAlexey Kardashevskiy /* Check the fdt consistency */ 1808fea35ca4SAlexey Kardashevskiy if (fdt_check_full(fdt, cb)) { 1809fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, 1810fea35ca4SAlexey Kardashevskiy fdt32_to_cpu(hdr.magic)); 1811fea35ca4SAlexey Kardashevskiy return H_PARAMETER; 1812fea35ca4SAlexey Kardashevskiy } 1813fea35ca4SAlexey Kardashevskiy 1814fea35ca4SAlexey Kardashevskiy g_free(spapr->fdt_blob); 1815fea35ca4SAlexey Kardashevskiy spapr->fdt_size = cb; 1816fea35ca4SAlexey Kardashevskiy spapr->fdt_blob = fdt; 1817fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt(cb); 1818c59704b2SSuraj Jitindar Singh 1819c59704b2SSuraj Jitindar Singh return H_SUCCESS; 1820c59704b2SSuraj Jitindar Singh } 1821c59704b2SSuraj Jitindar Singh 18229f64bd8aSPaolo Bonzini static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 18239f64bd8aSPaolo Bonzini static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 18249f64bd8aSPaolo Bonzini 18259f64bd8aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 18269f64bd8aSPaolo Bonzini { 18279f64bd8aSPaolo Bonzini spapr_hcall_fn *slot; 18289f64bd8aSPaolo Bonzini 18299f64bd8aSPaolo Bonzini if (opcode <= MAX_HCALL_OPCODE) { 18309f64bd8aSPaolo Bonzini assert((opcode & 0x3) == 0); 18319f64bd8aSPaolo Bonzini 18329f64bd8aSPaolo Bonzini slot = &papr_hypercall_table[opcode / 4]; 18339f64bd8aSPaolo Bonzini } else { 18349f64bd8aSPaolo Bonzini assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 18359f64bd8aSPaolo Bonzini 18369f64bd8aSPaolo Bonzini slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 18379f64bd8aSPaolo Bonzini } 18389f64bd8aSPaolo Bonzini 18399f64bd8aSPaolo Bonzini assert(!(*slot)); 18409f64bd8aSPaolo Bonzini *slot = fn; 18419f64bd8aSPaolo Bonzini } 18429f64bd8aSPaolo Bonzini 18439f64bd8aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 18449f64bd8aSPaolo Bonzini target_ulong *args) 18459f64bd8aSPaolo Bonzini { 1846ce2918cbSDavid Gibson SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 184728e02042SDavid Gibson 18489f64bd8aSPaolo Bonzini if ((opcode <= MAX_HCALL_OPCODE) 18499f64bd8aSPaolo Bonzini && ((opcode & 0x3) == 0)) { 18509f64bd8aSPaolo Bonzini spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 18519f64bd8aSPaolo Bonzini 18529f64bd8aSPaolo Bonzini if (fn) { 18539f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 18549f64bd8aSPaolo Bonzini } 18559f64bd8aSPaolo Bonzini } else if ((opcode >= KVMPPC_HCALL_BASE) && 18569f64bd8aSPaolo Bonzini (opcode <= KVMPPC_HCALL_MAX)) { 18579f64bd8aSPaolo Bonzini spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 18589f64bd8aSPaolo Bonzini 18599f64bd8aSPaolo Bonzini if (fn) { 18609f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 18619f64bd8aSPaolo Bonzini } 18629f64bd8aSPaolo Bonzini } 18639f64bd8aSPaolo Bonzini 1864aaf87c66SThomas Huth qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1865aaf87c66SThomas Huth opcode); 18669f64bd8aSPaolo Bonzini return H_FUNCTION; 18679f64bd8aSPaolo Bonzini } 18689f64bd8aSPaolo Bonzini 18699f64bd8aSPaolo Bonzini static void hypercall_register_types(void) 18709f64bd8aSPaolo Bonzini { 18719f64bd8aSPaolo Bonzini /* hcall-pft */ 18729f64bd8aSPaolo Bonzini spapr_register_hypercall(H_ENTER, h_enter); 18739f64bd8aSPaolo Bonzini spapr_register_hypercall(H_REMOVE, h_remove); 18749f64bd8aSPaolo Bonzini spapr_register_hypercall(H_PROTECT, h_protect); 1875fa388916SAnthony Liguori spapr_register_hypercall(H_READ, h_read); 18769f64bd8aSPaolo Bonzini 18779f64bd8aSPaolo Bonzini /* hcall-bulk */ 18789f64bd8aSPaolo Bonzini spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 18799f64bd8aSPaolo Bonzini 188030f4b05bSDavid Gibson /* hcall-hpt-resize */ 188130f4b05bSDavid Gibson spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 188230f4b05bSDavid Gibson spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 188330f4b05bSDavid Gibson 18849f64bd8aSPaolo Bonzini /* hcall-splpar */ 18859f64bd8aSPaolo Bonzini spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 18869f64bd8aSPaolo Bonzini spapr_register_hypercall(H_CEDE, h_cede); 18871c7ad77eSNicholas Piggin spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 18889f64bd8aSPaolo Bonzini 1889423576f7SThomas Huth /* processor register resource access h-calls */ 1890423576f7SThomas Huth spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1891af08a58fSThomas Huth spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1892e49ff266SThomas Huth spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 18933240dd9aSThomas Huth spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1894423576f7SThomas Huth spapr_register_hypercall(H_SET_MODE, h_set_mode); 1895423576f7SThomas Huth 1896d77a98b0SSuraj Jitindar Singh /* In Memory Table MMU h-calls */ 1897d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1898d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1899d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1900d77a98b0SSuraj Jitindar Singh 1901c59704b2SSuraj Jitindar Singh /* hcall-get-cpu-characteristics */ 1902c59704b2SSuraj Jitindar Singh spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 1903c59704b2SSuraj Jitindar Singh h_get_cpu_characteristics); 1904c59704b2SSuraj Jitindar Singh 19059f64bd8aSPaolo Bonzini /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 19069f64bd8aSPaolo Bonzini * here between the "CI" and the "CACHE" variants, they will use whatever 19079f64bd8aSPaolo Bonzini * mapping attributes qemu is using. When using KVM, the kernel will 19089f64bd8aSPaolo Bonzini * enforce the attributes more strongly 19099f64bd8aSPaolo Bonzini */ 19109f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 19119f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 19129f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 19139f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 19149f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 19159f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 19169f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 19179f64bd8aSPaolo Bonzini 19189f64bd8aSPaolo Bonzini /* qemu/KVM-PPC specific hcalls */ 19199f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 192042561bf2SAnton Blanchard 19212a6593cbSAlexey Kardashevskiy /* ibm,client-architecture-support support */ 19222a6593cbSAlexey Kardashevskiy spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1923c24ba3d0SLaurent Vivier 1924fea35ca4SAlexey Kardashevskiy spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); 1925fea35ca4SAlexey Kardashevskiy 1926c24ba3d0SLaurent Vivier /* Virtual Processor Home Node */ 1927c24ba3d0SLaurent Vivier spapr_register_hypercall(H_HOME_NODE_ASSOCIATIVITY, 1928c24ba3d0SLaurent Vivier h_home_node_associativity); 19299f64bd8aSPaolo Bonzini } 19309f64bd8aSPaolo Bonzini 19319f64bd8aSPaolo Bonzini type_init(hypercall_register_types) 1932