10d75590dSPeter Maydell #include "qemu/osdep.h" 2da34e65cSMarkus Armbruster #include "qapi/error.h" 3b3946626SVincent Palatin #include "sysemu/hw_accel.h" 49f64bd8aSPaolo Bonzini #include "sysemu/sysemu.h" 503dd024fSPaolo Bonzini #include "qemu/log.h" 60b0b8310SDavid Gibson #include "qemu/error-report.h" 79f64bd8aSPaolo Bonzini #include "cpu.h" 863c91552SPaolo Bonzini #include "exec/exec-all.h" 99f64bd8aSPaolo Bonzini #include "helper_regs.h" 100d09e41aSPaolo Bonzini #include "hw/ppc/spapr.h" 11d5aea6f3SDavid Gibson #include "mmu-hash64.h" 123794d548SAlexey Kardashevskiy #include "cpu-models.h" 133794d548SAlexey Kardashevskiy #include "trace.h" 143794d548SAlexey Kardashevskiy #include "kvm_ppc.h" 15facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 16b4db5413SSuraj Jitindar Singh #include "mmu-book3s-v3.h" 172cc0e2e8SDavid Hildenbrand #include "hw/mem/memory-device.h" 189f64bd8aSPaolo Bonzini 19295b6c26SDavid Gibson struct LPCRSyncState { 20a46622fdSAlexey Kardashevskiy target_ulong value; 21a46622fdSAlexey Kardashevskiy target_ulong mask; 22a46622fdSAlexey Kardashevskiy }; 23a46622fdSAlexey Kardashevskiy 24295b6c26SDavid Gibson static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 25a46622fdSAlexey Kardashevskiy { 26295b6c26SDavid Gibson struct LPCRSyncState *s = arg.host_ptr; 27e0eeb4a2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 28a46622fdSAlexey Kardashevskiy CPUPPCState *env = &cpu->env; 29295b6c26SDavid Gibson target_ulong lpcr; 30a46622fdSAlexey Kardashevskiy 31e0eeb4a2SAlex Bennée cpu_synchronize_state(cs); 32295b6c26SDavid Gibson lpcr = env->spr[SPR_LPCR]; 33295b6c26SDavid Gibson lpcr &= ~s->mask; 34295b6c26SDavid Gibson lpcr |= s->value; 35295b6c26SDavid Gibson ppc_store_lpcr(cpu, lpcr); 36a46622fdSAlexey Kardashevskiy } 37a46622fdSAlexey Kardashevskiy 38295b6c26SDavid Gibson static void set_all_lpcrs(target_ulong value, target_ulong mask) 39a46622fdSAlexey Kardashevskiy { 40295b6c26SDavid Gibson CPUState *cs; 41295b6c26SDavid Gibson struct LPCRSyncState s = { 42a46622fdSAlexey Kardashevskiy .value = value, 43a46622fdSAlexey Kardashevskiy .mask = mask 44a46622fdSAlexey Kardashevskiy }; 45295b6c26SDavid Gibson CPU_FOREACH(cs) { 46295b6c26SDavid Gibson run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 47295b6c26SDavid Gibson } 48a46622fdSAlexey Kardashevskiy } 49a46622fdSAlexey Kardashevskiy 50af08a58fSThomas Huth static bool has_spr(PowerPCCPU *cpu, int spr) 51af08a58fSThomas Huth { 52af08a58fSThomas Huth /* We can test whether the SPR is defined by checking for a valid name */ 53af08a58fSThomas Huth return cpu->env.spr_cb[spr].name != NULL; 54af08a58fSThomas Huth } 55af08a58fSThomas Huth 56c6404adeSDavid Gibson static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) 57f3c75d42SAneesh Kumar K.V { 58f3c75d42SAneesh Kumar K.V /* 5936778660SDavid Gibson * hash value/pteg group index is normalized by HPT mask 60f3c75d42SAneesh Kumar K.V */ 6136778660SDavid Gibson if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { 62f3c75d42SAneesh Kumar K.V return false; 63f3c75d42SAneesh Kumar K.V } 64f3c75d42SAneesh Kumar K.V return true; 65f3c75d42SAneesh Kumar K.V } 66f3c75d42SAneesh Kumar K.V 67ecbc25faSDavid Gibson static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr) 68ecbc25faSDavid Gibson { 69ecbc25faSDavid Gibson MachineState *machine = MACHINE(spapr); 70*e017da37SDavid Hildenbrand DeviceMemoryState *dms = machine->device_memory; 71ecbc25faSDavid Gibson 72ecbc25faSDavid Gibson if (addr < machine->ram_size) { 73ecbc25faSDavid Gibson return true; 74ecbc25faSDavid Gibson } 75*e017da37SDavid Hildenbrand if ((addr >= dms->base) 76*e017da37SDavid Hildenbrand && ((addr - dms->base) < memory_region_size(&dms->mr))) { 77ecbc25faSDavid Gibson return true; 78ecbc25faSDavid Gibson } 79ecbc25faSDavid Gibson 80ecbc25faSDavid Gibson return false; 81ecbc25faSDavid Gibson } 82ecbc25faSDavid Gibson 8328e02042SDavid Gibson static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, 849f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 859f64bd8aSPaolo Bonzini { 869f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 87c6404adeSDavid Gibson target_ulong ptex = args[1]; 889f64bd8aSPaolo Bonzini target_ulong pteh = args[2]; 899f64bd8aSPaolo Bonzini target_ulong ptel = args[3]; 901f0252e6SCédric Le Goater unsigned apshift; 919f64bd8aSPaolo Bonzini target_ulong raddr; 92c6404adeSDavid Gibson target_ulong slot; 937222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 949f64bd8aSPaolo Bonzini 951f0252e6SCédric Le Goater apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); 961114e712SDavid Gibson if (!apshift) { 971114e712SDavid Gibson /* Bad page size encoding */ 989f64bd8aSPaolo Bonzini return H_PARAMETER; 999f64bd8aSPaolo Bonzini } 1009f64bd8aSPaolo Bonzini 1011114e712SDavid Gibson raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); 1029f64bd8aSPaolo Bonzini 103ecbc25faSDavid Gibson if (is_ram_address(spapr, raddr)) { 1049f64bd8aSPaolo Bonzini /* Regular RAM - should have WIMG=0010 */ 105d5aea6f3SDavid Gibson if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 1069f64bd8aSPaolo Bonzini return H_PARAMETER; 1079f64bd8aSPaolo Bonzini } 1089f64bd8aSPaolo Bonzini } else { 109c1175907SAneesh Kumar K.V target_ulong wimg_flags; 1109f64bd8aSPaolo Bonzini /* Looks like an IO address */ 1119f64bd8aSPaolo Bonzini /* FIXME: What WIMG combinations could be sensible for IO? 1129f64bd8aSPaolo Bonzini * For now we allow WIMG=010x, but are there others? */ 1139f64bd8aSPaolo Bonzini /* FIXME: Should we check against registered IO addresses? */ 114c1175907SAneesh Kumar K.V wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); 115c1175907SAneesh Kumar K.V 116c1175907SAneesh Kumar K.V if (wimg_flags != HPTE64_R_I && 117c1175907SAneesh Kumar K.V wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { 1189f64bd8aSPaolo Bonzini return H_PARAMETER; 1199f64bd8aSPaolo Bonzini } 1209f64bd8aSPaolo Bonzini } 1219f64bd8aSPaolo Bonzini 1229f64bd8aSPaolo Bonzini pteh &= ~0x60ULL; 1239f64bd8aSPaolo Bonzini 124c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 1259f64bd8aSPaolo Bonzini return H_PARAMETER; 1269f64bd8aSPaolo Bonzini } 1277c43bca0SAneesh Kumar K.V 128c6404adeSDavid Gibson slot = ptex & 7ULL; 129c6404adeSDavid Gibson ptex = ptex & ~7ULL; 130c6404adeSDavid Gibson 1319f64bd8aSPaolo Bonzini if (likely((flags & H_EXACT) == 0)) { 1327222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 133c6404adeSDavid Gibson for (slot = 0; slot < 8; slot++) { 1347222b94aSDavid Gibson if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { 1359f64bd8aSPaolo Bonzini break; 1369f64bd8aSPaolo Bonzini } 1377aaf4957SAneesh Kumar K.V } 1387222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 139c6404adeSDavid Gibson if (slot == 8) { 1407aaf4957SAneesh Kumar K.V return H_PTEG_FULL; 1417aaf4957SAneesh Kumar K.V } 1429f64bd8aSPaolo Bonzini } else { 1437222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); 1447222b94aSDavid Gibson if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { 1457222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); 1469f64bd8aSPaolo Bonzini return H_PTEG_FULL; 1479f64bd8aSPaolo Bonzini } 1487222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 1499f64bd8aSPaolo Bonzini } 1507c43bca0SAneesh Kumar K.V 151c6404adeSDavid Gibson ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); 1529f64bd8aSPaolo Bonzini 153c6404adeSDavid Gibson args[0] = ptex + slot; 1549f64bd8aSPaolo Bonzini return H_SUCCESS; 1559f64bd8aSPaolo Bonzini } 1569f64bd8aSPaolo Bonzini 157a3801402SStefan Weil typedef enum { 1589f64bd8aSPaolo Bonzini REMOVE_SUCCESS = 0, 1599f64bd8aSPaolo Bonzini REMOVE_NOT_FOUND = 1, 1609f64bd8aSPaolo Bonzini REMOVE_PARM = 2, 1619f64bd8aSPaolo Bonzini REMOVE_HW = 3, 162a3801402SStefan Weil } RemoveResult; 1639f64bd8aSPaolo Bonzini 1647ef23068SDavid Gibson static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, 1659f64bd8aSPaolo Bonzini target_ulong avpn, 1669f64bd8aSPaolo Bonzini target_ulong flags, 1679f64bd8aSPaolo Bonzini target_ulong *vp, target_ulong *rp) 1689f64bd8aSPaolo Bonzini { 1697222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 17061a36c9bSDavid Gibson target_ulong v, r; 1719f64bd8aSPaolo Bonzini 172c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 1739f64bd8aSPaolo Bonzini return REMOVE_PARM; 1749f64bd8aSPaolo Bonzini } 1759f64bd8aSPaolo Bonzini 1767222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 1777222b94aSDavid Gibson v = ppc_hash64_hpte0(cpu, hptes, 0); 1787222b94aSDavid Gibson r = ppc_hash64_hpte1(cpu, hptes, 0); 1797222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 1809f64bd8aSPaolo Bonzini 181d5aea6f3SDavid Gibson if ((v & HPTE64_V_VALID) == 0 || 1829f64bd8aSPaolo Bonzini ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 1839f64bd8aSPaolo Bonzini ((flags & H_ANDCOND) && (v & avpn) != 0)) { 1849f64bd8aSPaolo Bonzini return REMOVE_NOT_FOUND; 1859f64bd8aSPaolo Bonzini } 1869f64bd8aSPaolo Bonzini *vp = v; 1879f64bd8aSPaolo Bonzini *rp = r; 1887ef23068SDavid Gibson ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); 18961a36c9bSDavid Gibson ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 1909f64bd8aSPaolo Bonzini return REMOVE_SUCCESS; 1919f64bd8aSPaolo Bonzini } 1929f64bd8aSPaolo Bonzini 19328e02042SDavid Gibson static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1949f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 1959f64bd8aSPaolo Bonzini { 196cd0c6f47SBenjamin Herrenschmidt CPUPPCState *env = &cpu->env; 1979f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 198c6404adeSDavid Gibson target_ulong ptex = args[1]; 1999f64bd8aSPaolo Bonzini target_ulong avpn = args[2]; 200a3801402SStefan Weil RemoveResult ret; 2019f64bd8aSPaolo Bonzini 202c6404adeSDavid Gibson ret = remove_hpte(cpu, ptex, avpn, flags, 2039f64bd8aSPaolo Bonzini &args[0], &args[1]); 2049f64bd8aSPaolo Bonzini 2059f64bd8aSPaolo Bonzini switch (ret) { 2069f64bd8aSPaolo Bonzini case REMOVE_SUCCESS: 207e3cffe6fSNikunj A Dadhania check_tlb_flush(env, true); 2089f64bd8aSPaolo Bonzini return H_SUCCESS; 2099f64bd8aSPaolo Bonzini 2109f64bd8aSPaolo Bonzini case REMOVE_NOT_FOUND: 2119f64bd8aSPaolo Bonzini return H_NOT_FOUND; 2129f64bd8aSPaolo Bonzini 2139f64bd8aSPaolo Bonzini case REMOVE_PARM: 2149f64bd8aSPaolo Bonzini return H_PARAMETER; 2159f64bd8aSPaolo Bonzini 2169f64bd8aSPaolo Bonzini case REMOVE_HW: 2179f64bd8aSPaolo Bonzini return H_HARDWARE; 2189f64bd8aSPaolo Bonzini } 2199f64bd8aSPaolo Bonzini 2209a39970dSStefan Weil g_assert_not_reached(); 2219f64bd8aSPaolo Bonzini } 2229f64bd8aSPaolo Bonzini 2239f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 2249f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 2259f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 2269f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_END 0xc000000000000000ULL 2279f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 2289f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 2299f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 2309f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 2319f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_HW 0x3000000000000000ULL 2329f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 2339f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 2349f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 2359f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 2369f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 2379f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 2389f64bd8aSPaolo Bonzini 2399f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_MAX_BATCH 4 2409f64bd8aSPaolo Bonzini 24128e02042SDavid Gibson static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 2429f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 2439f64bd8aSPaolo Bonzini { 244cd0c6f47SBenjamin Herrenschmidt CPUPPCState *env = &cpu->env; 2459f64bd8aSPaolo Bonzini int i; 246cd0c6f47SBenjamin Herrenschmidt target_ulong rc = H_SUCCESS; 2479f64bd8aSPaolo Bonzini 2489f64bd8aSPaolo Bonzini for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 2499f64bd8aSPaolo Bonzini target_ulong *tsh = &args[i*2]; 2509f64bd8aSPaolo Bonzini target_ulong tsl = args[i*2 + 1]; 2519f64bd8aSPaolo Bonzini target_ulong v, r, ret; 2529f64bd8aSPaolo Bonzini 2539f64bd8aSPaolo Bonzini if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 2549f64bd8aSPaolo Bonzini break; 2559f64bd8aSPaolo Bonzini } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 2569f64bd8aSPaolo Bonzini return H_PARAMETER; 2579f64bd8aSPaolo Bonzini } 2589f64bd8aSPaolo Bonzini 2599f64bd8aSPaolo Bonzini *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 2609f64bd8aSPaolo Bonzini *tsh |= H_BULK_REMOVE_RESPONSE; 2619f64bd8aSPaolo Bonzini 2629f64bd8aSPaolo Bonzini if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 2639f64bd8aSPaolo Bonzini *tsh |= H_BULK_REMOVE_PARM; 2649f64bd8aSPaolo Bonzini return H_PARAMETER; 2659f64bd8aSPaolo Bonzini } 2669f64bd8aSPaolo Bonzini 2677ef23068SDavid Gibson ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, 2689f64bd8aSPaolo Bonzini (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 2699f64bd8aSPaolo Bonzini &v, &r); 2709f64bd8aSPaolo Bonzini 2719f64bd8aSPaolo Bonzini *tsh |= ret << 60; 2729f64bd8aSPaolo Bonzini 2739f64bd8aSPaolo Bonzini switch (ret) { 2749f64bd8aSPaolo Bonzini case REMOVE_SUCCESS: 275d5aea6f3SDavid Gibson *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 2769f64bd8aSPaolo Bonzini break; 2779f64bd8aSPaolo Bonzini 2789f64bd8aSPaolo Bonzini case REMOVE_PARM: 279cd0c6f47SBenjamin Herrenschmidt rc = H_PARAMETER; 280cd0c6f47SBenjamin Herrenschmidt goto exit; 2819f64bd8aSPaolo Bonzini 2829f64bd8aSPaolo Bonzini case REMOVE_HW: 283cd0c6f47SBenjamin Herrenschmidt rc = H_HARDWARE; 284cd0c6f47SBenjamin Herrenschmidt goto exit; 2859f64bd8aSPaolo Bonzini } 2869f64bd8aSPaolo Bonzini } 287cd0c6f47SBenjamin Herrenschmidt exit: 288e3cffe6fSNikunj A Dadhania check_tlb_flush(env, true); 2899f64bd8aSPaolo Bonzini 290cd0c6f47SBenjamin Herrenschmidt return rc; 2919f64bd8aSPaolo Bonzini } 2929f64bd8aSPaolo Bonzini 29328e02042SDavid Gibson static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr, 2949f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 2959f64bd8aSPaolo Bonzini { 2969f64bd8aSPaolo Bonzini CPUPPCState *env = &cpu->env; 2979f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 298c6404adeSDavid Gibson target_ulong ptex = args[1]; 2999f64bd8aSPaolo Bonzini target_ulong avpn = args[2]; 3007222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 30161a36c9bSDavid Gibson target_ulong v, r; 3029f64bd8aSPaolo Bonzini 303c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 3049f64bd8aSPaolo Bonzini return H_PARAMETER; 3059f64bd8aSPaolo Bonzini } 3069f64bd8aSPaolo Bonzini 3077222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 3087222b94aSDavid Gibson v = ppc_hash64_hpte0(cpu, hptes, 0); 3097222b94aSDavid Gibson r = ppc_hash64_hpte1(cpu, hptes, 0); 3107222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 3119f64bd8aSPaolo Bonzini 312d5aea6f3SDavid Gibson if ((v & HPTE64_V_VALID) == 0 || 3139f64bd8aSPaolo Bonzini ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 3149f64bd8aSPaolo Bonzini return H_NOT_FOUND; 3159f64bd8aSPaolo Bonzini } 3169f64bd8aSPaolo Bonzini 317d5aea6f3SDavid Gibson r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 318d5aea6f3SDavid Gibson HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 319d5aea6f3SDavid Gibson r |= (flags << 55) & HPTE64_R_PP0; 320d5aea6f3SDavid Gibson r |= (flags << 48) & HPTE64_R_KEY_HI; 321d5aea6f3SDavid Gibson r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 322c6404adeSDavid Gibson ppc_hash64_store_hpte(cpu, ptex, 3233f94170bSAneesh Kumar K.V (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); 324c6404adeSDavid Gibson ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 325d76ab5e1SNikunj A Dadhania /* Flush the tlb */ 326d76ab5e1SNikunj A Dadhania check_tlb_flush(env, true); 3279f64bd8aSPaolo Bonzini /* Don't need a memory barrier, due to qemu's global lock */ 328c6404adeSDavid Gibson ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); 3299f64bd8aSPaolo Bonzini return H_SUCCESS; 3309f64bd8aSPaolo Bonzini } 3319f64bd8aSPaolo Bonzini 33228e02042SDavid Gibson static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr, 333fa388916SAnthony Liguori target_ulong opcode, target_ulong *args) 334fa388916SAnthony Liguori { 335fa388916SAnthony Liguori target_ulong flags = args[0]; 336c6404adeSDavid Gibson target_ulong ptex = args[1]; 337fa388916SAnthony Liguori uint8_t *hpte; 338fa388916SAnthony Liguori int i, ridx, n_entries = 1; 339fa388916SAnthony Liguori 340c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 341fa388916SAnthony Liguori return H_PARAMETER; 342fa388916SAnthony Liguori } 343fa388916SAnthony Liguori 344fa388916SAnthony Liguori if (flags & H_READ_4) { 345fa388916SAnthony Liguori /* Clear the two low order bits */ 346c6404adeSDavid Gibson ptex &= ~(3ULL); 347fa388916SAnthony Liguori n_entries = 4; 348fa388916SAnthony Liguori } 349fa388916SAnthony Liguori 350e57ca75cSDavid Gibson hpte = spapr->htab + (ptex * HASH_PTE_SIZE_64); 351fa388916SAnthony Liguori 352fa388916SAnthony Liguori for (i = 0, ridx = 0; i < n_entries; i++) { 353fa388916SAnthony Liguori args[ridx++] = ldq_p(hpte); 354fa388916SAnthony Liguori args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); 355fa388916SAnthony Liguori hpte += HASH_PTE_SIZE_64; 356fa388916SAnthony Liguori } 357fa388916SAnthony Liguori 358fa388916SAnthony Liguori return H_SUCCESS; 359fa388916SAnthony Liguori } 360fa388916SAnthony Liguori 3610b0b8310SDavid Gibson struct sPAPRPendingHPT { 3620b0b8310SDavid Gibson /* These fields are read-only after initialization */ 3630b0b8310SDavid Gibson int shift; 3640b0b8310SDavid Gibson QemuThread thread; 3650b0b8310SDavid Gibson 3660b0b8310SDavid Gibson /* These fields are protected by the BQL */ 3670b0b8310SDavid Gibson bool complete; 3680b0b8310SDavid Gibson 3690b0b8310SDavid Gibson /* These fields are private to the preparation thread if 3700b0b8310SDavid Gibson * !complete, otherwise protected by the BQL */ 3710b0b8310SDavid Gibson int ret; 3720b0b8310SDavid Gibson void *hpt; 3730b0b8310SDavid Gibson }; 3740b0b8310SDavid Gibson 3750b0b8310SDavid Gibson static void free_pending_hpt(sPAPRPendingHPT *pending) 3760b0b8310SDavid Gibson { 3770b0b8310SDavid Gibson if (pending->hpt) { 3780b0b8310SDavid Gibson qemu_vfree(pending->hpt); 3790b0b8310SDavid Gibson } 3800b0b8310SDavid Gibson 3810b0b8310SDavid Gibson g_free(pending); 3820b0b8310SDavid Gibson } 3830b0b8310SDavid Gibson 3840b0b8310SDavid Gibson static void *hpt_prepare_thread(void *opaque) 3850b0b8310SDavid Gibson { 3860b0b8310SDavid Gibson sPAPRPendingHPT *pending = opaque; 3870b0b8310SDavid Gibson size_t size = 1ULL << pending->shift; 3880b0b8310SDavid Gibson 3890b0b8310SDavid Gibson pending->hpt = qemu_memalign(size, size); 3900b0b8310SDavid Gibson if (pending->hpt) { 3910b0b8310SDavid Gibson memset(pending->hpt, 0, size); 3920b0b8310SDavid Gibson pending->ret = H_SUCCESS; 3930b0b8310SDavid Gibson } else { 3940b0b8310SDavid Gibson pending->ret = H_NO_MEM; 3950b0b8310SDavid Gibson } 3960b0b8310SDavid Gibson 3970b0b8310SDavid Gibson qemu_mutex_lock_iothread(); 3980b0b8310SDavid Gibson 3990b0b8310SDavid Gibson if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) { 4000b0b8310SDavid Gibson /* Ready to go */ 4010b0b8310SDavid Gibson pending->complete = true; 4020b0b8310SDavid Gibson } else { 4030b0b8310SDavid Gibson /* We've been cancelled, clean ourselves up */ 4040b0b8310SDavid Gibson free_pending_hpt(pending); 4050b0b8310SDavid Gibson } 4060b0b8310SDavid Gibson 4070b0b8310SDavid Gibson qemu_mutex_unlock_iothread(); 4080b0b8310SDavid Gibson return NULL; 4090b0b8310SDavid Gibson } 4100b0b8310SDavid Gibson 4110b0b8310SDavid Gibson /* Must be called with BQL held */ 4120b0b8310SDavid Gibson static void cancel_hpt_prepare(sPAPRMachineState *spapr) 4130b0b8310SDavid Gibson { 4140b0b8310SDavid Gibson sPAPRPendingHPT *pending = spapr->pending_hpt; 4150b0b8310SDavid Gibson 4160b0b8310SDavid Gibson /* Let the thread know it's cancelled */ 4170b0b8310SDavid Gibson spapr->pending_hpt = NULL; 4180b0b8310SDavid Gibson 4190b0b8310SDavid Gibson if (!pending) { 4200b0b8310SDavid Gibson /* Nothing to do */ 4210b0b8310SDavid Gibson return; 4220b0b8310SDavid Gibson } 4230b0b8310SDavid Gibson 4240b0b8310SDavid Gibson if (!pending->complete) { 4250b0b8310SDavid Gibson /* thread will clean itself up */ 4260b0b8310SDavid Gibson return; 4270b0b8310SDavid Gibson } 4280b0b8310SDavid Gibson 4290b0b8310SDavid Gibson free_pending_hpt(pending); 4300b0b8310SDavid Gibson } 4310b0b8310SDavid Gibson 432b55d295eSDavid Gibson /* Convert a return code from the KVM ioctl()s implementing resize HPT 433b55d295eSDavid Gibson * into a PAPR hypercall return code */ 434b55d295eSDavid Gibson static target_ulong resize_hpt_convert_rc(int ret) 435b55d295eSDavid Gibson { 436b55d295eSDavid Gibson if (ret >= 100000) { 437b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_100_SEC; 438b55d295eSDavid Gibson } else if (ret >= 10000) { 439b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_10_SEC; 440b55d295eSDavid Gibson } else if (ret >= 1000) { 441b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_1_SEC; 442b55d295eSDavid Gibson } else if (ret >= 100) { 443b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 444b55d295eSDavid Gibson } else if (ret >= 10) { 445b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_10_MSEC; 446b55d295eSDavid Gibson } else if (ret > 0) { 447b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_1_MSEC; 448b55d295eSDavid Gibson } 449b55d295eSDavid Gibson 450b55d295eSDavid Gibson switch (ret) { 451b55d295eSDavid Gibson case 0: 452b55d295eSDavid Gibson return H_SUCCESS; 453b55d295eSDavid Gibson case -EPERM: 454b55d295eSDavid Gibson return H_AUTHORITY; 455b55d295eSDavid Gibson case -EINVAL: 456b55d295eSDavid Gibson return H_PARAMETER; 457b55d295eSDavid Gibson case -ENXIO: 458b55d295eSDavid Gibson return H_CLOSED; 459b55d295eSDavid Gibson case -ENOSPC: 460b55d295eSDavid Gibson return H_PTEG_FULL; 461b55d295eSDavid Gibson case -EBUSY: 462b55d295eSDavid Gibson return H_BUSY; 463b55d295eSDavid Gibson case -ENOMEM: 464b55d295eSDavid Gibson return H_NO_MEM; 465b55d295eSDavid Gibson default: 466b55d295eSDavid Gibson return H_HARDWARE; 467b55d295eSDavid Gibson } 468b55d295eSDavid Gibson } 469b55d295eSDavid Gibson 47030f4b05bSDavid Gibson static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 47130f4b05bSDavid Gibson sPAPRMachineState *spapr, 47230f4b05bSDavid Gibson target_ulong opcode, 47330f4b05bSDavid Gibson target_ulong *args) 47430f4b05bSDavid Gibson { 47530f4b05bSDavid Gibson target_ulong flags = args[0]; 4760b0b8310SDavid Gibson int shift = args[1]; 4770b0b8310SDavid Gibson sPAPRPendingHPT *pending = spapr->pending_hpt; 478db50f280SDavid Gibson uint64_t current_ram_size; 479b55d295eSDavid Gibson int rc; 48030f4b05bSDavid Gibson 48130f4b05bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 48230f4b05bSDavid Gibson return H_AUTHORITY; 48330f4b05bSDavid Gibson } 48430f4b05bSDavid Gibson 4850b0b8310SDavid Gibson if (!spapr->htab_shift) { 4860b0b8310SDavid Gibson /* Radix guest, no HPT */ 4870b0b8310SDavid Gibson return H_NOT_AVAILABLE; 4880b0b8310SDavid Gibson } 4890b0b8310SDavid Gibson 49030f4b05bSDavid Gibson trace_spapr_h_resize_hpt_prepare(flags, shift); 4910b0b8310SDavid Gibson 4920b0b8310SDavid Gibson if (flags != 0) { 4930b0b8310SDavid Gibson return H_PARAMETER; 4940b0b8310SDavid Gibson } 4950b0b8310SDavid Gibson 4960b0b8310SDavid Gibson if (shift && ((shift < 18) || (shift > 46))) { 4970b0b8310SDavid Gibson return H_PARAMETER; 4980b0b8310SDavid Gibson } 4990b0b8310SDavid Gibson 500db50f280SDavid Gibson current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 5010b0b8310SDavid Gibson 5020b0b8310SDavid Gibson /* We only allow the guest to allocate an HPT one order above what 5030b0b8310SDavid Gibson * we'd normally give them (to stop a small guest claiming a huge 5040b0b8310SDavid Gibson * chunk of resources in the HPT */ 5050b0b8310SDavid Gibson if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 5060b0b8310SDavid Gibson return H_RESOURCE; 5070b0b8310SDavid Gibson } 5080b0b8310SDavid Gibson 509b55d295eSDavid Gibson rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 510b55d295eSDavid Gibson if (rc != -ENOSYS) { 511b55d295eSDavid Gibson return resize_hpt_convert_rc(rc); 512b55d295eSDavid Gibson } 513b55d295eSDavid Gibson 5140b0b8310SDavid Gibson if (pending) { 5150b0b8310SDavid Gibson /* something already in progress */ 5160b0b8310SDavid Gibson if (pending->shift == shift) { 5170b0b8310SDavid Gibson /* and it's suitable */ 5180b0b8310SDavid Gibson if (pending->complete) { 5190b0b8310SDavid Gibson return pending->ret; 5200b0b8310SDavid Gibson } else { 5210b0b8310SDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 5220b0b8310SDavid Gibson } 5230b0b8310SDavid Gibson } 5240b0b8310SDavid Gibson 5250b0b8310SDavid Gibson /* not suitable, cancel and replace */ 5260b0b8310SDavid Gibson cancel_hpt_prepare(spapr); 5270b0b8310SDavid Gibson } 5280b0b8310SDavid Gibson 5290b0b8310SDavid Gibson if (!shift) { 5300b0b8310SDavid Gibson /* nothing to do */ 5310b0b8310SDavid Gibson return H_SUCCESS; 5320b0b8310SDavid Gibson } 5330b0b8310SDavid Gibson 5340b0b8310SDavid Gibson /* start new prepare */ 5350b0b8310SDavid Gibson 5360b0b8310SDavid Gibson pending = g_new0(sPAPRPendingHPT, 1); 5370b0b8310SDavid Gibson pending->shift = shift; 5380b0b8310SDavid Gibson pending->ret = H_HARDWARE; 5390b0b8310SDavid Gibson 5400b0b8310SDavid Gibson qemu_thread_create(&pending->thread, "sPAPR HPT prepare", 5410b0b8310SDavid Gibson hpt_prepare_thread, pending, QEMU_THREAD_DETACHED); 5420b0b8310SDavid Gibson 5430b0b8310SDavid Gibson spapr->pending_hpt = pending; 5440b0b8310SDavid Gibson 5450b0b8310SDavid Gibson /* In theory we could estimate the time more accurately based on 5460b0b8310SDavid Gibson * the new size, but there's not much point */ 5470b0b8310SDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 5480b0b8310SDavid Gibson } 5490b0b8310SDavid Gibson 5500b0b8310SDavid Gibson static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot) 5510b0b8310SDavid Gibson { 5520b0b8310SDavid Gibson uint8_t *addr = htab; 5530b0b8310SDavid Gibson 5540b0b8310SDavid Gibson addr += pteg * HASH_PTEG_SIZE_64; 5550b0b8310SDavid Gibson addr += slot * HASH_PTE_SIZE_64; 5560b0b8310SDavid Gibson return ldq_p(addr); 5570b0b8310SDavid Gibson } 5580b0b8310SDavid Gibson 5590b0b8310SDavid Gibson static void new_hpte_store(void *htab, uint64_t pteg, int slot, 5600b0b8310SDavid Gibson uint64_t pte0, uint64_t pte1) 5610b0b8310SDavid Gibson { 5620b0b8310SDavid Gibson uint8_t *addr = htab; 5630b0b8310SDavid Gibson 5640b0b8310SDavid Gibson addr += pteg * HASH_PTEG_SIZE_64; 5650b0b8310SDavid Gibson addr += slot * HASH_PTE_SIZE_64; 5660b0b8310SDavid Gibson 5670b0b8310SDavid Gibson stq_p(addr, pte0); 5680b0b8310SDavid Gibson stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1); 5690b0b8310SDavid Gibson } 5700b0b8310SDavid Gibson 5710b0b8310SDavid Gibson static int rehash_hpte(PowerPCCPU *cpu, 5720b0b8310SDavid Gibson const ppc_hash_pte64_t *hptes, 5730b0b8310SDavid Gibson void *old_hpt, uint64_t oldsize, 5740b0b8310SDavid Gibson void *new_hpt, uint64_t newsize, 5750b0b8310SDavid Gibson uint64_t pteg, int slot) 5760b0b8310SDavid Gibson { 5770b0b8310SDavid Gibson uint64_t old_hash_mask = (oldsize >> 7) - 1; 5780b0b8310SDavid Gibson uint64_t new_hash_mask = (newsize >> 7) - 1; 5790b0b8310SDavid Gibson target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot); 5800b0b8310SDavid Gibson target_ulong pte1; 5810b0b8310SDavid Gibson uint64_t avpn; 5820b0b8310SDavid Gibson unsigned base_pg_shift; 5830b0b8310SDavid Gibson uint64_t hash, new_pteg, replace_pte0; 5840b0b8310SDavid Gibson 5850b0b8310SDavid Gibson if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) { 5860b0b8310SDavid Gibson return H_SUCCESS; 5870b0b8310SDavid Gibson } 5880b0b8310SDavid Gibson 5890b0b8310SDavid Gibson pte1 = ppc_hash64_hpte1(cpu, hptes, slot); 5900b0b8310SDavid Gibson 5910b0b8310SDavid Gibson base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1); 5920b0b8310SDavid Gibson assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */ 5930b0b8310SDavid Gibson avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23); 5940b0b8310SDavid Gibson 5950b0b8310SDavid Gibson if (pte0 & HPTE64_V_SECONDARY) { 5960b0b8310SDavid Gibson pteg = ~pteg; 5970b0b8310SDavid Gibson } 5980b0b8310SDavid Gibson 5990b0b8310SDavid Gibson if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) { 6000b0b8310SDavid Gibson uint64_t offset, vsid; 6010b0b8310SDavid Gibson 6020b0b8310SDavid Gibson /* We only have 28 - 23 bits of offset in avpn */ 6030b0b8310SDavid Gibson offset = (avpn & 0x1f) << 23; 6040b0b8310SDavid Gibson vsid = avpn >> 5; 6050b0b8310SDavid Gibson /* We can find more bits from the pteg value */ 6060b0b8310SDavid Gibson if (base_pg_shift < 23) { 6070b0b8310SDavid Gibson offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift; 6080b0b8310SDavid Gibson } 6090b0b8310SDavid Gibson 6100b0b8310SDavid Gibson hash = vsid ^ (offset >> base_pg_shift); 6110b0b8310SDavid Gibson } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) { 6120b0b8310SDavid Gibson uint64_t offset, vsid; 6130b0b8310SDavid Gibson 6140b0b8310SDavid Gibson /* We only have 40 - 23 bits of seg_off in avpn */ 6150b0b8310SDavid Gibson offset = (avpn & 0x1ffff) << 23; 6160b0b8310SDavid Gibson vsid = avpn >> 17; 6170b0b8310SDavid Gibson if (base_pg_shift < 23) { 6180b0b8310SDavid Gibson offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask) 6190b0b8310SDavid Gibson << base_pg_shift; 6200b0b8310SDavid Gibson } 6210b0b8310SDavid Gibson 6220b0b8310SDavid Gibson hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift); 6230b0b8310SDavid Gibson } else { 6240b0b8310SDavid Gibson error_report("rehash_pte: Bad segment size in HPTE"); 62530f4b05bSDavid Gibson return H_HARDWARE; 62630f4b05bSDavid Gibson } 62730f4b05bSDavid Gibson 6280b0b8310SDavid Gibson new_pteg = hash & new_hash_mask; 6290b0b8310SDavid Gibson if (pte0 & HPTE64_V_SECONDARY) { 6300b0b8310SDavid Gibson assert(~pteg == (hash & old_hash_mask)); 6310b0b8310SDavid Gibson new_pteg = ~new_pteg; 6320b0b8310SDavid Gibson } else { 6330b0b8310SDavid Gibson assert(pteg == (hash & old_hash_mask)); 6340b0b8310SDavid Gibson } 6350b0b8310SDavid Gibson assert((oldsize != newsize) || (pteg == new_pteg)); 6360b0b8310SDavid Gibson replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot); 6370b0b8310SDavid Gibson /* 6380b0b8310SDavid Gibson * Strictly speaking, we don't need all these tests, since we only 6390b0b8310SDavid Gibson * ever rehash bolted HPTEs. We might in future handle non-bolted 6400b0b8310SDavid Gibson * HPTEs, though so make the logic correct for those cases as 6410b0b8310SDavid Gibson * well. 6420b0b8310SDavid Gibson */ 6430b0b8310SDavid Gibson if (replace_pte0 & HPTE64_V_VALID) { 6440b0b8310SDavid Gibson assert(newsize < oldsize); 6450b0b8310SDavid Gibson if (replace_pte0 & HPTE64_V_BOLTED) { 6460b0b8310SDavid Gibson if (pte0 & HPTE64_V_BOLTED) { 6470b0b8310SDavid Gibson /* Bolted collision, nothing we can do */ 6480b0b8310SDavid Gibson return H_PTEG_FULL; 6490b0b8310SDavid Gibson } else { 6500b0b8310SDavid Gibson /* Discard this hpte */ 6510b0b8310SDavid Gibson return H_SUCCESS; 6520b0b8310SDavid Gibson } 6530b0b8310SDavid Gibson } 6540b0b8310SDavid Gibson } 6550b0b8310SDavid Gibson 6560b0b8310SDavid Gibson new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1); 6570b0b8310SDavid Gibson return H_SUCCESS; 6580b0b8310SDavid Gibson } 6590b0b8310SDavid Gibson 6600b0b8310SDavid Gibson static int rehash_hpt(PowerPCCPU *cpu, 6610b0b8310SDavid Gibson void *old_hpt, uint64_t oldsize, 6620b0b8310SDavid Gibson void *new_hpt, uint64_t newsize) 6630b0b8310SDavid Gibson { 6640b0b8310SDavid Gibson uint64_t n_ptegs = oldsize >> 7; 6650b0b8310SDavid Gibson uint64_t pteg; 6660b0b8310SDavid Gibson int slot; 6670b0b8310SDavid Gibson int rc; 6680b0b8310SDavid Gibson 6690b0b8310SDavid Gibson for (pteg = 0; pteg < n_ptegs; pteg++) { 6700b0b8310SDavid Gibson hwaddr ptex = pteg * HPTES_PER_GROUP; 6710b0b8310SDavid Gibson const ppc_hash_pte64_t *hptes 6720b0b8310SDavid Gibson = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 6730b0b8310SDavid Gibson 6740b0b8310SDavid Gibson if (!hptes) { 6750b0b8310SDavid Gibson return H_HARDWARE; 6760b0b8310SDavid Gibson } 6770b0b8310SDavid Gibson 6780b0b8310SDavid Gibson for (slot = 0; slot < HPTES_PER_GROUP; slot++) { 6790b0b8310SDavid Gibson rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize, 6800b0b8310SDavid Gibson pteg, slot); 6810b0b8310SDavid Gibson if (rc != H_SUCCESS) { 6820b0b8310SDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 6830b0b8310SDavid Gibson return rc; 6840b0b8310SDavid Gibson } 6850b0b8310SDavid Gibson } 6860b0b8310SDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 6870b0b8310SDavid Gibson } 6880b0b8310SDavid Gibson 6890b0b8310SDavid Gibson return H_SUCCESS; 6900b0b8310SDavid Gibson } 6910b0b8310SDavid Gibson 6921ec26c75SGreg Kurz static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 6931ec26c75SGreg Kurz { 6941ec26c75SGreg Kurz int ret; 6951ec26c75SGreg Kurz 6961ec26c75SGreg Kurz cpu_synchronize_state(cs); 6971ec26c75SGreg Kurz 6981ec26c75SGreg Kurz ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 6991ec26c75SGreg Kurz if (ret < 0) { 7001ec26c75SGreg Kurz error_report("failed to push sregs to KVM: %s", strerror(-ret)); 7011ec26c75SGreg Kurz exit(1); 7021ec26c75SGreg Kurz } 7031ec26c75SGreg Kurz } 7041ec26c75SGreg Kurz 7051ec26c75SGreg Kurz static void push_sregs_to_kvm_pr(sPAPRMachineState *spapr) 7061ec26c75SGreg Kurz { 7071ec26c75SGreg Kurz CPUState *cs; 7081ec26c75SGreg Kurz 7091ec26c75SGreg Kurz /* 7101ec26c75SGreg Kurz * This is a hack for the benefit of KVM PR - it abuses the SDR1 7111ec26c75SGreg Kurz * slot in kvm_sregs to communicate the userspace address of the 7121ec26c75SGreg Kurz * HPT 7131ec26c75SGreg Kurz */ 7141ec26c75SGreg Kurz if (!kvm_enabled() || !spapr->htab) { 7151ec26c75SGreg Kurz return; 7161ec26c75SGreg Kurz } 7171ec26c75SGreg Kurz 7181ec26c75SGreg Kurz CPU_FOREACH(cs) { 7191ec26c75SGreg Kurz run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 7201ec26c75SGreg Kurz } 7211ec26c75SGreg Kurz } 7221ec26c75SGreg Kurz 72330f4b05bSDavid Gibson static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 72430f4b05bSDavid Gibson sPAPRMachineState *spapr, 72530f4b05bSDavid Gibson target_ulong opcode, 72630f4b05bSDavid Gibson target_ulong *args) 72730f4b05bSDavid Gibson { 72830f4b05bSDavid Gibson target_ulong flags = args[0]; 72930f4b05bSDavid Gibson target_ulong shift = args[1]; 7300b0b8310SDavid Gibson sPAPRPendingHPT *pending = spapr->pending_hpt; 7310b0b8310SDavid Gibson int rc; 7320b0b8310SDavid Gibson size_t newsize; 73330f4b05bSDavid Gibson 73430f4b05bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 73530f4b05bSDavid Gibson return H_AUTHORITY; 73630f4b05bSDavid Gibson } 73730f4b05bSDavid Gibson 73894789567SDaniel Henrique Barboza if (!spapr->htab_shift) { 73994789567SDaniel Henrique Barboza /* Radix guest, no HPT */ 74094789567SDaniel Henrique Barboza return H_NOT_AVAILABLE; 74194789567SDaniel Henrique Barboza } 74294789567SDaniel Henrique Barboza 74330f4b05bSDavid Gibson trace_spapr_h_resize_hpt_commit(flags, shift); 7440b0b8310SDavid Gibson 745b55d295eSDavid Gibson rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 746b55d295eSDavid Gibson if (rc != -ENOSYS) { 74794789567SDaniel Henrique Barboza rc = resize_hpt_convert_rc(rc); 74894789567SDaniel Henrique Barboza if (rc == H_SUCCESS) { 74994789567SDaniel Henrique Barboza /* Need to set the new htab_shift in the machine state */ 75094789567SDaniel Henrique Barboza spapr->htab_shift = shift; 75194789567SDaniel Henrique Barboza } 75294789567SDaniel Henrique Barboza return rc; 753b55d295eSDavid Gibson } 754b55d295eSDavid Gibson 7550b0b8310SDavid Gibson if (flags != 0) { 7560b0b8310SDavid Gibson return H_PARAMETER; 7570b0b8310SDavid Gibson } 7580b0b8310SDavid Gibson 7590b0b8310SDavid Gibson if (!pending || (pending->shift != shift)) { 7600b0b8310SDavid Gibson /* no matching prepare */ 7610b0b8310SDavid Gibson return H_CLOSED; 7620b0b8310SDavid Gibson } 7630b0b8310SDavid Gibson 7640b0b8310SDavid Gibson if (!pending->complete) { 7650b0b8310SDavid Gibson /* prepare has not completed */ 7660b0b8310SDavid Gibson return H_BUSY; 7670b0b8310SDavid Gibson } 7680b0b8310SDavid Gibson 7690b0b8310SDavid Gibson /* Shouldn't have got past PREPARE without an HPT */ 7700b0b8310SDavid Gibson g_assert(spapr->htab_shift); 7710b0b8310SDavid Gibson 7720b0b8310SDavid Gibson newsize = 1ULL << pending->shift; 7730b0b8310SDavid Gibson rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr), 7740b0b8310SDavid Gibson pending->hpt, newsize); 7750b0b8310SDavid Gibson if (rc == H_SUCCESS) { 7760b0b8310SDavid Gibson qemu_vfree(spapr->htab); 7770b0b8310SDavid Gibson spapr->htab = pending->hpt; 7780b0b8310SDavid Gibson spapr->htab_shift = pending->shift; 7790b0b8310SDavid Gibson 7801ec26c75SGreg Kurz push_sregs_to_kvm_pr(spapr); 781b55d295eSDavid Gibson 7820b0b8310SDavid Gibson pending->hpt = NULL; /* so it's not free()d */ 7830b0b8310SDavid Gibson } 7840b0b8310SDavid Gibson 7850b0b8310SDavid Gibson /* Clean up */ 7860b0b8310SDavid Gibson spapr->pending_hpt = NULL; 7870b0b8310SDavid Gibson free_pending_hpt(pending); 7880b0b8310SDavid Gibson 7890b0b8310SDavid Gibson return rc; 79030f4b05bSDavid Gibson } 79130f4b05bSDavid Gibson 792423576f7SThomas Huth static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr, 793423576f7SThomas Huth target_ulong opcode, target_ulong *args) 794423576f7SThomas Huth { 795423576f7SThomas Huth cpu_synchronize_state(CPU(cpu)); 796423576f7SThomas Huth cpu->env.spr[SPR_SPRG0] = args[0]; 797423576f7SThomas Huth 798423576f7SThomas Huth return H_SUCCESS; 799423576f7SThomas Huth } 800423576f7SThomas Huth 80128e02042SDavid Gibson static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 8029f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 8039f64bd8aSPaolo Bonzini { 804af08a58fSThomas Huth if (!has_spr(cpu, SPR_DABR)) { 805af08a58fSThomas Huth return H_HARDWARE; /* DABR register not available */ 806af08a58fSThomas Huth } 807af08a58fSThomas Huth cpu_synchronize_state(CPU(cpu)); 808af08a58fSThomas Huth 809af08a58fSThomas Huth if (has_spr(cpu, SPR_DABRX)) { 810af08a58fSThomas Huth cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 811af08a58fSThomas Huth } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 812af08a58fSThomas Huth return H_RESERVED_DABR; 813af08a58fSThomas Huth } 814af08a58fSThomas Huth 815af08a58fSThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 816af08a58fSThomas Huth return H_SUCCESS; 8179f64bd8aSPaolo Bonzini } 8189f64bd8aSPaolo Bonzini 819e49ff266SThomas Huth static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 820e49ff266SThomas Huth target_ulong opcode, target_ulong *args) 821e49ff266SThomas Huth { 822e49ff266SThomas Huth target_ulong dabrx = args[1]; 823e49ff266SThomas Huth 824e49ff266SThomas Huth if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { 825e49ff266SThomas Huth return H_HARDWARE; 826e49ff266SThomas Huth } 827e49ff266SThomas Huth 828e49ff266SThomas Huth if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 829e49ff266SThomas Huth || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 830e49ff266SThomas Huth return H_PARAMETER; 831e49ff266SThomas Huth } 832e49ff266SThomas Huth 833e49ff266SThomas Huth cpu_synchronize_state(CPU(cpu)); 834e49ff266SThomas Huth cpu->env.spr[SPR_DABRX] = dabrx; 835e49ff266SThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 836e49ff266SThomas Huth 837e49ff266SThomas Huth return H_SUCCESS; 838e49ff266SThomas Huth } 839e49ff266SThomas Huth 8403240dd9aSThomas Huth static target_ulong h_page_init(PowerPCCPU *cpu, sPAPRMachineState *spapr, 8413240dd9aSThomas Huth target_ulong opcode, target_ulong *args) 8423240dd9aSThomas Huth { 8433240dd9aSThomas Huth target_ulong flags = args[0]; 8443240dd9aSThomas Huth hwaddr dst = args[1]; 8453240dd9aSThomas Huth hwaddr src = args[2]; 8463240dd9aSThomas Huth hwaddr len = TARGET_PAGE_SIZE; 8473240dd9aSThomas Huth uint8_t *pdst, *psrc; 8483240dd9aSThomas Huth target_long ret = H_SUCCESS; 8493240dd9aSThomas Huth 8503240dd9aSThomas Huth if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 8513240dd9aSThomas Huth | H_COPY_PAGE | H_ZERO_PAGE)) { 8523240dd9aSThomas Huth qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 8533240dd9aSThomas Huth flags); 8543240dd9aSThomas Huth return H_PARAMETER; 8553240dd9aSThomas Huth } 8563240dd9aSThomas Huth 8573240dd9aSThomas Huth /* Map-in destination */ 8583240dd9aSThomas Huth if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 8593240dd9aSThomas Huth return H_PARAMETER; 8603240dd9aSThomas Huth } 8613240dd9aSThomas Huth pdst = cpu_physical_memory_map(dst, &len, 1); 8623240dd9aSThomas Huth if (!pdst || len != TARGET_PAGE_SIZE) { 8633240dd9aSThomas Huth return H_PARAMETER; 8643240dd9aSThomas Huth } 8653240dd9aSThomas Huth 8663240dd9aSThomas Huth if (flags & H_COPY_PAGE) { 8673240dd9aSThomas Huth /* Map-in source, copy to destination, and unmap source again */ 8683240dd9aSThomas Huth if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 8693240dd9aSThomas Huth ret = H_PARAMETER; 8703240dd9aSThomas Huth goto unmap_out; 8713240dd9aSThomas Huth } 8723240dd9aSThomas Huth psrc = cpu_physical_memory_map(src, &len, 0); 8733240dd9aSThomas Huth if (!psrc || len != TARGET_PAGE_SIZE) { 8743240dd9aSThomas Huth ret = H_PARAMETER; 8753240dd9aSThomas Huth goto unmap_out; 8763240dd9aSThomas Huth } 8773240dd9aSThomas Huth memcpy(pdst, psrc, len); 8783240dd9aSThomas Huth cpu_physical_memory_unmap(psrc, len, 0, len); 8793240dd9aSThomas Huth } else if (flags & H_ZERO_PAGE) { 8803240dd9aSThomas Huth memset(pdst, 0, len); /* Just clear the destination page */ 8813240dd9aSThomas Huth } 8823240dd9aSThomas Huth 8833240dd9aSThomas Huth if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 8843240dd9aSThomas Huth kvmppc_dcbst_range(cpu, pdst, len); 8853240dd9aSThomas Huth } 8863240dd9aSThomas Huth if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 8873240dd9aSThomas Huth if (kvm_enabled()) { 8883240dd9aSThomas Huth kvmppc_icbi_range(cpu, pdst, len); 8893240dd9aSThomas Huth } else { 8903240dd9aSThomas Huth tb_flush(CPU(cpu)); 8913240dd9aSThomas Huth } 8923240dd9aSThomas Huth } 8933240dd9aSThomas Huth 8943240dd9aSThomas Huth unmap_out: 8953240dd9aSThomas Huth cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 8963240dd9aSThomas Huth return ret; 8973240dd9aSThomas Huth } 8983240dd9aSThomas Huth 8999f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 9009f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 9019f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 9029f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 9039f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 9049f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 9059f64bd8aSPaolo Bonzini 9069f64bd8aSPaolo Bonzini #define VPA_MIN_SIZE 640 9079f64bd8aSPaolo Bonzini #define VPA_SIZE_OFFSET 0x4 9089f64bd8aSPaolo Bonzini #define VPA_SHARED_PROC_OFFSET 0x9 9099f64bd8aSPaolo Bonzini #define VPA_SHARED_PROC_VAL 0x2 9109f64bd8aSPaolo Bonzini 9119f64bd8aSPaolo Bonzini static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) 9129f64bd8aSPaolo Bonzini { 91333276f1bSAndreas Färber CPUState *cs = CPU(ppc_env_get_cpu(env)); 9149f64bd8aSPaolo Bonzini uint16_t size; 9159f64bd8aSPaolo Bonzini uint8_t tmp; 9169f64bd8aSPaolo Bonzini 9179f64bd8aSPaolo Bonzini if (vpa == 0) { 9189f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 9199f64bd8aSPaolo Bonzini return H_HARDWARE; 9209f64bd8aSPaolo Bonzini } 9219f64bd8aSPaolo Bonzini 9229f64bd8aSPaolo Bonzini if (vpa % env->dcache_line_size) { 9239f64bd8aSPaolo Bonzini return H_PARAMETER; 9249f64bd8aSPaolo Bonzini } 9259f64bd8aSPaolo Bonzini /* FIXME: bounds check the address */ 9269f64bd8aSPaolo Bonzini 92741701aa4SEdgar E. Iglesias size = lduw_be_phys(cs->as, vpa + 0x4); 9289f64bd8aSPaolo Bonzini 9299f64bd8aSPaolo Bonzini if (size < VPA_MIN_SIZE) { 9309f64bd8aSPaolo Bonzini return H_PARAMETER; 9319f64bd8aSPaolo Bonzini } 9329f64bd8aSPaolo Bonzini 9339f64bd8aSPaolo Bonzini /* VPA is not allowed to cross a page boundary */ 9349f64bd8aSPaolo Bonzini if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 9359f64bd8aSPaolo Bonzini return H_PARAMETER; 9369f64bd8aSPaolo Bonzini } 9379f64bd8aSPaolo Bonzini 9389f64bd8aSPaolo Bonzini env->vpa_addr = vpa; 9399f64bd8aSPaolo Bonzini 9402c17449bSEdgar E. Iglesias tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); 9419f64bd8aSPaolo Bonzini tmp |= VPA_SHARED_PROC_VAL; 942db3be60dSEdgar E. Iglesias stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 9439f64bd8aSPaolo Bonzini 9449f64bd8aSPaolo Bonzini return H_SUCCESS; 9459f64bd8aSPaolo Bonzini } 9469f64bd8aSPaolo Bonzini 9479f64bd8aSPaolo Bonzini static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) 9489f64bd8aSPaolo Bonzini { 9499f64bd8aSPaolo Bonzini if (env->slb_shadow_addr) { 9509f64bd8aSPaolo Bonzini return H_RESOURCE; 9519f64bd8aSPaolo Bonzini } 9529f64bd8aSPaolo Bonzini 9539f64bd8aSPaolo Bonzini if (env->dtl_addr) { 9549f64bd8aSPaolo Bonzini return H_RESOURCE; 9559f64bd8aSPaolo Bonzini } 9569f64bd8aSPaolo Bonzini 9579f64bd8aSPaolo Bonzini env->vpa_addr = 0; 9589f64bd8aSPaolo Bonzini return H_SUCCESS; 9599f64bd8aSPaolo Bonzini } 9609f64bd8aSPaolo Bonzini 9619f64bd8aSPaolo Bonzini static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) 9629f64bd8aSPaolo Bonzini { 96333276f1bSAndreas Färber CPUState *cs = CPU(ppc_env_get_cpu(env)); 9649f64bd8aSPaolo Bonzini uint32_t size; 9659f64bd8aSPaolo Bonzini 9669f64bd8aSPaolo Bonzini if (addr == 0) { 9679f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 9689f64bd8aSPaolo Bonzini return H_HARDWARE; 9699f64bd8aSPaolo Bonzini } 9709f64bd8aSPaolo Bonzini 971fdfba1a2SEdgar E. Iglesias size = ldl_be_phys(cs->as, addr + 0x4); 9729f64bd8aSPaolo Bonzini if (size < 0x8) { 9739f64bd8aSPaolo Bonzini return H_PARAMETER; 9749f64bd8aSPaolo Bonzini } 9759f64bd8aSPaolo Bonzini 9769f64bd8aSPaolo Bonzini if ((addr / 4096) != ((addr + size - 1) / 4096)) { 9779f64bd8aSPaolo Bonzini return H_PARAMETER; 9789f64bd8aSPaolo Bonzini } 9799f64bd8aSPaolo Bonzini 9809f64bd8aSPaolo Bonzini if (!env->vpa_addr) { 9819f64bd8aSPaolo Bonzini return H_RESOURCE; 9829f64bd8aSPaolo Bonzini } 9839f64bd8aSPaolo Bonzini 9849f64bd8aSPaolo Bonzini env->slb_shadow_addr = addr; 9859f64bd8aSPaolo Bonzini env->slb_shadow_size = size; 9869f64bd8aSPaolo Bonzini 9879f64bd8aSPaolo Bonzini return H_SUCCESS; 9889f64bd8aSPaolo Bonzini } 9899f64bd8aSPaolo Bonzini 9909f64bd8aSPaolo Bonzini static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) 9919f64bd8aSPaolo Bonzini { 9929f64bd8aSPaolo Bonzini env->slb_shadow_addr = 0; 9939f64bd8aSPaolo Bonzini env->slb_shadow_size = 0; 9949f64bd8aSPaolo Bonzini return H_SUCCESS; 9959f64bd8aSPaolo Bonzini } 9969f64bd8aSPaolo Bonzini 9979f64bd8aSPaolo Bonzini static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) 9989f64bd8aSPaolo Bonzini { 99933276f1bSAndreas Färber CPUState *cs = CPU(ppc_env_get_cpu(env)); 10009f64bd8aSPaolo Bonzini uint32_t size; 10019f64bd8aSPaolo Bonzini 10029f64bd8aSPaolo Bonzini if (addr == 0) { 10039f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with DTL at logical 0\n"); 10049f64bd8aSPaolo Bonzini return H_HARDWARE; 10059f64bd8aSPaolo Bonzini } 10069f64bd8aSPaolo Bonzini 1007fdfba1a2SEdgar E. Iglesias size = ldl_be_phys(cs->as, addr + 0x4); 10089f64bd8aSPaolo Bonzini 10099f64bd8aSPaolo Bonzini if (size < 48) { 10109f64bd8aSPaolo Bonzini return H_PARAMETER; 10119f64bd8aSPaolo Bonzini } 10129f64bd8aSPaolo Bonzini 10139f64bd8aSPaolo Bonzini if (!env->vpa_addr) { 10149f64bd8aSPaolo Bonzini return H_RESOURCE; 10159f64bd8aSPaolo Bonzini } 10169f64bd8aSPaolo Bonzini 10179f64bd8aSPaolo Bonzini env->dtl_addr = addr; 10189f64bd8aSPaolo Bonzini env->dtl_size = size; 10199f64bd8aSPaolo Bonzini 10209f64bd8aSPaolo Bonzini return H_SUCCESS; 10219f64bd8aSPaolo Bonzini } 10229f64bd8aSPaolo Bonzini 10239f64bd8aSPaolo Bonzini static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) 10249f64bd8aSPaolo Bonzini { 10259f64bd8aSPaolo Bonzini env->dtl_addr = 0; 10269f64bd8aSPaolo Bonzini env->dtl_size = 0; 10279f64bd8aSPaolo Bonzini 10289f64bd8aSPaolo Bonzini return H_SUCCESS; 10299f64bd8aSPaolo Bonzini } 10309f64bd8aSPaolo Bonzini 103128e02042SDavid Gibson static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr, 10329f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 10339f64bd8aSPaolo Bonzini { 10349f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 10359f64bd8aSPaolo Bonzini target_ulong procno = args[1]; 10369f64bd8aSPaolo Bonzini target_ulong vpa = args[2]; 10379f64bd8aSPaolo Bonzini target_ulong ret = H_PARAMETER; 10389f64bd8aSPaolo Bonzini CPUPPCState *tenv; 10390f20ba62SAlexey Kardashevskiy PowerPCCPU *tcpu; 10409f64bd8aSPaolo Bonzini 10412e886fb3SSam Bobroff tcpu = spapr_find_cpu(procno); 10429f64bd8aSPaolo Bonzini if (!tcpu) { 10439f64bd8aSPaolo Bonzini return H_PARAMETER; 10449f64bd8aSPaolo Bonzini } 10450f20ba62SAlexey Kardashevskiy tenv = &tcpu->env; 10469f64bd8aSPaolo Bonzini 10479f64bd8aSPaolo Bonzini switch (flags) { 10489f64bd8aSPaolo Bonzini case FLAGS_REGISTER_VPA: 10499f64bd8aSPaolo Bonzini ret = register_vpa(tenv, vpa); 10509f64bd8aSPaolo Bonzini break; 10519f64bd8aSPaolo Bonzini 10529f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_VPA: 10539f64bd8aSPaolo Bonzini ret = deregister_vpa(tenv, vpa); 10549f64bd8aSPaolo Bonzini break; 10559f64bd8aSPaolo Bonzini 10569f64bd8aSPaolo Bonzini case FLAGS_REGISTER_SLBSHADOW: 10579f64bd8aSPaolo Bonzini ret = register_slb_shadow(tenv, vpa); 10589f64bd8aSPaolo Bonzini break; 10599f64bd8aSPaolo Bonzini 10609f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_SLBSHADOW: 10619f64bd8aSPaolo Bonzini ret = deregister_slb_shadow(tenv, vpa); 10629f64bd8aSPaolo Bonzini break; 10639f64bd8aSPaolo Bonzini 10649f64bd8aSPaolo Bonzini case FLAGS_REGISTER_DTL: 10659f64bd8aSPaolo Bonzini ret = register_dtl(tenv, vpa); 10669f64bd8aSPaolo Bonzini break; 10679f64bd8aSPaolo Bonzini 10689f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_DTL: 10699f64bd8aSPaolo Bonzini ret = deregister_dtl(tenv, vpa); 10709f64bd8aSPaolo Bonzini break; 10719f64bd8aSPaolo Bonzini } 10729f64bd8aSPaolo Bonzini 10739f64bd8aSPaolo Bonzini return ret; 10749f64bd8aSPaolo Bonzini } 10759f64bd8aSPaolo Bonzini 107628e02042SDavid Gibson static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr, 10779f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 10789f64bd8aSPaolo Bonzini { 10799f64bd8aSPaolo Bonzini CPUPPCState *env = &cpu->env; 10809f64bd8aSPaolo Bonzini CPUState *cs = CPU(cpu); 10819f64bd8aSPaolo Bonzini 10829f64bd8aSPaolo Bonzini env->msr |= (1ULL << MSR_EE); 10839f64bd8aSPaolo Bonzini hreg_compute_hflags(env); 10849f64bd8aSPaolo Bonzini if (!cpu_has_work(cs)) { 1085259186a7SAndreas Färber cs->halted = 1; 108627103424SAndreas Färber cs->exception_index = EXCP_HLT; 10879f64bd8aSPaolo Bonzini cs->exit_request = 1; 10889f64bd8aSPaolo Bonzini } 10899f64bd8aSPaolo Bonzini return H_SUCCESS; 10909f64bd8aSPaolo Bonzini } 10919f64bd8aSPaolo Bonzini 109228e02042SDavid Gibson static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr, 10939f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 10949f64bd8aSPaolo Bonzini { 10959f64bd8aSPaolo Bonzini target_ulong rtas_r3 = args[0]; 10964fe822e0SAlexey Kardashevskiy uint32_t token = rtas_ld(rtas_r3, 0); 10974fe822e0SAlexey Kardashevskiy uint32_t nargs = rtas_ld(rtas_r3, 1); 10984fe822e0SAlexey Kardashevskiy uint32_t nret = rtas_ld(rtas_r3, 2); 10999f64bd8aSPaolo Bonzini 1100210b580bSAnthony Liguori return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 11019f64bd8aSPaolo Bonzini nret, rtas_r3 + 12 + 4*nargs); 11029f64bd8aSPaolo Bonzini } 11039f64bd8aSPaolo Bonzini 110428e02042SDavid Gibson static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr, 11059f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 11069f64bd8aSPaolo Bonzini { 1107fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 11089f64bd8aSPaolo Bonzini target_ulong size = args[0]; 11099f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 11109f64bd8aSPaolo Bonzini 11119f64bd8aSPaolo Bonzini switch (size) { 11129f64bd8aSPaolo Bonzini case 1: 11132c17449bSEdgar E. Iglesias args[0] = ldub_phys(cs->as, addr); 11149f64bd8aSPaolo Bonzini return H_SUCCESS; 11159f64bd8aSPaolo Bonzini case 2: 111641701aa4SEdgar E. Iglesias args[0] = lduw_phys(cs->as, addr); 11179f64bd8aSPaolo Bonzini return H_SUCCESS; 11189f64bd8aSPaolo Bonzini case 4: 1119fdfba1a2SEdgar E. Iglesias args[0] = ldl_phys(cs->as, addr); 11209f64bd8aSPaolo Bonzini return H_SUCCESS; 11219f64bd8aSPaolo Bonzini case 8: 11222c17449bSEdgar E. Iglesias args[0] = ldq_phys(cs->as, addr); 11239f64bd8aSPaolo Bonzini return H_SUCCESS; 11249f64bd8aSPaolo Bonzini } 11259f64bd8aSPaolo Bonzini return H_PARAMETER; 11269f64bd8aSPaolo Bonzini } 11279f64bd8aSPaolo Bonzini 112828e02042SDavid Gibson static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, 11299f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 11309f64bd8aSPaolo Bonzini { 1131f606604fSEdgar E. Iglesias CPUState *cs = CPU(cpu); 1132f606604fSEdgar E. Iglesias 11339f64bd8aSPaolo Bonzini target_ulong size = args[0]; 11349f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 11359f64bd8aSPaolo Bonzini target_ulong val = args[2]; 11369f64bd8aSPaolo Bonzini 11379f64bd8aSPaolo Bonzini switch (size) { 11389f64bd8aSPaolo Bonzini case 1: 1139db3be60dSEdgar E. Iglesias stb_phys(cs->as, addr, val); 11409f64bd8aSPaolo Bonzini return H_SUCCESS; 11419f64bd8aSPaolo Bonzini case 2: 11425ce5944dSEdgar E. Iglesias stw_phys(cs->as, addr, val); 11439f64bd8aSPaolo Bonzini return H_SUCCESS; 11449f64bd8aSPaolo Bonzini case 4: 1145ab1da857SEdgar E. Iglesias stl_phys(cs->as, addr, val); 11469f64bd8aSPaolo Bonzini return H_SUCCESS; 11479f64bd8aSPaolo Bonzini case 8: 1148f606604fSEdgar E. Iglesias stq_phys(cs->as, addr, val); 11499f64bd8aSPaolo Bonzini return H_SUCCESS; 11509f64bd8aSPaolo Bonzini } 11519f64bd8aSPaolo Bonzini return H_PARAMETER; 11529f64bd8aSPaolo Bonzini } 11539f64bd8aSPaolo Bonzini 115428e02042SDavid Gibson static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr, 11559f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 11569f64bd8aSPaolo Bonzini { 1157fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 1158fdfba1a2SEdgar E. Iglesias 11599f64bd8aSPaolo Bonzini target_ulong dst = args[0]; /* Destination address */ 11609f64bd8aSPaolo Bonzini target_ulong src = args[1]; /* Source address */ 11619f64bd8aSPaolo Bonzini target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 11629f64bd8aSPaolo Bonzini target_ulong count = args[3]; /* Element count */ 11639f64bd8aSPaolo Bonzini target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 11649f64bd8aSPaolo Bonzini uint64_t tmp; 11659f64bd8aSPaolo Bonzini unsigned int mask = (1 << esize) - 1; 11669f64bd8aSPaolo Bonzini int step = 1 << esize; 11679f64bd8aSPaolo Bonzini 11689f64bd8aSPaolo Bonzini if (count > 0x80000000) { 11699f64bd8aSPaolo Bonzini return H_PARAMETER; 11709f64bd8aSPaolo Bonzini } 11719f64bd8aSPaolo Bonzini 11729f64bd8aSPaolo Bonzini if ((dst & mask) || (src & mask) || (op > 1)) { 11739f64bd8aSPaolo Bonzini return H_PARAMETER; 11749f64bd8aSPaolo Bonzini } 11759f64bd8aSPaolo Bonzini 11769f64bd8aSPaolo Bonzini if (dst >= src && dst < (src + (count << esize))) { 11779f64bd8aSPaolo Bonzini dst = dst + ((count - 1) << esize); 11789f64bd8aSPaolo Bonzini src = src + ((count - 1) << esize); 11799f64bd8aSPaolo Bonzini step = -step; 11809f64bd8aSPaolo Bonzini } 11819f64bd8aSPaolo Bonzini 11829f64bd8aSPaolo Bonzini while (count--) { 11839f64bd8aSPaolo Bonzini switch (esize) { 11849f64bd8aSPaolo Bonzini case 0: 11852c17449bSEdgar E. Iglesias tmp = ldub_phys(cs->as, src); 11869f64bd8aSPaolo Bonzini break; 11879f64bd8aSPaolo Bonzini case 1: 118841701aa4SEdgar E. Iglesias tmp = lduw_phys(cs->as, src); 11899f64bd8aSPaolo Bonzini break; 11909f64bd8aSPaolo Bonzini case 2: 1191fdfba1a2SEdgar E. Iglesias tmp = ldl_phys(cs->as, src); 11929f64bd8aSPaolo Bonzini break; 11939f64bd8aSPaolo Bonzini case 3: 11942c17449bSEdgar E. Iglesias tmp = ldq_phys(cs->as, src); 11959f64bd8aSPaolo Bonzini break; 11969f64bd8aSPaolo Bonzini default: 11979f64bd8aSPaolo Bonzini return H_PARAMETER; 11989f64bd8aSPaolo Bonzini } 11999f64bd8aSPaolo Bonzini if (op == 1) { 12009f64bd8aSPaolo Bonzini tmp = ~tmp; 12019f64bd8aSPaolo Bonzini } 12029f64bd8aSPaolo Bonzini switch (esize) { 12039f64bd8aSPaolo Bonzini case 0: 1204db3be60dSEdgar E. Iglesias stb_phys(cs->as, dst, tmp); 12059f64bd8aSPaolo Bonzini break; 12069f64bd8aSPaolo Bonzini case 1: 12075ce5944dSEdgar E. Iglesias stw_phys(cs->as, dst, tmp); 12089f64bd8aSPaolo Bonzini break; 12099f64bd8aSPaolo Bonzini case 2: 1210ab1da857SEdgar E. Iglesias stl_phys(cs->as, dst, tmp); 12119f64bd8aSPaolo Bonzini break; 12129f64bd8aSPaolo Bonzini case 3: 1213f606604fSEdgar E. Iglesias stq_phys(cs->as, dst, tmp); 12149f64bd8aSPaolo Bonzini break; 12159f64bd8aSPaolo Bonzini } 12169f64bd8aSPaolo Bonzini dst = dst + step; 12179f64bd8aSPaolo Bonzini src = src + step; 12189f64bd8aSPaolo Bonzini } 12199f64bd8aSPaolo Bonzini 12209f64bd8aSPaolo Bonzini return H_SUCCESS; 12219f64bd8aSPaolo Bonzini } 12229f64bd8aSPaolo Bonzini 122328e02042SDavid Gibson static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 12249f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 12259f64bd8aSPaolo Bonzini { 12269f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 12279f64bd8aSPaolo Bonzini return H_SUCCESS; 12289f64bd8aSPaolo Bonzini } 12299f64bd8aSPaolo Bonzini 123028e02042SDavid Gibson static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr, 12319f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 12329f64bd8aSPaolo Bonzini { 12339f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 12349f64bd8aSPaolo Bonzini return H_SUCCESS; 12359f64bd8aSPaolo Bonzini } 12369f64bd8aSPaolo Bonzini 12377d0cd464SPeter Maydell static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 1238c4015bbdSAlexey Kardashevskiy target_ulong mflags, 1239c4015bbdSAlexey Kardashevskiy target_ulong value1, 1240c4015bbdSAlexey Kardashevskiy target_ulong value2) 124142561bf2SAnton Blanchard { 124242561bf2SAnton Blanchard if (value1) { 1243c4015bbdSAlexey Kardashevskiy return H_P3; 124442561bf2SAnton Blanchard } 124542561bf2SAnton Blanchard if (value2) { 1246c4015bbdSAlexey Kardashevskiy return H_P4; 124742561bf2SAnton Blanchard } 1248c4015bbdSAlexey Kardashevskiy 124942561bf2SAnton Blanchard switch (mflags) { 125042561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_BIG: 1251295b6c26SDavid Gibson set_all_lpcrs(0, LPCR_ILE); 1252eefaccc0SDavid Gibson spapr_pci_switch_vga(true); 1253c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 125442561bf2SAnton Blanchard 125542561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_LITTLE: 1256295b6c26SDavid Gibson set_all_lpcrs(LPCR_ILE, LPCR_ILE); 1257eefaccc0SDavid Gibson spapr_pci_switch_vga(false); 1258c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 1259c4015bbdSAlexey Kardashevskiy } 1260c4015bbdSAlexey Kardashevskiy 1261c4015bbdSAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 1262c4015bbdSAlexey Kardashevskiy } 1263c4015bbdSAlexey Kardashevskiy 12647d0cd464SPeter Maydell static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 1265d5ac4f54SAlexey Kardashevskiy target_ulong mflags, 1266d5ac4f54SAlexey Kardashevskiy target_ulong value1, 1267d5ac4f54SAlexey Kardashevskiy target_ulong value2) 1268d5ac4f54SAlexey Kardashevskiy { 1269d5ac4f54SAlexey Kardashevskiy PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 1270d5ac4f54SAlexey Kardashevskiy 1271d5ac4f54SAlexey Kardashevskiy if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 1272d5ac4f54SAlexey Kardashevskiy return H_P2; 1273d5ac4f54SAlexey Kardashevskiy } 1274d5ac4f54SAlexey Kardashevskiy if (value1) { 1275d5ac4f54SAlexey Kardashevskiy return H_P3; 1276d5ac4f54SAlexey Kardashevskiy } 1277d5ac4f54SAlexey Kardashevskiy if (value2) { 1278d5ac4f54SAlexey Kardashevskiy return H_P4; 1279d5ac4f54SAlexey Kardashevskiy } 1280d5ac4f54SAlexey Kardashevskiy 12815c94b2a5SCédric Le Goater if (mflags == AIL_RESERVED) { 1282d5ac4f54SAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 1283d5ac4f54SAlexey Kardashevskiy } 1284d5ac4f54SAlexey Kardashevskiy 1285295b6c26SDavid Gibson set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); 1286d5ac4f54SAlexey Kardashevskiy 1287d5ac4f54SAlexey Kardashevskiy return H_SUCCESS; 1288d5ac4f54SAlexey Kardashevskiy } 1289d5ac4f54SAlexey Kardashevskiy 129028e02042SDavid Gibson static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1291c4015bbdSAlexey Kardashevskiy target_ulong opcode, target_ulong *args) 1292c4015bbdSAlexey Kardashevskiy { 1293c4015bbdSAlexey Kardashevskiy target_ulong resource = args[1]; 1294c4015bbdSAlexey Kardashevskiy target_ulong ret = H_P2; 1295c4015bbdSAlexey Kardashevskiy 1296c4015bbdSAlexey Kardashevskiy switch (resource) { 1297c4015bbdSAlexey Kardashevskiy case H_SET_MODE_RESOURCE_LE: 12987d0cd464SPeter Maydell ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); 129942561bf2SAnton Blanchard break; 1300d5ac4f54SAlexey Kardashevskiy case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 13017d0cd464SPeter Maydell ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 1302d5ac4f54SAlexey Kardashevskiy args[2], args[3]); 1303d5ac4f54SAlexey Kardashevskiy break; 130442561bf2SAnton Blanchard } 130542561bf2SAnton Blanchard 130642561bf2SAnton Blanchard return ret; 130742561bf2SAnton Blanchard } 130842561bf2SAnton Blanchard 1309d77a98b0SSuraj Jitindar Singh static target_ulong h_clean_slb(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1310d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 1311d77a98b0SSuraj Jitindar Singh { 1312d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1313d77a98b0SSuraj Jitindar Singh opcode, " (H_CLEAN_SLB)"); 1314d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 1315d77a98b0SSuraj Jitindar Singh } 1316d77a98b0SSuraj Jitindar Singh 1317d77a98b0SSuraj Jitindar Singh static target_ulong h_invalidate_pid(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1318d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 1319d77a98b0SSuraj Jitindar Singh { 1320d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1321d77a98b0SSuraj Jitindar Singh opcode, " (H_INVALIDATE_PID)"); 1322d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 1323d77a98b0SSuraj Jitindar Singh } 1324d77a98b0SSuraj Jitindar Singh 1325b4db5413SSuraj Jitindar Singh static void spapr_check_setup_free_hpt(sPAPRMachineState *spapr, 1326b4db5413SSuraj Jitindar Singh uint64_t patbe_old, uint64_t patbe_new) 1327b4db5413SSuraj Jitindar Singh { 1328b4db5413SSuraj Jitindar Singh /* 1329b4db5413SSuraj Jitindar Singh * We have 4 Options: 1330b4db5413SSuraj Jitindar Singh * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 1331b4db5413SSuraj Jitindar Singh * HASH->RADIX : Free HPT 1332b4db5413SSuraj Jitindar Singh * RADIX->HASH : Allocate HPT 1333b4db5413SSuraj Jitindar Singh * NOTHING->HASH : Allocate HPT 1334b4db5413SSuraj Jitindar Singh * Note: NOTHING implies the case where we said the guest could choose 1335b4db5413SSuraj Jitindar Singh * later and so assumed radix and now it's called H_REG_PROC_TBL 1336b4db5413SSuraj Jitindar Singh */ 1337b4db5413SSuraj Jitindar Singh 1338b4db5413SSuraj Jitindar Singh if ((patbe_old & PATBE1_GR) == (patbe_new & PATBE1_GR)) { 1339b4db5413SSuraj Jitindar Singh /* We assume RADIX, so this catches all the "Do Nothing" cases */ 1340b4db5413SSuraj Jitindar Singh } else if (!(patbe_old & PATBE1_GR)) { 1341b4db5413SSuraj Jitindar Singh /* HASH->RADIX : Free HPT */ 134206ec79e8SBharata B Rao spapr_free_hpt(spapr); 1343b4db5413SSuraj Jitindar Singh } else if (!(patbe_new & PATBE1_GR)) { 1344b4db5413SSuraj Jitindar Singh /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 1345b4db5413SSuraj Jitindar Singh spapr_setup_hpt_and_vrma(spapr); 1346b4db5413SSuraj Jitindar Singh } 1347b4db5413SSuraj Jitindar Singh return; 1348b4db5413SSuraj Jitindar Singh } 1349b4db5413SSuraj Jitindar Singh 1350b4db5413SSuraj Jitindar Singh #define FLAGS_MASK 0x01FULL 1351b4db5413SSuraj Jitindar Singh #define FLAG_MODIFY 0x10 1352b4db5413SSuraj Jitindar Singh #define FLAG_REGISTER 0x08 1353b4db5413SSuraj Jitindar Singh #define FLAG_RADIX 0x04 1354b4db5413SSuraj Jitindar Singh #define FLAG_HASH_PROC_TBL 0x02 1355b4db5413SSuraj Jitindar Singh #define FLAG_GTSE 0x01 1356b4db5413SSuraj Jitindar Singh 1357d77a98b0SSuraj Jitindar Singh static target_ulong h_register_process_table(PowerPCCPU *cpu, 1358d77a98b0SSuraj Jitindar Singh sPAPRMachineState *spapr, 1359d77a98b0SSuraj Jitindar Singh target_ulong opcode, 1360d77a98b0SSuraj Jitindar Singh target_ulong *args) 1361d77a98b0SSuraj Jitindar Singh { 1362b4db5413SSuraj Jitindar Singh target_ulong flags = args[0]; 1363b4db5413SSuraj Jitindar Singh target_ulong proc_tbl = args[1]; 1364b4db5413SSuraj Jitindar Singh target_ulong page_size = args[2]; 1365b4db5413SSuraj Jitindar Singh target_ulong table_size = args[3]; 1366b4db5413SSuraj Jitindar Singh uint64_t cproc; 1367b4db5413SSuraj Jitindar Singh 1368b4db5413SSuraj Jitindar Singh if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 1369b4db5413SSuraj Jitindar Singh return H_PARAMETER; 1370b4db5413SSuraj Jitindar Singh } 1371b4db5413SSuraj Jitindar Singh if (flags & FLAG_MODIFY) { 1372b4db5413SSuraj Jitindar Singh if (flags & FLAG_REGISTER) { 1373b4db5413SSuraj Jitindar Singh if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 1374b4db5413SSuraj Jitindar Singh if (proc_tbl & 0xfff || proc_tbl >> 60) { 1375b4db5413SSuraj Jitindar Singh return H_P2; 1376b4db5413SSuraj Jitindar Singh } else if (page_size) { 1377b4db5413SSuraj Jitindar Singh return H_P3; 1378b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 1379b4db5413SSuraj Jitindar Singh return H_P4; 1380b4db5413SSuraj Jitindar Singh } 1381b4db5413SSuraj Jitindar Singh cproc = PATBE1_GR | proc_tbl | table_size; 1382b4db5413SSuraj Jitindar Singh } else { /* Register new HPT process table */ 1383b4db5413SSuraj Jitindar Singh if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 1384b4db5413SSuraj Jitindar Singh /* TODO - Not Supported */ 1385b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 1386b4db5413SSuraj Jitindar Singh return H_PARAMETER; 1387b4db5413SSuraj Jitindar Singh } else { /* Hash with SLB */ 1388b4db5413SSuraj Jitindar Singh if (proc_tbl >> 38) { 1389b4db5413SSuraj Jitindar Singh return H_P2; 1390b4db5413SSuraj Jitindar Singh } else if (page_size & ~0x7) { 1391b4db5413SSuraj Jitindar Singh return H_P3; 1392b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 1393b4db5413SSuraj Jitindar Singh return H_P4; 1394b4db5413SSuraj Jitindar Singh } 1395b4db5413SSuraj Jitindar Singh } 1396b4db5413SSuraj Jitindar Singh cproc = (proc_tbl << 25) | page_size << 5 | table_size; 1397b4db5413SSuraj Jitindar Singh } 1398b4db5413SSuraj Jitindar Singh 1399b4db5413SSuraj Jitindar Singh } else { /* Deregister current process table */ 1400b4db5413SSuraj Jitindar Singh /* Set to benign value: (current GR) | 0. This allows 1401b4db5413SSuraj Jitindar Singh * deregistration in KVM to succeed even if the radix bit in flags 1402b4db5413SSuraj Jitindar Singh * doesn't match the radix bit in the old PATB. */ 1403b4db5413SSuraj Jitindar Singh cproc = spapr->patb_entry & PATBE1_GR; 1404b4db5413SSuraj Jitindar Singh } 1405b4db5413SSuraj Jitindar Singh } else { /* Maintain current registration */ 1406b4db5413SSuraj Jitindar Singh if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATBE1_GR)) { 1407b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 1408b4db5413SSuraj Jitindar Singh return H_PARAMETER; /* Existing Process Table Mismatch */ 1409b4db5413SSuraj Jitindar Singh } 1410b4db5413SSuraj Jitindar Singh cproc = spapr->patb_entry; 1411b4db5413SSuraj Jitindar Singh } 1412b4db5413SSuraj Jitindar Singh 1413b4db5413SSuraj Jitindar Singh /* Check if we need to setup OR free the hpt */ 1414b4db5413SSuraj Jitindar Singh spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 1415b4db5413SSuraj Jitindar Singh 1416b4db5413SSuraj Jitindar Singh spapr->patb_entry = cproc; /* Save new process table */ 14176de83307SSuraj Jitindar Singh 14186de83307SSuraj Jitindar Singh /* Update the UPRT and GTSE bits in the LPCR for all cpus */ 1419295b6c26SDavid Gibson set_all_lpcrs(((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT : 0) | 142060694bc6SSuraj Jitindar Singh ((flags & FLAG_GTSE) ? LPCR_GTSE : 0), 142160694bc6SSuraj Jitindar Singh LPCR_UPRT | LPCR_GTSE); 1422b4db5413SSuraj Jitindar Singh 1423b4db5413SSuraj Jitindar Singh if (kvm_enabled()) { 1424b4db5413SSuraj Jitindar Singh return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1425b4db5413SSuraj Jitindar Singh flags & FLAG_GTSE, cproc); 1426b4db5413SSuraj Jitindar Singh } 1427b4db5413SSuraj Jitindar Singh return H_SUCCESS; 1428d77a98b0SSuraj Jitindar Singh } 1429d77a98b0SSuraj Jitindar Singh 14301c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALL -1 14311c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 14321c7ad77eSNicholas Piggin 14331c7ad77eSNicholas Piggin static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 14341c7ad77eSNicholas Piggin sPAPRMachineState *spapr, 14351c7ad77eSNicholas Piggin target_ulong opcode, target_ulong *args) 14361c7ad77eSNicholas Piggin { 14371c7ad77eSNicholas Piggin target_long target = args[0]; 14381c7ad77eSNicholas Piggin CPUState *cs; 14391c7ad77eSNicholas Piggin 14401c7ad77eSNicholas Piggin if (target < 0) { 14411c7ad77eSNicholas Piggin /* Broadcast */ 14421c7ad77eSNicholas Piggin if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 14431c7ad77eSNicholas Piggin return H_PARAMETER; 14441c7ad77eSNicholas Piggin } 14451c7ad77eSNicholas Piggin 14461c7ad77eSNicholas Piggin CPU_FOREACH(cs) { 14471c7ad77eSNicholas Piggin PowerPCCPU *c = POWERPC_CPU(cs); 14481c7ad77eSNicholas Piggin 14491c7ad77eSNicholas Piggin if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 14501c7ad77eSNicholas Piggin if (c == cpu) { 14511c7ad77eSNicholas Piggin continue; 14521c7ad77eSNicholas Piggin } 14531c7ad77eSNicholas Piggin } 14541c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 14551c7ad77eSNicholas Piggin } 14561c7ad77eSNicholas Piggin return H_SUCCESS; 14571c7ad77eSNicholas Piggin 14581c7ad77eSNicholas Piggin } else { 14591c7ad77eSNicholas Piggin /* Unicast */ 14602e886fb3SSam Bobroff cs = CPU(spapr_find_cpu(target)); 1461f57467e3SSam Bobroff if (cs) { 14621c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 14631c7ad77eSNicholas Piggin return H_SUCCESS; 14641c7ad77eSNicholas Piggin } 14651c7ad77eSNicholas Piggin return H_PARAMETER; 14661c7ad77eSNicholas Piggin } 14671c7ad77eSNicholas Piggin } 14681c7ad77eSNicholas Piggin 14697843c0d6SDavid Gibson static uint32_t cas_check_pvr(sPAPRMachineState *spapr, PowerPCCPU *cpu, 1470cc7b35b1SGreg Kurz target_ulong *addr, bool *raw_mode_supported, 1471cc7b35b1SGreg Kurz Error **errp) 14722a6593cbSAlexey Kardashevskiy { 1473152ef803SDavid Gibson bool explicit_match = false; /* Matched the CPU's real PVR */ 14747843c0d6SDavid Gibson uint32_t max_compat = spapr->max_compat_pvr; 1475152ef803SDavid Gibson uint32_t best_compat = 0; 1476152ef803SDavid Gibson int i; 14773794d548SAlexey Kardashevskiy 1478152ef803SDavid Gibson /* 1479152ef803SDavid Gibson * We scan the supplied table of PVRs looking for two things 1480152ef803SDavid Gibson * 1. Is our real CPU PVR in the list? 1481152ef803SDavid Gibson * 2. What's the "best" listed logical PVR 1482152ef803SDavid Gibson */ 1483152ef803SDavid Gibson for (i = 0; i < 512; ++i) { 14843794d548SAlexey Kardashevskiy uint32_t pvr, pvr_mask; 14853794d548SAlexey Kardashevskiy 148680c33d34SDavid Gibson pvr_mask = ldl_be_phys(&address_space_memory, *addr); 148780c33d34SDavid Gibson pvr = ldl_be_phys(&address_space_memory, *addr + 4); 148880c33d34SDavid Gibson *addr += 8; 14893794d548SAlexey Kardashevskiy 14903794d548SAlexey Kardashevskiy if (~pvr_mask & pvr) { 1491152ef803SDavid Gibson break; /* Terminator record */ 14923794d548SAlexey Kardashevskiy } 1493152ef803SDavid Gibson 1494152ef803SDavid Gibson if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1495152ef803SDavid Gibson explicit_match = true; 1496152ef803SDavid Gibson } else { 1497152ef803SDavid Gibson if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1498152ef803SDavid Gibson best_compat = pvr; 1499152ef803SDavid Gibson } 1500152ef803SDavid Gibson } 1501152ef803SDavid Gibson } 1502152ef803SDavid Gibson 1503152ef803SDavid Gibson if ((best_compat == 0) && (!explicit_match || max_compat)) { 1504152ef803SDavid Gibson /* We couldn't find a suitable compatibility mode, and either 1505152ef803SDavid Gibson * the guest doesn't support "raw" mode for this CPU, or raw 1506152ef803SDavid Gibson * mode is disabled because a maximum compat mode is set */ 150780c33d34SDavid Gibson error_setg(errp, "Couldn't negotiate a suitable PVR during CAS"); 150880c33d34SDavid Gibson return 0; 15093794d548SAlexey Kardashevskiy } 15103794d548SAlexey Kardashevskiy 1511cc7b35b1SGreg Kurz *raw_mode_supported = explicit_match; 1512cc7b35b1SGreg Kurz 15133794d548SAlexey Kardashevskiy /* Parsing finished */ 1514152ef803SDavid Gibson trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 15153794d548SAlexey Kardashevskiy 151680c33d34SDavid Gibson return best_compat; 151780c33d34SDavid Gibson } 151880c33d34SDavid Gibson 151980c33d34SDavid Gibson static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 152080c33d34SDavid Gibson sPAPRMachineState *spapr, 152180c33d34SDavid Gibson target_ulong opcode, 152280c33d34SDavid Gibson target_ulong *args) 152380c33d34SDavid Gibson { 152480c33d34SDavid Gibson /* Working address in data buffer */ 152580c33d34SDavid Gibson target_ulong addr = ppc64_phys_to_real(args[0]); 152680c33d34SDavid Gibson target_ulong ov_table; 152780c33d34SDavid Gibson uint32_t cas_pvr; 152880c33d34SDavid Gibson sPAPROptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates; 152980c33d34SDavid Gibson bool guest_radix; 1530f6f242c7SDavid Gibson Error *local_err = NULL; 1531cc7b35b1SGreg Kurz bool raw_mode_supported = false; 15323794d548SAlexey Kardashevskiy 1533cc7b35b1SGreg Kurz cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err); 153480c33d34SDavid Gibson if (local_err) { 153580c33d34SDavid Gibson error_report_err(local_err); 153680c33d34SDavid Gibson return H_HARDWARE; 153780c33d34SDavid Gibson } 153880c33d34SDavid Gibson 153980c33d34SDavid Gibson /* Update CPUs */ 154080c33d34SDavid Gibson if (cpu->compat_pvr != cas_pvr) { 154180c33d34SDavid Gibson ppc_set_compat_all(cas_pvr, &local_err); 1542f6f242c7SDavid Gibson if (local_err) { 1543cc7b35b1SGreg Kurz /* We fail to set compat mode (likely because running with KVM PR), 1544cc7b35b1SGreg Kurz * but maybe we can fallback to raw mode if the guest supports it. 1545cc7b35b1SGreg Kurz */ 1546cc7b35b1SGreg Kurz if (!raw_mode_supported) { 1547f6f242c7SDavid Gibson error_report_err(local_err); 15483794d548SAlexey Kardashevskiy return H_HARDWARE; 15493794d548SAlexey Kardashevskiy } 1550cc7b35b1SGreg Kurz local_err = NULL; 1551cc7b35b1SGreg Kurz } 15523794d548SAlexey Kardashevskiy } 15533794d548SAlexey Kardashevskiy 155403d196b7SBharata B Rao /* For the future use: here @ov_table points to the first option vector */ 155580c33d34SDavid Gibson ov_table = addr; 155603d196b7SBharata B Rao 1557e957f6a9SSam Bobroff ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1558facdb8b6SMichael Roth ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 15599fb4541fSSam Bobroff if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 15609fb4541fSSam Bobroff error_report("guest requested hash and radix MMU, which is invalid."); 15619fb4541fSSam Bobroff exit(EXIT_FAILURE); 15629fb4541fSSam Bobroff } 15639fb4541fSSam Bobroff /* The radix/hash bit in byte 24 requires special handling: */ 15649fb4541fSSam Bobroff guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 15659fb4541fSSam Bobroff spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300); 15662a6593cbSAlexey Kardashevskiy 15672772cf6bSDavid Gibson /* 15682772cf6bSDavid Gibson * HPT resizing is a bit of a special case, because when enabled 15692772cf6bSDavid Gibson * we assume an HPT guest will support it until it says it 15702772cf6bSDavid Gibson * doesn't, instead of assuming it won't support it until it says 15712772cf6bSDavid Gibson * it does. Strictly speaking that approach could break for 15722772cf6bSDavid Gibson * guests which don't make a CAS call, but those are so old we 15732772cf6bSDavid Gibson * don't care about them. Without that assumption we'd have to 15742772cf6bSDavid Gibson * make at least a temporary allocation of an HPT sized for max 15752772cf6bSDavid Gibson * memory, which could be impossibly difficult under KVM HV if 15762772cf6bSDavid Gibson * maxram is large. 15772772cf6bSDavid Gibson */ 15782772cf6bSDavid Gibson if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 15792772cf6bSDavid Gibson int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 15802772cf6bSDavid Gibson 15812772cf6bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 15822772cf6bSDavid Gibson error_report( 15832772cf6bSDavid Gibson "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 15842772cf6bSDavid Gibson exit(1); 15852772cf6bSDavid Gibson } 15862772cf6bSDavid Gibson 15872772cf6bSDavid Gibson if (spapr->htab_shift < maxshift) { 15882772cf6bSDavid Gibson /* Guest doesn't know about HPT resizing, so we 15892772cf6bSDavid Gibson * pre-emptively resize for the maximum permitted RAM. At 15902772cf6bSDavid Gibson * the point this is called, nothing should have been 15912772cf6bSDavid Gibson * entered into the existing HPT */ 15922772cf6bSDavid Gibson spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 15931ec26c75SGreg Kurz push_sregs_to_kvm_pr(spapr); 1594b55d295eSDavid Gibson } 15952772cf6bSDavid Gibson } 15962772cf6bSDavid Gibson 1597facdb8b6SMichael Roth /* NOTE: there are actually a number of ov5 bits where input from the 1598facdb8b6SMichael Roth * guest is always zero, and the platform/QEMU enables them independently 1599facdb8b6SMichael Roth * of guest input. To model these properly we'd want some sort of mask, 1600facdb8b6SMichael Roth * but since they only currently apply to memory migration as defined 1601facdb8b6SMichael Roth * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 16026787d27bSMichael Roth * to worry about this for now. 1603facdb8b6SMichael Roth */ 16046787d27bSMichael Roth ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); 160530bf9ed1SCédric Le Goater 160630bf9ed1SCédric Le Goater /* also clear the radix/hash bit from the current ov5_cas bits to 160730bf9ed1SCédric Le Goater * be in sync with the newly ov5 bits. Else the radix bit will be 160830bf9ed1SCédric Le Goater * seen as being removed and this will generate a reset loop 160930bf9ed1SCédric Le Goater */ 161030bf9ed1SCédric Le Goater spapr_ovec_clear(ov5_cas_old, OV5_MMU_RADIX_300); 161130bf9ed1SCédric Le Goater 16126787d27bSMichael Roth /* full range of negotiated ov5 capabilities */ 1613facdb8b6SMichael Roth spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1614facdb8b6SMichael Roth spapr_ovec_cleanup(ov5_guest); 16156787d27bSMichael Roth /* capabilities that have been added since CAS-generated guest reset. 16166787d27bSMichael Roth * if capabilities have since been removed, generate another reset 16176787d27bSMichael Roth */ 16186787d27bSMichael Roth ov5_updates = spapr_ovec_new(); 16196787d27bSMichael Roth spapr->cas_reboot = spapr_ovec_diff(ov5_updates, 16206787d27bSMichael Roth ov5_cas_old, spapr->ov5_cas); 16219fb4541fSSam Bobroff /* Now that processing is finished, set the radix/hash bit for the 16229fb4541fSSam Bobroff * guest if it requested a valid mode; otherwise terminate the boot. */ 16239fb4541fSSam Bobroff if (guest_radix) { 16249fb4541fSSam Bobroff if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 16259fb4541fSSam Bobroff error_report("Guest requested unavailable MMU mode (radix)."); 16269fb4541fSSam Bobroff exit(EXIT_FAILURE); 16279fb4541fSSam Bobroff } 16289fb4541fSSam Bobroff spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300); 16299fb4541fSSam Bobroff } else { 16309fb4541fSSam Bobroff if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 16319fb4541fSSam Bobroff && !kvmppc_has_cap_mmu_hash_v3()) { 16329fb4541fSSam Bobroff error_report("Guest requested unavailable MMU mode (hash)."); 16339fb4541fSSam Bobroff exit(EXIT_FAILURE); 16349fb4541fSSam Bobroff } 16359fb4541fSSam Bobroff } 1636e957f6a9SSam Bobroff spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest, 1637e957f6a9SSam Bobroff OV1_PPC_3_00); 16386787d27bSMichael Roth if (!spapr->cas_reboot) { 1639b472b1a7SDaniel Henrique Barboza /* If spapr_machine_reset() did not set up a HPT but one is necessary 1640e05fba50SSam Bobroff * (because the guest isn't going to use radix) then set it up here. */ 1641e05fba50SSam Bobroff if ((spapr->patb_entry & PATBE1_GR) && !guest_radix) { 1642e05fba50SSam Bobroff /* legacy hash or new hash: */ 1643e05fba50SSam Bobroff spapr_setup_hpt_and_vrma(spapr); 1644e05fba50SSam Bobroff } 16456787d27bSMichael Roth spapr->cas_reboot = 16465b120785SDavid Gibson (spapr_h_cas_compose_response(spapr, args[1], args[2], 16476787d27bSMichael Roth ov5_updates) != 0); 16486787d27bSMichael Roth } 16496787d27bSMichael Roth spapr_ovec_cleanup(ov5_updates); 16506787d27bSMichael Roth 16516787d27bSMichael Roth if (spapr->cas_reboot) { 1652cf83f140SEric Blake qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 16532a6593cbSAlexey Kardashevskiy } 16542a6593cbSAlexey Kardashevskiy 16552a6593cbSAlexey Kardashevskiy return H_SUCCESS; 16562a6593cbSAlexey Kardashevskiy } 16572a6593cbSAlexey Kardashevskiy 1658c59704b2SSuraj Jitindar Singh static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1659c59704b2SSuraj Jitindar Singh sPAPRMachineState *spapr, 1660c59704b2SSuraj Jitindar Singh target_ulong opcode, 1661c59704b2SSuraj Jitindar Singh target_ulong *args) 1662c59704b2SSuraj Jitindar Singh { 1663c59704b2SSuraj Jitindar Singh uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1664c59704b2SSuraj Jitindar Singh ~H_CPU_CHAR_THR_RECONF_TRIG; 1665c59704b2SSuraj Jitindar Singh uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1666c59704b2SSuraj Jitindar Singh uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1667c59704b2SSuraj Jitindar Singh uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1668c59704b2SSuraj Jitindar Singh uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 1669c59704b2SSuraj Jitindar Singh 1670c59704b2SSuraj Jitindar Singh switch (safe_cache) { 1671c59704b2SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1672c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1673c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1674c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1675c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1676c59704b2SSuraj Jitindar Singh break; 1677c59704b2SSuraj Jitindar Singh case SPAPR_CAP_FIXED: 1678c59704b2SSuraj Jitindar Singh break; 1679c59704b2SSuraj Jitindar Singh default: /* broken */ 1680c59704b2SSuraj Jitindar Singh assert(safe_cache == SPAPR_CAP_BROKEN); 1681c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1682c59704b2SSuraj Jitindar Singh break; 1683c59704b2SSuraj Jitindar Singh } 1684c59704b2SSuraj Jitindar Singh 1685c59704b2SSuraj Jitindar Singh switch (safe_bounds_check) { 1686c59704b2SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1687c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1688c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1689c59704b2SSuraj Jitindar Singh break; 1690c59704b2SSuraj Jitindar Singh case SPAPR_CAP_FIXED: 1691c59704b2SSuraj Jitindar Singh break; 1692c59704b2SSuraj Jitindar Singh default: /* broken */ 1693c59704b2SSuraj Jitindar Singh assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1694c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1695c59704b2SSuraj Jitindar Singh break; 1696c59704b2SSuraj Jitindar Singh } 1697c59704b2SSuraj Jitindar Singh 1698c59704b2SSuraj Jitindar Singh switch (safe_indirect_branch) { 1699c76c0d30SSuraj Jitindar Singh case SPAPR_CAP_FIXED_CCD: 1700c76c0d30SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; 1701c76c0d30SSuraj Jitindar Singh break; 1702c76c0d30SSuraj Jitindar Singh case SPAPR_CAP_FIXED_IBS: 1703c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1704fa86f592SGreg Kurz break; 1705c59704b2SSuraj Jitindar Singh default: /* broken */ 1706c59704b2SSuraj Jitindar Singh assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1707c59704b2SSuraj Jitindar Singh break; 1708c59704b2SSuraj Jitindar Singh } 1709c59704b2SSuraj Jitindar Singh 1710c59704b2SSuraj Jitindar Singh args[0] = characteristics; 1711c59704b2SSuraj Jitindar Singh args[1] = behaviour; 1712c59704b2SSuraj Jitindar Singh 1713c59704b2SSuraj Jitindar Singh return H_SUCCESS; 1714c59704b2SSuraj Jitindar Singh } 1715c59704b2SSuraj Jitindar Singh 17169f64bd8aSPaolo Bonzini static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 17179f64bd8aSPaolo Bonzini static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 17189f64bd8aSPaolo Bonzini 17199f64bd8aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 17209f64bd8aSPaolo Bonzini { 17219f64bd8aSPaolo Bonzini spapr_hcall_fn *slot; 17229f64bd8aSPaolo Bonzini 17239f64bd8aSPaolo Bonzini if (opcode <= MAX_HCALL_OPCODE) { 17249f64bd8aSPaolo Bonzini assert((opcode & 0x3) == 0); 17259f64bd8aSPaolo Bonzini 17269f64bd8aSPaolo Bonzini slot = &papr_hypercall_table[opcode / 4]; 17279f64bd8aSPaolo Bonzini } else { 17289f64bd8aSPaolo Bonzini assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 17299f64bd8aSPaolo Bonzini 17309f64bd8aSPaolo Bonzini slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 17319f64bd8aSPaolo Bonzini } 17329f64bd8aSPaolo Bonzini 17339f64bd8aSPaolo Bonzini assert(!(*slot)); 17349f64bd8aSPaolo Bonzini *slot = fn; 17359f64bd8aSPaolo Bonzini } 17369f64bd8aSPaolo Bonzini 17379f64bd8aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 17389f64bd8aSPaolo Bonzini target_ulong *args) 17399f64bd8aSPaolo Bonzini { 174028e02042SDavid Gibson sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 174128e02042SDavid Gibson 17429f64bd8aSPaolo Bonzini if ((opcode <= MAX_HCALL_OPCODE) 17439f64bd8aSPaolo Bonzini && ((opcode & 0x3) == 0)) { 17449f64bd8aSPaolo Bonzini spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 17459f64bd8aSPaolo Bonzini 17469f64bd8aSPaolo Bonzini if (fn) { 17479f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 17489f64bd8aSPaolo Bonzini } 17499f64bd8aSPaolo Bonzini } else if ((opcode >= KVMPPC_HCALL_BASE) && 17509f64bd8aSPaolo Bonzini (opcode <= KVMPPC_HCALL_MAX)) { 17519f64bd8aSPaolo Bonzini spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 17529f64bd8aSPaolo Bonzini 17539f64bd8aSPaolo Bonzini if (fn) { 17549f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 17559f64bd8aSPaolo Bonzini } 17569f64bd8aSPaolo Bonzini } 17579f64bd8aSPaolo Bonzini 1758aaf87c66SThomas Huth qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1759aaf87c66SThomas Huth opcode); 17609f64bd8aSPaolo Bonzini return H_FUNCTION; 17619f64bd8aSPaolo Bonzini } 17629f64bd8aSPaolo Bonzini 17639f64bd8aSPaolo Bonzini static void hypercall_register_types(void) 17649f64bd8aSPaolo Bonzini { 17659f64bd8aSPaolo Bonzini /* hcall-pft */ 17669f64bd8aSPaolo Bonzini spapr_register_hypercall(H_ENTER, h_enter); 17679f64bd8aSPaolo Bonzini spapr_register_hypercall(H_REMOVE, h_remove); 17689f64bd8aSPaolo Bonzini spapr_register_hypercall(H_PROTECT, h_protect); 1769fa388916SAnthony Liguori spapr_register_hypercall(H_READ, h_read); 17709f64bd8aSPaolo Bonzini 17719f64bd8aSPaolo Bonzini /* hcall-bulk */ 17729f64bd8aSPaolo Bonzini spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 17739f64bd8aSPaolo Bonzini 177430f4b05bSDavid Gibson /* hcall-hpt-resize */ 177530f4b05bSDavid Gibson spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 177630f4b05bSDavid Gibson spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 177730f4b05bSDavid Gibson 17789f64bd8aSPaolo Bonzini /* hcall-splpar */ 17799f64bd8aSPaolo Bonzini spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 17809f64bd8aSPaolo Bonzini spapr_register_hypercall(H_CEDE, h_cede); 17811c7ad77eSNicholas Piggin spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 17829f64bd8aSPaolo Bonzini 1783423576f7SThomas Huth /* processor register resource access h-calls */ 1784423576f7SThomas Huth spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1785af08a58fSThomas Huth spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1786e49ff266SThomas Huth spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 17873240dd9aSThomas Huth spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1788423576f7SThomas Huth spapr_register_hypercall(H_SET_MODE, h_set_mode); 1789423576f7SThomas Huth 1790d77a98b0SSuraj Jitindar Singh /* In Memory Table MMU h-calls */ 1791d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1792d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1793d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1794d77a98b0SSuraj Jitindar Singh 1795c59704b2SSuraj Jitindar Singh /* hcall-get-cpu-characteristics */ 1796c59704b2SSuraj Jitindar Singh spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 1797c59704b2SSuraj Jitindar Singh h_get_cpu_characteristics); 1798c59704b2SSuraj Jitindar Singh 17999f64bd8aSPaolo Bonzini /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 18009f64bd8aSPaolo Bonzini * here between the "CI" and the "CACHE" variants, they will use whatever 18019f64bd8aSPaolo Bonzini * mapping attributes qemu is using. When using KVM, the kernel will 18029f64bd8aSPaolo Bonzini * enforce the attributes more strongly 18039f64bd8aSPaolo Bonzini */ 18049f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 18059f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 18069f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 18079f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 18089f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 18099f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 18109f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 18119f64bd8aSPaolo Bonzini 18129f64bd8aSPaolo Bonzini /* qemu/KVM-PPC specific hcalls */ 18139f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 181442561bf2SAnton Blanchard 18152a6593cbSAlexey Kardashevskiy /* ibm,client-architecture-support support */ 18162a6593cbSAlexey Kardashevskiy spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 18179f64bd8aSPaolo Bonzini } 18189f64bd8aSPaolo Bonzini 18199f64bd8aSPaolo Bonzini type_init(hypercall_register_types) 1820