10d75590dSPeter Maydell #include "qemu/osdep.h" 20c21e073SDavid Gibson #include "qemu/cutils.h" 3da34e65cSMarkus Armbruster #include "qapi/error.h" 4b3946626SVincent Palatin #include "sysemu/hw_accel.h" 554d31236SMarkus Armbruster #include "sysemu/runstate.h" 603dd024fSPaolo Bonzini #include "qemu/log.h" 7db725815SMarkus Armbruster #include "qemu/main-loop.h" 80b8fa32fSMarkus Armbruster #include "qemu/module.h" 90b0b8310SDavid Gibson #include "qemu/error-report.h" 1063c91552SPaolo Bonzini #include "exec/exec-all.h" 11548c9609SAlex Bennée #include "exec/tb-flush.h" 129f64bd8aSPaolo Bonzini #include "helper_regs.h" 13120f738aSNicholas Piggin #include "hw/ppc/ppc.h" 140d09e41aSPaolo Bonzini #include "hw/ppc/spapr.h" 157388efafSDavid Gibson #include "hw/ppc/spapr_cpu_core.h" 166b8a0537SNicholas Piggin #include "hw/ppc/spapr_nested.h" 17d5aea6f3SDavid Gibson #include "mmu-hash64.h" 183794d548SAlexey Kardashevskiy #include "cpu-models.h" 193794d548SAlexey Kardashevskiy #include "trace.h" 203794d548SAlexey Kardashevskiy #include "kvm_ppc.h" 210c21e073SDavid Gibson #include "hw/ppc/fdt.h" 22facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 23a165ac67SDaniel Henrique Barboza #include "hw/ppc/spapr_numa.h" 24b4db5413SSuraj Jitindar Singh #include "mmu-book3s-v3.h" 252cc0e2e8SDavid Hildenbrand #include "hw/mem/memory-device.h" 269f64bd8aSPaolo Bonzini 27962104f0SLucas Mateus Castro (alqotel) bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) 28ecbc25faSDavid Gibson { 29ecbc25faSDavid Gibson MachineState *machine = MACHINE(spapr); 30e017da37SDavid Hildenbrand DeviceMemoryState *dms = machine->device_memory; 31ecbc25faSDavid Gibson 32ecbc25faSDavid Gibson if (addr < machine->ram_size) { 33ecbc25faSDavid Gibson return true; 34ecbc25faSDavid Gibson } 35*c0ce7b4aSDavid Hildenbrand if (dms && (addr >= dms->base) 36e017da37SDavid Hildenbrand && ((addr - dms->base) < memory_region_size(&dms->mr))) { 37ecbc25faSDavid Gibson return true; 38ecbc25faSDavid Gibson } 39ecbc25faSDavid Gibson 40ecbc25faSDavid Gibson return false; 41ecbc25faSDavid Gibson } 42ecbc25faSDavid Gibson 43b55d295eSDavid Gibson /* Convert a return code from the KVM ioctl()s implementing resize HPT 44b55d295eSDavid Gibson * into a PAPR hypercall return code */ 45b55d295eSDavid Gibson static target_ulong resize_hpt_convert_rc(int ret) 46b55d295eSDavid Gibson { 47b55d295eSDavid Gibson if (ret >= 100000) { 48b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_100_SEC; 49b55d295eSDavid Gibson } else if (ret >= 10000) { 50b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_10_SEC; 51b55d295eSDavid Gibson } else if (ret >= 1000) { 52b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_1_SEC; 53b55d295eSDavid Gibson } else if (ret >= 100) { 54b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 55b55d295eSDavid Gibson } else if (ret >= 10) { 56b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_10_MSEC; 57b55d295eSDavid Gibson } else if (ret > 0) { 58b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_1_MSEC; 59b55d295eSDavid Gibson } 60b55d295eSDavid Gibson 61b55d295eSDavid Gibson switch (ret) { 62b55d295eSDavid Gibson case 0: 63b55d295eSDavid Gibson return H_SUCCESS; 64b55d295eSDavid Gibson case -EPERM: 65b55d295eSDavid Gibson return H_AUTHORITY; 66b55d295eSDavid Gibson case -EINVAL: 67b55d295eSDavid Gibson return H_PARAMETER; 68b55d295eSDavid Gibson case -ENXIO: 69b55d295eSDavid Gibson return H_CLOSED; 70b55d295eSDavid Gibson case -ENOSPC: 71b55d295eSDavid Gibson return H_PTEG_FULL; 72b55d295eSDavid Gibson case -EBUSY: 73b55d295eSDavid Gibson return H_BUSY; 74b55d295eSDavid Gibson case -ENOMEM: 75b55d295eSDavid Gibson return H_NO_MEM; 76b55d295eSDavid Gibson default: 77b55d295eSDavid Gibson return H_HARDWARE; 78b55d295eSDavid Gibson } 79b55d295eSDavid Gibson } 80b55d295eSDavid Gibson 8130f4b05bSDavid Gibson static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 82ce2918cbSDavid Gibson SpaprMachineState *spapr, 8330f4b05bSDavid Gibson target_ulong opcode, 8430f4b05bSDavid Gibson target_ulong *args) 8530f4b05bSDavid Gibson { 8630f4b05bSDavid Gibson target_ulong flags = args[0]; 870b0b8310SDavid Gibson int shift = args[1]; 88db50f280SDavid Gibson uint64_t current_ram_size; 89b55d295eSDavid Gibson int rc; 9030f4b05bSDavid Gibson 9130f4b05bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 9230f4b05bSDavid Gibson return H_AUTHORITY; 9330f4b05bSDavid Gibson } 9430f4b05bSDavid Gibson 950b0b8310SDavid Gibson if (!spapr->htab_shift) { 960b0b8310SDavid Gibson /* Radix guest, no HPT */ 970b0b8310SDavid Gibson return H_NOT_AVAILABLE; 980b0b8310SDavid Gibson } 990b0b8310SDavid Gibson 10030f4b05bSDavid Gibson trace_spapr_h_resize_hpt_prepare(flags, shift); 1010b0b8310SDavid Gibson 1020b0b8310SDavid Gibson if (flags != 0) { 1030b0b8310SDavid Gibson return H_PARAMETER; 1040b0b8310SDavid Gibson } 1050b0b8310SDavid Gibson 1060b0b8310SDavid Gibson if (shift && ((shift < 18) || (shift > 46))) { 1070b0b8310SDavid Gibson return H_PARAMETER; 1080b0b8310SDavid Gibson } 1090b0b8310SDavid Gibson 110db50f280SDavid Gibson current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1110b0b8310SDavid Gibson 1120b0b8310SDavid Gibson /* We only allow the guest to allocate an HPT one order above what 1130b0b8310SDavid Gibson * we'd normally give them (to stop a small guest claiming a huge 1140b0b8310SDavid Gibson * chunk of resources in the HPT */ 1150b0b8310SDavid Gibson if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 1160b0b8310SDavid Gibson return H_RESOURCE; 1170b0b8310SDavid Gibson } 1180b0b8310SDavid Gibson 119b55d295eSDavid Gibson rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 120b55d295eSDavid Gibson if (rc != -ENOSYS) { 121b55d295eSDavid Gibson return resize_hpt_convert_rc(rc); 122b55d295eSDavid Gibson } 123b55d295eSDavid Gibson 124962104f0SLucas Mateus Castro (alqotel) if (kvm_enabled()) { 12530f4b05bSDavid Gibson return H_HARDWARE; 12630f4b05bSDavid Gibson } 12730f4b05bSDavid Gibson 128962104f0SLucas Mateus Castro (alqotel) return softmmu_resize_hpt_prepare(cpu, spapr, shift); 1290b0b8310SDavid Gibson } 1300b0b8310SDavid Gibson 1311ec26c75SGreg Kurz static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 1321ec26c75SGreg Kurz { 1331ec26c75SGreg Kurz int ret; 1341ec26c75SGreg Kurz 1351ec26c75SGreg Kurz cpu_synchronize_state(cs); 1361ec26c75SGreg Kurz 1371ec26c75SGreg Kurz ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 1381ec26c75SGreg Kurz if (ret < 0) { 1391ec26c75SGreg Kurz error_report("failed to push sregs to KVM: %s", strerror(-ret)); 1401ec26c75SGreg Kurz exit(1); 1411ec26c75SGreg Kurz } 1421ec26c75SGreg Kurz } 1431ec26c75SGreg Kurz 144962104f0SLucas Mateus Castro (alqotel) void push_sregs_to_kvm_pr(SpaprMachineState *spapr) 1451ec26c75SGreg Kurz { 1461ec26c75SGreg Kurz CPUState *cs; 1471ec26c75SGreg Kurz 1481ec26c75SGreg Kurz /* 1491ec26c75SGreg Kurz * This is a hack for the benefit of KVM PR - it abuses the SDR1 1501ec26c75SGreg Kurz * slot in kvm_sregs to communicate the userspace address of the 1511ec26c75SGreg Kurz * HPT 1521ec26c75SGreg Kurz */ 1531ec26c75SGreg Kurz if (!kvm_enabled() || !spapr->htab) { 1541ec26c75SGreg Kurz return; 1551ec26c75SGreg Kurz } 1561ec26c75SGreg Kurz 1571ec26c75SGreg Kurz CPU_FOREACH(cs) { 1581ec26c75SGreg Kurz run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 1591ec26c75SGreg Kurz } 1601ec26c75SGreg Kurz } 1611ec26c75SGreg Kurz 16230f4b05bSDavid Gibson static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 163ce2918cbSDavid Gibson SpaprMachineState *spapr, 16430f4b05bSDavid Gibson target_ulong opcode, 16530f4b05bSDavid Gibson target_ulong *args) 16630f4b05bSDavid Gibson { 16730f4b05bSDavid Gibson target_ulong flags = args[0]; 16830f4b05bSDavid Gibson target_ulong shift = args[1]; 1690b0b8310SDavid Gibson int rc; 17030f4b05bSDavid Gibson 17130f4b05bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 17230f4b05bSDavid Gibson return H_AUTHORITY; 17330f4b05bSDavid Gibson } 17430f4b05bSDavid Gibson 17594789567SDaniel Henrique Barboza if (!spapr->htab_shift) { 17694789567SDaniel Henrique Barboza /* Radix guest, no HPT */ 17794789567SDaniel Henrique Barboza return H_NOT_AVAILABLE; 17894789567SDaniel Henrique Barboza } 17994789567SDaniel Henrique Barboza 18030f4b05bSDavid Gibson trace_spapr_h_resize_hpt_commit(flags, shift); 1810b0b8310SDavid Gibson 182b55d295eSDavid Gibson rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 183b55d295eSDavid Gibson if (rc != -ENOSYS) { 18494789567SDaniel Henrique Barboza rc = resize_hpt_convert_rc(rc); 18594789567SDaniel Henrique Barboza if (rc == H_SUCCESS) { 18694789567SDaniel Henrique Barboza /* Need to set the new htab_shift in the machine state */ 18794789567SDaniel Henrique Barboza spapr->htab_shift = shift; 18894789567SDaniel Henrique Barboza } 18994789567SDaniel Henrique Barboza return rc; 190b55d295eSDavid Gibson } 191b55d295eSDavid Gibson 192962104f0SLucas Mateus Castro (alqotel) if (kvm_enabled()) { 193962104f0SLucas Mateus Castro (alqotel) return H_HARDWARE; 1940b0b8310SDavid Gibson } 1950b0b8310SDavid Gibson 196962104f0SLucas Mateus Castro (alqotel) return softmmu_resize_hpt_commit(cpu, spapr, flags, shift); 1970b0b8310SDavid Gibson } 1980b0b8310SDavid Gibson 1990b0b8310SDavid Gibson 20030f4b05bSDavid Gibson 201ce2918cbSDavid Gibson static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, 202423576f7SThomas Huth target_ulong opcode, target_ulong *args) 203423576f7SThomas Huth { 204423576f7SThomas Huth cpu_synchronize_state(CPU(cpu)); 205423576f7SThomas Huth cpu->env.spr[SPR_SPRG0] = args[0]; 206423576f7SThomas Huth 207423576f7SThomas Huth return H_SUCCESS; 208423576f7SThomas Huth } 209423576f7SThomas Huth 210ce2918cbSDavid Gibson static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 2119f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 2129f64bd8aSPaolo Bonzini { 21303282a3aSLucas Mateus Castro (alqotel) if (!ppc_has_spr(cpu, SPR_DABR)) { 214af08a58fSThomas Huth return H_HARDWARE; /* DABR register not available */ 215af08a58fSThomas Huth } 216af08a58fSThomas Huth cpu_synchronize_state(CPU(cpu)); 217af08a58fSThomas Huth 21803282a3aSLucas Mateus Castro (alqotel) if (ppc_has_spr(cpu, SPR_DABRX)) { 219af08a58fSThomas Huth cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 220af08a58fSThomas Huth } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 221af08a58fSThomas Huth return H_RESERVED_DABR; 222af08a58fSThomas Huth } 223af08a58fSThomas Huth 224af08a58fSThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 225af08a58fSThomas Huth return H_SUCCESS; 2269f64bd8aSPaolo Bonzini } 2279f64bd8aSPaolo Bonzini 228ce2918cbSDavid Gibson static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 229e49ff266SThomas Huth target_ulong opcode, target_ulong *args) 230e49ff266SThomas Huth { 231e49ff266SThomas Huth target_ulong dabrx = args[1]; 232e49ff266SThomas Huth 23303282a3aSLucas Mateus Castro (alqotel) if (!ppc_has_spr(cpu, SPR_DABR) || !ppc_has_spr(cpu, SPR_DABRX)) { 234e49ff266SThomas Huth return H_HARDWARE; 235e49ff266SThomas Huth } 236e49ff266SThomas Huth 237e49ff266SThomas Huth if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 238e49ff266SThomas Huth || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 239e49ff266SThomas Huth return H_PARAMETER; 240e49ff266SThomas Huth } 241e49ff266SThomas Huth 242e49ff266SThomas Huth cpu_synchronize_state(CPU(cpu)); 243e49ff266SThomas Huth cpu->env.spr[SPR_DABRX] = dabrx; 244e49ff266SThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 245e49ff266SThomas Huth 246e49ff266SThomas Huth return H_SUCCESS; 247e49ff266SThomas Huth } 248e49ff266SThomas Huth 249ce2918cbSDavid Gibson static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, 2503240dd9aSThomas Huth target_ulong opcode, target_ulong *args) 2513240dd9aSThomas Huth { 2523240dd9aSThomas Huth target_ulong flags = args[0]; 2533240dd9aSThomas Huth hwaddr dst = args[1]; 2543240dd9aSThomas Huth hwaddr src = args[2]; 2553240dd9aSThomas Huth hwaddr len = TARGET_PAGE_SIZE; 2563240dd9aSThomas Huth uint8_t *pdst, *psrc; 2573240dd9aSThomas Huth target_long ret = H_SUCCESS; 2583240dd9aSThomas Huth 2593240dd9aSThomas Huth if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 2603240dd9aSThomas Huth | H_COPY_PAGE | H_ZERO_PAGE)) { 2613240dd9aSThomas Huth qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 2623240dd9aSThomas Huth flags); 2633240dd9aSThomas Huth return H_PARAMETER; 2643240dd9aSThomas Huth } 2653240dd9aSThomas Huth 2663240dd9aSThomas Huth /* Map-in destination */ 2673240dd9aSThomas Huth if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 2683240dd9aSThomas Huth return H_PARAMETER; 2693240dd9aSThomas Huth } 27085eb7c18SPhilippe Mathieu-Daudé pdst = cpu_physical_memory_map(dst, &len, true); 2713240dd9aSThomas Huth if (!pdst || len != TARGET_PAGE_SIZE) { 2723240dd9aSThomas Huth return H_PARAMETER; 2733240dd9aSThomas Huth } 2743240dd9aSThomas Huth 2753240dd9aSThomas Huth if (flags & H_COPY_PAGE) { 2763240dd9aSThomas Huth /* Map-in source, copy to destination, and unmap source again */ 2773240dd9aSThomas Huth if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 2783240dd9aSThomas Huth ret = H_PARAMETER; 2793240dd9aSThomas Huth goto unmap_out; 2803240dd9aSThomas Huth } 28185eb7c18SPhilippe Mathieu-Daudé psrc = cpu_physical_memory_map(src, &len, false); 2823240dd9aSThomas Huth if (!psrc || len != TARGET_PAGE_SIZE) { 2833240dd9aSThomas Huth ret = H_PARAMETER; 2843240dd9aSThomas Huth goto unmap_out; 2853240dd9aSThomas Huth } 2863240dd9aSThomas Huth memcpy(pdst, psrc, len); 2873240dd9aSThomas Huth cpu_physical_memory_unmap(psrc, len, 0, len); 2883240dd9aSThomas Huth } else if (flags & H_ZERO_PAGE) { 2893240dd9aSThomas Huth memset(pdst, 0, len); /* Just clear the destination page */ 2903240dd9aSThomas Huth } 2913240dd9aSThomas Huth 2923240dd9aSThomas Huth if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 2933240dd9aSThomas Huth kvmppc_dcbst_range(cpu, pdst, len); 2943240dd9aSThomas Huth } 2953240dd9aSThomas Huth if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 2963240dd9aSThomas Huth if (kvm_enabled()) { 2973240dd9aSThomas Huth kvmppc_icbi_range(cpu, pdst, len); 2983240dd9aSThomas Huth } else { 2993240dd9aSThomas Huth tb_flush(CPU(cpu)); 3003240dd9aSThomas Huth } 3013240dd9aSThomas Huth } 3023240dd9aSThomas Huth 3033240dd9aSThomas Huth unmap_out: 3043240dd9aSThomas Huth cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 3053240dd9aSThomas Huth return ret; 3063240dd9aSThomas Huth } 3073240dd9aSThomas Huth 3089f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 3099f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 3109f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 3119f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 3129f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 3139f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 3149f64bd8aSPaolo Bonzini 3157388efafSDavid Gibson static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) 3169f64bd8aSPaolo Bonzini { 3177388efafSDavid Gibson CPUState *cs = CPU(cpu); 3187388efafSDavid Gibson CPUPPCState *env = &cpu->env; 319ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 3209f64bd8aSPaolo Bonzini uint16_t size; 3219f64bd8aSPaolo Bonzini uint8_t tmp; 3229f64bd8aSPaolo Bonzini 3239f64bd8aSPaolo Bonzini if (vpa == 0) { 3249f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 3259f64bd8aSPaolo Bonzini return H_HARDWARE; 3269f64bd8aSPaolo Bonzini } 3279f64bd8aSPaolo Bonzini 3289f64bd8aSPaolo Bonzini if (vpa % env->dcache_line_size) { 3299f64bd8aSPaolo Bonzini return H_PARAMETER; 3309f64bd8aSPaolo Bonzini } 3319f64bd8aSPaolo Bonzini /* FIXME: bounds check the address */ 3329f64bd8aSPaolo Bonzini 33341701aa4SEdgar E. Iglesias size = lduw_be_phys(cs->as, vpa + 0x4); 3349f64bd8aSPaolo Bonzini 3359f64bd8aSPaolo Bonzini if (size < VPA_MIN_SIZE) { 3369f64bd8aSPaolo Bonzini return H_PARAMETER; 3379f64bd8aSPaolo Bonzini } 3389f64bd8aSPaolo Bonzini 3399f64bd8aSPaolo Bonzini /* VPA is not allowed to cross a page boundary */ 3409f64bd8aSPaolo Bonzini if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 3419f64bd8aSPaolo Bonzini return H_PARAMETER; 3429f64bd8aSPaolo Bonzini } 3439f64bd8aSPaolo Bonzini 3447388efafSDavid Gibson spapr_cpu->vpa_addr = vpa; 3459f64bd8aSPaolo Bonzini 3467388efafSDavid Gibson tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET); 3479f64bd8aSPaolo Bonzini tmp |= VPA_SHARED_PROC_VAL; 3487388efafSDavid Gibson stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 3499f64bd8aSPaolo Bonzini 3509f64bd8aSPaolo Bonzini return H_SUCCESS; 3519f64bd8aSPaolo Bonzini } 3529f64bd8aSPaolo Bonzini 3537388efafSDavid Gibson static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) 3549f64bd8aSPaolo Bonzini { 355ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 3567388efafSDavid Gibson 3577388efafSDavid Gibson if (spapr_cpu->slb_shadow_addr) { 3589f64bd8aSPaolo Bonzini return H_RESOURCE; 3599f64bd8aSPaolo Bonzini } 3609f64bd8aSPaolo Bonzini 3617388efafSDavid Gibson if (spapr_cpu->dtl_addr) { 3629f64bd8aSPaolo Bonzini return H_RESOURCE; 3639f64bd8aSPaolo Bonzini } 3649f64bd8aSPaolo Bonzini 3657388efafSDavid Gibson spapr_cpu->vpa_addr = 0; 3669f64bd8aSPaolo Bonzini return H_SUCCESS; 3679f64bd8aSPaolo Bonzini } 3689f64bd8aSPaolo Bonzini 3697388efafSDavid Gibson static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 3709f64bd8aSPaolo Bonzini { 371ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 3729f64bd8aSPaolo Bonzini uint32_t size; 3739f64bd8aSPaolo Bonzini 3749f64bd8aSPaolo Bonzini if (addr == 0) { 3759f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 3769f64bd8aSPaolo Bonzini return H_HARDWARE; 3779f64bd8aSPaolo Bonzini } 3789f64bd8aSPaolo Bonzini 3797388efafSDavid Gibson size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 3809f64bd8aSPaolo Bonzini if (size < 0x8) { 3819f64bd8aSPaolo Bonzini return H_PARAMETER; 3829f64bd8aSPaolo Bonzini } 3839f64bd8aSPaolo Bonzini 3849f64bd8aSPaolo Bonzini if ((addr / 4096) != ((addr + size - 1) / 4096)) { 3859f64bd8aSPaolo Bonzini return H_PARAMETER; 3869f64bd8aSPaolo Bonzini } 3879f64bd8aSPaolo Bonzini 3887388efafSDavid Gibson if (!spapr_cpu->vpa_addr) { 3899f64bd8aSPaolo Bonzini return H_RESOURCE; 3909f64bd8aSPaolo Bonzini } 3919f64bd8aSPaolo Bonzini 3927388efafSDavid Gibson spapr_cpu->slb_shadow_addr = addr; 3937388efafSDavid Gibson spapr_cpu->slb_shadow_size = size; 3949f64bd8aSPaolo Bonzini 3959f64bd8aSPaolo Bonzini return H_SUCCESS; 3969f64bd8aSPaolo Bonzini } 3979f64bd8aSPaolo Bonzini 3987388efafSDavid Gibson static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 3999f64bd8aSPaolo Bonzini { 400ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4017388efafSDavid Gibson 4027388efafSDavid Gibson spapr_cpu->slb_shadow_addr = 0; 4037388efafSDavid Gibson spapr_cpu->slb_shadow_size = 0; 4049f64bd8aSPaolo Bonzini return H_SUCCESS; 4059f64bd8aSPaolo Bonzini } 4069f64bd8aSPaolo Bonzini 4077388efafSDavid Gibson static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) 4089f64bd8aSPaolo Bonzini { 409ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4109f64bd8aSPaolo Bonzini uint32_t size; 4119f64bd8aSPaolo Bonzini 4129f64bd8aSPaolo Bonzini if (addr == 0) { 4139f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with DTL at logical 0\n"); 4149f64bd8aSPaolo Bonzini return H_HARDWARE; 4159f64bd8aSPaolo Bonzini } 4169f64bd8aSPaolo Bonzini 4177388efafSDavid Gibson size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 4189f64bd8aSPaolo Bonzini 4199f64bd8aSPaolo Bonzini if (size < 48) { 4209f64bd8aSPaolo Bonzini return H_PARAMETER; 4219f64bd8aSPaolo Bonzini } 4229f64bd8aSPaolo Bonzini 4237388efafSDavid Gibson if (!spapr_cpu->vpa_addr) { 4249f64bd8aSPaolo Bonzini return H_RESOURCE; 4259f64bd8aSPaolo Bonzini } 4269f64bd8aSPaolo Bonzini 4277388efafSDavid Gibson spapr_cpu->dtl_addr = addr; 4287388efafSDavid Gibson spapr_cpu->dtl_size = size; 4299f64bd8aSPaolo Bonzini 4309f64bd8aSPaolo Bonzini return H_SUCCESS; 4319f64bd8aSPaolo Bonzini } 4329f64bd8aSPaolo Bonzini 4337388efafSDavid Gibson static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) 4349f64bd8aSPaolo Bonzini { 435ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4367388efafSDavid Gibson 4377388efafSDavid Gibson spapr_cpu->dtl_addr = 0; 4387388efafSDavid Gibson spapr_cpu->dtl_size = 0; 4399f64bd8aSPaolo Bonzini 4409f64bd8aSPaolo Bonzini return H_SUCCESS; 4419f64bd8aSPaolo Bonzini } 4429f64bd8aSPaolo Bonzini 443ce2918cbSDavid Gibson static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr, 4449f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 4459f64bd8aSPaolo Bonzini { 4469f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 4479f64bd8aSPaolo Bonzini target_ulong procno = args[1]; 4489f64bd8aSPaolo Bonzini target_ulong vpa = args[2]; 4499f64bd8aSPaolo Bonzini target_ulong ret = H_PARAMETER; 4500f20ba62SAlexey Kardashevskiy PowerPCCPU *tcpu; 4519f64bd8aSPaolo Bonzini 4522e886fb3SSam Bobroff tcpu = spapr_find_cpu(procno); 4539f64bd8aSPaolo Bonzini if (!tcpu) { 4549f64bd8aSPaolo Bonzini return H_PARAMETER; 4559f64bd8aSPaolo Bonzini } 4569f64bd8aSPaolo Bonzini 4579f64bd8aSPaolo Bonzini switch (flags) { 4589f64bd8aSPaolo Bonzini case FLAGS_REGISTER_VPA: 4597388efafSDavid Gibson ret = register_vpa(tcpu, vpa); 4609f64bd8aSPaolo Bonzini break; 4619f64bd8aSPaolo Bonzini 4629f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_VPA: 4637388efafSDavid Gibson ret = deregister_vpa(tcpu, vpa); 4649f64bd8aSPaolo Bonzini break; 4659f64bd8aSPaolo Bonzini 4669f64bd8aSPaolo Bonzini case FLAGS_REGISTER_SLBSHADOW: 4677388efafSDavid Gibson ret = register_slb_shadow(tcpu, vpa); 4689f64bd8aSPaolo Bonzini break; 4699f64bd8aSPaolo Bonzini 4709f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_SLBSHADOW: 4717388efafSDavid Gibson ret = deregister_slb_shadow(tcpu, vpa); 4729f64bd8aSPaolo Bonzini break; 4739f64bd8aSPaolo Bonzini 4749f64bd8aSPaolo Bonzini case FLAGS_REGISTER_DTL: 4757388efafSDavid Gibson ret = register_dtl(tcpu, vpa); 4769f64bd8aSPaolo Bonzini break; 4779f64bd8aSPaolo Bonzini 4789f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_DTL: 4797388efafSDavid Gibson ret = deregister_dtl(tcpu, vpa); 4809f64bd8aSPaolo Bonzini break; 4819f64bd8aSPaolo Bonzini } 4829f64bd8aSPaolo Bonzini 4839f64bd8aSPaolo Bonzini return ret; 4849f64bd8aSPaolo Bonzini } 4859f64bd8aSPaolo Bonzini 486ce2918cbSDavid Gibson static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, 4879f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 4889f64bd8aSPaolo Bonzini { 4899f64bd8aSPaolo Bonzini CPUPPCState *env = &cpu->env; 4909f64bd8aSPaolo Bonzini CPUState *cs = CPU(cpu); 4913a6e6224SNicholas Piggin SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4929f64bd8aSPaolo Bonzini 4939f64bd8aSPaolo Bonzini env->msr |= (1ULL << MSR_EE); 4949f64bd8aSPaolo Bonzini hreg_compute_hflags(env); 4952fdedcbcSMatheus Ferst ppc_maybe_interrupt(env); 4963a6e6224SNicholas Piggin 4973a6e6224SNicholas Piggin if (spapr_cpu->prod) { 4983a6e6224SNicholas Piggin spapr_cpu->prod = false; 4993a6e6224SNicholas Piggin return H_SUCCESS; 5003a6e6224SNicholas Piggin } 5013a6e6224SNicholas Piggin 5029f64bd8aSPaolo Bonzini if (!cpu_has_work(cs)) { 503259186a7SAndreas Färber cs->halted = 1; 50427103424SAndreas Färber cs->exception_index = EXCP_HLT; 5059f64bd8aSPaolo Bonzini cs->exit_request = 1; 5062fdedcbcSMatheus Ferst ppc_maybe_interrupt(env); 5079f64bd8aSPaolo Bonzini } 5083a6e6224SNicholas Piggin 5093a6e6224SNicholas Piggin return H_SUCCESS; 5103a6e6224SNicholas Piggin } 5113a6e6224SNicholas Piggin 51210741314SNicholas Piggin /* 51310741314SNicholas Piggin * Confer to self, aka join. Cede could use the same pattern as well, if 51410741314SNicholas Piggin * EXCP_HLT can be changed to ECXP_HALTED. 51510741314SNicholas Piggin */ 51610741314SNicholas Piggin static target_ulong h_confer_self(PowerPCCPU *cpu) 51710741314SNicholas Piggin { 51810741314SNicholas Piggin CPUState *cs = CPU(cpu); 51910741314SNicholas Piggin SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 52010741314SNicholas Piggin 52110741314SNicholas Piggin if (spapr_cpu->prod) { 52210741314SNicholas Piggin spapr_cpu->prod = false; 52310741314SNicholas Piggin return H_SUCCESS; 52410741314SNicholas Piggin } 52510741314SNicholas Piggin cs->halted = 1; 52610741314SNicholas Piggin cs->exception_index = EXCP_HALTED; 52710741314SNicholas Piggin cs->exit_request = 1; 5282fdedcbcSMatheus Ferst ppc_maybe_interrupt(&cpu->env); 52910741314SNicholas Piggin 53010741314SNicholas Piggin return H_SUCCESS; 53110741314SNicholas Piggin } 53210741314SNicholas Piggin 53310741314SNicholas Piggin static target_ulong h_join(PowerPCCPU *cpu, SpaprMachineState *spapr, 53410741314SNicholas Piggin target_ulong opcode, target_ulong *args) 53510741314SNicholas Piggin { 53610741314SNicholas Piggin CPUPPCState *env = &cpu->env; 53710741314SNicholas Piggin CPUState *cs; 53810741314SNicholas Piggin bool last_unjoined = true; 53910741314SNicholas Piggin 54010741314SNicholas Piggin if (env->msr & (1ULL << MSR_EE)) { 54110741314SNicholas Piggin return H_BAD_MODE; 54210741314SNicholas Piggin } 54310741314SNicholas Piggin 54410741314SNicholas Piggin /* 54510741314SNicholas Piggin * Must not join the last CPU running. Interestingly, no such restriction 54610741314SNicholas Piggin * for H_CONFER-to-self, but that is probably not intended to be used 54710741314SNicholas Piggin * when H_JOIN is available. 54810741314SNicholas Piggin */ 54910741314SNicholas Piggin CPU_FOREACH(cs) { 55010741314SNicholas Piggin PowerPCCPU *c = POWERPC_CPU(cs); 55110741314SNicholas Piggin CPUPPCState *e = &c->env; 55210741314SNicholas Piggin if (c == cpu) { 55310741314SNicholas Piggin continue; 55410741314SNicholas Piggin } 55510741314SNicholas Piggin 55610741314SNicholas Piggin /* Don't have a way to indicate joined, so use halted && MSR[EE]=0 */ 55710741314SNicholas Piggin if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { 55810741314SNicholas Piggin last_unjoined = false; 55910741314SNicholas Piggin break; 56010741314SNicholas Piggin } 56110741314SNicholas Piggin } 56210741314SNicholas Piggin if (last_unjoined) { 56310741314SNicholas Piggin return H_CONTINUE; 56410741314SNicholas Piggin } 56510741314SNicholas Piggin 56610741314SNicholas Piggin return h_confer_self(cpu); 56710741314SNicholas Piggin } 56810741314SNicholas Piggin 569e8ce0e40SNicholas Piggin static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr, 570e8ce0e40SNicholas Piggin target_ulong opcode, target_ulong *args) 571e8ce0e40SNicholas Piggin { 572e8ce0e40SNicholas Piggin target_long target = args[0]; 573e8ce0e40SNicholas Piggin uint32_t dispatch = args[1]; 574e8ce0e40SNicholas Piggin CPUState *cs = CPU(cpu); 575e8ce0e40SNicholas Piggin SpaprCpuState *spapr_cpu; 576e8ce0e40SNicholas Piggin 577e8ce0e40SNicholas Piggin /* 578e8ce0e40SNicholas Piggin * -1 means confer to all other CPUs without dispatch counter check, 579e8ce0e40SNicholas Piggin * otherwise it's a targeted confer. 580e8ce0e40SNicholas Piggin */ 581e8ce0e40SNicholas Piggin if (target != -1) { 582e8ce0e40SNicholas Piggin PowerPCCPU *target_cpu = spapr_find_cpu(target); 583e8ce0e40SNicholas Piggin uint32_t target_dispatch; 584e8ce0e40SNicholas Piggin 585e8ce0e40SNicholas Piggin if (!target_cpu) { 586e8ce0e40SNicholas Piggin return H_PARAMETER; 587e8ce0e40SNicholas Piggin } 588e8ce0e40SNicholas Piggin 589e8ce0e40SNicholas Piggin /* 590e8ce0e40SNicholas Piggin * target == self is a special case, we wait until prodded, without 591e8ce0e40SNicholas Piggin * dispatch counter check. 592e8ce0e40SNicholas Piggin */ 593e8ce0e40SNicholas Piggin if (cpu == target_cpu) { 59410741314SNicholas Piggin return h_confer_self(cpu); 595e8ce0e40SNicholas Piggin } 596e8ce0e40SNicholas Piggin 59710741314SNicholas Piggin spapr_cpu = spapr_cpu_state(target_cpu); 598e8ce0e40SNicholas Piggin if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) { 599e8ce0e40SNicholas Piggin return H_SUCCESS; 600e8ce0e40SNicholas Piggin } 601e8ce0e40SNicholas Piggin 602e8ce0e40SNicholas Piggin target_dispatch = ldl_be_phys(cs->as, 603e8ce0e40SNicholas Piggin spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 604e8ce0e40SNicholas Piggin if (target_dispatch != dispatch) { 605e8ce0e40SNicholas Piggin return H_SUCCESS; 606e8ce0e40SNicholas Piggin } 607e8ce0e40SNicholas Piggin 608e8ce0e40SNicholas Piggin /* 609e8ce0e40SNicholas Piggin * The targeted confer does not do anything special beyond yielding 610e8ce0e40SNicholas Piggin * the current vCPU, but even this should be better than nothing. 611e8ce0e40SNicholas Piggin * At least for single-threaded tcg, it gives the target a chance to 612e8ce0e40SNicholas Piggin * run before we run again. Multi-threaded tcg does not really do 613e8ce0e40SNicholas Piggin * anything with EXCP_YIELD yet. 614e8ce0e40SNicholas Piggin */ 615e8ce0e40SNicholas Piggin } 616e8ce0e40SNicholas Piggin 617e8ce0e40SNicholas Piggin cs->exception_index = EXCP_YIELD; 618e8ce0e40SNicholas Piggin cs->exit_request = 1; 619e8ce0e40SNicholas Piggin cpu_loop_exit(cs); 620e8ce0e40SNicholas Piggin 621e8ce0e40SNicholas Piggin return H_SUCCESS; 622e8ce0e40SNicholas Piggin } 623e8ce0e40SNicholas Piggin 6243a6e6224SNicholas Piggin static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr, 6253a6e6224SNicholas Piggin target_ulong opcode, target_ulong *args) 6263a6e6224SNicholas Piggin { 6273a6e6224SNicholas Piggin target_long target = args[0]; 6283a6e6224SNicholas Piggin PowerPCCPU *tcpu; 6293a6e6224SNicholas Piggin CPUState *cs; 6303a6e6224SNicholas Piggin SpaprCpuState *spapr_cpu; 6313a6e6224SNicholas Piggin 6323a6e6224SNicholas Piggin tcpu = spapr_find_cpu(target); 6333a6e6224SNicholas Piggin cs = CPU(tcpu); 6343a6e6224SNicholas Piggin if (!cs) { 6353a6e6224SNicholas Piggin return H_PARAMETER; 6363a6e6224SNicholas Piggin } 6373a6e6224SNicholas Piggin 6383a6e6224SNicholas Piggin spapr_cpu = spapr_cpu_state(tcpu); 6393a6e6224SNicholas Piggin spapr_cpu->prod = true; 6403a6e6224SNicholas Piggin cs->halted = 0; 6412fdedcbcSMatheus Ferst ppc_maybe_interrupt(&cpu->env); 6423a6e6224SNicholas Piggin qemu_cpu_kick(cs); 6433a6e6224SNicholas Piggin 6449f64bd8aSPaolo Bonzini return H_SUCCESS; 6459f64bd8aSPaolo Bonzini } 6469f64bd8aSPaolo Bonzini 647ce2918cbSDavid Gibson static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, 6489f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 6499f64bd8aSPaolo Bonzini { 6509f64bd8aSPaolo Bonzini target_ulong rtas_r3 = args[0]; 6514fe822e0SAlexey Kardashevskiy uint32_t token = rtas_ld(rtas_r3, 0); 6524fe822e0SAlexey Kardashevskiy uint32_t nargs = rtas_ld(rtas_r3, 1); 6534fe822e0SAlexey Kardashevskiy uint32_t nret = rtas_ld(rtas_r3, 2); 6549f64bd8aSPaolo Bonzini 655210b580bSAnthony Liguori return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 6569f64bd8aSPaolo Bonzini nret, rtas_r3 + 12 + 4*nargs); 6579f64bd8aSPaolo Bonzini } 6589f64bd8aSPaolo Bonzini 659ce2918cbSDavid Gibson static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr, 6609f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 6619f64bd8aSPaolo Bonzini { 662fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 6639f64bd8aSPaolo Bonzini target_ulong size = args[0]; 6649f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 6659f64bd8aSPaolo Bonzini 6669f64bd8aSPaolo Bonzini switch (size) { 6679f64bd8aSPaolo Bonzini case 1: 6682c17449bSEdgar E. Iglesias args[0] = ldub_phys(cs->as, addr); 6699f64bd8aSPaolo Bonzini return H_SUCCESS; 6709f64bd8aSPaolo Bonzini case 2: 67141701aa4SEdgar E. Iglesias args[0] = lduw_phys(cs->as, addr); 6729f64bd8aSPaolo Bonzini return H_SUCCESS; 6739f64bd8aSPaolo Bonzini case 4: 674fdfba1a2SEdgar E. Iglesias args[0] = ldl_phys(cs->as, addr); 6759f64bd8aSPaolo Bonzini return H_SUCCESS; 6769f64bd8aSPaolo Bonzini case 8: 6772c17449bSEdgar E. Iglesias args[0] = ldq_phys(cs->as, addr); 6789f64bd8aSPaolo Bonzini return H_SUCCESS; 6799f64bd8aSPaolo Bonzini } 6809f64bd8aSPaolo Bonzini return H_PARAMETER; 6819f64bd8aSPaolo Bonzini } 6829f64bd8aSPaolo Bonzini 683ce2918cbSDavid Gibson static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr, 6849f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 6859f64bd8aSPaolo Bonzini { 686f606604fSEdgar E. Iglesias CPUState *cs = CPU(cpu); 687f606604fSEdgar E. Iglesias 6889f64bd8aSPaolo Bonzini target_ulong size = args[0]; 6899f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 6909f64bd8aSPaolo Bonzini target_ulong val = args[2]; 6919f64bd8aSPaolo Bonzini 6929f64bd8aSPaolo Bonzini switch (size) { 6939f64bd8aSPaolo Bonzini case 1: 694db3be60dSEdgar E. Iglesias stb_phys(cs->as, addr, val); 6959f64bd8aSPaolo Bonzini return H_SUCCESS; 6969f64bd8aSPaolo Bonzini case 2: 6975ce5944dSEdgar E. Iglesias stw_phys(cs->as, addr, val); 6989f64bd8aSPaolo Bonzini return H_SUCCESS; 6999f64bd8aSPaolo Bonzini case 4: 700ab1da857SEdgar E. Iglesias stl_phys(cs->as, addr, val); 7019f64bd8aSPaolo Bonzini return H_SUCCESS; 7029f64bd8aSPaolo Bonzini case 8: 703f606604fSEdgar E. Iglesias stq_phys(cs->as, addr, val); 7049f64bd8aSPaolo Bonzini return H_SUCCESS; 7059f64bd8aSPaolo Bonzini } 7069f64bd8aSPaolo Bonzini return H_PARAMETER; 7079f64bd8aSPaolo Bonzini } 7089f64bd8aSPaolo Bonzini 709ce2918cbSDavid Gibson static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr, 7109f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 7119f64bd8aSPaolo Bonzini { 712fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 713fdfba1a2SEdgar E. Iglesias 7149f64bd8aSPaolo Bonzini target_ulong dst = args[0]; /* Destination address */ 7159f64bd8aSPaolo Bonzini target_ulong src = args[1]; /* Source address */ 7169f64bd8aSPaolo Bonzini target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 7179f64bd8aSPaolo Bonzini target_ulong count = args[3]; /* Element count */ 7189f64bd8aSPaolo Bonzini target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 7199f64bd8aSPaolo Bonzini uint64_t tmp; 7209f64bd8aSPaolo Bonzini unsigned int mask = (1 << esize) - 1; 7219f64bd8aSPaolo Bonzini int step = 1 << esize; 7229f64bd8aSPaolo Bonzini 7239f64bd8aSPaolo Bonzini if (count > 0x80000000) { 7249f64bd8aSPaolo Bonzini return H_PARAMETER; 7259f64bd8aSPaolo Bonzini } 7269f64bd8aSPaolo Bonzini 7279f64bd8aSPaolo Bonzini if ((dst & mask) || (src & mask) || (op > 1)) { 7289f64bd8aSPaolo Bonzini return H_PARAMETER; 7299f64bd8aSPaolo Bonzini } 7309f64bd8aSPaolo Bonzini 7319f64bd8aSPaolo Bonzini if (dst >= src && dst < (src + (count << esize))) { 7329f64bd8aSPaolo Bonzini dst = dst + ((count - 1) << esize); 7339f64bd8aSPaolo Bonzini src = src + ((count - 1) << esize); 7349f64bd8aSPaolo Bonzini step = -step; 7359f64bd8aSPaolo Bonzini } 7369f64bd8aSPaolo Bonzini 7379f64bd8aSPaolo Bonzini while (count--) { 7389f64bd8aSPaolo Bonzini switch (esize) { 7399f64bd8aSPaolo Bonzini case 0: 7402c17449bSEdgar E. Iglesias tmp = ldub_phys(cs->as, src); 7419f64bd8aSPaolo Bonzini break; 7429f64bd8aSPaolo Bonzini case 1: 74341701aa4SEdgar E. Iglesias tmp = lduw_phys(cs->as, src); 7449f64bd8aSPaolo Bonzini break; 7459f64bd8aSPaolo Bonzini case 2: 746fdfba1a2SEdgar E. Iglesias tmp = ldl_phys(cs->as, src); 7479f64bd8aSPaolo Bonzini break; 7489f64bd8aSPaolo Bonzini case 3: 7492c17449bSEdgar E. Iglesias tmp = ldq_phys(cs->as, src); 7509f64bd8aSPaolo Bonzini break; 7519f64bd8aSPaolo Bonzini default: 7529f64bd8aSPaolo Bonzini return H_PARAMETER; 7539f64bd8aSPaolo Bonzini } 7549f64bd8aSPaolo Bonzini if (op == 1) { 7559f64bd8aSPaolo Bonzini tmp = ~tmp; 7569f64bd8aSPaolo Bonzini } 7579f64bd8aSPaolo Bonzini switch (esize) { 7589f64bd8aSPaolo Bonzini case 0: 759db3be60dSEdgar E. Iglesias stb_phys(cs->as, dst, tmp); 7609f64bd8aSPaolo Bonzini break; 7619f64bd8aSPaolo Bonzini case 1: 7625ce5944dSEdgar E. Iglesias stw_phys(cs->as, dst, tmp); 7639f64bd8aSPaolo Bonzini break; 7649f64bd8aSPaolo Bonzini case 2: 765ab1da857SEdgar E. Iglesias stl_phys(cs->as, dst, tmp); 7669f64bd8aSPaolo Bonzini break; 7679f64bd8aSPaolo Bonzini case 3: 768f606604fSEdgar E. Iglesias stq_phys(cs->as, dst, tmp); 7699f64bd8aSPaolo Bonzini break; 7709f64bd8aSPaolo Bonzini } 7719f64bd8aSPaolo Bonzini dst = dst + step; 7729f64bd8aSPaolo Bonzini src = src + step; 7739f64bd8aSPaolo Bonzini } 7749f64bd8aSPaolo Bonzini 7759f64bd8aSPaolo Bonzini return H_SUCCESS; 7769f64bd8aSPaolo Bonzini } 7779f64bd8aSPaolo Bonzini 778ce2918cbSDavid Gibson static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr, 7799f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 7809f64bd8aSPaolo Bonzini { 7819f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 7829f64bd8aSPaolo Bonzini return H_SUCCESS; 7839f64bd8aSPaolo Bonzini } 7849f64bd8aSPaolo Bonzini 785ce2918cbSDavid Gibson static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, 7869f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 7879f64bd8aSPaolo Bonzini { 7889f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 7899f64bd8aSPaolo Bonzini return H_SUCCESS; 7909f64bd8aSPaolo Bonzini } 7919f64bd8aSPaolo Bonzini 7927d0cd464SPeter Maydell static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 793c4c81d7dSGreg Kurz SpaprMachineState *spapr, 794c4015bbdSAlexey Kardashevskiy target_ulong mflags, 795c4015bbdSAlexey Kardashevskiy target_ulong value1, 796c4015bbdSAlexey Kardashevskiy target_ulong value2) 79742561bf2SAnton Blanchard { 79842561bf2SAnton Blanchard if (value1) { 799c4015bbdSAlexey Kardashevskiy return H_P3; 80042561bf2SAnton Blanchard } 80142561bf2SAnton Blanchard if (value2) { 802c4015bbdSAlexey Kardashevskiy return H_P4; 80342561bf2SAnton Blanchard } 804c4015bbdSAlexey Kardashevskiy 80542561bf2SAnton Blanchard switch (mflags) { 80642561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_BIG: 80700fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(0, LPCR_ILE); 808c4c81d7dSGreg Kurz spapr_pci_switch_vga(spapr, true); 809c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 81042561bf2SAnton Blanchard 81142561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_LITTLE: 81200fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); 813c4c81d7dSGreg Kurz spapr_pci_switch_vga(spapr, false); 814c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 815c4015bbdSAlexey Kardashevskiy } 816c4015bbdSAlexey Kardashevskiy 817c4015bbdSAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 818c4015bbdSAlexey Kardashevskiy } 819c4015bbdSAlexey Kardashevskiy 8207d0cd464SPeter Maydell static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 821ccc5a4c5SNicholas Piggin SpaprMachineState *spapr, 822d5ac4f54SAlexey Kardashevskiy target_ulong mflags, 823d5ac4f54SAlexey Kardashevskiy target_ulong value1, 824d5ac4f54SAlexey Kardashevskiy target_ulong value2) 825d5ac4f54SAlexey Kardashevskiy { 826d5ac4f54SAlexey Kardashevskiy if (value1) { 827d5ac4f54SAlexey Kardashevskiy return H_P3; 828d5ac4f54SAlexey Kardashevskiy } 829ccc5a4c5SNicholas Piggin 830d5ac4f54SAlexey Kardashevskiy if (value2) { 831d5ac4f54SAlexey Kardashevskiy return H_P4; 832d5ac4f54SAlexey Kardashevskiy } 833d5ac4f54SAlexey Kardashevskiy 834ccc5a4c5SNicholas Piggin /* 835ccc5a4c5SNicholas Piggin * AIL-1 is not architected, and AIL-2 is not supported by QEMU spapr. 836ccc5a4c5SNicholas Piggin * It is supported for faithful emulation of bare metal systems, but for 837ccc5a4c5SNicholas Piggin * compatibility concerns we leave it out of the pseries machine. 838ccc5a4c5SNicholas Piggin */ 839ccc5a4c5SNicholas Piggin if (mflags != 0 && mflags != 3) { 840526cdce7SNicholas Piggin return H_UNSUPPORTED_FLAG; 841526cdce7SNicholas Piggin } 842526cdce7SNicholas Piggin 843ccc5a4c5SNicholas Piggin if (mflags == 3) { 844ccc5a4c5SNicholas Piggin if (!spapr_get_cap(spapr, SPAPR_CAP_AIL_MODE_3)) { 845d5ac4f54SAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 846d5ac4f54SAlexey Kardashevskiy } 847ccc5a4c5SNicholas Piggin } 848d5ac4f54SAlexey Kardashevskiy 84900fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); 850d5ac4f54SAlexey Kardashevskiy 851d5ac4f54SAlexey Kardashevskiy return H_SUCCESS; 852d5ac4f54SAlexey Kardashevskiy } 853d5ac4f54SAlexey Kardashevskiy 854ce2918cbSDavid Gibson static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, 855c4015bbdSAlexey Kardashevskiy target_ulong opcode, target_ulong *args) 856c4015bbdSAlexey Kardashevskiy { 857c4015bbdSAlexey Kardashevskiy target_ulong resource = args[1]; 858c4015bbdSAlexey Kardashevskiy target_ulong ret = H_P2; 859c4015bbdSAlexey Kardashevskiy 860c4015bbdSAlexey Kardashevskiy switch (resource) { 861c4015bbdSAlexey Kardashevskiy case H_SET_MODE_RESOURCE_LE: 862c4c81d7dSGreg Kurz ret = h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[3]); 86342561bf2SAnton Blanchard break; 864d5ac4f54SAlexey Kardashevskiy case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 865ccc5a4c5SNicholas Piggin ret = h_set_mode_resource_addr_trans_mode(cpu, spapr, args[0], 866d5ac4f54SAlexey Kardashevskiy args[2], args[3]); 867d5ac4f54SAlexey Kardashevskiy break; 86842561bf2SAnton Blanchard } 86942561bf2SAnton Blanchard 87042561bf2SAnton Blanchard return ret; 87142561bf2SAnton Blanchard } 87242561bf2SAnton Blanchard 873ce2918cbSDavid Gibson static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, 874d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 875d77a98b0SSuraj Jitindar Singh { 876d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 877d77a98b0SSuraj Jitindar Singh opcode, " (H_CLEAN_SLB)"); 878d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 879d77a98b0SSuraj Jitindar Singh } 880d77a98b0SSuraj Jitindar Singh 881ce2918cbSDavid Gibson static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr, 882d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 883d77a98b0SSuraj Jitindar Singh { 884d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 885d77a98b0SSuraj Jitindar Singh opcode, " (H_INVALIDATE_PID)"); 886d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 887d77a98b0SSuraj Jitindar Singh } 888d77a98b0SSuraj Jitindar Singh 889ce2918cbSDavid Gibson static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, 890b4db5413SSuraj Jitindar Singh uint64_t patbe_old, uint64_t patbe_new) 891b4db5413SSuraj Jitindar Singh { 892b4db5413SSuraj Jitindar Singh /* 893b4db5413SSuraj Jitindar Singh * We have 4 Options: 894b4db5413SSuraj Jitindar Singh * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 895b4db5413SSuraj Jitindar Singh * HASH->RADIX : Free HPT 896b4db5413SSuraj Jitindar Singh * RADIX->HASH : Allocate HPT 897b4db5413SSuraj Jitindar Singh * NOTHING->HASH : Allocate HPT 898b4db5413SSuraj Jitindar Singh * Note: NOTHING implies the case where we said the guest could choose 899b4db5413SSuraj Jitindar Singh * later and so assumed radix and now it's called H_REG_PROC_TBL 900b4db5413SSuraj Jitindar Singh */ 901b4db5413SSuraj Jitindar Singh 90279825f4dSBenjamin Herrenschmidt if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) { 903b4db5413SSuraj Jitindar Singh /* We assume RADIX, so this catches all the "Do Nothing" cases */ 90479825f4dSBenjamin Herrenschmidt } else if (!(patbe_old & PATE1_GR)) { 905b4db5413SSuraj Jitindar Singh /* HASH->RADIX : Free HPT */ 90606ec79e8SBharata B Rao spapr_free_hpt(spapr); 90779825f4dSBenjamin Herrenschmidt } else if (!(patbe_new & PATE1_GR)) { 908b4db5413SSuraj Jitindar Singh /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 9098897ea5aSDavid Gibson spapr_setup_hpt(spapr); 910b4db5413SSuraj Jitindar Singh } 911b4db5413SSuraj Jitindar Singh return; 912b4db5413SSuraj Jitindar Singh } 913b4db5413SSuraj Jitindar Singh 914b4db5413SSuraj Jitindar Singh #define FLAGS_MASK 0x01FULL 915b4db5413SSuraj Jitindar Singh #define FLAG_MODIFY 0x10 916b4db5413SSuraj Jitindar Singh #define FLAG_REGISTER 0x08 917b4db5413SSuraj Jitindar Singh #define FLAG_RADIX 0x04 918b4db5413SSuraj Jitindar Singh #define FLAG_HASH_PROC_TBL 0x02 919b4db5413SSuraj Jitindar Singh #define FLAG_GTSE 0x01 920b4db5413SSuraj Jitindar Singh 921d77a98b0SSuraj Jitindar Singh static target_ulong h_register_process_table(PowerPCCPU *cpu, 922ce2918cbSDavid Gibson SpaprMachineState *spapr, 923d77a98b0SSuraj Jitindar Singh target_ulong opcode, 924d77a98b0SSuraj Jitindar Singh target_ulong *args) 925d77a98b0SSuraj Jitindar Singh { 926b4db5413SSuraj Jitindar Singh target_ulong flags = args[0]; 927b4db5413SSuraj Jitindar Singh target_ulong proc_tbl = args[1]; 928b4db5413SSuraj Jitindar Singh target_ulong page_size = args[2]; 929b4db5413SSuraj Jitindar Singh target_ulong table_size = args[3]; 930176dcceeSSuraj Jitindar Singh target_ulong update_lpcr = 0; 9313c2e80adSLeandro Lupori target_ulong table_byte_size; 932b4db5413SSuraj Jitindar Singh uint64_t cproc; 933b4db5413SSuraj Jitindar Singh 934b4db5413SSuraj Jitindar Singh if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 935b4db5413SSuraj Jitindar Singh return H_PARAMETER; 936b4db5413SSuraj Jitindar Singh } 937b4db5413SSuraj Jitindar Singh if (flags & FLAG_MODIFY) { 938b4db5413SSuraj Jitindar Singh if (flags & FLAG_REGISTER) { 9393c2e80adSLeandro Lupori /* Check process table alignment */ 9403c2e80adSLeandro Lupori table_byte_size = 1ULL << (table_size + 12); 9413c2e80adSLeandro Lupori if (proc_tbl & (table_byte_size - 1)) { 9423c2e80adSLeandro Lupori qemu_log_mask(LOG_GUEST_ERROR, 9433c2e80adSLeandro Lupori "%s: process table not properly aligned: proc_tbl 0x" 9443c2e80adSLeandro Lupori TARGET_FMT_lx" proc_tbl_size 0x"TARGET_FMT_lx"\n", 9453c2e80adSLeandro Lupori __func__, proc_tbl, table_byte_size); 9463c2e80adSLeandro Lupori } 947b4db5413SSuraj Jitindar Singh if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 948b4db5413SSuraj Jitindar Singh if (proc_tbl & 0xfff || proc_tbl >> 60) { 949b4db5413SSuraj Jitindar Singh return H_P2; 950b4db5413SSuraj Jitindar Singh } else if (page_size) { 951b4db5413SSuraj Jitindar Singh return H_P3; 952b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 953b4db5413SSuraj Jitindar Singh return H_P4; 954b4db5413SSuraj Jitindar Singh } 95579825f4dSBenjamin Herrenschmidt cproc = PATE1_GR | proc_tbl | table_size; 956b4db5413SSuraj Jitindar Singh } else { /* Register new HPT process table */ 957b4db5413SSuraj Jitindar Singh if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 958b4db5413SSuraj Jitindar Singh /* TODO - Not Supported */ 959b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 960b4db5413SSuraj Jitindar Singh return H_PARAMETER; 961b4db5413SSuraj Jitindar Singh } else { /* Hash with SLB */ 962b4db5413SSuraj Jitindar Singh if (proc_tbl >> 38) { 963b4db5413SSuraj Jitindar Singh return H_P2; 964b4db5413SSuraj Jitindar Singh } else if (page_size & ~0x7) { 965b4db5413SSuraj Jitindar Singh return H_P3; 966b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 967b4db5413SSuraj Jitindar Singh return H_P4; 968b4db5413SSuraj Jitindar Singh } 969b4db5413SSuraj Jitindar Singh } 970b4db5413SSuraj Jitindar Singh cproc = (proc_tbl << 25) | page_size << 5 | table_size; 971b4db5413SSuraj Jitindar Singh } 972b4db5413SSuraj Jitindar Singh 973b4db5413SSuraj Jitindar Singh } else { /* Deregister current process table */ 97479825f4dSBenjamin Herrenschmidt /* 97579825f4dSBenjamin Herrenschmidt * Set to benign value: (current GR) | 0. This allows 97679825f4dSBenjamin Herrenschmidt * deregistration in KVM to succeed even if the radix bit 97779825f4dSBenjamin Herrenschmidt * in flags doesn't match the radix bit in the old PATE. 97879825f4dSBenjamin Herrenschmidt */ 97979825f4dSBenjamin Herrenschmidt cproc = spapr->patb_entry & PATE1_GR; 980b4db5413SSuraj Jitindar Singh } 981b4db5413SSuraj Jitindar Singh } else { /* Maintain current registration */ 98279825f4dSBenjamin Herrenschmidt if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) { 983b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 984b4db5413SSuraj Jitindar Singh return H_PARAMETER; /* Existing Process Table Mismatch */ 985b4db5413SSuraj Jitindar Singh } 986b4db5413SSuraj Jitindar Singh cproc = spapr->patb_entry; 987b4db5413SSuraj Jitindar Singh } 988b4db5413SSuraj Jitindar Singh 989b4db5413SSuraj Jitindar Singh /* Check if we need to setup OR free the hpt */ 990b4db5413SSuraj Jitindar Singh spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 991b4db5413SSuraj Jitindar Singh 992b4db5413SSuraj Jitindar Singh spapr->patb_entry = cproc; /* Save new process table */ 9936de83307SSuraj Jitindar Singh 99400fd075eSBenjamin Herrenschmidt /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ 995176dcceeSSuraj Jitindar Singh if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */ 996176dcceeSSuraj Jitindar Singh update_lpcr |= (LPCR_UPRT | LPCR_HR); 997176dcceeSSuraj Jitindar Singh else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ 998176dcceeSSuraj Jitindar Singh update_lpcr |= LPCR_UPRT; 999176dcceeSSuraj Jitindar Singh if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ 100049e9fdd7SDavid Gibson update_lpcr |= LPCR_GTSE; 100149e9fdd7SDavid Gibson 1002176dcceeSSuraj Jitindar Singh spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); 1003b4db5413SSuraj Jitindar Singh 1004b4db5413SSuraj Jitindar Singh if (kvm_enabled()) { 1005b4db5413SSuraj Jitindar Singh return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1006b4db5413SSuraj Jitindar Singh flags & FLAG_GTSE, cproc); 1007b4db5413SSuraj Jitindar Singh } 1008b4db5413SSuraj Jitindar Singh return H_SUCCESS; 1009d77a98b0SSuraj Jitindar Singh } 1010d77a98b0SSuraj Jitindar Singh 10111c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALL -1 10121c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 10131c7ad77eSNicholas Piggin 10141c7ad77eSNicholas Piggin static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1015ce2918cbSDavid Gibson SpaprMachineState *spapr, 10161c7ad77eSNicholas Piggin target_ulong opcode, target_ulong *args) 10171c7ad77eSNicholas Piggin { 10181c7ad77eSNicholas Piggin target_long target = args[0]; 10191c7ad77eSNicholas Piggin CPUState *cs; 10201c7ad77eSNicholas Piggin 10211c7ad77eSNicholas Piggin if (target < 0) { 10221c7ad77eSNicholas Piggin /* Broadcast */ 10231c7ad77eSNicholas Piggin if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 10241c7ad77eSNicholas Piggin return H_PARAMETER; 10251c7ad77eSNicholas Piggin } 10261c7ad77eSNicholas Piggin 10271c7ad77eSNicholas Piggin CPU_FOREACH(cs) { 10281c7ad77eSNicholas Piggin PowerPCCPU *c = POWERPC_CPU(cs); 10291c7ad77eSNicholas Piggin 10301c7ad77eSNicholas Piggin if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 10311c7ad77eSNicholas Piggin if (c == cpu) { 10321c7ad77eSNicholas Piggin continue; 10331c7ad77eSNicholas Piggin } 10341c7ad77eSNicholas Piggin } 10351c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 10361c7ad77eSNicholas Piggin } 10371c7ad77eSNicholas Piggin return H_SUCCESS; 10381c7ad77eSNicholas Piggin 10391c7ad77eSNicholas Piggin } else { 10401c7ad77eSNicholas Piggin /* Unicast */ 10412e886fb3SSam Bobroff cs = CPU(spapr_find_cpu(target)); 1042f57467e3SSam Bobroff if (cs) { 10431c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 10441c7ad77eSNicholas Piggin return H_SUCCESS; 10451c7ad77eSNicholas Piggin } 10461c7ad77eSNicholas Piggin return H_PARAMETER; 10471c7ad77eSNicholas Piggin } 10481c7ad77eSNicholas Piggin } 10491c7ad77eSNicholas Piggin 1050121afbe4SGreg Kurz /* Returns either a logical PVR or zero if none was found */ 1051121afbe4SGreg Kurz static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32_t max_compat, 1052121afbe4SGreg Kurz target_ulong *addr, bool *raw_mode_supported) 10532a6593cbSAlexey Kardashevskiy { 1054152ef803SDavid Gibson bool explicit_match = false; /* Matched the CPU's real PVR */ 1055152ef803SDavid Gibson uint32_t best_compat = 0; 1056152ef803SDavid Gibson int i; 10573794d548SAlexey Kardashevskiy 1058152ef803SDavid Gibson /* 1059152ef803SDavid Gibson * We scan the supplied table of PVRs looking for two things 1060152ef803SDavid Gibson * 1. Is our real CPU PVR in the list? 1061152ef803SDavid Gibson * 2. What's the "best" listed logical PVR 1062152ef803SDavid Gibson */ 1063152ef803SDavid Gibson for (i = 0; i < 512; ++i) { 10643794d548SAlexey Kardashevskiy uint32_t pvr, pvr_mask; 10653794d548SAlexey Kardashevskiy 106680c33d34SDavid Gibson pvr_mask = ldl_be_phys(&address_space_memory, *addr); 106780c33d34SDavid Gibson pvr = ldl_be_phys(&address_space_memory, *addr + 4); 106880c33d34SDavid Gibson *addr += 8; 10693794d548SAlexey Kardashevskiy 10703794d548SAlexey Kardashevskiy if (~pvr_mask & pvr) { 1071152ef803SDavid Gibson break; /* Terminator record */ 10723794d548SAlexey Kardashevskiy } 1073152ef803SDavid Gibson 1074152ef803SDavid Gibson if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1075152ef803SDavid Gibson explicit_match = true; 1076152ef803SDavid Gibson } else { 1077152ef803SDavid Gibson if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1078152ef803SDavid Gibson best_compat = pvr; 1079152ef803SDavid Gibson } 1080152ef803SDavid Gibson } 1081152ef803SDavid Gibson } 1082152ef803SDavid Gibson 1083cc7b35b1SGreg Kurz *raw_mode_supported = explicit_match; 1084cc7b35b1SGreg Kurz 10853794d548SAlexey Kardashevskiy /* Parsing finished */ 1086152ef803SDavid Gibson trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 10873794d548SAlexey Kardashevskiy 108880c33d34SDavid Gibson return best_compat; 108980c33d34SDavid Gibson } 109080c33d34SDavid Gibson 1091eb72b639SDaniel Henrique Barboza static 109291067db1SAlexey Kardashevskiy target_ulong do_client_architecture_support(PowerPCCPU *cpu, 1093ce2918cbSDavid Gibson SpaprMachineState *spapr, 109491067db1SAlexey Kardashevskiy target_ulong vec, 109591067db1SAlexey Kardashevskiy target_ulong fdt_bufsize) 109680c33d34SDavid Gibson { 109791067db1SAlexey Kardashevskiy target_ulong ov_table; /* Working address in data buffer */ 109880c33d34SDavid Gibson uint32_t cas_pvr; 109986962462SGreg Kurz SpaprOptionVector *ov1_guest, *ov5_guest; 110080c33d34SDavid Gibson bool guest_radix; 1101cc7b35b1SGreg Kurz bool raw_mode_supported = false; 110221bde1ecSAlexey Kardashevskiy bool guest_xive; 110312b3868eSGreg Kurz CPUState *cs; 1104087820e3SGreg Kurz void *fdt; 1105121afbe4SGreg Kurz uint32_t max_compat = spapr->max_compat_pvr; 110612b3868eSGreg Kurz 110712b3868eSGreg Kurz /* CAS is supposed to be called early when only the boot vCPU is active. */ 110812b3868eSGreg Kurz CPU_FOREACH(cs) { 110912b3868eSGreg Kurz if (cs == CPU(cpu)) { 111012b3868eSGreg Kurz continue; 111112b3868eSGreg Kurz } 111212b3868eSGreg Kurz if (!cs->halted) { 111312b3868eSGreg Kurz warn_report("guest has multiple active vCPUs at CAS, which is not allowed"); 111412b3868eSGreg Kurz return H_MULTI_THREADS_ACTIVE; 111512b3868eSGreg Kurz } 111612b3868eSGreg Kurz } 11173794d548SAlexey Kardashevskiy 1118121afbe4SGreg Kurz cas_pvr = cas_check_pvr(cpu, max_compat, &vec, &raw_mode_supported); 1119121afbe4SGreg Kurz if (!cas_pvr && (!raw_mode_supported || max_compat)) { 1120121afbe4SGreg Kurz /* 1121121afbe4SGreg Kurz * We couldn't find a suitable compatibility mode, and either 1122121afbe4SGreg Kurz * the guest doesn't support "raw" mode for this CPU, or "raw" 1123121afbe4SGreg Kurz * mode is disabled because a maximum compat mode is set. 1124121afbe4SGreg Kurz */ 1125121afbe4SGreg Kurz error_report("Couldn't negotiate a suitable PVR during CAS"); 112680c33d34SDavid Gibson return H_HARDWARE; 112780c33d34SDavid Gibson } 112880c33d34SDavid Gibson 112980c33d34SDavid Gibson /* Update CPUs */ 113080c33d34SDavid Gibson if (cpu->compat_pvr != cas_pvr) { 11317e92da81SGreg Kurz Error *local_err = NULL; 11327e92da81SGreg Kurz 11337e92da81SGreg Kurz if (ppc_set_compat_all(cas_pvr, &local_err) < 0) { 1134cc7b35b1SGreg Kurz /* We fail to set compat mode (likely because running with KVM PR), 1135cc7b35b1SGreg Kurz * but maybe we can fallback to raw mode if the guest supports it. 1136cc7b35b1SGreg Kurz */ 1137cc7b35b1SGreg Kurz if (!raw_mode_supported) { 1138f6f242c7SDavid Gibson error_report_err(local_err); 11393794d548SAlexey Kardashevskiy return H_HARDWARE; 11403794d548SAlexey Kardashevskiy } 11412c9dfdacSGreg Kurz error_free(local_err); 1142cc7b35b1SGreg Kurz } 11433794d548SAlexey Kardashevskiy } 11443794d548SAlexey Kardashevskiy 114503d196b7SBharata B Rao /* For the future use: here @ov_table points to the first option vector */ 114691067db1SAlexey Kardashevskiy ov_table = vec; 114703d196b7SBharata B Rao 1148e957f6a9SSam Bobroff ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1149cbd0d7f3SGreg Kurz if (!ov1_guest) { 1150cbd0d7f3SGreg Kurz warn_report("guest didn't provide option vector 1"); 1151cbd0d7f3SGreg Kurz return H_PARAMETER; 1152cbd0d7f3SGreg Kurz } 1153facdb8b6SMichael Roth ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1154cbd0d7f3SGreg Kurz if (!ov5_guest) { 1155ce05fa0fSGreg Kurz spapr_ovec_cleanup(ov1_guest); 1156cbd0d7f3SGreg Kurz warn_report("guest didn't provide option vector 5"); 1157cbd0d7f3SGreg Kurz return H_PARAMETER; 1158cbd0d7f3SGreg Kurz } 11599fb4541fSSam Bobroff if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 11609fb4541fSSam Bobroff error_report("guest requested hash and radix MMU, which is invalid."); 11619fb4541fSSam Bobroff exit(EXIT_FAILURE); 11629fb4541fSSam Bobroff } 1163e7f78db9SGreg Kurz if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { 1164e7f78db9SGreg Kurz error_report("guest requested an invalid interrupt mode"); 1165e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1166e7f78db9SGreg Kurz } 1167e7f78db9SGreg Kurz 11689fb4541fSSam Bobroff guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 11692a6593cbSAlexey Kardashevskiy 1170e7f78db9SGreg Kurz guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); 1171e7f78db9SGreg Kurz 11722772cf6bSDavid Gibson /* 11732772cf6bSDavid Gibson * HPT resizing is a bit of a special case, because when enabled 11742772cf6bSDavid Gibson * we assume an HPT guest will support it until it says it 11752772cf6bSDavid Gibson * doesn't, instead of assuming it won't support it until it says 11762772cf6bSDavid Gibson * it does. Strictly speaking that approach could break for 11772772cf6bSDavid Gibson * guests which don't make a CAS call, but those are so old we 11782772cf6bSDavid Gibson * don't care about them. Without that assumption we'd have to 11792772cf6bSDavid Gibson * make at least a temporary allocation of an HPT sized for max 11802772cf6bSDavid Gibson * memory, which could be impossibly difficult under KVM HV if 11812772cf6bSDavid Gibson * maxram is large. 11822772cf6bSDavid Gibson */ 11832772cf6bSDavid Gibson if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 11842772cf6bSDavid Gibson int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 11852772cf6bSDavid Gibson 11862772cf6bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 11872772cf6bSDavid Gibson error_report( 11882772cf6bSDavid Gibson "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 11892772cf6bSDavid Gibson exit(1); 11902772cf6bSDavid Gibson } 11912772cf6bSDavid Gibson 11922772cf6bSDavid Gibson if (spapr->htab_shift < maxshift) { 11932772cf6bSDavid Gibson /* Guest doesn't know about HPT resizing, so we 11942772cf6bSDavid Gibson * pre-emptively resize for the maximum permitted RAM. At 11952772cf6bSDavid Gibson * the point this is called, nothing should have been 11962772cf6bSDavid Gibson * entered into the existing HPT */ 11972772cf6bSDavid Gibson spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 11981ec26c75SGreg Kurz push_sregs_to_kvm_pr(spapr); 1199b55d295eSDavid Gibson } 12002772cf6bSDavid Gibson } 12012772cf6bSDavid Gibson 1202facdb8b6SMichael Roth /* NOTE: there are actually a number of ov5 bits where input from the 1203facdb8b6SMichael Roth * guest is always zero, and the platform/QEMU enables them independently 1204facdb8b6SMichael Roth * of guest input. To model these properly we'd want some sort of mask, 1205facdb8b6SMichael Roth * but since they only currently apply to memory migration as defined 1206facdb8b6SMichael Roth * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 12076787d27bSMichael Roth * to worry about this for now. 1208facdb8b6SMichael Roth */ 120930bf9ed1SCédric Le Goater 12106787d27bSMichael Roth /* full range of negotiated ov5 capabilities */ 1211facdb8b6SMichael Roth spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1212facdb8b6SMichael Roth spapr_ovec_cleanup(ov5_guest); 1213b4b83312SGreg Kurz 1214068479e1SFabiano Rosas spapr_check_mmu_mode(guest_radix); 1215068479e1SFabiano Rosas 1216daa36379SDavid Gibson spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00); 121700005f22SShivaprasad G Bhat spapr_ovec_cleanup(ov1_guest); 121813db0cd9SCédric Le Goater 121913db0cd9SCédric Le Goater /* 12205dab5abeSDaniel Henrique Barboza * Check for NUMA affinity conditions now that we know which NUMA 12215dab5abeSDaniel Henrique Barboza * affinity the guest will use. 12225dab5abeSDaniel Henrique Barboza */ 12235dab5abeSDaniel Henrique Barboza spapr_numa_associativity_check(spapr); 12245dab5abeSDaniel Henrique Barboza 12255dab5abeSDaniel Henrique Barboza /* 12268deb8019SDavid Gibson * Ensure the guest asks for an interrupt mode we support; 12278deb8019SDavid Gibson * otherwise terminate the boot. 1228e7f78db9SGreg Kurz */ 1229e7f78db9SGreg Kurz if (guest_xive) { 1230ca62823bSDavid Gibson if (!spapr->irq->xive) { 123175de5941SGreg Kurz error_report( 123275de5941SGreg Kurz "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property"); 1233e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1234e7f78db9SGreg Kurz } 1235e7f78db9SGreg Kurz } else { 1236ca62823bSDavid Gibson if (!spapr->irq->xics) { 123775de5941SGreg Kurz error_report( 123875de5941SGreg Kurz "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual"); 1239e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1240e7f78db9SGreg Kurz } 1241e7f78db9SGreg Kurz } 1242e7f78db9SGreg Kurz 12438deb8019SDavid Gibson spapr_irq_update_active_intc(spapr); 12448deb8019SDavid Gibson 1245babb819fSGreg Kurz /* 1246babb819fSGreg Kurz * Process all pending hot-plug/unplug requests now. An updated full 1247babb819fSGreg Kurz * rendered FDT will be returned to the guest. 1248babb819fSGreg Kurz */ 1249babb819fSGreg Kurz spapr_drc_reset_all(spapr); 1250babb819fSGreg Kurz spapr_clear_pending_hotplug_events(spapr); 12510c21e073SDavid Gibson 1252087820e3SGreg Kurz /* 1253087820e3SGreg Kurz * If spapr_machine_reset() did not set up a HPT but one is necessary 1254087820e3SGreg Kurz * (because the guest isn't going to use radix) then set it up here. 1255087820e3SGreg Kurz */ 12568deb8019SDavid Gibson if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { 12578deb8019SDavid Gibson /* legacy hash or new hash: */ 12588897ea5aSDavid Gibson spapr_setup_hpt(spapr); 12598deb8019SDavid Gibson } 12600c21e073SDavid Gibson 126121bde1ecSAlexey Kardashevskiy fdt = spapr_build_fdt(spapr, spapr->vof != NULL, fdt_bufsize); 12620c21e073SDavid Gibson g_free(spapr->fdt_blob); 12630c21e073SDavid Gibson spapr->fdt_size = fdt_totalsize(fdt); 12640c21e073SDavid Gibson spapr->fdt_initial_size = spapr->fdt_size; 12650c21e073SDavid Gibson spapr->fdt_blob = fdt; 12662a6593cbSAlexey Kardashevskiy 1267d890f2faSDaniel Henrique Barboza /* 1268d890f2faSDaniel Henrique Barboza * Set the machine->fdt pointer again since we just freed 1269d890f2faSDaniel Henrique Barboza * it above (by freeing spapr->fdt_blob). We set this 1270d890f2faSDaniel Henrique Barboza * pointer to enable support for the 'dumpdtb' QMP/HMP 1271d890f2faSDaniel Henrique Barboza * command. 1272d890f2faSDaniel Henrique Barboza */ 1273d890f2faSDaniel Henrique Barboza MACHINE(spapr)->fdt = fdt; 1274d890f2faSDaniel Henrique Barboza 12752a6593cbSAlexey Kardashevskiy return H_SUCCESS; 12762a6593cbSAlexey Kardashevskiy } 12772a6593cbSAlexey Kardashevskiy 127891067db1SAlexey Kardashevskiy static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 127991067db1SAlexey Kardashevskiy SpaprMachineState *spapr, 128091067db1SAlexey Kardashevskiy target_ulong opcode, 128191067db1SAlexey Kardashevskiy target_ulong *args) 128291067db1SAlexey Kardashevskiy { 128391067db1SAlexey Kardashevskiy target_ulong vec = ppc64_phys_to_real(args[0]); 128491067db1SAlexey Kardashevskiy target_ulong fdt_buf = args[1]; 128591067db1SAlexey Kardashevskiy target_ulong fdt_bufsize = args[2]; 128691067db1SAlexey Kardashevskiy target_ulong ret; 128791067db1SAlexey Kardashevskiy SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 128891067db1SAlexey Kardashevskiy 128991067db1SAlexey Kardashevskiy if (fdt_bufsize < sizeof(hdr)) { 129091067db1SAlexey Kardashevskiy error_report("SLOF provided insufficient CAS buffer " 129191067db1SAlexey Kardashevskiy TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr)); 129291067db1SAlexey Kardashevskiy exit(EXIT_FAILURE); 129391067db1SAlexey Kardashevskiy } 129491067db1SAlexey Kardashevskiy 129591067db1SAlexey Kardashevskiy fdt_bufsize -= sizeof(hdr); 129691067db1SAlexey Kardashevskiy 129791067db1SAlexey Kardashevskiy ret = do_client_architecture_support(cpu, spapr, vec, fdt_bufsize); 129891067db1SAlexey Kardashevskiy if (ret == H_SUCCESS) { 129991067db1SAlexey Kardashevskiy _FDT((fdt_pack(spapr->fdt_blob))); 130091067db1SAlexey Kardashevskiy spapr->fdt_size = fdt_totalsize(spapr->fdt_blob); 130191067db1SAlexey Kardashevskiy spapr->fdt_initial_size = spapr->fdt_size; 130291067db1SAlexey Kardashevskiy 130391067db1SAlexey Kardashevskiy cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr)); 130491067db1SAlexey Kardashevskiy cpu_physical_memory_write(fdt_buf + sizeof(hdr), spapr->fdt_blob, 130591067db1SAlexey Kardashevskiy spapr->fdt_size); 130691067db1SAlexey Kardashevskiy trace_spapr_cas_continue(spapr->fdt_size + sizeof(hdr)); 130791067db1SAlexey Kardashevskiy } 130891067db1SAlexey Kardashevskiy 130991067db1SAlexey Kardashevskiy return ret; 131091067db1SAlexey Kardashevskiy } 131191067db1SAlexey Kardashevskiy 1312fc8c745dSAlexey Kardashevskiy target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1313fc8c745dSAlexey Kardashevskiy CPUState *cs, 1314fc8c745dSAlexey Kardashevskiy target_ulong ovec_addr) 1315fc8c745dSAlexey Kardashevskiy { 1316fc8c745dSAlexey Kardashevskiy SpaprMachineState *spapr = SPAPR_MACHINE(ms); 1317fc8c745dSAlexey Kardashevskiy 1318fc8c745dSAlexey Kardashevskiy target_ulong ret = do_client_architecture_support(POWERPC_CPU(cs), spapr, 1319fc8c745dSAlexey Kardashevskiy ovec_addr, FDT_MAX_SIZE); 1320fc8c745dSAlexey Kardashevskiy 1321fc8c745dSAlexey Kardashevskiy /* 1322fc8c745dSAlexey Kardashevskiy * This adds stdout and generates phandles for boottime and CAS FDTs. 1323fc8c745dSAlexey Kardashevskiy * It is alright to update the FDT here as do_client_architecture_support() 1324fc8c745dSAlexey Kardashevskiy * does not pack it. 1325fc8c745dSAlexey Kardashevskiy */ 1326fc8c745dSAlexey Kardashevskiy spapr_vof_client_dt_finalize(spapr, spapr->fdt_blob); 1327fc8c745dSAlexey Kardashevskiy 1328fc8c745dSAlexey Kardashevskiy return ret; 1329fc8c745dSAlexey Kardashevskiy } 1330fc8c745dSAlexey Kardashevskiy 1331c59704b2SSuraj Jitindar Singh static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1332ce2918cbSDavid Gibson SpaprMachineState *spapr, 1333c59704b2SSuraj Jitindar Singh target_ulong opcode, 1334c59704b2SSuraj Jitindar Singh target_ulong *args) 1335c59704b2SSuraj Jitindar Singh { 1336c59704b2SSuraj Jitindar Singh uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1337c59704b2SSuraj Jitindar Singh ~H_CPU_CHAR_THR_RECONF_TRIG; 1338c59704b2SSuraj Jitindar Singh uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1339c59704b2SSuraj Jitindar Singh uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1340c59704b2SSuraj Jitindar Singh uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1341c59704b2SSuraj Jitindar Singh uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 13428ff43ee4SSuraj Jitindar Singh uint8_t count_cache_flush_assist = spapr_get_cap(spapr, 13438ff43ee4SSuraj Jitindar Singh SPAPR_CAP_CCF_ASSIST); 1344c59704b2SSuraj Jitindar Singh 1345c59704b2SSuraj Jitindar Singh switch (safe_cache) { 1346c59704b2SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1347c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1348c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1349c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1350c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1351c59704b2SSuraj Jitindar Singh break; 1352c59704b2SSuraj Jitindar Singh case SPAPR_CAP_FIXED: 135317fd09c0SNicholas Piggin behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY; 135417fd09c0SNicholas Piggin behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS; 1355c59704b2SSuraj Jitindar Singh break; 1356c59704b2SSuraj Jitindar Singh default: /* broken */ 1357c59704b2SSuraj Jitindar Singh assert(safe_cache == SPAPR_CAP_BROKEN); 1358c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1359c59704b2SSuraj Jitindar Singh break; 1360c59704b2SSuraj Jitindar Singh } 1361c59704b2SSuraj Jitindar Singh 1362c59704b2SSuraj Jitindar Singh switch (safe_bounds_check) { 1363c59704b2SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1364c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1365c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1366c59704b2SSuraj Jitindar Singh break; 1367c59704b2SSuraj Jitindar Singh case SPAPR_CAP_FIXED: 1368c59704b2SSuraj Jitindar Singh break; 1369c59704b2SSuraj Jitindar Singh default: /* broken */ 1370c59704b2SSuraj Jitindar Singh assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1371c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1372c59704b2SSuraj Jitindar Singh break; 1373c59704b2SSuraj Jitindar Singh } 1374c59704b2SSuraj Jitindar Singh 1375c59704b2SSuraj Jitindar Singh switch (safe_indirect_branch) { 1376399b2896SSuraj Jitindar Singh case SPAPR_CAP_FIXED_NA: 1377399b2896SSuraj Jitindar Singh break; 1378c76c0d30SSuraj Jitindar Singh case SPAPR_CAP_FIXED_CCD: 1379c76c0d30SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; 1380c76c0d30SSuraj Jitindar Singh break; 1381c76c0d30SSuraj Jitindar Singh case SPAPR_CAP_FIXED_IBS: 1382c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1383fa86f592SGreg Kurz break; 1384399b2896SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1385399b2896SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE; 13868ff43ee4SSuraj Jitindar Singh if (count_cache_flush_assist) { 13878ff43ee4SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST; 13888ff43ee4SSuraj Jitindar Singh } 1389399b2896SSuraj Jitindar Singh break; 1390c59704b2SSuraj Jitindar Singh default: /* broken */ 1391c59704b2SSuraj Jitindar Singh assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1392c59704b2SSuraj Jitindar Singh break; 1393c59704b2SSuraj Jitindar Singh } 1394c59704b2SSuraj Jitindar Singh 1395c59704b2SSuraj Jitindar Singh args[0] = characteristics; 1396c59704b2SSuraj Jitindar Singh args[1] = behaviour; 1397fea35ca4SAlexey Kardashevskiy return H_SUCCESS; 1398fea35ca4SAlexey Kardashevskiy } 1399fea35ca4SAlexey Kardashevskiy 1400ce2918cbSDavid Gibson static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, 1401fea35ca4SAlexey Kardashevskiy target_ulong opcode, target_ulong *args) 1402fea35ca4SAlexey Kardashevskiy { 1403fea35ca4SAlexey Kardashevskiy target_ulong dt = ppc64_phys_to_real(args[0]); 1404fea35ca4SAlexey Kardashevskiy struct fdt_header hdr = { 0 }; 1405fea35ca4SAlexey Kardashevskiy unsigned cb; 1406ce2918cbSDavid Gibson SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1407fea35ca4SAlexey Kardashevskiy void *fdt; 1408fea35ca4SAlexey Kardashevskiy 1409fea35ca4SAlexey Kardashevskiy cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); 1410fea35ca4SAlexey Kardashevskiy cb = fdt32_to_cpu(hdr.totalsize); 1411fea35ca4SAlexey Kardashevskiy 1412fea35ca4SAlexey Kardashevskiy if (!smc->update_dt_enabled) { 1413fea35ca4SAlexey Kardashevskiy return H_SUCCESS; 1414fea35ca4SAlexey Kardashevskiy } 1415fea35ca4SAlexey Kardashevskiy 1416fea35ca4SAlexey Kardashevskiy /* Check that the fdt did not grow out of proportion */ 1417fea35ca4SAlexey Kardashevskiy if (cb > spapr->fdt_initial_size * 2) { 1418fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, 1419fea35ca4SAlexey Kardashevskiy fdt32_to_cpu(hdr.magic)); 1420fea35ca4SAlexey Kardashevskiy return H_PARAMETER; 1421fea35ca4SAlexey Kardashevskiy } 1422fea35ca4SAlexey Kardashevskiy 1423fea35ca4SAlexey Kardashevskiy fdt = g_malloc0(cb); 1424fea35ca4SAlexey Kardashevskiy cpu_physical_memory_read(dt, fdt, cb); 1425fea35ca4SAlexey Kardashevskiy 1426fea35ca4SAlexey Kardashevskiy /* Check the fdt consistency */ 1427fea35ca4SAlexey Kardashevskiy if (fdt_check_full(fdt, cb)) { 1428fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, 1429fea35ca4SAlexey Kardashevskiy fdt32_to_cpu(hdr.magic)); 1430fea35ca4SAlexey Kardashevskiy return H_PARAMETER; 1431fea35ca4SAlexey Kardashevskiy } 1432fea35ca4SAlexey Kardashevskiy 1433fea35ca4SAlexey Kardashevskiy g_free(spapr->fdt_blob); 1434fea35ca4SAlexey Kardashevskiy spapr->fdt_size = cb; 1435fea35ca4SAlexey Kardashevskiy spapr->fdt_blob = fdt; 1436fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt(cb); 1437c59704b2SSuraj Jitindar Singh 1438c59704b2SSuraj Jitindar Singh return H_SUCCESS; 1439c59704b2SSuraj Jitindar Singh } 1440c59704b2SSuraj Jitindar Singh 14419f64bd8aSPaolo Bonzini static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 14429f64bd8aSPaolo Bonzini static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 14430fb6bd07SMichael Roth static spapr_hcall_fn svm_hypercall_table[(SVM_HCALL_MAX - SVM_HCALL_BASE) / 4 + 1]; 14449f64bd8aSPaolo Bonzini 14459f64bd8aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 14469f64bd8aSPaolo Bonzini { 14479f64bd8aSPaolo Bonzini spapr_hcall_fn *slot; 14489f64bd8aSPaolo Bonzini 14499f64bd8aSPaolo Bonzini if (opcode <= MAX_HCALL_OPCODE) { 14509f64bd8aSPaolo Bonzini assert((opcode & 0x3) == 0); 14519f64bd8aSPaolo Bonzini 14529f64bd8aSPaolo Bonzini slot = &papr_hypercall_table[opcode / 4]; 14530fb6bd07SMichael Roth } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { 14540fb6bd07SMichael Roth /* we only have SVM-related hcall numbers assigned in multiples of 4 */ 14550fb6bd07SMichael Roth assert((opcode & 0x3) == 0); 14560fb6bd07SMichael Roth 14570fb6bd07SMichael Roth slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 14589f64bd8aSPaolo Bonzini } else { 14599f64bd8aSPaolo Bonzini assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 14609f64bd8aSPaolo Bonzini 14619f64bd8aSPaolo Bonzini slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 14629f64bd8aSPaolo Bonzini } 14639f64bd8aSPaolo Bonzini 14649f64bd8aSPaolo Bonzini assert(!(*slot)); 14659f64bd8aSPaolo Bonzini *slot = fn; 14669f64bd8aSPaolo Bonzini } 14679f64bd8aSPaolo Bonzini 14689f64bd8aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 14699f64bd8aSPaolo Bonzini target_ulong *args) 14709f64bd8aSPaolo Bonzini { 1471ce2918cbSDavid Gibson SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 147228e02042SDavid Gibson 14739f64bd8aSPaolo Bonzini if ((opcode <= MAX_HCALL_OPCODE) 14749f64bd8aSPaolo Bonzini && ((opcode & 0x3) == 0)) { 14759f64bd8aSPaolo Bonzini spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 14769f64bd8aSPaolo Bonzini 14779f64bd8aSPaolo Bonzini if (fn) { 14789f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 14799f64bd8aSPaolo Bonzini } 14800fb6bd07SMichael Roth } else if ((opcode >= SVM_HCALL_BASE) && 14810fb6bd07SMichael Roth (opcode <= SVM_HCALL_MAX)) { 14820fb6bd07SMichael Roth spapr_hcall_fn fn = svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 14830fb6bd07SMichael Roth 14840fb6bd07SMichael Roth if (fn) { 14850fb6bd07SMichael Roth return fn(cpu, spapr, opcode, args); 14860fb6bd07SMichael Roth } 14879f64bd8aSPaolo Bonzini } else if ((opcode >= KVMPPC_HCALL_BASE) && 14889f64bd8aSPaolo Bonzini (opcode <= KVMPPC_HCALL_MAX)) { 14899f64bd8aSPaolo Bonzini spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 14909f64bd8aSPaolo Bonzini 14919f64bd8aSPaolo Bonzini if (fn) { 14929f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 14939f64bd8aSPaolo Bonzini } 14949f64bd8aSPaolo Bonzini } 14959f64bd8aSPaolo Bonzini 1496aaf87c66SThomas Huth qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1497aaf87c66SThomas Huth opcode); 14989f64bd8aSPaolo Bonzini return H_FUNCTION; 14999f64bd8aSPaolo Bonzini } 15009f64bd8aSPaolo Bonzini 1501365acf15SFabiano Rosas #ifdef CONFIG_TCG 15020939ac2cSFabiano Rosas static void hypercall_register_softmmu(void) 15030939ac2cSFabiano Rosas { 15040939ac2cSFabiano Rosas /* DO NOTHING */ 15050939ac2cSFabiano Rosas } 15060939ac2cSFabiano Rosas #else 15070939ac2cSFabiano Rosas static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr, 15080939ac2cSFabiano Rosas target_ulong opcode, target_ulong *args) 15090939ac2cSFabiano Rosas { 15100939ac2cSFabiano Rosas g_assert_not_reached(); 15110939ac2cSFabiano Rosas } 15120939ac2cSFabiano Rosas 15130939ac2cSFabiano Rosas static void hypercall_register_softmmu(void) 15140939ac2cSFabiano Rosas { 15150939ac2cSFabiano Rosas /* hcall-pft */ 15160939ac2cSFabiano Rosas spapr_register_hypercall(H_ENTER, h_softmmu); 15170939ac2cSFabiano Rosas spapr_register_hypercall(H_REMOVE, h_softmmu); 15180939ac2cSFabiano Rosas spapr_register_hypercall(H_PROTECT, h_softmmu); 15190939ac2cSFabiano Rosas spapr_register_hypercall(H_READ, h_softmmu); 15200939ac2cSFabiano Rosas 15210939ac2cSFabiano Rosas /* hcall-bulk */ 15220939ac2cSFabiano Rosas spapr_register_hypercall(H_BULK_REMOVE, h_softmmu); 15230939ac2cSFabiano Rosas } 15240939ac2cSFabiano Rosas #endif 15250939ac2cSFabiano Rosas 1526962104f0SLucas Mateus Castro (alqotel) static void hypercall_register_types(void) 1527962104f0SLucas Mateus Castro (alqotel) { 1528962104f0SLucas Mateus Castro (alqotel) hypercall_register_softmmu(); 15299f64bd8aSPaolo Bonzini 153030f4b05bSDavid Gibson /* hcall-hpt-resize */ 153130f4b05bSDavid Gibson spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 153230f4b05bSDavid Gibson spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 153330f4b05bSDavid Gibson 15349f64bd8aSPaolo Bonzini /* hcall-splpar */ 15359f64bd8aSPaolo Bonzini spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 15369f64bd8aSPaolo Bonzini spapr_register_hypercall(H_CEDE, h_cede); 1537e8ce0e40SNicholas Piggin spapr_register_hypercall(H_CONFER, h_confer); 15383a6e6224SNicholas Piggin spapr_register_hypercall(H_PROD, h_prod); 15393a6e6224SNicholas Piggin 154010741314SNicholas Piggin /* hcall-join */ 154110741314SNicholas Piggin spapr_register_hypercall(H_JOIN, h_join); 154210741314SNicholas Piggin 15431c7ad77eSNicholas Piggin spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 15449f64bd8aSPaolo Bonzini 1545423576f7SThomas Huth /* processor register resource access h-calls */ 1546423576f7SThomas Huth spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1547af08a58fSThomas Huth spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1548e49ff266SThomas Huth spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 15493240dd9aSThomas Huth spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1550423576f7SThomas Huth spapr_register_hypercall(H_SET_MODE, h_set_mode); 1551423576f7SThomas Huth 1552d77a98b0SSuraj Jitindar Singh /* In Memory Table MMU h-calls */ 1553d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1554d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1555d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1556d77a98b0SSuraj Jitindar Singh 1557c59704b2SSuraj Jitindar Singh /* hcall-get-cpu-characteristics */ 1558c59704b2SSuraj Jitindar Singh spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 1559c59704b2SSuraj Jitindar Singh h_get_cpu_characteristics); 1560c59704b2SSuraj Jitindar Singh 15619f64bd8aSPaolo Bonzini /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 15629f64bd8aSPaolo Bonzini * here between the "CI" and the "CACHE" variants, they will use whatever 15639f64bd8aSPaolo Bonzini * mapping attributes qemu is using. When using KVM, the kernel will 15649f64bd8aSPaolo Bonzini * enforce the attributes more strongly 15659f64bd8aSPaolo Bonzini */ 15669f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 15679f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 15689f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 15699f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 15709f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 15719f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 15729f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 15739f64bd8aSPaolo Bonzini 15749f64bd8aSPaolo Bonzini /* qemu/KVM-PPC specific hcalls */ 15759f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 157642561bf2SAnton Blanchard 15772a6593cbSAlexey Kardashevskiy /* ibm,client-architecture-support support */ 15782a6593cbSAlexey Kardashevskiy spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1579c24ba3d0SLaurent Vivier 1580fea35ca4SAlexey Kardashevskiy spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); 1581120f738aSNicholas Piggin 15826b8a0537SNicholas Piggin spapr_register_nested(); 15839f64bd8aSPaolo Bonzini } 15849f64bd8aSPaolo Bonzini 15859f64bd8aSPaolo Bonzini type_init(hypercall_register_types) 1586