10d75590dSPeter Maydell #include "qemu/osdep.h" 2da34e65cSMarkus Armbruster #include "qapi/error.h" 3b3946626SVincent Palatin #include "sysemu/hw_accel.h" 49f64bd8aSPaolo Bonzini #include "sysemu/sysemu.h" 503dd024fSPaolo Bonzini #include "qemu/log.h" 69f64bd8aSPaolo Bonzini #include "cpu.h" 763c91552SPaolo Bonzini #include "exec/exec-all.h" 89f64bd8aSPaolo Bonzini #include "helper_regs.h" 90d09e41aSPaolo Bonzini #include "hw/ppc/spapr.h" 10d5aea6f3SDavid Gibson #include "mmu-hash64.h" 113794d548SAlexey Kardashevskiy #include "cpu-models.h" 123794d548SAlexey Kardashevskiy #include "trace.h" 133794d548SAlexey Kardashevskiy #include "kvm_ppc.h" 14facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 15b4db5413SSuraj Jitindar Singh #include "qemu/error-report.h" 16b4db5413SSuraj Jitindar Singh #include "mmu-book3s-v3.h" 179f64bd8aSPaolo Bonzini 18a46622fdSAlexey Kardashevskiy struct SPRSyncState { 19a46622fdSAlexey Kardashevskiy int spr; 20a46622fdSAlexey Kardashevskiy target_ulong value; 21a46622fdSAlexey Kardashevskiy target_ulong mask; 22a46622fdSAlexey Kardashevskiy }; 23a46622fdSAlexey Kardashevskiy 2414e6fe12SPaolo Bonzini static void do_spr_sync(CPUState *cs, run_on_cpu_data arg) 25a46622fdSAlexey Kardashevskiy { 2614e6fe12SPaolo Bonzini struct SPRSyncState *s = arg.host_ptr; 27e0eeb4a2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 28a46622fdSAlexey Kardashevskiy CPUPPCState *env = &cpu->env; 29a46622fdSAlexey Kardashevskiy 30e0eeb4a2SAlex Bennée cpu_synchronize_state(cs); 31a46622fdSAlexey Kardashevskiy env->spr[s->spr] &= ~s->mask; 32a46622fdSAlexey Kardashevskiy env->spr[s->spr] |= s->value; 33a46622fdSAlexey Kardashevskiy } 34a46622fdSAlexey Kardashevskiy 35a46622fdSAlexey Kardashevskiy static void set_spr(CPUState *cs, int spr, target_ulong value, 36a46622fdSAlexey Kardashevskiy target_ulong mask) 37a46622fdSAlexey Kardashevskiy { 38a46622fdSAlexey Kardashevskiy struct SPRSyncState s = { 39a46622fdSAlexey Kardashevskiy .spr = spr, 40a46622fdSAlexey Kardashevskiy .value = value, 41a46622fdSAlexey Kardashevskiy .mask = mask 42a46622fdSAlexey Kardashevskiy }; 4314e6fe12SPaolo Bonzini run_on_cpu(cs, do_spr_sync, RUN_ON_CPU_HOST_PTR(&s)); 44a46622fdSAlexey Kardashevskiy } 45a46622fdSAlexey Kardashevskiy 46af08a58fSThomas Huth static bool has_spr(PowerPCCPU *cpu, int spr) 47af08a58fSThomas Huth { 48af08a58fSThomas Huth /* We can test whether the SPR is defined by checking for a valid name */ 49af08a58fSThomas Huth return cpu->env.spr_cb[spr].name != NULL; 50af08a58fSThomas Huth } 51af08a58fSThomas Huth 52c6404adeSDavid Gibson static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) 53f3c75d42SAneesh Kumar K.V { 54f3c75d42SAneesh Kumar K.V /* 5536778660SDavid Gibson * hash value/pteg group index is normalized by HPT mask 56f3c75d42SAneesh Kumar K.V */ 5736778660SDavid Gibson if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { 58f3c75d42SAneesh Kumar K.V return false; 59f3c75d42SAneesh Kumar K.V } 60f3c75d42SAneesh Kumar K.V return true; 61f3c75d42SAneesh Kumar K.V } 62f3c75d42SAneesh Kumar K.V 63ecbc25faSDavid Gibson static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr) 64ecbc25faSDavid Gibson { 65ecbc25faSDavid Gibson MachineState *machine = MACHINE(spapr); 66ecbc25faSDavid Gibson MemoryHotplugState *hpms = &spapr->hotplug_memory; 67ecbc25faSDavid Gibson 68ecbc25faSDavid Gibson if (addr < machine->ram_size) { 69ecbc25faSDavid Gibson return true; 70ecbc25faSDavid Gibson } 71ecbc25faSDavid Gibson if ((addr >= hpms->base) 72ecbc25faSDavid Gibson && ((addr - hpms->base) < memory_region_size(&hpms->mr))) { 73ecbc25faSDavid Gibson return true; 74ecbc25faSDavid Gibson } 75ecbc25faSDavid Gibson 76ecbc25faSDavid Gibson return false; 77ecbc25faSDavid Gibson } 78ecbc25faSDavid Gibson 7928e02042SDavid Gibson static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, 809f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 819f64bd8aSPaolo Bonzini { 829f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 83c6404adeSDavid Gibson target_ulong ptex = args[1]; 849f64bd8aSPaolo Bonzini target_ulong pteh = args[2]; 859f64bd8aSPaolo Bonzini target_ulong ptel = args[3]; 861f0252e6SCédric Le Goater unsigned apshift; 879f64bd8aSPaolo Bonzini target_ulong raddr; 88c6404adeSDavid Gibson target_ulong slot; 897222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 909f64bd8aSPaolo Bonzini 911f0252e6SCédric Le Goater apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); 921114e712SDavid Gibson if (!apshift) { 931114e712SDavid Gibson /* Bad page size encoding */ 949f64bd8aSPaolo Bonzini return H_PARAMETER; 959f64bd8aSPaolo Bonzini } 969f64bd8aSPaolo Bonzini 971114e712SDavid Gibson raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); 989f64bd8aSPaolo Bonzini 99ecbc25faSDavid Gibson if (is_ram_address(spapr, raddr)) { 1009f64bd8aSPaolo Bonzini /* Regular RAM - should have WIMG=0010 */ 101d5aea6f3SDavid Gibson if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 1029f64bd8aSPaolo Bonzini return H_PARAMETER; 1039f64bd8aSPaolo Bonzini } 1049f64bd8aSPaolo Bonzini } else { 105c1175907SAneesh Kumar K.V target_ulong wimg_flags; 1069f64bd8aSPaolo Bonzini /* Looks like an IO address */ 1079f64bd8aSPaolo Bonzini /* FIXME: What WIMG combinations could be sensible for IO? 1089f64bd8aSPaolo Bonzini * For now we allow WIMG=010x, but are there others? */ 1099f64bd8aSPaolo Bonzini /* FIXME: Should we check against registered IO addresses? */ 110c1175907SAneesh Kumar K.V wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); 111c1175907SAneesh Kumar K.V 112c1175907SAneesh Kumar K.V if (wimg_flags != HPTE64_R_I && 113c1175907SAneesh Kumar K.V wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { 1149f64bd8aSPaolo Bonzini return H_PARAMETER; 1159f64bd8aSPaolo Bonzini } 1169f64bd8aSPaolo Bonzini } 1179f64bd8aSPaolo Bonzini 1189f64bd8aSPaolo Bonzini pteh &= ~0x60ULL; 1199f64bd8aSPaolo Bonzini 120c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 1219f64bd8aSPaolo Bonzini return H_PARAMETER; 1229f64bd8aSPaolo Bonzini } 1237c43bca0SAneesh Kumar K.V 124c6404adeSDavid Gibson slot = ptex & 7ULL; 125c6404adeSDavid Gibson ptex = ptex & ~7ULL; 126c6404adeSDavid Gibson 1279f64bd8aSPaolo Bonzini if (likely((flags & H_EXACT) == 0)) { 1287222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 129c6404adeSDavid Gibson for (slot = 0; slot < 8; slot++) { 1307222b94aSDavid Gibson if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { 1319f64bd8aSPaolo Bonzini break; 1329f64bd8aSPaolo Bonzini } 1337aaf4957SAneesh Kumar K.V } 1347222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 135c6404adeSDavid Gibson if (slot == 8) { 1367aaf4957SAneesh Kumar K.V return H_PTEG_FULL; 1377aaf4957SAneesh Kumar K.V } 1389f64bd8aSPaolo Bonzini } else { 1397222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); 1407222b94aSDavid Gibson if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { 1417222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); 1429f64bd8aSPaolo Bonzini return H_PTEG_FULL; 1439f64bd8aSPaolo Bonzini } 1447222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 1459f64bd8aSPaolo Bonzini } 1467c43bca0SAneesh Kumar K.V 147c6404adeSDavid Gibson ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); 1489f64bd8aSPaolo Bonzini 149c6404adeSDavid Gibson args[0] = ptex + slot; 1509f64bd8aSPaolo Bonzini return H_SUCCESS; 1519f64bd8aSPaolo Bonzini } 1529f64bd8aSPaolo Bonzini 153a3801402SStefan Weil typedef enum { 1549f64bd8aSPaolo Bonzini REMOVE_SUCCESS = 0, 1559f64bd8aSPaolo Bonzini REMOVE_NOT_FOUND = 1, 1569f64bd8aSPaolo Bonzini REMOVE_PARM = 2, 1579f64bd8aSPaolo Bonzini REMOVE_HW = 3, 158a3801402SStefan Weil } RemoveResult; 1599f64bd8aSPaolo Bonzini 1607ef23068SDavid Gibson static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, 1619f64bd8aSPaolo Bonzini target_ulong avpn, 1629f64bd8aSPaolo Bonzini target_ulong flags, 1639f64bd8aSPaolo Bonzini target_ulong *vp, target_ulong *rp) 1649f64bd8aSPaolo Bonzini { 1657222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 16661a36c9bSDavid Gibson target_ulong v, r; 1679f64bd8aSPaolo Bonzini 168c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 1699f64bd8aSPaolo Bonzini return REMOVE_PARM; 1709f64bd8aSPaolo Bonzini } 1719f64bd8aSPaolo Bonzini 1727222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 1737222b94aSDavid Gibson v = ppc_hash64_hpte0(cpu, hptes, 0); 1747222b94aSDavid Gibson r = ppc_hash64_hpte1(cpu, hptes, 0); 1757222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 1769f64bd8aSPaolo Bonzini 177d5aea6f3SDavid Gibson if ((v & HPTE64_V_VALID) == 0 || 1789f64bd8aSPaolo Bonzini ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 1799f64bd8aSPaolo Bonzini ((flags & H_ANDCOND) && (v & avpn) != 0)) { 1809f64bd8aSPaolo Bonzini return REMOVE_NOT_FOUND; 1819f64bd8aSPaolo Bonzini } 1829f64bd8aSPaolo Bonzini *vp = v; 1839f64bd8aSPaolo Bonzini *rp = r; 1847ef23068SDavid Gibson ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); 18561a36c9bSDavid Gibson ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 1869f64bd8aSPaolo Bonzini return REMOVE_SUCCESS; 1879f64bd8aSPaolo Bonzini } 1889f64bd8aSPaolo Bonzini 18928e02042SDavid Gibson static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1909f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 1919f64bd8aSPaolo Bonzini { 192cd0c6f47SBenjamin Herrenschmidt CPUPPCState *env = &cpu->env; 1939f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 194c6404adeSDavid Gibson target_ulong ptex = args[1]; 1959f64bd8aSPaolo Bonzini target_ulong avpn = args[2]; 196a3801402SStefan Weil RemoveResult ret; 1979f64bd8aSPaolo Bonzini 198c6404adeSDavid Gibson ret = remove_hpte(cpu, ptex, avpn, flags, 1999f64bd8aSPaolo Bonzini &args[0], &args[1]); 2009f64bd8aSPaolo Bonzini 2019f64bd8aSPaolo Bonzini switch (ret) { 2029f64bd8aSPaolo Bonzini case REMOVE_SUCCESS: 203e3cffe6fSNikunj A Dadhania check_tlb_flush(env, true); 2049f64bd8aSPaolo Bonzini return H_SUCCESS; 2059f64bd8aSPaolo Bonzini 2069f64bd8aSPaolo Bonzini case REMOVE_NOT_FOUND: 2079f64bd8aSPaolo Bonzini return H_NOT_FOUND; 2089f64bd8aSPaolo Bonzini 2099f64bd8aSPaolo Bonzini case REMOVE_PARM: 2109f64bd8aSPaolo Bonzini return H_PARAMETER; 2119f64bd8aSPaolo Bonzini 2129f64bd8aSPaolo Bonzini case REMOVE_HW: 2139f64bd8aSPaolo Bonzini return H_HARDWARE; 2149f64bd8aSPaolo Bonzini } 2159f64bd8aSPaolo Bonzini 2169a39970dSStefan Weil g_assert_not_reached(); 2179f64bd8aSPaolo Bonzini } 2189f64bd8aSPaolo Bonzini 2199f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 2209f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 2219f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 2229f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_END 0xc000000000000000ULL 2239f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 2249f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 2259f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 2269f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 2279f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_HW 0x3000000000000000ULL 2289f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 2299f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 2309f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 2319f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 2329f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 2339f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 2349f64bd8aSPaolo Bonzini 2359f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_MAX_BATCH 4 2369f64bd8aSPaolo Bonzini 23728e02042SDavid Gibson static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 2389f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 2399f64bd8aSPaolo Bonzini { 240cd0c6f47SBenjamin Herrenschmidt CPUPPCState *env = &cpu->env; 2419f64bd8aSPaolo Bonzini int i; 242cd0c6f47SBenjamin Herrenschmidt target_ulong rc = H_SUCCESS; 2439f64bd8aSPaolo Bonzini 2449f64bd8aSPaolo Bonzini for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 2459f64bd8aSPaolo Bonzini target_ulong *tsh = &args[i*2]; 2469f64bd8aSPaolo Bonzini target_ulong tsl = args[i*2 + 1]; 2479f64bd8aSPaolo Bonzini target_ulong v, r, ret; 2489f64bd8aSPaolo Bonzini 2499f64bd8aSPaolo Bonzini if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 2509f64bd8aSPaolo Bonzini break; 2519f64bd8aSPaolo Bonzini } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 2529f64bd8aSPaolo Bonzini return H_PARAMETER; 2539f64bd8aSPaolo Bonzini } 2549f64bd8aSPaolo Bonzini 2559f64bd8aSPaolo Bonzini *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 2569f64bd8aSPaolo Bonzini *tsh |= H_BULK_REMOVE_RESPONSE; 2579f64bd8aSPaolo Bonzini 2589f64bd8aSPaolo Bonzini if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 2599f64bd8aSPaolo Bonzini *tsh |= H_BULK_REMOVE_PARM; 2609f64bd8aSPaolo Bonzini return H_PARAMETER; 2619f64bd8aSPaolo Bonzini } 2629f64bd8aSPaolo Bonzini 2637ef23068SDavid Gibson ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, 2649f64bd8aSPaolo Bonzini (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 2659f64bd8aSPaolo Bonzini &v, &r); 2669f64bd8aSPaolo Bonzini 2679f64bd8aSPaolo Bonzini *tsh |= ret << 60; 2689f64bd8aSPaolo Bonzini 2699f64bd8aSPaolo Bonzini switch (ret) { 2709f64bd8aSPaolo Bonzini case REMOVE_SUCCESS: 271d5aea6f3SDavid Gibson *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 2729f64bd8aSPaolo Bonzini break; 2739f64bd8aSPaolo Bonzini 2749f64bd8aSPaolo Bonzini case REMOVE_PARM: 275cd0c6f47SBenjamin Herrenschmidt rc = H_PARAMETER; 276cd0c6f47SBenjamin Herrenschmidt goto exit; 2779f64bd8aSPaolo Bonzini 2789f64bd8aSPaolo Bonzini case REMOVE_HW: 279cd0c6f47SBenjamin Herrenschmidt rc = H_HARDWARE; 280cd0c6f47SBenjamin Herrenschmidt goto exit; 2819f64bd8aSPaolo Bonzini } 2829f64bd8aSPaolo Bonzini } 283cd0c6f47SBenjamin Herrenschmidt exit: 284e3cffe6fSNikunj A Dadhania check_tlb_flush(env, true); 2859f64bd8aSPaolo Bonzini 286cd0c6f47SBenjamin Herrenschmidt return rc; 2879f64bd8aSPaolo Bonzini } 2889f64bd8aSPaolo Bonzini 28928e02042SDavid Gibson static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr, 2909f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 2919f64bd8aSPaolo Bonzini { 2929f64bd8aSPaolo Bonzini CPUPPCState *env = &cpu->env; 2939f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 294c6404adeSDavid Gibson target_ulong ptex = args[1]; 2959f64bd8aSPaolo Bonzini target_ulong avpn = args[2]; 2967222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 29761a36c9bSDavid Gibson target_ulong v, r; 2989f64bd8aSPaolo Bonzini 299c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 3009f64bd8aSPaolo Bonzini return H_PARAMETER; 3019f64bd8aSPaolo Bonzini } 3029f64bd8aSPaolo Bonzini 3037222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 3047222b94aSDavid Gibson v = ppc_hash64_hpte0(cpu, hptes, 0); 3057222b94aSDavid Gibson r = ppc_hash64_hpte1(cpu, hptes, 0); 3067222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 3079f64bd8aSPaolo Bonzini 308d5aea6f3SDavid Gibson if ((v & HPTE64_V_VALID) == 0 || 3099f64bd8aSPaolo Bonzini ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 3109f64bd8aSPaolo Bonzini return H_NOT_FOUND; 3119f64bd8aSPaolo Bonzini } 3129f64bd8aSPaolo Bonzini 313d5aea6f3SDavid Gibson r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 314d5aea6f3SDavid Gibson HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 315d5aea6f3SDavid Gibson r |= (flags << 55) & HPTE64_R_PP0; 316d5aea6f3SDavid Gibson r |= (flags << 48) & HPTE64_R_KEY_HI; 317d5aea6f3SDavid Gibson r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 318c6404adeSDavid Gibson ppc_hash64_store_hpte(cpu, ptex, 3193f94170bSAneesh Kumar K.V (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); 320c6404adeSDavid Gibson ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 321d76ab5e1SNikunj A Dadhania /* Flush the tlb */ 322d76ab5e1SNikunj A Dadhania check_tlb_flush(env, true); 3239f64bd8aSPaolo Bonzini /* Don't need a memory barrier, due to qemu's global lock */ 324c6404adeSDavid Gibson ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); 3259f64bd8aSPaolo Bonzini return H_SUCCESS; 3269f64bd8aSPaolo Bonzini } 3279f64bd8aSPaolo Bonzini 32828e02042SDavid Gibson static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr, 329fa388916SAnthony Liguori target_ulong opcode, target_ulong *args) 330fa388916SAnthony Liguori { 331fa388916SAnthony Liguori target_ulong flags = args[0]; 332c6404adeSDavid Gibson target_ulong ptex = args[1]; 333fa388916SAnthony Liguori uint8_t *hpte; 334fa388916SAnthony Liguori int i, ridx, n_entries = 1; 335fa388916SAnthony Liguori 336c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 337fa388916SAnthony Liguori return H_PARAMETER; 338fa388916SAnthony Liguori } 339fa388916SAnthony Liguori 340fa388916SAnthony Liguori if (flags & H_READ_4) { 341fa388916SAnthony Liguori /* Clear the two low order bits */ 342c6404adeSDavid Gibson ptex &= ~(3ULL); 343fa388916SAnthony Liguori n_entries = 4; 344fa388916SAnthony Liguori } 345fa388916SAnthony Liguori 346e57ca75cSDavid Gibson hpte = spapr->htab + (ptex * HASH_PTE_SIZE_64); 347fa388916SAnthony Liguori 348fa388916SAnthony Liguori for (i = 0, ridx = 0; i < n_entries; i++) { 349fa388916SAnthony Liguori args[ridx++] = ldq_p(hpte); 350fa388916SAnthony Liguori args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); 351fa388916SAnthony Liguori hpte += HASH_PTE_SIZE_64; 352fa388916SAnthony Liguori } 353fa388916SAnthony Liguori 354fa388916SAnthony Liguori return H_SUCCESS; 355fa388916SAnthony Liguori } 356fa388916SAnthony Liguori 357423576f7SThomas Huth static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr, 358423576f7SThomas Huth target_ulong opcode, target_ulong *args) 359423576f7SThomas Huth { 360423576f7SThomas Huth cpu_synchronize_state(CPU(cpu)); 361423576f7SThomas Huth cpu->env.spr[SPR_SPRG0] = args[0]; 362423576f7SThomas Huth 363423576f7SThomas Huth return H_SUCCESS; 364423576f7SThomas Huth } 365423576f7SThomas Huth 36628e02042SDavid Gibson static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 3679f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 3689f64bd8aSPaolo Bonzini { 369af08a58fSThomas Huth if (!has_spr(cpu, SPR_DABR)) { 370af08a58fSThomas Huth return H_HARDWARE; /* DABR register not available */ 371af08a58fSThomas Huth } 372af08a58fSThomas Huth cpu_synchronize_state(CPU(cpu)); 373af08a58fSThomas Huth 374af08a58fSThomas Huth if (has_spr(cpu, SPR_DABRX)) { 375af08a58fSThomas Huth cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 376af08a58fSThomas Huth } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 377af08a58fSThomas Huth return H_RESERVED_DABR; 378af08a58fSThomas Huth } 379af08a58fSThomas Huth 380af08a58fSThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 381af08a58fSThomas Huth return H_SUCCESS; 3829f64bd8aSPaolo Bonzini } 3839f64bd8aSPaolo Bonzini 384e49ff266SThomas Huth static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 385e49ff266SThomas Huth target_ulong opcode, target_ulong *args) 386e49ff266SThomas Huth { 387e49ff266SThomas Huth target_ulong dabrx = args[1]; 388e49ff266SThomas Huth 389e49ff266SThomas Huth if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { 390e49ff266SThomas Huth return H_HARDWARE; 391e49ff266SThomas Huth } 392e49ff266SThomas Huth 393e49ff266SThomas Huth if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 394e49ff266SThomas Huth || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 395e49ff266SThomas Huth return H_PARAMETER; 396e49ff266SThomas Huth } 397e49ff266SThomas Huth 398e49ff266SThomas Huth cpu_synchronize_state(CPU(cpu)); 399e49ff266SThomas Huth cpu->env.spr[SPR_DABRX] = dabrx; 400e49ff266SThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 401e49ff266SThomas Huth 402e49ff266SThomas Huth return H_SUCCESS; 403e49ff266SThomas Huth } 404e49ff266SThomas Huth 4053240dd9aSThomas Huth static target_ulong h_page_init(PowerPCCPU *cpu, sPAPRMachineState *spapr, 4063240dd9aSThomas Huth target_ulong opcode, target_ulong *args) 4073240dd9aSThomas Huth { 4083240dd9aSThomas Huth target_ulong flags = args[0]; 4093240dd9aSThomas Huth hwaddr dst = args[1]; 4103240dd9aSThomas Huth hwaddr src = args[2]; 4113240dd9aSThomas Huth hwaddr len = TARGET_PAGE_SIZE; 4123240dd9aSThomas Huth uint8_t *pdst, *psrc; 4133240dd9aSThomas Huth target_long ret = H_SUCCESS; 4143240dd9aSThomas Huth 4153240dd9aSThomas Huth if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 4163240dd9aSThomas Huth | H_COPY_PAGE | H_ZERO_PAGE)) { 4173240dd9aSThomas Huth qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 4183240dd9aSThomas Huth flags); 4193240dd9aSThomas Huth return H_PARAMETER; 4203240dd9aSThomas Huth } 4213240dd9aSThomas Huth 4223240dd9aSThomas Huth /* Map-in destination */ 4233240dd9aSThomas Huth if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 4243240dd9aSThomas Huth return H_PARAMETER; 4253240dd9aSThomas Huth } 4263240dd9aSThomas Huth pdst = cpu_physical_memory_map(dst, &len, 1); 4273240dd9aSThomas Huth if (!pdst || len != TARGET_PAGE_SIZE) { 4283240dd9aSThomas Huth return H_PARAMETER; 4293240dd9aSThomas Huth } 4303240dd9aSThomas Huth 4313240dd9aSThomas Huth if (flags & H_COPY_PAGE) { 4323240dd9aSThomas Huth /* Map-in source, copy to destination, and unmap source again */ 4333240dd9aSThomas Huth if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 4343240dd9aSThomas Huth ret = H_PARAMETER; 4353240dd9aSThomas Huth goto unmap_out; 4363240dd9aSThomas Huth } 4373240dd9aSThomas Huth psrc = cpu_physical_memory_map(src, &len, 0); 4383240dd9aSThomas Huth if (!psrc || len != TARGET_PAGE_SIZE) { 4393240dd9aSThomas Huth ret = H_PARAMETER; 4403240dd9aSThomas Huth goto unmap_out; 4413240dd9aSThomas Huth } 4423240dd9aSThomas Huth memcpy(pdst, psrc, len); 4433240dd9aSThomas Huth cpu_physical_memory_unmap(psrc, len, 0, len); 4443240dd9aSThomas Huth } else if (flags & H_ZERO_PAGE) { 4453240dd9aSThomas Huth memset(pdst, 0, len); /* Just clear the destination page */ 4463240dd9aSThomas Huth } 4473240dd9aSThomas Huth 4483240dd9aSThomas Huth if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 4493240dd9aSThomas Huth kvmppc_dcbst_range(cpu, pdst, len); 4503240dd9aSThomas Huth } 4513240dd9aSThomas Huth if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 4523240dd9aSThomas Huth if (kvm_enabled()) { 4533240dd9aSThomas Huth kvmppc_icbi_range(cpu, pdst, len); 4543240dd9aSThomas Huth } else { 4553240dd9aSThomas Huth tb_flush(CPU(cpu)); 4563240dd9aSThomas Huth } 4573240dd9aSThomas Huth } 4583240dd9aSThomas Huth 4593240dd9aSThomas Huth unmap_out: 4603240dd9aSThomas Huth cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 4613240dd9aSThomas Huth return ret; 4623240dd9aSThomas Huth } 4633240dd9aSThomas Huth 4649f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 4659f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 4669f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 4679f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 4689f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 4699f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 4709f64bd8aSPaolo Bonzini 4719f64bd8aSPaolo Bonzini #define VPA_MIN_SIZE 640 4729f64bd8aSPaolo Bonzini #define VPA_SIZE_OFFSET 0x4 4739f64bd8aSPaolo Bonzini #define VPA_SHARED_PROC_OFFSET 0x9 4749f64bd8aSPaolo Bonzini #define VPA_SHARED_PROC_VAL 0x2 4759f64bd8aSPaolo Bonzini 4769f64bd8aSPaolo Bonzini static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) 4779f64bd8aSPaolo Bonzini { 47833276f1bSAndreas Färber CPUState *cs = CPU(ppc_env_get_cpu(env)); 4799f64bd8aSPaolo Bonzini uint16_t size; 4809f64bd8aSPaolo Bonzini uint8_t tmp; 4819f64bd8aSPaolo Bonzini 4829f64bd8aSPaolo Bonzini if (vpa == 0) { 4839f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 4849f64bd8aSPaolo Bonzini return H_HARDWARE; 4859f64bd8aSPaolo Bonzini } 4869f64bd8aSPaolo Bonzini 4879f64bd8aSPaolo Bonzini if (vpa % env->dcache_line_size) { 4889f64bd8aSPaolo Bonzini return H_PARAMETER; 4899f64bd8aSPaolo Bonzini } 4909f64bd8aSPaolo Bonzini /* FIXME: bounds check the address */ 4919f64bd8aSPaolo Bonzini 49241701aa4SEdgar E. Iglesias size = lduw_be_phys(cs->as, vpa + 0x4); 4939f64bd8aSPaolo Bonzini 4949f64bd8aSPaolo Bonzini if (size < VPA_MIN_SIZE) { 4959f64bd8aSPaolo Bonzini return H_PARAMETER; 4969f64bd8aSPaolo Bonzini } 4979f64bd8aSPaolo Bonzini 4989f64bd8aSPaolo Bonzini /* VPA is not allowed to cross a page boundary */ 4999f64bd8aSPaolo Bonzini if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 5009f64bd8aSPaolo Bonzini return H_PARAMETER; 5019f64bd8aSPaolo Bonzini } 5029f64bd8aSPaolo Bonzini 5039f64bd8aSPaolo Bonzini env->vpa_addr = vpa; 5049f64bd8aSPaolo Bonzini 5052c17449bSEdgar E. Iglesias tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); 5069f64bd8aSPaolo Bonzini tmp |= VPA_SHARED_PROC_VAL; 507db3be60dSEdgar E. Iglesias stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 5089f64bd8aSPaolo Bonzini 5099f64bd8aSPaolo Bonzini return H_SUCCESS; 5109f64bd8aSPaolo Bonzini } 5119f64bd8aSPaolo Bonzini 5129f64bd8aSPaolo Bonzini static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) 5139f64bd8aSPaolo Bonzini { 5149f64bd8aSPaolo Bonzini if (env->slb_shadow_addr) { 5159f64bd8aSPaolo Bonzini return H_RESOURCE; 5169f64bd8aSPaolo Bonzini } 5179f64bd8aSPaolo Bonzini 5189f64bd8aSPaolo Bonzini if (env->dtl_addr) { 5199f64bd8aSPaolo Bonzini return H_RESOURCE; 5209f64bd8aSPaolo Bonzini } 5219f64bd8aSPaolo Bonzini 5229f64bd8aSPaolo Bonzini env->vpa_addr = 0; 5239f64bd8aSPaolo Bonzini return H_SUCCESS; 5249f64bd8aSPaolo Bonzini } 5259f64bd8aSPaolo Bonzini 5269f64bd8aSPaolo Bonzini static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) 5279f64bd8aSPaolo Bonzini { 52833276f1bSAndreas Färber CPUState *cs = CPU(ppc_env_get_cpu(env)); 5299f64bd8aSPaolo Bonzini uint32_t size; 5309f64bd8aSPaolo Bonzini 5319f64bd8aSPaolo Bonzini if (addr == 0) { 5329f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 5339f64bd8aSPaolo Bonzini return H_HARDWARE; 5349f64bd8aSPaolo Bonzini } 5359f64bd8aSPaolo Bonzini 536fdfba1a2SEdgar E. Iglesias size = ldl_be_phys(cs->as, addr + 0x4); 5379f64bd8aSPaolo Bonzini if (size < 0x8) { 5389f64bd8aSPaolo Bonzini return H_PARAMETER; 5399f64bd8aSPaolo Bonzini } 5409f64bd8aSPaolo Bonzini 5419f64bd8aSPaolo Bonzini if ((addr / 4096) != ((addr + size - 1) / 4096)) { 5429f64bd8aSPaolo Bonzini return H_PARAMETER; 5439f64bd8aSPaolo Bonzini } 5449f64bd8aSPaolo Bonzini 5459f64bd8aSPaolo Bonzini if (!env->vpa_addr) { 5469f64bd8aSPaolo Bonzini return H_RESOURCE; 5479f64bd8aSPaolo Bonzini } 5489f64bd8aSPaolo Bonzini 5499f64bd8aSPaolo Bonzini env->slb_shadow_addr = addr; 5509f64bd8aSPaolo Bonzini env->slb_shadow_size = size; 5519f64bd8aSPaolo Bonzini 5529f64bd8aSPaolo Bonzini return H_SUCCESS; 5539f64bd8aSPaolo Bonzini } 5549f64bd8aSPaolo Bonzini 5559f64bd8aSPaolo Bonzini static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) 5569f64bd8aSPaolo Bonzini { 5579f64bd8aSPaolo Bonzini env->slb_shadow_addr = 0; 5589f64bd8aSPaolo Bonzini env->slb_shadow_size = 0; 5599f64bd8aSPaolo Bonzini return H_SUCCESS; 5609f64bd8aSPaolo Bonzini } 5619f64bd8aSPaolo Bonzini 5629f64bd8aSPaolo Bonzini static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) 5639f64bd8aSPaolo Bonzini { 56433276f1bSAndreas Färber CPUState *cs = CPU(ppc_env_get_cpu(env)); 5659f64bd8aSPaolo Bonzini uint32_t size; 5669f64bd8aSPaolo Bonzini 5679f64bd8aSPaolo Bonzini if (addr == 0) { 5689f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with DTL at logical 0\n"); 5699f64bd8aSPaolo Bonzini return H_HARDWARE; 5709f64bd8aSPaolo Bonzini } 5719f64bd8aSPaolo Bonzini 572fdfba1a2SEdgar E. Iglesias size = ldl_be_phys(cs->as, addr + 0x4); 5739f64bd8aSPaolo Bonzini 5749f64bd8aSPaolo Bonzini if (size < 48) { 5759f64bd8aSPaolo Bonzini return H_PARAMETER; 5769f64bd8aSPaolo Bonzini } 5779f64bd8aSPaolo Bonzini 5789f64bd8aSPaolo Bonzini if (!env->vpa_addr) { 5799f64bd8aSPaolo Bonzini return H_RESOURCE; 5809f64bd8aSPaolo Bonzini } 5819f64bd8aSPaolo Bonzini 5829f64bd8aSPaolo Bonzini env->dtl_addr = addr; 5839f64bd8aSPaolo Bonzini env->dtl_size = size; 5849f64bd8aSPaolo Bonzini 5859f64bd8aSPaolo Bonzini return H_SUCCESS; 5869f64bd8aSPaolo Bonzini } 5879f64bd8aSPaolo Bonzini 5889f64bd8aSPaolo Bonzini static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) 5899f64bd8aSPaolo Bonzini { 5909f64bd8aSPaolo Bonzini env->dtl_addr = 0; 5919f64bd8aSPaolo Bonzini env->dtl_size = 0; 5929f64bd8aSPaolo Bonzini 5939f64bd8aSPaolo Bonzini return H_SUCCESS; 5949f64bd8aSPaolo Bonzini } 5959f64bd8aSPaolo Bonzini 59628e02042SDavid Gibson static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr, 5979f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 5989f64bd8aSPaolo Bonzini { 5999f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 6009f64bd8aSPaolo Bonzini target_ulong procno = args[1]; 6019f64bd8aSPaolo Bonzini target_ulong vpa = args[2]; 6029f64bd8aSPaolo Bonzini target_ulong ret = H_PARAMETER; 6039f64bd8aSPaolo Bonzini CPUPPCState *tenv; 6040f20ba62SAlexey Kardashevskiy PowerPCCPU *tcpu; 6059f64bd8aSPaolo Bonzini 6060f20ba62SAlexey Kardashevskiy tcpu = ppc_get_vcpu_by_dt_id(procno); 6079f64bd8aSPaolo Bonzini if (!tcpu) { 6089f64bd8aSPaolo Bonzini return H_PARAMETER; 6099f64bd8aSPaolo Bonzini } 6100f20ba62SAlexey Kardashevskiy tenv = &tcpu->env; 6119f64bd8aSPaolo Bonzini 6129f64bd8aSPaolo Bonzini switch (flags) { 6139f64bd8aSPaolo Bonzini case FLAGS_REGISTER_VPA: 6149f64bd8aSPaolo Bonzini ret = register_vpa(tenv, vpa); 6159f64bd8aSPaolo Bonzini break; 6169f64bd8aSPaolo Bonzini 6179f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_VPA: 6189f64bd8aSPaolo Bonzini ret = deregister_vpa(tenv, vpa); 6199f64bd8aSPaolo Bonzini break; 6209f64bd8aSPaolo Bonzini 6219f64bd8aSPaolo Bonzini case FLAGS_REGISTER_SLBSHADOW: 6229f64bd8aSPaolo Bonzini ret = register_slb_shadow(tenv, vpa); 6239f64bd8aSPaolo Bonzini break; 6249f64bd8aSPaolo Bonzini 6259f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_SLBSHADOW: 6269f64bd8aSPaolo Bonzini ret = deregister_slb_shadow(tenv, vpa); 6279f64bd8aSPaolo Bonzini break; 6289f64bd8aSPaolo Bonzini 6299f64bd8aSPaolo Bonzini case FLAGS_REGISTER_DTL: 6309f64bd8aSPaolo Bonzini ret = register_dtl(tenv, vpa); 6319f64bd8aSPaolo Bonzini break; 6329f64bd8aSPaolo Bonzini 6339f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_DTL: 6349f64bd8aSPaolo Bonzini ret = deregister_dtl(tenv, vpa); 6359f64bd8aSPaolo Bonzini break; 6369f64bd8aSPaolo Bonzini } 6379f64bd8aSPaolo Bonzini 6389f64bd8aSPaolo Bonzini return ret; 6399f64bd8aSPaolo Bonzini } 6409f64bd8aSPaolo Bonzini 64128e02042SDavid Gibson static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr, 6429f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 6439f64bd8aSPaolo Bonzini { 6449f64bd8aSPaolo Bonzini CPUPPCState *env = &cpu->env; 6459f64bd8aSPaolo Bonzini CPUState *cs = CPU(cpu); 6469f64bd8aSPaolo Bonzini 6479f64bd8aSPaolo Bonzini env->msr |= (1ULL << MSR_EE); 6489f64bd8aSPaolo Bonzini hreg_compute_hflags(env); 6499f64bd8aSPaolo Bonzini if (!cpu_has_work(cs)) { 650259186a7SAndreas Färber cs->halted = 1; 65127103424SAndreas Färber cs->exception_index = EXCP_HLT; 6529f64bd8aSPaolo Bonzini cs->exit_request = 1; 6539f64bd8aSPaolo Bonzini } 6549f64bd8aSPaolo Bonzini return H_SUCCESS; 6559f64bd8aSPaolo Bonzini } 6569f64bd8aSPaolo Bonzini 65728e02042SDavid Gibson static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr, 6589f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 6599f64bd8aSPaolo Bonzini { 6609f64bd8aSPaolo Bonzini target_ulong rtas_r3 = args[0]; 6614fe822e0SAlexey Kardashevskiy uint32_t token = rtas_ld(rtas_r3, 0); 6624fe822e0SAlexey Kardashevskiy uint32_t nargs = rtas_ld(rtas_r3, 1); 6634fe822e0SAlexey Kardashevskiy uint32_t nret = rtas_ld(rtas_r3, 2); 6649f64bd8aSPaolo Bonzini 665210b580bSAnthony Liguori return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 6669f64bd8aSPaolo Bonzini nret, rtas_r3 + 12 + 4*nargs); 6679f64bd8aSPaolo Bonzini } 6689f64bd8aSPaolo Bonzini 66928e02042SDavid Gibson static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr, 6709f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 6719f64bd8aSPaolo Bonzini { 672fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 6739f64bd8aSPaolo Bonzini target_ulong size = args[0]; 6749f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 6759f64bd8aSPaolo Bonzini 6769f64bd8aSPaolo Bonzini switch (size) { 6779f64bd8aSPaolo Bonzini case 1: 6782c17449bSEdgar E. Iglesias args[0] = ldub_phys(cs->as, addr); 6799f64bd8aSPaolo Bonzini return H_SUCCESS; 6809f64bd8aSPaolo Bonzini case 2: 68141701aa4SEdgar E. Iglesias args[0] = lduw_phys(cs->as, addr); 6829f64bd8aSPaolo Bonzini return H_SUCCESS; 6839f64bd8aSPaolo Bonzini case 4: 684fdfba1a2SEdgar E. Iglesias args[0] = ldl_phys(cs->as, addr); 6859f64bd8aSPaolo Bonzini return H_SUCCESS; 6869f64bd8aSPaolo Bonzini case 8: 6872c17449bSEdgar E. Iglesias args[0] = ldq_phys(cs->as, addr); 6889f64bd8aSPaolo Bonzini return H_SUCCESS; 6899f64bd8aSPaolo Bonzini } 6909f64bd8aSPaolo Bonzini return H_PARAMETER; 6919f64bd8aSPaolo Bonzini } 6929f64bd8aSPaolo Bonzini 69328e02042SDavid Gibson static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, 6949f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 6959f64bd8aSPaolo Bonzini { 696f606604fSEdgar E. Iglesias CPUState *cs = CPU(cpu); 697f606604fSEdgar E. Iglesias 6989f64bd8aSPaolo Bonzini target_ulong size = args[0]; 6999f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 7009f64bd8aSPaolo Bonzini target_ulong val = args[2]; 7019f64bd8aSPaolo Bonzini 7029f64bd8aSPaolo Bonzini switch (size) { 7039f64bd8aSPaolo Bonzini case 1: 704db3be60dSEdgar E. Iglesias stb_phys(cs->as, addr, val); 7059f64bd8aSPaolo Bonzini return H_SUCCESS; 7069f64bd8aSPaolo Bonzini case 2: 7075ce5944dSEdgar E. Iglesias stw_phys(cs->as, addr, val); 7089f64bd8aSPaolo Bonzini return H_SUCCESS; 7099f64bd8aSPaolo Bonzini case 4: 710ab1da857SEdgar E. Iglesias stl_phys(cs->as, addr, val); 7119f64bd8aSPaolo Bonzini return H_SUCCESS; 7129f64bd8aSPaolo Bonzini case 8: 713f606604fSEdgar E. Iglesias stq_phys(cs->as, addr, val); 7149f64bd8aSPaolo Bonzini return H_SUCCESS; 7159f64bd8aSPaolo Bonzini } 7169f64bd8aSPaolo Bonzini return H_PARAMETER; 7179f64bd8aSPaolo Bonzini } 7189f64bd8aSPaolo Bonzini 71928e02042SDavid Gibson static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr, 7209f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 7219f64bd8aSPaolo Bonzini { 722fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 723fdfba1a2SEdgar E. Iglesias 7249f64bd8aSPaolo Bonzini target_ulong dst = args[0]; /* Destination address */ 7259f64bd8aSPaolo Bonzini target_ulong src = args[1]; /* Source address */ 7269f64bd8aSPaolo Bonzini target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 7279f64bd8aSPaolo Bonzini target_ulong count = args[3]; /* Element count */ 7289f64bd8aSPaolo Bonzini target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 7299f64bd8aSPaolo Bonzini uint64_t tmp; 7309f64bd8aSPaolo Bonzini unsigned int mask = (1 << esize) - 1; 7319f64bd8aSPaolo Bonzini int step = 1 << esize; 7329f64bd8aSPaolo Bonzini 7339f64bd8aSPaolo Bonzini if (count > 0x80000000) { 7349f64bd8aSPaolo Bonzini return H_PARAMETER; 7359f64bd8aSPaolo Bonzini } 7369f64bd8aSPaolo Bonzini 7379f64bd8aSPaolo Bonzini if ((dst & mask) || (src & mask) || (op > 1)) { 7389f64bd8aSPaolo Bonzini return H_PARAMETER; 7399f64bd8aSPaolo Bonzini } 7409f64bd8aSPaolo Bonzini 7419f64bd8aSPaolo Bonzini if (dst >= src && dst < (src + (count << esize))) { 7429f64bd8aSPaolo Bonzini dst = dst + ((count - 1) << esize); 7439f64bd8aSPaolo Bonzini src = src + ((count - 1) << esize); 7449f64bd8aSPaolo Bonzini step = -step; 7459f64bd8aSPaolo Bonzini } 7469f64bd8aSPaolo Bonzini 7479f64bd8aSPaolo Bonzini while (count--) { 7489f64bd8aSPaolo Bonzini switch (esize) { 7499f64bd8aSPaolo Bonzini case 0: 7502c17449bSEdgar E. Iglesias tmp = ldub_phys(cs->as, src); 7519f64bd8aSPaolo Bonzini break; 7529f64bd8aSPaolo Bonzini case 1: 75341701aa4SEdgar E. Iglesias tmp = lduw_phys(cs->as, src); 7549f64bd8aSPaolo Bonzini break; 7559f64bd8aSPaolo Bonzini case 2: 756fdfba1a2SEdgar E. Iglesias tmp = ldl_phys(cs->as, src); 7579f64bd8aSPaolo Bonzini break; 7589f64bd8aSPaolo Bonzini case 3: 7592c17449bSEdgar E. Iglesias tmp = ldq_phys(cs->as, src); 7609f64bd8aSPaolo Bonzini break; 7619f64bd8aSPaolo Bonzini default: 7629f64bd8aSPaolo Bonzini return H_PARAMETER; 7639f64bd8aSPaolo Bonzini } 7649f64bd8aSPaolo Bonzini if (op == 1) { 7659f64bd8aSPaolo Bonzini tmp = ~tmp; 7669f64bd8aSPaolo Bonzini } 7679f64bd8aSPaolo Bonzini switch (esize) { 7689f64bd8aSPaolo Bonzini case 0: 769db3be60dSEdgar E. Iglesias stb_phys(cs->as, dst, tmp); 7709f64bd8aSPaolo Bonzini break; 7719f64bd8aSPaolo Bonzini case 1: 7725ce5944dSEdgar E. Iglesias stw_phys(cs->as, dst, tmp); 7739f64bd8aSPaolo Bonzini break; 7749f64bd8aSPaolo Bonzini case 2: 775ab1da857SEdgar E. Iglesias stl_phys(cs->as, dst, tmp); 7769f64bd8aSPaolo Bonzini break; 7779f64bd8aSPaolo Bonzini case 3: 778f606604fSEdgar E. Iglesias stq_phys(cs->as, dst, tmp); 7799f64bd8aSPaolo Bonzini break; 7809f64bd8aSPaolo Bonzini } 7819f64bd8aSPaolo Bonzini dst = dst + step; 7829f64bd8aSPaolo Bonzini src = src + step; 7839f64bd8aSPaolo Bonzini } 7849f64bd8aSPaolo Bonzini 7859f64bd8aSPaolo Bonzini return H_SUCCESS; 7869f64bd8aSPaolo Bonzini } 7879f64bd8aSPaolo Bonzini 78828e02042SDavid Gibson static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 7899f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 7909f64bd8aSPaolo Bonzini { 7919f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 7929f64bd8aSPaolo Bonzini return H_SUCCESS; 7939f64bd8aSPaolo Bonzini } 7949f64bd8aSPaolo Bonzini 79528e02042SDavid Gibson static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr, 7969f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 7979f64bd8aSPaolo Bonzini { 7989f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 7999f64bd8aSPaolo Bonzini return H_SUCCESS; 8009f64bd8aSPaolo Bonzini } 8019f64bd8aSPaolo Bonzini 8027d0cd464SPeter Maydell static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 803c4015bbdSAlexey Kardashevskiy target_ulong mflags, 804c4015bbdSAlexey Kardashevskiy target_ulong value1, 805c4015bbdSAlexey Kardashevskiy target_ulong value2) 80642561bf2SAnton Blanchard { 80742561bf2SAnton Blanchard CPUState *cs; 80842561bf2SAnton Blanchard 80942561bf2SAnton Blanchard if (value1) { 810c4015bbdSAlexey Kardashevskiy return H_P3; 81142561bf2SAnton Blanchard } 81242561bf2SAnton Blanchard if (value2) { 813c4015bbdSAlexey Kardashevskiy return H_P4; 81442561bf2SAnton Blanchard } 815c4015bbdSAlexey Kardashevskiy 81642561bf2SAnton Blanchard switch (mflags) { 81742561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_BIG: 818bdc44640SAndreas Färber CPU_FOREACH(cs) { 819a46622fdSAlexey Kardashevskiy set_spr(cs, SPR_LPCR, 0, LPCR_ILE); 82042561bf2SAnton Blanchard } 821eefaccc0SDavid Gibson spapr_pci_switch_vga(true); 822c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 82342561bf2SAnton Blanchard 82442561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_LITTLE: 825bdc44640SAndreas Färber CPU_FOREACH(cs) { 826a46622fdSAlexey Kardashevskiy set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE); 82742561bf2SAnton Blanchard } 828eefaccc0SDavid Gibson spapr_pci_switch_vga(false); 829c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 830c4015bbdSAlexey Kardashevskiy } 831c4015bbdSAlexey Kardashevskiy 832c4015bbdSAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 833c4015bbdSAlexey Kardashevskiy } 834c4015bbdSAlexey Kardashevskiy 8357d0cd464SPeter Maydell static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 836d5ac4f54SAlexey Kardashevskiy target_ulong mflags, 837d5ac4f54SAlexey Kardashevskiy target_ulong value1, 838d5ac4f54SAlexey Kardashevskiy target_ulong value2) 839d5ac4f54SAlexey Kardashevskiy { 840d5ac4f54SAlexey Kardashevskiy CPUState *cs; 841d5ac4f54SAlexey Kardashevskiy PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 842d5ac4f54SAlexey Kardashevskiy 843d5ac4f54SAlexey Kardashevskiy if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 844d5ac4f54SAlexey Kardashevskiy return H_P2; 845d5ac4f54SAlexey Kardashevskiy } 846d5ac4f54SAlexey Kardashevskiy if (value1) { 847d5ac4f54SAlexey Kardashevskiy return H_P3; 848d5ac4f54SAlexey Kardashevskiy } 849d5ac4f54SAlexey Kardashevskiy if (value2) { 850d5ac4f54SAlexey Kardashevskiy return H_P4; 851d5ac4f54SAlexey Kardashevskiy } 852d5ac4f54SAlexey Kardashevskiy 8535c94b2a5SCédric Le Goater if (mflags == AIL_RESERVED) { 854d5ac4f54SAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 855d5ac4f54SAlexey Kardashevskiy } 856d5ac4f54SAlexey Kardashevskiy 857d5ac4f54SAlexey Kardashevskiy CPU_FOREACH(cs) { 858d5ac4f54SAlexey Kardashevskiy set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL); 859d5ac4f54SAlexey Kardashevskiy } 860d5ac4f54SAlexey Kardashevskiy 861d5ac4f54SAlexey Kardashevskiy return H_SUCCESS; 862d5ac4f54SAlexey Kardashevskiy } 863d5ac4f54SAlexey Kardashevskiy 86428e02042SDavid Gibson static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr, 865c4015bbdSAlexey Kardashevskiy target_ulong opcode, target_ulong *args) 866c4015bbdSAlexey Kardashevskiy { 867c4015bbdSAlexey Kardashevskiy target_ulong resource = args[1]; 868c4015bbdSAlexey Kardashevskiy target_ulong ret = H_P2; 869c4015bbdSAlexey Kardashevskiy 870c4015bbdSAlexey Kardashevskiy switch (resource) { 871c4015bbdSAlexey Kardashevskiy case H_SET_MODE_RESOURCE_LE: 8727d0cd464SPeter Maydell ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); 87342561bf2SAnton Blanchard break; 874d5ac4f54SAlexey Kardashevskiy case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 8757d0cd464SPeter Maydell ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 876d5ac4f54SAlexey Kardashevskiy args[2], args[3]); 877d5ac4f54SAlexey Kardashevskiy break; 87842561bf2SAnton Blanchard } 87942561bf2SAnton Blanchard 88042561bf2SAnton Blanchard return ret; 88142561bf2SAnton Blanchard } 88242561bf2SAnton Blanchard 883d77a98b0SSuraj Jitindar Singh static target_ulong h_clean_slb(PowerPCCPU *cpu, sPAPRMachineState *spapr, 884d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 885d77a98b0SSuraj Jitindar Singh { 886d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 887d77a98b0SSuraj Jitindar Singh opcode, " (H_CLEAN_SLB)"); 888d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 889d77a98b0SSuraj Jitindar Singh } 890d77a98b0SSuraj Jitindar Singh 891d77a98b0SSuraj Jitindar Singh static target_ulong h_invalidate_pid(PowerPCCPU *cpu, sPAPRMachineState *spapr, 892d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 893d77a98b0SSuraj Jitindar Singh { 894d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 895d77a98b0SSuraj Jitindar Singh opcode, " (H_INVALIDATE_PID)"); 896d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 897d77a98b0SSuraj Jitindar Singh } 898d77a98b0SSuraj Jitindar Singh 899b4db5413SSuraj Jitindar Singh static void spapr_check_setup_free_hpt(sPAPRMachineState *spapr, 900b4db5413SSuraj Jitindar Singh uint64_t patbe_old, uint64_t patbe_new) 901b4db5413SSuraj Jitindar Singh { 902b4db5413SSuraj Jitindar Singh /* 903b4db5413SSuraj Jitindar Singh * We have 4 Options: 904b4db5413SSuraj Jitindar Singh * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 905b4db5413SSuraj Jitindar Singh * HASH->RADIX : Free HPT 906b4db5413SSuraj Jitindar Singh * RADIX->HASH : Allocate HPT 907b4db5413SSuraj Jitindar Singh * NOTHING->HASH : Allocate HPT 908b4db5413SSuraj Jitindar Singh * Note: NOTHING implies the case where we said the guest could choose 909b4db5413SSuraj Jitindar Singh * later and so assumed radix and now it's called H_REG_PROC_TBL 910b4db5413SSuraj Jitindar Singh */ 911b4db5413SSuraj Jitindar Singh 912b4db5413SSuraj Jitindar Singh if ((patbe_old & PATBE1_GR) == (patbe_new & PATBE1_GR)) { 913b4db5413SSuraj Jitindar Singh /* We assume RADIX, so this catches all the "Do Nothing" cases */ 914b4db5413SSuraj Jitindar Singh } else if (!(patbe_old & PATBE1_GR)) { 915b4db5413SSuraj Jitindar Singh /* HASH->RADIX : Free HPT */ 916b4db5413SSuraj Jitindar Singh g_free(spapr->htab); 917b4db5413SSuraj Jitindar Singh spapr->htab = NULL; 918b4db5413SSuraj Jitindar Singh spapr->htab_shift = 0; 919b4db5413SSuraj Jitindar Singh close_htab_fd(spapr); 920b4db5413SSuraj Jitindar Singh } else if (!(patbe_new & PATBE1_GR)) { 921b4db5413SSuraj Jitindar Singh /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 922b4db5413SSuraj Jitindar Singh spapr_setup_hpt_and_vrma(spapr); 923b4db5413SSuraj Jitindar Singh } 924b4db5413SSuraj Jitindar Singh return; 925b4db5413SSuraj Jitindar Singh } 926b4db5413SSuraj Jitindar Singh 927b4db5413SSuraj Jitindar Singh #define FLAGS_MASK 0x01FULL 928b4db5413SSuraj Jitindar Singh #define FLAG_MODIFY 0x10 929b4db5413SSuraj Jitindar Singh #define FLAG_REGISTER 0x08 930b4db5413SSuraj Jitindar Singh #define FLAG_RADIX 0x04 931b4db5413SSuraj Jitindar Singh #define FLAG_HASH_PROC_TBL 0x02 932b4db5413SSuraj Jitindar Singh #define FLAG_GTSE 0x01 933b4db5413SSuraj Jitindar Singh 934d77a98b0SSuraj Jitindar Singh static target_ulong h_register_process_table(PowerPCCPU *cpu, 935d77a98b0SSuraj Jitindar Singh sPAPRMachineState *spapr, 936d77a98b0SSuraj Jitindar Singh target_ulong opcode, 937d77a98b0SSuraj Jitindar Singh target_ulong *args) 938d77a98b0SSuraj Jitindar Singh { 939*6de83307SSuraj Jitindar Singh CPUState *cs; 940b4db5413SSuraj Jitindar Singh target_ulong flags = args[0]; 941b4db5413SSuraj Jitindar Singh target_ulong proc_tbl = args[1]; 942b4db5413SSuraj Jitindar Singh target_ulong page_size = args[2]; 943b4db5413SSuraj Jitindar Singh target_ulong table_size = args[3]; 944b4db5413SSuraj Jitindar Singh uint64_t cproc; 945b4db5413SSuraj Jitindar Singh 946b4db5413SSuraj Jitindar Singh if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 947b4db5413SSuraj Jitindar Singh return H_PARAMETER; 948b4db5413SSuraj Jitindar Singh } 949b4db5413SSuraj Jitindar Singh if (flags & FLAG_MODIFY) { 950b4db5413SSuraj Jitindar Singh if (flags & FLAG_REGISTER) { 951b4db5413SSuraj Jitindar Singh if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 952b4db5413SSuraj Jitindar Singh if (proc_tbl & 0xfff || proc_tbl >> 60) { 953b4db5413SSuraj Jitindar Singh return H_P2; 954b4db5413SSuraj Jitindar Singh } else if (page_size) { 955b4db5413SSuraj Jitindar Singh return H_P3; 956b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 957b4db5413SSuraj Jitindar Singh return H_P4; 958b4db5413SSuraj Jitindar Singh } 959b4db5413SSuraj Jitindar Singh cproc = PATBE1_GR | proc_tbl | table_size; 960b4db5413SSuraj Jitindar Singh } else { /* Register new HPT process table */ 961b4db5413SSuraj Jitindar Singh if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 962b4db5413SSuraj Jitindar Singh /* TODO - Not Supported */ 963b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 964b4db5413SSuraj Jitindar Singh return H_PARAMETER; 965b4db5413SSuraj Jitindar Singh } else { /* Hash with SLB */ 966b4db5413SSuraj Jitindar Singh if (proc_tbl >> 38) { 967b4db5413SSuraj Jitindar Singh return H_P2; 968b4db5413SSuraj Jitindar Singh } else if (page_size & ~0x7) { 969b4db5413SSuraj Jitindar Singh return H_P3; 970b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 971b4db5413SSuraj Jitindar Singh return H_P4; 972b4db5413SSuraj Jitindar Singh } 973b4db5413SSuraj Jitindar Singh } 974b4db5413SSuraj Jitindar Singh cproc = (proc_tbl << 25) | page_size << 5 | table_size; 975b4db5413SSuraj Jitindar Singh } 976b4db5413SSuraj Jitindar Singh 977b4db5413SSuraj Jitindar Singh } else { /* Deregister current process table */ 978b4db5413SSuraj Jitindar Singh /* Set to benign value: (current GR) | 0. This allows 979b4db5413SSuraj Jitindar Singh * deregistration in KVM to succeed even if the radix bit in flags 980b4db5413SSuraj Jitindar Singh * doesn't match the radix bit in the old PATB. */ 981b4db5413SSuraj Jitindar Singh cproc = spapr->patb_entry & PATBE1_GR; 982b4db5413SSuraj Jitindar Singh } 983b4db5413SSuraj Jitindar Singh } else { /* Maintain current registration */ 984b4db5413SSuraj Jitindar Singh if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATBE1_GR)) { 985b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 986b4db5413SSuraj Jitindar Singh return H_PARAMETER; /* Existing Process Table Mismatch */ 987b4db5413SSuraj Jitindar Singh } 988b4db5413SSuraj Jitindar Singh cproc = spapr->patb_entry; 989b4db5413SSuraj Jitindar Singh } 990b4db5413SSuraj Jitindar Singh 991b4db5413SSuraj Jitindar Singh /* Check if we need to setup OR free the hpt */ 992b4db5413SSuraj Jitindar Singh spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 993b4db5413SSuraj Jitindar Singh 994b4db5413SSuraj Jitindar Singh spapr->patb_entry = cproc; /* Save new process table */ 995*6de83307SSuraj Jitindar Singh 996*6de83307SSuraj Jitindar Singh /* Update the UPRT and GTSE bits in the LPCR for all cpus */ 997*6de83307SSuraj Jitindar Singh CPU_FOREACH(cs) { 998*6de83307SSuraj Jitindar Singh set_spr(cs, SPR_LPCR, LPCR_UPRT | LPCR_GTSE, 999*6de83307SSuraj Jitindar Singh ((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT : 0) | 1000*6de83307SSuraj Jitindar Singh ((flags & FLAG_GTSE) ? LPCR_GTSE : 0)); 1001b4db5413SSuraj Jitindar Singh } 1002b4db5413SSuraj Jitindar Singh 1003b4db5413SSuraj Jitindar Singh if (kvm_enabled()) { 1004b4db5413SSuraj Jitindar Singh return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1005b4db5413SSuraj Jitindar Singh flags & FLAG_GTSE, cproc); 1006b4db5413SSuraj Jitindar Singh } 1007b4db5413SSuraj Jitindar Singh return H_SUCCESS; 1008d77a98b0SSuraj Jitindar Singh } 1009d77a98b0SSuraj Jitindar Singh 10101c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALL -1 10111c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 10121c7ad77eSNicholas Piggin 10131c7ad77eSNicholas Piggin static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 10141c7ad77eSNicholas Piggin sPAPRMachineState *spapr, 10151c7ad77eSNicholas Piggin target_ulong opcode, target_ulong *args) 10161c7ad77eSNicholas Piggin { 10171c7ad77eSNicholas Piggin target_long target = args[0]; 10181c7ad77eSNicholas Piggin CPUState *cs; 10191c7ad77eSNicholas Piggin 10201c7ad77eSNicholas Piggin if (target < 0) { 10211c7ad77eSNicholas Piggin /* Broadcast */ 10221c7ad77eSNicholas Piggin if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 10231c7ad77eSNicholas Piggin return H_PARAMETER; 10241c7ad77eSNicholas Piggin } 10251c7ad77eSNicholas Piggin 10261c7ad77eSNicholas Piggin CPU_FOREACH(cs) { 10271c7ad77eSNicholas Piggin PowerPCCPU *c = POWERPC_CPU(cs); 10281c7ad77eSNicholas Piggin 10291c7ad77eSNicholas Piggin if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 10301c7ad77eSNicholas Piggin if (c == cpu) { 10311c7ad77eSNicholas Piggin continue; 10321c7ad77eSNicholas Piggin } 10331c7ad77eSNicholas Piggin } 10341c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 10351c7ad77eSNicholas Piggin } 10361c7ad77eSNicholas Piggin return H_SUCCESS; 10371c7ad77eSNicholas Piggin 10381c7ad77eSNicholas Piggin } else { 10391c7ad77eSNicholas Piggin /* Unicast */ 10401c7ad77eSNicholas Piggin CPU_FOREACH(cs) { 10411c7ad77eSNicholas Piggin if (cpu->cpu_dt_id == target) { 10421c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 10431c7ad77eSNicholas Piggin return H_SUCCESS; 10441c7ad77eSNicholas Piggin } 10451c7ad77eSNicholas Piggin } 10461c7ad77eSNicholas Piggin return H_PARAMETER; 10471c7ad77eSNicholas Piggin } 10481c7ad77eSNicholas Piggin } 10491c7ad77eSNicholas Piggin 1050152ef803SDavid Gibson static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 105128e02042SDavid Gibson sPAPRMachineState *spapr, 10522a6593cbSAlexey Kardashevskiy target_ulong opcode, 10532a6593cbSAlexey Kardashevskiy target_ulong *args) 10542a6593cbSAlexey Kardashevskiy { 105527ac3e06SDavid Gibson target_ulong list = ppc64_phys_to_real(args[0]); 1056facdb8b6SMichael Roth target_ulong ov_table; 1057152ef803SDavid Gibson bool explicit_match = false; /* Matched the CPU's real PVR */ 1058152ef803SDavid Gibson uint32_t max_compat = cpu->max_compat; 1059152ef803SDavid Gibson uint32_t best_compat = 0; 1060152ef803SDavid Gibson int i; 1061e957f6a9SSam Bobroff sPAPROptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates; 10629fb4541fSSam Bobroff bool guest_radix; 10633794d548SAlexey Kardashevskiy 1064152ef803SDavid Gibson /* 1065152ef803SDavid Gibson * We scan the supplied table of PVRs looking for two things 1066152ef803SDavid Gibson * 1. Is our real CPU PVR in the list? 1067152ef803SDavid Gibson * 2. What's the "best" listed logical PVR 1068152ef803SDavid Gibson */ 1069152ef803SDavid Gibson for (i = 0; i < 512; ++i) { 10703794d548SAlexey Kardashevskiy uint32_t pvr, pvr_mask; 10713794d548SAlexey Kardashevskiy 107227ac3e06SDavid Gibson pvr_mask = ldl_be_phys(&address_space_memory, list); 1073152ef803SDavid Gibson pvr = ldl_be_phys(&address_space_memory, list + 4); 1074152ef803SDavid Gibson list += 8; 10753794d548SAlexey Kardashevskiy 10763794d548SAlexey Kardashevskiy if (~pvr_mask & pvr) { 1077152ef803SDavid Gibson break; /* Terminator record */ 10783794d548SAlexey Kardashevskiy } 1079152ef803SDavid Gibson 1080152ef803SDavid Gibson if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1081152ef803SDavid Gibson explicit_match = true; 1082152ef803SDavid Gibson } else { 1083152ef803SDavid Gibson if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1084152ef803SDavid Gibson best_compat = pvr; 1085152ef803SDavid Gibson } 1086152ef803SDavid Gibson } 1087152ef803SDavid Gibson } 1088152ef803SDavid Gibson 1089152ef803SDavid Gibson if ((best_compat == 0) && (!explicit_match || max_compat)) { 1090152ef803SDavid Gibson /* We couldn't find a suitable compatibility mode, and either 1091152ef803SDavid Gibson * the guest doesn't support "raw" mode for this CPU, or raw 1092152ef803SDavid Gibson * mode is disabled because a maximum compat mode is set */ 1093152ef803SDavid Gibson return H_HARDWARE; 10943794d548SAlexey Kardashevskiy } 10953794d548SAlexey Kardashevskiy 10963794d548SAlexey Kardashevskiy /* Parsing finished */ 1097152ef803SDavid Gibson trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 10983794d548SAlexey Kardashevskiy 10993794d548SAlexey Kardashevskiy /* Update CPUs */ 1100152ef803SDavid Gibson if (cpu->compat_pvr != best_compat) { 1101f6f242c7SDavid Gibson Error *local_err = NULL; 11023794d548SAlexey Kardashevskiy 1103f6f242c7SDavid Gibson ppc_set_compat_all(best_compat, &local_err); 1104f6f242c7SDavid Gibson if (local_err) { 1105f6f242c7SDavid Gibson error_report_err(local_err); 11063794d548SAlexey Kardashevskiy return H_HARDWARE; 11073794d548SAlexey Kardashevskiy } 11083794d548SAlexey Kardashevskiy } 11093794d548SAlexey Kardashevskiy 111003d196b7SBharata B Rao /* For the future use: here @ov_table points to the first option vector */ 111103d196b7SBharata B Rao ov_table = list; 111203d196b7SBharata B Rao 1113e957f6a9SSam Bobroff ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1114facdb8b6SMichael Roth ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 11159fb4541fSSam Bobroff if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 11169fb4541fSSam Bobroff error_report("guest requested hash and radix MMU, which is invalid."); 11179fb4541fSSam Bobroff exit(EXIT_FAILURE); 11189fb4541fSSam Bobroff } 11199fb4541fSSam Bobroff /* The radix/hash bit in byte 24 requires special handling: */ 11209fb4541fSSam Bobroff guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 11219fb4541fSSam Bobroff spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300); 11222a6593cbSAlexey Kardashevskiy 1123facdb8b6SMichael Roth /* NOTE: there are actually a number of ov5 bits where input from the 1124facdb8b6SMichael Roth * guest is always zero, and the platform/QEMU enables them independently 1125facdb8b6SMichael Roth * of guest input. To model these properly we'd want some sort of mask, 1126facdb8b6SMichael Roth * but since they only currently apply to memory migration as defined 1127facdb8b6SMichael Roth * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 11286787d27bSMichael Roth * to worry about this for now. 1129facdb8b6SMichael Roth */ 11306787d27bSMichael Roth ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); 11316787d27bSMichael Roth /* full range of negotiated ov5 capabilities */ 1132facdb8b6SMichael Roth spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1133facdb8b6SMichael Roth spapr_ovec_cleanup(ov5_guest); 11346787d27bSMichael Roth /* capabilities that have been added since CAS-generated guest reset. 11356787d27bSMichael Roth * if capabilities have since been removed, generate another reset 11366787d27bSMichael Roth */ 11376787d27bSMichael Roth ov5_updates = spapr_ovec_new(); 11386787d27bSMichael Roth spapr->cas_reboot = spapr_ovec_diff(ov5_updates, 11396787d27bSMichael Roth ov5_cas_old, spapr->ov5_cas); 11409fb4541fSSam Bobroff /* Now that processing is finished, set the radix/hash bit for the 11419fb4541fSSam Bobroff * guest if it requested a valid mode; otherwise terminate the boot. */ 11429fb4541fSSam Bobroff if (guest_radix) { 11439fb4541fSSam Bobroff if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 11449fb4541fSSam Bobroff error_report("Guest requested unavailable MMU mode (radix)."); 11459fb4541fSSam Bobroff exit(EXIT_FAILURE); 11469fb4541fSSam Bobroff } 11479fb4541fSSam Bobroff spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300); 11489fb4541fSSam Bobroff } else { 11499fb4541fSSam Bobroff if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 11509fb4541fSSam Bobroff && !kvmppc_has_cap_mmu_hash_v3()) { 11519fb4541fSSam Bobroff error_report("Guest requested unavailable MMU mode (hash)."); 11529fb4541fSSam Bobroff exit(EXIT_FAILURE); 11539fb4541fSSam Bobroff } 11549fb4541fSSam Bobroff } 1155e957f6a9SSam Bobroff spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest, 1156e957f6a9SSam Bobroff OV1_PPC_3_00); 11576787d27bSMichael Roth if (!spapr->cas_reboot) { 11586787d27bSMichael Roth spapr->cas_reboot = 11595b120785SDavid Gibson (spapr_h_cas_compose_response(spapr, args[1], args[2], 11606787d27bSMichael Roth ov5_updates) != 0); 11616787d27bSMichael Roth } 11626787d27bSMichael Roth spapr_ovec_cleanup(ov5_updates); 11636787d27bSMichael Roth 11646787d27bSMichael Roth if (spapr->cas_reboot) { 11652a6593cbSAlexey Kardashevskiy qemu_system_reset_request(); 11669fb4541fSSam Bobroff } else { 11679fb4541fSSam Bobroff /* If ppc_spapr_reset() did not set up a HPT but one is necessary 11689fb4541fSSam Bobroff * (because the guest isn't going to use radix) then set it up here. */ 11699fb4541fSSam Bobroff if ((spapr->patb_entry & PATBE1_GR) && !guest_radix) { 11709fb4541fSSam Bobroff /* legacy hash or new hash: */ 11719fb4541fSSam Bobroff spapr_setup_hpt_and_vrma(spapr); 11729fb4541fSSam Bobroff } 11732a6593cbSAlexey Kardashevskiy } 11742a6593cbSAlexey Kardashevskiy 11752a6593cbSAlexey Kardashevskiy return H_SUCCESS; 11762a6593cbSAlexey Kardashevskiy } 11772a6593cbSAlexey Kardashevskiy 11789f64bd8aSPaolo Bonzini static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 11799f64bd8aSPaolo Bonzini static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 11809f64bd8aSPaolo Bonzini 11819f64bd8aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 11829f64bd8aSPaolo Bonzini { 11839f64bd8aSPaolo Bonzini spapr_hcall_fn *slot; 11849f64bd8aSPaolo Bonzini 11859f64bd8aSPaolo Bonzini if (opcode <= MAX_HCALL_OPCODE) { 11869f64bd8aSPaolo Bonzini assert((opcode & 0x3) == 0); 11879f64bd8aSPaolo Bonzini 11889f64bd8aSPaolo Bonzini slot = &papr_hypercall_table[opcode / 4]; 11899f64bd8aSPaolo Bonzini } else { 11909f64bd8aSPaolo Bonzini assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 11919f64bd8aSPaolo Bonzini 11929f64bd8aSPaolo Bonzini slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 11939f64bd8aSPaolo Bonzini } 11949f64bd8aSPaolo Bonzini 11959f64bd8aSPaolo Bonzini assert(!(*slot)); 11969f64bd8aSPaolo Bonzini *slot = fn; 11979f64bd8aSPaolo Bonzini } 11989f64bd8aSPaolo Bonzini 11999f64bd8aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 12009f64bd8aSPaolo Bonzini target_ulong *args) 12019f64bd8aSPaolo Bonzini { 120228e02042SDavid Gibson sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 120328e02042SDavid Gibson 12049f64bd8aSPaolo Bonzini if ((opcode <= MAX_HCALL_OPCODE) 12059f64bd8aSPaolo Bonzini && ((opcode & 0x3) == 0)) { 12069f64bd8aSPaolo Bonzini spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 12079f64bd8aSPaolo Bonzini 12089f64bd8aSPaolo Bonzini if (fn) { 12099f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 12109f64bd8aSPaolo Bonzini } 12119f64bd8aSPaolo Bonzini } else if ((opcode >= KVMPPC_HCALL_BASE) && 12129f64bd8aSPaolo Bonzini (opcode <= KVMPPC_HCALL_MAX)) { 12139f64bd8aSPaolo Bonzini spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 12149f64bd8aSPaolo Bonzini 12159f64bd8aSPaolo Bonzini if (fn) { 12169f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 12179f64bd8aSPaolo Bonzini } 12189f64bd8aSPaolo Bonzini } 12199f64bd8aSPaolo Bonzini 1220aaf87c66SThomas Huth qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1221aaf87c66SThomas Huth opcode); 12229f64bd8aSPaolo Bonzini return H_FUNCTION; 12239f64bd8aSPaolo Bonzini } 12249f64bd8aSPaolo Bonzini 12259f64bd8aSPaolo Bonzini static void hypercall_register_types(void) 12269f64bd8aSPaolo Bonzini { 12279f64bd8aSPaolo Bonzini /* hcall-pft */ 12289f64bd8aSPaolo Bonzini spapr_register_hypercall(H_ENTER, h_enter); 12299f64bd8aSPaolo Bonzini spapr_register_hypercall(H_REMOVE, h_remove); 12309f64bd8aSPaolo Bonzini spapr_register_hypercall(H_PROTECT, h_protect); 1231fa388916SAnthony Liguori spapr_register_hypercall(H_READ, h_read); 12329f64bd8aSPaolo Bonzini 12339f64bd8aSPaolo Bonzini /* hcall-bulk */ 12349f64bd8aSPaolo Bonzini spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 12359f64bd8aSPaolo Bonzini 12369f64bd8aSPaolo Bonzini /* hcall-splpar */ 12379f64bd8aSPaolo Bonzini spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 12389f64bd8aSPaolo Bonzini spapr_register_hypercall(H_CEDE, h_cede); 12391c7ad77eSNicholas Piggin spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 12409f64bd8aSPaolo Bonzini 1241423576f7SThomas Huth /* processor register resource access h-calls */ 1242423576f7SThomas Huth spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1243af08a58fSThomas Huth spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1244e49ff266SThomas Huth spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 12453240dd9aSThomas Huth spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1246423576f7SThomas Huth spapr_register_hypercall(H_SET_MODE, h_set_mode); 1247423576f7SThomas Huth 1248d77a98b0SSuraj Jitindar Singh /* In Memory Table MMU h-calls */ 1249d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1250d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1251d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1252d77a98b0SSuraj Jitindar Singh 12539f64bd8aSPaolo Bonzini /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 12549f64bd8aSPaolo Bonzini * here between the "CI" and the "CACHE" variants, they will use whatever 12559f64bd8aSPaolo Bonzini * mapping attributes qemu is using. When using KVM, the kernel will 12569f64bd8aSPaolo Bonzini * enforce the attributes more strongly 12579f64bd8aSPaolo Bonzini */ 12589f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 12599f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 12609f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 12619f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 12629f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 12639f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 12649f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 12659f64bd8aSPaolo Bonzini 12669f64bd8aSPaolo Bonzini /* qemu/KVM-PPC specific hcalls */ 12679f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 126842561bf2SAnton Blanchard 12692a6593cbSAlexey Kardashevskiy /* ibm,client-architecture-support support */ 12702a6593cbSAlexey Kardashevskiy spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 12719f64bd8aSPaolo Bonzini } 12729f64bd8aSPaolo Bonzini 12739f64bd8aSPaolo Bonzini type_init(hypercall_register_types) 1274