10d75590dSPeter Maydell #include "qemu/osdep.h" 20c21e073SDavid Gibson #include "qemu/cutils.h" 3da34e65cSMarkus Armbruster #include "qapi/error.h" 4b3946626SVincent Palatin #include "sysemu/hw_accel.h" 554d31236SMarkus Armbruster #include "sysemu/runstate.h" 603dd024fSPaolo Bonzini #include "qemu/log.h" 7db725815SMarkus Armbruster #include "qemu/main-loop.h" 80b8fa32fSMarkus Armbruster #include "qemu/module.h" 90b0b8310SDavid Gibson #include "qemu/error-report.h" 1063c91552SPaolo Bonzini #include "exec/exec-all.h" 119f64bd8aSPaolo Bonzini #include "helper_regs.h" 120d09e41aSPaolo Bonzini #include "hw/ppc/spapr.h" 137388efafSDavid Gibson #include "hw/ppc/spapr_cpu_core.h" 14d5aea6f3SDavid Gibson #include "mmu-hash64.h" 153794d548SAlexey Kardashevskiy #include "cpu-models.h" 163794d548SAlexey Kardashevskiy #include "trace.h" 173794d548SAlexey Kardashevskiy #include "kvm_ppc.h" 180c21e073SDavid Gibson #include "hw/ppc/fdt.h" 19facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 20a165ac67SDaniel Henrique Barboza #include "hw/ppc/spapr_numa.h" 21b4db5413SSuraj Jitindar Singh #include "mmu-book3s-v3.h" 222cc0e2e8SDavid Hildenbrand #include "hw/mem/memory-device.h" 239f64bd8aSPaolo Bonzini 24962104f0SLucas Mateus Castro (alqotel) bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) 25ecbc25faSDavid Gibson { 26ecbc25faSDavid Gibson MachineState *machine = MACHINE(spapr); 27e017da37SDavid Hildenbrand DeviceMemoryState *dms = machine->device_memory; 28ecbc25faSDavid Gibson 29ecbc25faSDavid Gibson if (addr < machine->ram_size) { 30ecbc25faSDavid Gibson return true; 31ecbc25faSDavid Gibson } 32e017da37SDavid Hildenbrand if ((addr >= dms->base) 33e017da37SDavid Hildenbrand && ((addr - dms->base) < memory_region_size(&dms->mr))) { 34ecbc25faSDavid Gibson return true; 35ecbc25faSDavid Gibson } 36ecbc25faSDavid Gibson 37ecbc25faSDavid Gibson return false; 38ecbc25faSDavid Gibson } 39ecbc25faSDavid Gibson 40b55d295eSDavid Gibson /* Convert a return code from the KVM ioctl()s implementing resize HPT 41b55d295eSDavid Gibson * into a PAPR hypercall return code */ 42b55d295eSDavid Gibson static target_ulong resize_hpt_convert_rc(int ret) 43b55d295eSDavid Gibson { 44b55d295eSDavid Gibson if (ret >= 100000) { 45b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_100_SEC; 46b55d295eSDavid Gibson } else if (ret >= 10000) { 47b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_10_SEC; 48b55d295eSDavid Gibson } else if (ret >= 1000) { 49b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_1_SEC; 50b55d295eSDavid Gibson } else if (ret >= 100) { 51b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 52b55d295eSDavid Gibson } else if (ret >= 10) { 53b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_10_MSEC; 54b55d295eSDavid Gibson } else if (ret > 0) { 55b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_1_MSEC; 56b55d295eSDavid Gibson } 57b55d295eSDavid Gibson 58b55d295eSDavid Gibson switch (ret) { 59b55d295eSDavid Gibson case 0: 60b55d295eSDavid Gibson return H_SUCCESS; 61b55d295eSDavid Gibson case -EPERM: 62b55d295eSDavid Gibson return H_AUTHORITY; 63b55d295eSDavid Gibson case -EINVAL: 64b55d295eSDavid Gibson return H_PARAMETER; 65b55d295eSDavid Gibson case -ENXIO: 66b55d295eSDavid Gibson return H_CLOSED; 67b55d295eSDavid Gibson case -ENOSPC: 68b55d295eSDavid Gibson return H_PTEG_FULL; 69b55d295eSDavid Gibson case -EBUSY: 70b55d295eSDavid Gibson return H_BUSY; 71b55d295eSDavid Gibson case -ENOMEM: 72b55d295eSDavid Gibson return H_NO_MEM; 73b55d295eSDavid Gibson default: 74b55d295eSDavid Gibson return H_HARDWARE; 75b55d295eSDavid Gibson } 76b55d295eSDavid Gibson } 77b55d295eSDavid Gibson 7830f4b05bSDavid Gibson static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 79ce2918cbSDavid Gibson SpaprMachineState *spapr, 8030f4b05bSDavid Gibson target_ulong opcode, 8130f4b05bSDavid Gibson target_ulong *args) 8230f4b05bSDavid Gibson { 8330f4b05bSDavid Gibson target_ulong flags = args[0]; 840b0b8310SDavid Gibson int shift = args[1]; 85db50f280SDavid Gibson uint64_t current_ram_size; 86b55d295eSDavid Gibson int rc; 8730f4b05bSDavid Gibson 8830f4b05bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 8930f4b05bSDavid Gibson return H_AUTHORITY; 9030f4b05bSDavid Gibson } 9130f4b05bSDavid Gibson 920b0b8310SDavid Gibson if (!spapr->htab_shift) { 930b0b8310SDavid Gibson /* Radix guest, no HPT */ 940b0b8310SDavid Gibson return H_NOT_AVAILABLE; 950b0b8310SDavid Gibson } 960b0b8310SDavid Gibson 9730f4b05bSDavid Gibson trace_spapr_h_resize_hpt_prepare(flags, shift); 980b0b8310SDavid Gibson 990b0b8310SDavid Gibson if (flags != 0) { 1000b0b8310SDavid Gibson return H_PARAMETER; 1010b0b8310SDavid Gibson } 1020b0b8310SDavid Gibson 1030b0b8310SDavid Gibson if (shift && ((shift < 18) || (shift > 46))) { 1040b0b8310SDavid Gibson return H_PARAMETER; 1050b0b8310SDavid Gibson } 1060b0b8310SDavid Gibson 107db50f280SDavid Gibson current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1080b0b8310SDavid Gibson 1090b0b8310SDavid Gibson /* We only allow the guest to allocate an HPT one order above what 1100b0b8310SDavid Gibson * we'd normally give them (to stop a small guest claiming a huge 1110b0b8310SDavid Gibson * chunk of resources in the HPT */ 1120b0b8310SDavid Gibson if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 1130b0b8310SDavid Gibson return H_RESOURCE; 1140b0b8310SDavid Gibson } 1150b0b8310SDavid Gibson 116b55d295eSDavid Gibson rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 117b55d295eSDavid Gibson if (rc != -ENOSYS) { 118b55d295eSDavid Gibson return resize_hpt_convert_rc(rc); 119b55d295eSDavid Gibson } 120b55d295eSDavid Gibson 121962104f0SLucas Mateus Castro (alqotel) if (kvm_enabled()) { 12230f4b05bSDavid Gibson return H_HARDWARE; 12330f4b05bSDavid Gibson } 12430f4b05bSDavid Gibson 125962104f0SLucas Mateus Castro (alqotel) return softmmu_resize_hpt_prepare(cpu, spapr, shift); 1260b0b8310SDavid Gibson } 1270b0b8310SDavid Gibson 1281ec26c75SGreg Kurz static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 1291ec26c75SGreg Kurz { 1301ec26c75SGreg Kurz int ret; 1311ec26c75SGreg Kurz 1321ec26c75SGreg Kurz cpu_synchronize_state(cs); 1331ec26c75SGreg Kurz 1341ec26c75SGreg Kurz ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 1351ec26c75SGreg Kurz if (ret < 0) { 1361ec26c75SGreg Kurz error_report("failed to push sregs to KVM: %s", strerror(-ret)); 1371ec26c75SGreg Kurz exit(1); 1381ec26c75SGreg Kurz } 1391ec26c75SGreg Kurz } 1401ec26c75SGreg Kurz 141962104f0SLucas Mateus Castro (alqotel) void push_sregs_to_kvm_pr(SpaprMachineState *spapr) 1421ec26c75SGreg Kurz { 1431ec26c75SGreg Kurz CPUState *cs; 1441ec26c75SGreg Kurz 1451ec26c75SGreg Kurz /* 1461ec26c75SGreg Kurz * This is a hack for the benefit of KVM PR - it abuses the SDR1 1471ec26c75SGreg Kurz * slot in kvm_sregs to communicate the userspace address of the 1481ec26c75SGreg Kurz * HPT 1491ec26c75SGreg Kurz */ 1501ec26c75SGreg Kurz if (!kvm_enabled() || !spapr->htab) { 1511ec26c75SGreg Kurz return; 1521ec26c75SGreg Kurz } 1531ec26c75SGreg Kurz 1541ec26c75SGreg Kurz CPU_FOREACH(cs) { 1551ec26c75SGreg Kurz run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 1561ec26c75SGreg Kurz } 1571ec26c75SGreg Kurz } 1581ec26c75SGreg Kurz 15930f4b05bSDavid Gibson static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 160ce2918cbSDavid Gibson SpaprMachineState *spapr, 16130f4b05bSDavid Gibson target_ulong opcode, 16230f4b05bSDavid Gibson target_ulong *args) 16330f4b05bSDavid Gibson { 16430f4b05bSDavid Gibson target_ulong flags = args[0]; 16530f4b05bSDavid Gibson target_ulong shift = args[1]; 1660b0b8310SDavid Gibson int rc; 16730f4b05bSDavid Gibson 16830f4b05bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 16930f4b05bSDavid Gibson return H_AUTHORITY; 17030f4b05bSDavid Gibson } 17130f4b05bSDavid Gibson 17294789567SDaniel Henrique Barboza if (!spapr->htab_shift) { 17394789567SDaniel Henrique Barboza /* Radix guest, no HPT */ 17494789567SDaniel Henrique Barboza return H_NOT_AVAILABLE; 17594789567SDaniel Henrique Barboza } 17694789567SDaniel Henrique Barboza 17730f4b05bSDavid Gibson trace_spapr_h_resize_hpt_commit(flags, shift); 1780b0b8310SDavid Gibson 179b55d295eSDavid Gibson rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 180b55d295eSDavid Gibson if (rc != -ENOSYS) { 18194789567SDaniel Henrique Barboza rc = resize_hpt_convert_rc(rc); 18294789567SDaniel Henrique Barboza if (rc == H_SUCCESS) { 18394789567SDaniel Henrique Barboza /* Need to set the new htab_shift in the machine state */ 18494789567SDaniel Henrique Barboza spapr->htab_shift = shift; 18594789567SDaniel Henrique Barboza } 18694789567SDaniel Henrique Barboza return rc; 187b55d295eSDavid Gibson } 188b55d295eSDavid Gibson 189962104f0SLucas Mateus Castro (alqotel) if (kvm_enabled()) { 190962104f0SLucas Mateus Castro (alqotel) return H_HARDWARE; 1910b0b8310SDavid Gibson } 1920b0b8310SDavid Gibson 193962104f0SLucas Mateus Castro (alqotel) return softmmu_resize_hpt_commit(cpu, spapr, flags, shift); 1940b0b8310SDavid Gibson } 1950b0b8310SDavid Gibson 1960b0b8310SDavid Gibson 19730f4b05bSDavid Gibson 198ce2918cbSDavid Gibson static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, 199423576f7SThomas Huth target_ulong opcode, target_ulong *args) 200423576f7SThomas Huth { 201423576f7SThomas Huth cpu_synchronize_state(CPU(cpu)); 202423576f7SThomas Huth cpu->env.spr[SPR_SPRG0] = args[0]; 203423576f7SThomas Huth 204423576f7SThomas Huth return H_SUCCESS; 205423576f7SThomas Huth } 206423576f7SThomas Huth 207ce2918cbSDavid Gibson static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 2089f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 2099f64bd8aSPaolo Bonzini { 21003282a3aSLucas Mateus Castro (alqotel) if (!ppc_has_spr(cpu, SPR_DABR)) { 211af08a58fSThomas Huth return H_HARDWARE; /* DABR register not available */ 212af08a58fSThomas Huth } 213af08a58fSThomas Huth cpu_synchronize_state(CPU(cpu)); 214af08a58fSThomas Huth 21503282a3aSLucas Mateus Castro (alqotel) if (ppc_has_spr(cpu, SPR_DABRX)) { 216af08a58fSThomas Huth cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 217af08a58fSThomas Huth } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 218af08a58fSThomas Huth return H_RESERVED_DABR; 219af08a58fSThomas Huth } 220af08a58fSThomas Huth 221af08a58fSThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 222af08a58fSThomas Huth return H_SUCCESS; 2239f64bd8aSPaolo Bonzini } 2249f64bd8aSPaolo Bonzini 225ce2918cbSDavid Gibson static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 226e49ff266SThomas Huth target_ulong opcode, target_ulong *args) 227e49ff266SThomas Huth { 228e49ff266SThomas Huth target_ulong dabrx = args[1]; 229e49ff266SThomas Huth 23003282a3aSLucas Mateus Castro (alqotel) if (!ppc_has_spr(cpu, SPR_DABR) || !ppc_has_spr(cpu, SPR_DABRX)) { 231e49ff266SThomas Huth return H_HARDWARE; 232e49ff266SThomas Huth } 233e49ff266SThomas Huth 234e49ff266SThomas Huth if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 235e49ff266SThomas Huth || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 236e49ff266SThomas Huth return H_PARAMETER; 237e49ff266SThomas Huth } 238e49ff266SThomas Huth 239e49ff266SThomas Huth cpu_synchronize_state(CPU(cpu)); 240e49ff266SThomas Huth cpu->env.spr[SPR_DABRX] = dabrx; 241e49ff266SThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 242e49ff266SThomas Huth 243e49ff266SThomas Huth return H_SUCCESS; 244e49ff266SThomas Huth } 245e49ff266SThomas Huth 246ce2918cbSDavid Gibson static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, 2473240dd9aSThomas Huth target_ulong opcode, target_ulong *args) 2483240dd9aSThomas Huth { 2493240dd9aSThomas Huth target_ulong flags = args[0]; 2503240dd9aSThomas Huth hwaddr dst = args[1]; 2513240dd9aSThomas Huth hwaddr src = args[2]; 2523240dd9aSThomas Huth hwaddr len = TARGET_PAGE_SIZE; 2533240dd9aSThomas Huth uint8_t *pdst, *psrc; 2543240dd9aSThomas Huth target_long ret = H_SUCCESS; 2553240dd9aSThomas Huth 2563240dd9aSThomas Huth if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 2573240dd9aSThomas Huth | H_COPY_PAGE | H_ZERO_PAGE)) { 2583240dd9aSThomas Huth qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 2593240dd9aSThomas Huth flags); 2603240dd9aSThomas Huth return H_PARAMETER; 2613240dd9aSThomas Huth } 2623240dd9aSThomas Huth 2633240dd9aSThomas Huth /* Map-in destination */ 2643240dd9aSThomas Huth if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 2653240dd9aSThomas Huth return H_PARAMETER; 2663240dd9aSThomas Huth } 26785eb7c18SPhilippe Mathieu-Daudé pdst = cpu_physical_memory_map(dst, &len, true); 2683240dd9aSThomas Huth if (!pdst || len != TARGET_PAGE_SIZE) { 2693240dd9aSThomas Huth return H_PARAMETER; 2703240dd9aSThomas Huth } 2713240dd9aSThomas Huth 2723240dd9aSThomas Huth if (flags & H_COPY_PAGE) { 2733240dd9aSThomas Huth /* Map-in source, copy to destination, and unmap source again */ 2743240dd9aSThomas Huth if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 2753240dd9aSThomas Huth ret = H_PARAMETER; 2763240dd9aSThomas Huth goto unmap_out; 2773240dd9aSThomas Huth } 27885eb7c18SPhilippe Mathieu-Daudé psrc = cpu_physical_memory_map(src, &len, false); 2793240dd9aSThomas Huth if (!psrc || len != TARGET_PAGE_SIZE) { 2803240dd9aSThomas Huth ret = H_PARAMETER; 2813240dd9aSThomas Huth goto unmap_out; 2823240dd9aSThomas Huth } 2833240dd9aSThomas Huth memcpy(pdst, psrc, len); 2843240dd9aSThomas Huth cpu_physical_memory_unmap(psrc, len, 0, len); 2853240dd9aSThomas Huth } else if (flags & H_ZERO_PAGE) { 2863240dd9aSThomas Huth memset(pdst, 0, len); /* Just clear the destination page */ 2873240dd9aSThomas Huth } 2883240dd9aSThomas Huth 2893240dd9aSThomas Huth if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 2903240dd9aSThomas Huth kvmppc_dcbst_range(cpu, pdst, len); 2913240dd9aSThomas Huth } 2923240dd9aSThomas Huth if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 2933240dd9aSThomas Huth if (kvm_enabled()) { 2943240dd9aSThomas Huth kvmppc_icbi_range(cpu, pdst, len); 2953240dd9aSThomas Huth } else { 2963240dd9aSThomas Huth tb_flush(CPU(cpu)); 2973240dd9aSThomas Huth } 2983240dd9aSThomas Huth } 2993240dd9aSThomas Huth 3003240dd9aSThomas Huth unmap_out: 3013240dd9aSThomas Huth cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 3023240dd9aSThomas Huth return ret; 3033240dd9aSThomas Huth } 3043240dd9aSThomas Huth 3059f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 3069f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 3079f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 3089f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 3099f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 3109f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 3119f64bd8aSPaolo Bonzini 3127388efafSDavid Gibson static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) 3139f64bd8aSPaolo Bonzini { 3147388efafSDavid Gibson CPUState *cs = CPU(cpu); 3157388efafSDavid Gibson CPUPPCState *env = &cpu->env; 316ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 3179f64bd8aSPaolo Bonzini uint16_t size; 3189f64bd8aSPaolo Bonzini uint8_t tmp; 3199f64bd8aSPaolo Bonzini 3209f64bd8aSPaolo Bonzini if (vpa == 0) { 3219f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 3229f64bd8aSPaolo Bonzini return H_HARDWARE; 3239f64bd8aSPaolo Bonzini } 3249f64bd8aSPaolo Bonzini 3259f64bd8aSPaolo Bonzini if (vpa % env->dcache_line_size) { 3269f64bd8aSPaolo Bonzini return H_PARAMETER; 3279f64bd8aSPaolo Bonzini } 3289f64bd8aSPaolo Bonzini /* FIXME: bounds check the address */ 3299f64bd8aSPaolo Bonzini 33041701aa4SEdgar E. Iglesias size = lduw_be_phys(cs->as, vpa + 0x4); 3319f64bd8aSPaolo Bonzini 3329f64bd8aSPaolo Bonzini if (size < VPA_MIN_SIZE) { 3339f64bd8aSPaolo Bonzini return H_PARAMETER; 3349f64bd8aSPaolo Bonzini } 3359f64bd8aSPaolo Bonzini 3369f64bd8aSPaolo Bonzini /* VPA is not allowed to cross a page boundary */ 3379f64bd8aSPaolo Bonzini if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 3389f64bd8aSPaolo Bonzini return H_PARAMETER; 3399f64bd8aSPaolo Bonzini } 3409f64bd8aSPaolo Bonzini 3417388efafSDavid Gibson spapr_cpu->vpa_addr = vpa; 3429f64bd8aSPaolo Bonzini 3437388efafSDavid Gibson tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET); 3449f64bd8aSPaolo Bonzini tmp |= VPA_SHARED_PROC_VAL; 3457388efafSDavid Gibson stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 3469f64bd8aSPaolo Bonzini 3479f64bd8aSPaolo Bonzini return H_SUCCESS; 3489f64bd8aSPaolo Bonzini } 3499f64bd8aSPaolo Bonzini 3507388efafSDavid Gibson static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) 3519f64bd8aSPaolo Bonzini { 352ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 3537388efafSDavid Gibson 3547388efafSDavid Gibson if (spapr_cpu->slb_shadow_addr) { 3559f64bd8aSPaolo Bonzini return H_RESOURCE; 3569f64bd8aSPaolo Bonzini } 3579f64bd8aSPaolo Bonzini 3587388efafSDavid Gibson if (spapr_cpu->dtl_addr) { 3599f64bd8aSPaolo Bonzini return H_RESOURCE; 3609f64bd8aSPaolo Bonzini } 3619f64bd8aSPaolo Bonzini 3627388efafSDavid Gibson spapr_cpu->vpa_addr = 0; 3639f64bd8aSPaolo Bonzini return H_SUCCESS; 3649f64bd8aSPaolo Bonzini } 3659f64bd8aSPaolo Bonzini 3667388efafSDavid Gibson static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 3679f64bd8aSPaolo Bonzini { 368ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 3699f64bd8aSPaolo Bonzini uint32_t size; 3709f64bd8aSPaolo Bonzini 3719f64bd8aSPaolo Bonzini if (addr == 0) { 3729f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 3739f64bd8aSPaolo Bonzini return H_HARDWARE; 3749f64bd8aSPaolo Bonzini } 3759f64bd8aSPaolo Bonzini 3767388efafSDavid Gibson size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 3779f64bd8aSPaolo Bonzini if (size < 0x8) { 3789f64bd8aSPaolo Bonzini return H_PARAMETER; 3799f64bd8aSPaolo Bonzini } 3809f64bd8aSPaolo Bonzini 3819f64bd8aSPaolo Bonzini if ((addr / 4096) != ((addr + size - 1) / 4096)) { 3829f64bd8aSPaolo Bonzini return H_PARAMETER; 3839f64bd8aSPaolo Bonzini } 3849f64bd8aSPaolo Bonzini 3857388efafSDavid Gibson if (!spapr_cpu->vpa_addr) { 3869f64bd8aSPaolo Bonzini return H_RESOURCE; 3879f64bd8aSPaolo Bonzini } 3889f64bd8aSPaolo Bonzini 3897388efafSDavid Gibson spapr_cpu->slb_shadow_addr = addr; 3907388efafSDavid Gibson spapr_cpu->slb_shadow_size = size; 3919f64bd8aSPaolo Bonzini 3929f64bd8aSPaolo Bonzini return H_SUCCESS; 3939f64bd8aSPaolo Bonzini } 3949f64bd8aSPaolo Bonzini 3957388efafSDavid Gibson static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 3969f64bd8aSPaolo Bonzini { 397ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 3987388efafSDavid Gibson 3997388efafSDavid Gibson spapr_cpu->slb_shadow_addr = 0; 4007388efafSDavid Gibson spapr_cpu->slb_shadow_size = 0; 4019f64bd8aSPaolo Bonzini return H_SUCCESS; 4029f64bd8aSPaolo Bonzini } 4039f64bd8aSPaolo Bonzini 4047388efafSDavid Gibson static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) 4059f64bd8aSPaolo Bonzini { 406ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4079f64bd8aSPaolo Bonzini uint32_t size; 4089f64bd8aSPaolo Bonzini 4099f64bd8aSPaolo Bonzini if (addr == 0) { 4109f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with DTL at logical 0\n"); 4119f64bd8aSPaolo Bonzini return H_HARDWARE; 4129f64bd8aSPaolo Bonzini } 4139f64bd8aSPaolo Bonzini 4147388efafSDavid Gibson size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 4159f64bd8aSPaolo Bonzini 4169f64bd8aSPaolo Bonzini if (size < 48) { 4179f64bd8aSPaolo Bonzini return H_PARAMETER; 4189f64bd8aSPaolo Bonzini } 4199f64bd8aSPaolo Bonzini 4207388efafSDavid Gibson if (!spapr_cpu->vpa_addr) { 4219f64bd8aSPaolo Bonzini return H_RESOURCE; 4229f64bd8aSPaolo Bonzini } 4239f64bd8aSPaolo Bonzini 4247388efafSDavid Gibson spapr_cpu->dtl_addr = addr; 4257388efafSDavid Gibson spapr_cpu->dtl_size = size; 4269f64bd8aSPaolo Bonzini 4279f64bd8aSPaolo Bonzini return H_SUCCESS; 4289f64bd8aSPaolo Bonzini } 4299f64bd8aSPaolo Bonzini 4307388efafSDavid Gibson static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) 4319f64bd8aSPaolo Bonzini { 432ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4337388efafSDavid Gibson 4347388efafSDavid Gibson spapr_cpu->dtl_addr = 0; 4357388efafSDavid Gibson spapr_cpu->dtl_size = 0; 4369f64bd8aSPaolo Bonzini 4379f64bd8aSPaolo Bonzini return H_SUCCESS; 4389f64bd8aSPaolo Bonzini } 4399f64bd8aSPaolo Bonzini 440ce2918cbSDavid Gibson static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr, 4419f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 4429f64bd8aSPaolo Bonzini { 4439f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 4449f64bd8aSPaolo Bonzini target_ulong procno = args[1]; 4459f64bd8aSPaolo Bonzini target_ulong vpa = args[2]; 4469f64bd8aSPaolo Bonzini target_ulong ret = H_PARAMETER; 4470f20ba62SAlexey Kardashevskiy PowerPCCPU *tcpu; 4489f64bd8aSPaolo Bonzini 4492e886fb3SSam Bobroff tcpu = spapr_find_cpu(procno); 4509f64bd8aSPaolo Bonzini if (!tcpu) { 4519f64bd8aSPaolo Bonzini return H_PARAMETER; 4529f64bd8aSPaolo Bonzini } 4539f64bd8aSPaolo Bonzini 4549f64bd8aSPaolo Bonzini switch (flags) { 4559f64bd8aSPaolo Bonzini case FLAGS_REGISTER_VPA: 4567388efafSDavid Gibson ret = register_vpa(tcpu, vpa); 4579f64bd8aSPaolo Bonzini break; 4589f64bd8aSPaolo Bonzini 4599f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_VPA: 4607388efafSDavid Gibson ret = deregister_vpa(tcpu, vpa); 4619f64bd8aSPaolo Bonzini break; 4629f64bd8aSPaolo Bonzini 4639f64bd8aSPaolo Bonzini case FLAGS_REGISTER_SLBSHADOW: 4647388efafSDavid Gibson ret = register_slb_shadow(tcpu, vpa); 4659f64bd8aSPaolo Bonzini break; 4669f64bd8aSPaolo Bonzini 4679f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_SLBSHADOW: 4687388efafSDavid Gibson ret = deregister_slb_shadow(tcpu, vpa); 4699f64bd8aSPaolo Bonzini break; 4709f64bd8aSPaolo Bonzini 4719f64bd8aSPaolo Bonzini case FLAGS_REGISTER_DTL: 4727388efafSDavid Gibson ret = register_dtl(tcpu, vpa); 4739f64bd8aSPaolo Bonzini break; 4749f64bd8aSPaolo Bonzini 4759f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_DTL: 4767388efafSDavid Gibson ret = deregister_dtl(tcpu, vpa); 4779f64bd8aSPaolo Bonzini break; 4789f64bd8aSPaolo Bonzini } 4799f64bd8aSPaolo Bonzini 4809f64bd8aSPaolo Bonzini return ret; 4819f64bd8aSPaolo Bonzini } 4829f64bd8aSPaolo Bonzini 483ce2918cbSDavid Gibson static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, 4849f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 4859f64bd8aSPaolo Bonzini { 4869f64bd8aSPaolo Bonzini CPUPPCState *env = &cpu->env; 4879f64bd8aSPaolo Bonzini CPUState *cs = CPU(cpu); 4883a6e6224SNicholas Piggin SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4899f64bd8aSPaolo Bonzini 4909f64bd8aSPaolo Bonzini env->msr |= (1ULL << MSR_EE); 4919f64bd8aSPaolo Bonzini hreg_compute_hflags(env); 4923a6e6224SNicholas Piggin 4933a6e6224SNicholas Piggin if (spapr_cpu->prod) { 4943a6e6224SNicholas Piggin spapr_cpu->prod = false; 4953a6e6224SNicholas Piggin return H_SUCCESS; 4963a6e6224SNicholas Piggin } 4973a6e6224SNicholas Piggin 4989f64bd8aSPaolo Bonzini if (!cpu_has_work(cs)) { 499259186a7SAndreas Färber cs->halted = 1; 50027103424SAndreas Färber cs->exception_index = EXCP_HLT; 5019f64bd8aSPaolo Bonzini cs->exit_request = 1; 5029f64bd8aSPaolo Bonzini } 5033a6e6224SNicholas Piggin 5043a6e6224SNicholas Piggin return H_SUCCESS; 5053a6e6224SNicholas Piggin } 5063a6e6224SNicholas Piggin 50710741314SNicholas Piggin /* 50810741314SNicholas Piggin * Confer to self, aka join. Cede could use the same pattern as well, if 50910741314SNicholas Piggin * EXCP_HLT can be changed to ECXP_HALTED. 51010741314SNicholas Piggin */ 51110741314SNicholas Piggin static target_ulong h_confer_self(PowerPCCPU *cpu) 51210741314SNicholas Piggin { 51310741314SNicholas Piggin CPUState *cs = CPU(cpu); 51410741314SNicholas Piggin SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 51510741314SNicholas Piggin 51610741314SNicholas Piggin if (spapr_cpu->prod) { 51710741314SNicholas Piggin spapr_cpu->prod = false; 51810741314SNicholas Piggin return H_SUCCESS; 51910741314SNicholas Piggin } 52010741314SNicholas Piggin cs->halted = 1; 52110741314SNicholas Piggin cs->exception_index = EXCP_HALTED; 52210741314SNicholas Piggin cs->exit_request = 1; 52310741314SNicholas Piggin 52410741314SNicholas Piggin return H_SUCCESS; 52510741314SNicholas Piggin } 52610741314SNicholas Piggin 52710741314SNicholas Piggin static target_ulong h_join(PowerPCCPU *cpu, SpaprMachineState *spapr, 52810741314SNicholas Piggin target_ulong opcode, target_ulong *args) 52910741314SNicholas Piggin { 53010741314SNicholas Piggin CPUPPCState *env = &cpu->env; 53110741314SNicholas Piggin CPUState *cs; 53210741314SNicholas Piggin bool last_unjoined = true; 53310741314SNicholas Piggin 53410741314SNicholas Piggin if (env->msr & (1ULL << MSR_EE)) { 53510741314SNicholas Piggin return H_BAD_MODE; 53610741314SNicholas Piggin } 53710741314SNicholas Piggin 53810741314SNicholas Piggin /* 53910741314SNicholas Piggin * Must not join the last CPU running. Interestingly, no such restriction 54010741314SNicholas Piggin * for H_CONFER-to-self, but that is probably not intended to be used 54110741314SNicholas Piggin * when H_JOIN is available. 54210741314SNicholas Piggin */ 54310741314SNicholas Piggin CPU_FOREACH(cs) { 54410741314SNicholas Piggin PowerPCCPU *c = POWERPC_CPU(cs); 54510741314SNicholas Piggin CPUPPCState *e = &c->env; 54610741314SNicholas Piggin if (c == cpu) { 54710741314SNicholas Piggin continue; 54810741314SNicholas Piggin } 54910741314SNicholas Piggin 55010741314SNicholas Piggin /* Don't have a way to indicate joined, so use halted && MSR[EE]=0 */ 55110741314SNicholas Piggin if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { 55210741314SNicholas Piggin last_unjoined = false; 55310741314SNicholas Piggin break; 55410741314SNicholas Piggin } 55510741314SNicholas Piggin } 55610741314SNicholas Piggin if (last_unjoined) { 55710741314SNicholas Piggin return H_CONTINUE; 55810741314SNicholas Piggin } 55910741314SNicholas Piggin 56010741314SNicholas Piggin return h_confer_self(cpu); 56110741314SNicholas Piggin } 56210741314SNicholas Piggin 563e8ce0e40SNicholas Piggin static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr, 564e8ce0e40SNicholas Piggin target_ulong opcode, target_ulong *args) 565e8ce0e40SNicholas Piggin { 566e8ce0e40SNicholas Piggin target_long target = args[0]; 567e8ce0e40SNicholas Piggin uint32_t dispatch = args[1]; 568e8ce0e40SNicholas Piggin CPUState *cs = CPU(cpu); 569e8ce0e40SNicholas Piggin SpaprCpuState *spapr_cpu; 570e8ce0e40SNicholas Piggin 571e8ce0e40SNicholas Piggin /* 572e8ce0e40SNicholas Piggin * -1 means confer to all other CPUs without dispatch counter check, 573e8ce0e40SNicholas Piggin * otherwise it's a targeted confer. 574e8ce0e40SNicholas Piggin */ 575e8ce0e40SNicholas Piggin if (target != -1) { 576e8ce0e40SNicholas Piggin PowerPCCPU *target_cpu = spapr_find_cpu(target); 577e8ce0e40SNicholas Piggin uint32_t target_dispatch; 578e8ce0e40SNicholas Piggin 579e8ce0e40SNicholas Piggin if (!target_cpu) { 580e8ce0e40SNicholas Piggin return H_PARAMETER; 581e8ce0e40SNicholas Piggin } 582e8ce0e40SNicholas Piggin 583e8ce0e40SNicholas Piggin /* 584e8ce0e40SNicholas Piggin * target == self is a special case, we wait until prodded, without 585e8ce0e40SNicholas Piggin * dispatch counter check. 586e8ce0e40SNicholas Piggin */ 587e8ce0e40SNicholas Piggin if (cpu == target_cpu) { 58810741314SNicholas Piggin return h_confer_self(cpu); 589e8ce0e40SNicholas Piggin } 590e8ce0e40SNicholas Piggin 59110741314SNicholas Piggin spapr_cpu = spapr_cpu_state(target_cpu); 592e8ce0e40SNicholas Piggin if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) { 593e8ce0e40SNicholas Piggin return H_SUCCESS; 594e8ce0e40SNicholas Piggin } 595e8ce0e40SNicholas Piggin 596e8ce0e40SNicholas Piggin target_dispatch = ldl_be_phys(cs->as, 597e8ce0e40SNicholas Piggin spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 598e8ce0e40SNicholas Piggin if (target_dispatch != dispatch) { 599e8ce0e40SNicholas Piggin return H_SUCCESS; 600e8ce0e40SNicholas Piggin } 601e8ce0e40SNicholas Piggin 602e8ce0e40SNicholas Piggin /* 603e8ce0e40SNicholas Piggin * The targeted confer does not do anything special beyond yielding 604e8ce0e40SNicholas Piggin * the current vCPU, but even this should be better than nothing. 605e8ce0e40SNicholas Piggin * At least for single-threaded tcg, it gives the target a chance to 606e8ce0e40SNicholas Piggin * run before we run again. Multi-threaded tcg does not really do 607e8ce0e40SNicholas Piggin * anything with EXCP_YIELD yet. 608e8ce0e40SNicholas Piggin */ 609e8ce0e40SNicholas Piggin } 610e8ce0e40SNicholas Piggin 611e8ce0e40SNicholas Piggin cs->exception_index = EXCP_YIELD; 612e8ce0e40SNicholas Piggin cs->exit_request = 1; 613e8ce0e40SNicholas Piggin cpu_loop_exit(cs); 614e8ce0e40SNicholas Piggin 615e8ce0e40SNicholas Piggin return H_SUCCESS; 616e8ce0e40SNicholas Piggin } 617e8ce0e40SNicholas Piggin 6183a6e6224SNicholas Piggin static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr, 6193a6e6224SNicholas Piggin target_ulong opcode, target_ulong *args) 6203a6e6224SNicholas Piggin { 6213a6e6224SNicholas Piggin target_long target = args[0]; 6223a6e6224SNicholas Piggin PowerPCCPU *tcpu; 6233a6e6224SNicholas Piggin CPUState *cs; 6243a6e6224SNicholas Piggin SpaprCpuState *spapr_cpu; 6253a6e6224SNicholas Piggin 6263a6e6224SNicholas Piggin tcpu = spapr_find_cpu(target); 6273a6e6224SNicholas Piggin cs = CPU(tcpu); 6283a6e6224SNicholas Piggin if (!cs) { 6293a6e6224SNicholas Piggin return H_PARAMETER; 6303a6e6224SNicholas Piggin } 6313a6e6224SNicholas Piggin 6323a6e6224SNicholas Piggin spapr_cpu = spapr_cpu_state(tcpu); 6333a6e6224SNicholas Piggin spapr_cpu->prod = true; 6343a6e6224SNicholas Piggin cs->halted = 0; 6353a6e6224SNicholas Piggin qemu_cpu_kick(cs); 6363a6e6224SNicholas Piggin 6379f64bd8aSPaolo Bonzini return H_SUCCESS; 6389f64bd8aSPaolo Bonzini } 6399f64bd8aSPaolo Bonzini 640ce2918cbSDavid Gibson static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, 6419f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 6429f64bd8aSPaolo Bonzini { 6439f64bd8aSPaolo Bonzini target_ulong rtas_r3 = args[0]; 6444fe822e0SAlexey Kardashevskiy uint32_t token = rtas_ld(rtas_r3, 0); 6454fe822e0SAlexey Kardashevskiy uint32_t nargs = rtas_ld(rtas_r3, 1); 6464fe822e0SAlexey Kardashevskiy uint32_t nret = rtas_ld(rtas_r3, 2); 6479f64bd8aSPaolo Bonzini 648210b580bSAnthony Liguori return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 6499f64bd8aSPaolo Bonzini nret, rtas_r3 + 12 + 4*nargs); 6509f64bd8aSPaolo Bonzini } 6519f64bd8aSPaolo Bonzini 652ce2918cbSDavid Gibson static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr, 6539f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 6549f64bd8aSPaolo Bonzini { 655fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 6569f64bd8aSPaolo Bonzini target_ulong size = args[0]; 6579f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 6589f64bd8aSPaolo Bonzini 6599f64bd8aSPaolo Bonzini switch (size) { 6609f64bd8aSPaolo Bonzini case 1: 6612c17449bSEdgar E. Iglesias args[0] = ldub_phys(cs->as, addr); 6629f64bd8aSPaolo Bonzini return H_SUCCESS; 6639f64bd8aSPaolo Bonzini case 2: 66441701aa4SEdgar E. Iglesias args[0] = lduw_phys(cs->as, addr); 6659f64bd8aSPaolo Bonzini return H_SUCCESS; 6669f64bd8aSPaolo Bonzini case 4: 667fdfba1a2SEdgar E. Iglesias args[0] = ldl_phys(cs->as, addr); 6689f64bd8aSPaolo Bonzini return H_SUCCESS; 6699f64bd8aSPaolo Bonzini case 8: 6702c17449bSEdgar E. Iglesias args[0] = ldq_phys(cs->as, addr); 6719f64bd8aSPaolo Bonzini return H_SUCCESS; 6729f64bd8aSPaolo Bonzini } 6739f64bd8aSPaolo Bonzini return H_PARAMETER; 6749f64bd8aSPaolo Bonzini } 6759f64bd8aSPaolo Bonzini 676ce2918cbSDavid Gibson static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr, 6779f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 6789f64bd8aSPaolo Bonzini { 679f606604fSEdgar E. Iglesias CPUState *cs = CPU(cpu); 680f606604fSEdgar E. Iglesias 6819f64bd8aSPaolo Bonzini target_ulong size = args[0]; 6829f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 6839f64bd8aSPaolo Bonzini target_ulong val = args[2]; 6849f64bd8aSPaolo Bonzini 6859f64bd8aSPaolo Bonzini switch (size) { 6869f64bd8aSPaolo Bonzini case 1: 687db3be60dSEdgar E. Iglesias stb_phys(cs->as, addr, val); 6889f64bd8aSPaolo Bonzini return H_SUCCESS; 6899f64bd8aSPaolo Bonzini case 2: 6905ce5944dSEdgar E. Iglesias stw_phys(cs->as, addr, val); 6919f64bd8aSPaolo Bonzini return H_SUCCESS; 6929f64bd8aSPaolo Bonzini case 4: 693ab1da857SEdgar E. Iglesias stl_phys(cs->as, addr, val); 6949f64bd8aSPaolo Bonzini return H_SUCCESS; 6959f64bd8aSPaolo Bonzini case 8: 696f606604fSEdgar E. Iglesias stq_phys(cs->as, addr, val); 6979f64bd8aSPaolo Bonzini return H_SUCCESS; 6989f64bd8aSPaolo Bonzini } 6999f64bd8aSPaolo Bonzini return H_PARAMETER; 7009f64bd8aSPaolo Bonzini } 7019f64bd8aSPaolo Bonzini 702ce2918cbSDavid Gibson static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr, 7039f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 7049f64bd8aSPaolo Bonzini { 705fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 706fdfba1a2SEdgar E. Iglesias 7079f64bd8aSPaolo Bonzini target_ulong dst = args[0]; /* Destination address */ 7089f64bd8aSPaolo Bonzini target_ulong src = args[1]; /* Source address */ 7099f64bd8aSPaolo Bonzini target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 7109f64bd8aSPaolo Bonzini target_ulong count = args[3]; /* Element count */ 7119f64bd8aSPaolo Bonzini target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 7129f64bd8aSPaolo Bonzini uint64_t tmp; 7139f64bd8aSPaolo Bonzini unsigned int mask = (1 << esize) - 1; 7149f64bd8aSPaolo Bonzini int step = 1 << esize; 7159f64bd8aSPaolo Bonzini 7169f64bd8aSPaolo Bonzini if (count > 0x80000000) { 7179f64bd8aSPaolo Bonzini return H_PARAMETER; 7189f64bd8aSPaolo Bonzini } 7199f64bd8aSPaolo Bonzini 7209f64bd8aSPaolo Bonzini if ((dst & mask) || (src & mask) || (op > 1)) { 7219f64bd8aSPaolo Bonzini return H_PARAMETER; 7229f64bd8aSPaolo Bonzini } 7239f64bd8aSPaolo Bonzini 7249f64bd8aSPaolo Bonzini if (dst >= src && dst < (src + (count << esize))) { 7259f64bd8aSPaolo Bonzini dst = dst + ((count - 1) << esize); 7269f64bd8aSPaolo Bonzini src = src + ((count - 1) << esize); 7279f64bd8aSPaolo Bonzini step = -step; 7289f64bd8aSPaolo Bonzini } 7299f64bd8aSPaolo Bonzini 7309f64bd8aSPaolo Bonzini while (count--) { 7319f64bd8aSPaolo Bonzini switch (esize) { 7329f64bd8aSPaolo Bonzini case 0: 7332c17449bSEdgar E. Iglesias tmp = ldub_phys(cs->as, src); 7349f64bd8aSPaolo Bonzini break; 7359f64bd8aSPaolo Bonzini case 1: 73641701aa4SEdgar E. Iglesias tmp = lduw_phys(cs->as, src); 7379f64bd8aSPaolo Bonzini break; 7389f64bd8aSPaolo Bonzini case 2: 739fdfba1a2SEdgar E. Iglesias tmp = ldl_phys(cs->as, src); 7409f64bd8aSPaolo Bonzini break; 7419f64bd8aSPaolo Bonzini case 3: 7422c17449bSEdgar E. Iglesias tmp = ldq_phys(cs->as, src); 7439f64bd8aSPaolo Bonzini break; 7449f64bd8aSPaolo Bonzini default: 7459f64bd8aSPaolo Bonzini return H_PARAMETER; 7469f64bd8aSPaolo Bonzini } 7479f64bd8aSPaolo Bonzini if (op == 1) { 7489f64bd8aSPaolo Bonzini tmp = ~tmp; 7499f64bd8aSPaolo Bonzini } 7509f64bd8aSPaolo Bonzini switch (esize) { 7519f64bd8aSPaolo Bonzini case 0: 752db3be60dSEdgar E. Iglesias stb_phys(cs->as, dst, tmp); 7539f64bd8aSPaolo Bonzini break; 7549f64bd8aSPaolo Bonzini case 1: 7555ce5944dSEdgar E. Iglesias stw_phys(cs->as, dst, tmp); 7569f64bd8aSPaolo Bonzini break; 7579f64bd8aSPaolo Bonzini case 2: 758ab1da857SEdgar E. Iglesias stl_phys(cs->as, dst, tmp); 7599f64bd8aSPaolo Bonzini break; 7609f64bd8aSPaolo Bonzini case 3: 761f606604fSEdgar E. Iglesias stq_phys(cs->as, dst, tmp); 7629f64bd8aSPaolo Bonzini break; 7639f64bd8aSPaolo Bonzini } 7649f64bd8aSPaolo Bonzini dst = dst + step; 7659f64bd8aSPaolo Bonzini src = src + step; 7669f64bd8aSPaolo Bonzini } 7679f64bd8aSPaolo Bonzini 7689f64bd8aSPaolo Bonzini return H_SUCCESS; 7699f64bd8aSPaolo Bonzini } 7709f64bd8aSPaolo Bonzini 771ce2918cbSDavid Gibson static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr, 7729f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 7739f64bd8aSPaolo Bonzini { 7749f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 7759f64bd8aSPaolo Bonzini return H_SUCCESS; 7769f64bd8aSPaolo Bonzini } 7779f64bd8aSPaolo Bonzini 778ce2918cbSDavid Gibson static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, 7799f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 7809f64bd8aSPaolo Bonzini { 7819f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 7829f64bd8aSPaolo Bonzini return H_SUCCESS; 7839f64bd8aSPaolo Bonzini } 7849f64bd8aSPaolo Bonzini 7857d0cd464SPeter Maydell static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 786c4c81d7dSGreg Kurz SpaprMachineState *spapr, 787c4015bbdSAlexey Kardashevskiy target_ulong mflags, 788c4015bbdSAlexey Kardashevskiy target_ulong value1, 789c4015bbdSAlexey Kardashevskiy target_ulong value2) 79042561bf2SAnton Blanchard { 79142561bf2SAnton Blanchard if (value1) { 792c4015bbdSAlexey Kardashevskiy return H_P3; 79342561bf2SAnton Blanchard } 79442561bf2SAnton Blanchard if (value2) { 795c4015bbdSAlexey Kardashevskiy return H_P4; 79642561bf2SAnton Blanchard } 797c4015bbdSAlexey Kardashevskiy 79842561bf2SAnton Blanchard switch (mflags) { 79942561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_BIG: 80000fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(0, LPCR_ILE); 801c4c81d7dSGreg Kurz spapr_pci_switch_vga(spapr, true); 802c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 80342561bf2SAnton Blanchard 80442561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_LITTLE: 80500fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); 806c4c81d7dSGreg Kurz spapr_pci_switch_vga(spapr, false); 807c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 808c4015bbdSAlexey Kardashevskiy } 809c4015bbdSAlexey Kardashevskiy 810c4015bbdSAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 811c4015bbdSAlexey Kardashevskiy } 812c4015bbdSAlexey Kardashevskiy 8137d0cd464SPeter Maydell static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 814d5ac4f54SAlexey Kardashevskiy target_ulong mflags, 815d5ac4f54SAlexey Kardashevskiy target_ulong value1, 816d5ac4f54SAlexey Kardashevskiy target_ulong value2) 817d5ac4f54SAlexey Kardashevskiy { 818d5ac4f54SAlexey Kardashevskiy PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 819d5ac4f54SAlexey Kardashevskiy 820d5ac4f54SAlexey Kardashevskiy if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 821d5ac4f54SAlexey Kardashevskiy return H_P2; 822d5ac4f54SAlexey Kardashevskiy } 823d5ac4f54SAlexey Kardashevskiy if (value1) { 824d5ac4f54SAlexey Kardashevskiy return H_P3; 825d5ac4f54SAlexey Kardashevskiy } 826d5ac4f54SAlexey Kardashevskiy if (value2) { 827d5ac4f54SAlexey Kardashevskiy return H_P4; 828d5ac4f54SAlexey Kardashevskiy } 829d5ac4f54SAlexey Kardashevskiy 8308b7e6b07SNicholas Piggin if (mflags == 1) { 831526cdce7SNicholas Piggin /* AIL=1 is reserved in POWER8/POWER9/POWER10 */ 832526cdce7SNicholas Piggin return H_UNSUPPORTED_FLAG; 833526cdce7SNicholas Piggin } 834526cdce7SNicholas Piggin 835526cdce7SNicholas Piggin if (mflags == 2 && (pcc->insns_flags2 & PPC2_ISA310)) { 836526cdce7SNicholas Piggin /* AIL=2 is reserved in POWER10 (ISA v3.1) */ 837d5ac4f54SAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 838d5ac4f54SAlexey Kardashevskiy } 839d5ac4f54SAlexey Kardashevskiy 84000fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); 841d5ac4f54SAlexey Kardashevskiy 842d5ac4f54SAlexey Kardashevskiy return H_SUCCESS; 843d5ac4f54SAlexey Kardashevskiy } 844d5ac4f54SAlexey Kardashevskiy 845ce2918cbSDavid Gibson static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, 846c4015bbdSAlexey Kardashevskiy target_ulong opcode, target_ulong *args) 847c4015bbdSAlexey Kardashevskiy { 848c4015bbdSAlexey Kardashevskiy target_ulong resource = args[1]; 849c4015bbdSAlexey Kardashevskiy target_ulong ret = H_P2; 850c4015bbdSAlexey Kardashevskiy 851c4015bbdSAlexey Kardashevskiy switch (resource) { 852c4015bbdSAlexey Kardashevskiy case H_SET_MODE_RESOURCE_LE: 853c4c81d7dSGreg Kurz ret = h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[3]); 85442561bf2SAnton Blanchard break; 855d5ac4f54SAlexey Kardashevskiy case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 8567d0cd464SPeter Maydell ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 857d5ac4f54SAlexey Kardashevskiy args[2], args[3]); 858d5ac4f54SAlexey Kardashevskiy break; 85942561bf2SAnton Blanchard } 86042561bf2SAnton Blanchard 86142561bf2SAnton Blanchard return ret; 86242561bf2SAnton Blanchard } 86342561bf2SAnton Blanchard 864ce2918cbSDavid Gibson static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, 865d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 866d77a98b0SSuraj Jitindar Singh { 867d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 868d77a98b0SSuraj Jitindar Singh opcode, " (H_CLEAN_SLB)"); 869d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 870d77a98b0SSuraj Jitindar Singh } 871d77a98b0SSuraj Jitindar Singh 872ce2918cbSDavid Gibson static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr, 873d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 874d77a98b0SSuraj Jitindar Singh { 875d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 876d77a98b0SSuraj Jitindar Singh opcode, " (H_INVALIDATE_PID)"); 877d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 878d77a98b0SSuraj Jitindar Singh } 879d77a98b0SSuraj Jitindar Singh 880ce2918cbSDavid Gibson static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, 881b4db5413SSuraj Jitindar Singh uint64_t patbe_old, uint64_t patbe_new) 882b4db5413SSuraj Jitindar Singh { 883b4db5413SSuraj Jitindar Singh /* 884b4db5413SSuraj Jitindar Singh * We have 4 Options: 885b4db5413SSuraj Jitindar Singh * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 886b4db5413SSuraj Jitindar Singh * HASH->RADIX : Free HPT 887b4db5413SSuraj Jitindar Singh * RADIX->HASH : Allocate HPT 888b4db5413SSuraj Jitindar Singh * NOTHING->HASH : Allocate HPT 889b4db5413SSuraj Jitindar Singh * Note: NOTHING implies the case where we said the guest could choose 890b4db5413SSuraj Jitindar Singh * later and so assumed radix and now it's called H_REG_PROC_TBL 891b4db5413SSuraj Jitindar Singh */ 892b4db5413SSuraj Jitindar Singh 89379825f4dSBenjamin Herrenschmidt if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) { 894b4db5413SSuraj Jitindar Singh /* We assume RADIX, so this catches all the "Do Nothing" cases */ 89579825f4dSBenjamin Herrenschmidt } else if (!(patbe_old & PATE1_GR)) { 896b4db5413SSuraj Jitindar Singh /* HASH->RADIX : Free HPT */ 89706ec79e8SBharata B Rao spapr_free_hpt(spapr); 89879825f4dSBenjamin Herrenschmidt } else if (!(patbe_new & PATE1_GR)) { 899b4db5413SSuraj Jitindar Singh /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 9008897ea5aSDavid Gibson spapr_setup_hpt(spapr); 901b4db5413SSuraj Jitindar Singh } 902b4db5413SSuraj Jitindar Singh return; 903b4db5413SSuraj Jitindar Singh } 904b4db5413SSuraj Jitindar Singh 905b4db5413SSuraj Jitindar Singh #define FLAGS_MASK 0x01FULL 906b4db5413SSuraj Jitindar Singh #define FLAG_MODIFY 0x10 907b4db5413SSuraj Jitindar Singh #define FLAG_REGISTER 0x08 908b4db5413SSuraj Jitindar Singh #define FLAG_RADIX 0x04 909b4db5413SSuraj Jitindar Singh #define FLAG_HASH_PROC_TBL 0x02 910b4db5413SSuraj Jitindar Singh #define FLAG_GTSE 0x01 911b4db5413SSuraj Jitindar Singh 912d77a98b0SSuraj Jitindar Singh static target_ulong h_register_process_table(PowerPCCPU *cpu, 913ce2918cbSDavid Gibson SpaprMachineState *spapr, 914d77a98b0SSuraj Jitindar Singh target_ulong opcode, 915d77a98b0SSuraj Jitindar Singh target_ulong *args) 916d77a98b0SSuraj Jitindar Singh { 917b4db5413SSuraj Jitindar Singh target_ulong flags = args[0]; 918b4db5413SSuraj Jitindar Singh target_ulong proc_tbl = args[1]; 919b4db5413SSuraj Jitindar Singh target_ulong page_size = args[2]; 920b4db5413SSuraj Jitindar Singh target_ulong table_size = args[3]; 921176dcceeSSuraj Jitindar Singh target_ulong update_lpcr = 0; 922b4db5413SSuraj Jitindar Singh uint64_t cproc; 923b4db5413SSuraj Jitindar Singh 924b4db5413SSuraj Jitindar Singh if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 925b4db5413SSuraj Jitindar Singh return H_PARAMETER; 926b4db5413SSuraj Jitindar Singh } 927b4db5413SSuraj Jitindar Singh if (flags & FLAG_MODIFY) { 928b4db5413SSuraj Jitindar Singh if (flags & FLAG_REGISTER) { 929b4db5413SSuraj Jitindar Singh if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 930b4db5413SSuraj Jitindar Singh if (proc_tbl & 0xfff || proc_tbl >> 60) { 931b4db5413SSuraj Jitindar Singh return H_P2; 932b4db5413SSuraj Jitindar Singh } else if (page_size) { 933b4db5413SSuraj Jitindar Singh return H_P3; 934b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 935b4db5413SSuraj Jitindar Singh return H_P4; 936b4db5413SSuraj Jitindar Singh } 93779825f4dSBenjamin Herrenschmidt cproc = PATE1_GR | proc_tbl | table_size; 938b4db5413SSuraj Jitindar Singh } else { /* Register new HPT process table */ 939b4db5413SSuraj Jitindar Singh if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 940b4db5413SSuraj Jitindar Singh /* TODO - Not Supported */ 941b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 942b4db5413SSuraj Jitindar Singh return H_PARAMETER; 943b4db5413SSuraj Jitindar Singh } else { /* Hash with SLB */ 944b4db5413SSuraj Jitindar Singh if (proc_tbl >> 38) { 945b4db5413SSuraj Jitindar Singh return H_P2; 946b4db5413SSuraj Jitindar Singh } else if (page_size & ~0x7) { 947b4db5413SSuraj Jitindar Singh return H_P3; 948b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 949b4db5413SSuraj Jitindar Singh return H_P4; 950b4db5413SSuraj Jitindar Singh } 951b4db5413SSuraj Jitindar Singh } 952b4db5413SSuraj Jitindar Singh cproc = (proc_tbl << 25) | page_size << 5 | table_size; 953b4db5413SSuraj Jitindar Singh } 954b4db5413SSuraj Jitindar Singh 955b4db5413SSuraj Jitindar Singh } else { /* Deregister current process table */ 95679825f4dSBenjamin Herrenschmidt /* 95779825f4dSBenjamin Herrenschmidt * Set to benign value: (current GR) | 0. This allows 95879825f4dSBenjamin Herrenschmidt * deregistration in KVM to succeed even if the radix bit 95979825f4dSBenjamin Herrenschmidt * in flags doesn't match the radix bit in the old PATE. 96079825f4dSBenjamin Herrenschmidt */ 96179825f4dSBenjamin Herrenschmidt cproc = spapr->patb_entry & PATE1_GR; 962b4db5413SSuraj Jitindar Singh } 963b4db5413SSuraj Jitindar Singh } else { /* Maintain current registration */ 96479825f4dSBenjamin Herrenschmidt if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) { 965b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 966b4db5413SSuraj Jitindar Singh return H_PARAMETER; /* Existing Process Table Mismatch */ 967b4db5413SSuraj Jitindar Singh } 968b4db5413SSuraj Jitindar Singh cproc = spapr->patb_entry; 969b4db5413SSuraj Jitindar Singh } 970b4db5413SSuraj Jitindar Singh 971b4db5413SSuraj Jitindar Singh /* Check if we need to setup OR free the hpt */ 972b4db5413SSuraj Jitindar Singh spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 973b4db5413SSuraj Jitindar Singh 974b4db5413SSuraj Jitindar Singh spapr->patb_entry = cproc; /* Save new process table */ 9756de83307SSuraj Jitindar Singh 97600fd075eSBenjamin Herrenschmidt /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ 977176dcceeSSuraj Jitindar Singh if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */ 978176dcceeSSuraj Jitindar Singh update_lpcr |= (LPCR_UPRT | LPCR_HR); 979176dcceeSSuraj Jitindar Singh else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ 980176dcceeSSuraj Jitindar Singh update_lpcr |= LPCR_UPRT; 981176dcceeSSuraj Jitindar Singh if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ 98249e9fdd7SDavid Gibson update_lpcr |= LPCR_GTSE; 98349e9fdd7SDavid Gibson 984176dcceeSSuraj Jitindar Singh spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); 985b4db5413SSuraj Jitindar Singh 986b4db5413SSuraj Jitindar Singh if (kvm_enabled()) { 987b4db5413SSuraj Jitindar Singh return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 988b4db5413SSuraj Jitindar Singh flags & FLAG_GTSE, cproc); 989b4db5413SSuraj Jitindar Singh } 990b4db5413SSuraj Jitindar Singh return H_SUCCESS; 991d77a98b0SSuraj Jitindar Singh } 992d77a98b0SSuraj Jitindar Singh 9931c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALL -1 9941c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 9951c7ad77eSNicholas Piggin 9961c7ad77eSNicholas Piggin static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 997ce2918cbSDavid Gibson SpaprMachineState *spapr, 9981c7ad77eSNicholas Piggin target_ulong opcode, target_ulong *args) 9991c7ad77eSNicholas Piggin { 10001c7ad77eSNicholas Piggin target_long target = args[0]; 10011c7ad77eSNicholas Piggin CPUState *cs; 10021c7ad77eSNicholas Piggin 10031c7ad77eSNicholas Piggin if (target < 0) { 10041c7ad77eSNicholas Piggin /* Broadcast */ 10051c7ad77eSNicholas Piggin if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 10061c7ad77eSNicholas Piggin return H_PARAMETER; 10071c7ad77eSNicholas Piggin } 10081c7ad77eSNicholas Piggin 10091c7ad77eSNicholas Piggin CPU_FOREACH(cs) { 10101c7ad77eSNicholas Piggin PowerPCCPU *c = POWERPC_CPU(cs); 10111c7ad77eSNicholas Piggin 10121c7ad77eSNicholas Piggin if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 10131c7ad77eSNicholas Piggin if (c == cpu) { 10141c7ad77eSNicholas Piggin continue; 10151c7ad77eSNicholas Piggin } 10161c7ad77eSNicholas Piggin } 10171c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 10181c7ad77eSNicholas Piggin } 10191c7ad77eSNicholas Piggin return H_SUCCESS; 10201c7ad77eSNicholas Piggin 10211c7ad77eSNicholas Piggin } else { 10221c7ad77eSNicholas Piggin /* Unicast */ 10232e886fb3SSam Bobroff cs = CPU(spapr_find_cpu(target)); 1024f57467e3SSam Bobroff if (cs) { 10251c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 10261c7ad77eSNicholas Piggin return H_SUCCESS; 10271c7ad77eSNicholas Piggin } 10281c7ad77eSNicholas Piggin return H_PARAMETER; 10291c7ad77eSNicholas Piggin } 10301c7ad77eSNicholas Piggin } 10311c7ad77eSNicholas Piggin 1032121afbe4SGreg Kurz /* Returns either a logical PVR or zero if none was found */ 1033121afbe4SGreg Kurz static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32_t max_compat, 1034121afbe4SGreg Kurz target_ulong *addr, bool *raw_mode_supported) 10352a6593cbSAlexey Kardashevskiy { 1036152ef803SDavid Gibson bool explicit_match = false; /* Matched the CPU's real PVR */ 1037152ef803SDavid Gibson uint32_t best_compat = 0; 1038152ef803SDavid Gibson int i; 10393794d548SAlexey Kardashevskiy 1040152ef803SDavid Gibson /* 1041152ef803SDavid Gibson * We scan the supplied table of PVRs looking for two things 1042152ef803SDavid Gibson * 1. Is our real CPU PVR in the list? 1043152ef803SDavid Gibson * 2. What's the "best" listed logical PVR 1044152ef803SDavid Gibson */ 1045152ef803SDavid Gibson for (i = 0; i < 512; ++i) { 10463794d548SAlexey Kardashevskiy uint32_t pvr, pvr_mask; 10473794d548SAlexey Kardashevskiy 104880c33d34SDavid Gibson pvr_mask = ldl_be_phys(&address_space_memory, *addr); 104980c33d34SDavid Gibson pvr = ldl_be_phys(&address_space_memory, *addr + 4); 105080c33d34SDavid Gibson *addr += 8; 10513794d548SAlexey Kardashevskiy 10523794d548SAlexey Kardashevskiy if (~pvr_mask & pvr) { 1053152ef803SDavid Gibson break; /* Terminator record */ 10543794d548SAlexey Kardashevskiy } 1055152ef803SDavid Gibson 1056152ef803SDavid Gibson if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1057152ef803SDavid Gibson explicit_match = true; 1058152ef803SDavid Gibson } else { 1059152ef803SDavid Gibson if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1060152ef803SDavid Gibson best_compat = pvr; 1061152ef803SDavid Gibson } 1062152ef803SDavid Gibson } 1063152ef803SDavid Gibson } 1064152ef803SDavid Gibson 1065cc7b35b1SGreg Kurz *raw_mode_supported = explicit_match; 1066cc7b35b1SGreg Kurz 10673794d548SAlexey Kardashevskiy /* Parsing finished */ 1068152ef803SDavid Gibson trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 10693794d548SAlexey Kardashevskiy 107080c33d34SDavid Gibson return best_compat; 107180c33d34SDavid Gibson } 107280c33d34SDavid Gibson 1073eb72b639SDaniel Henrique Barboza static 107491067db1SAlexey Kardashevskiy target_ulong do_client_architecture_support(PowerPCCPU *cpu, 1075ce2918cbSDavid Gibson SpaprMachineState *spapr, 107691067db1SAlexey Kardashevskiy target_ulong vec, 107791067db1SAlexey Kardashevskiy target_ulong fdt_bufsize) 107880c33d34SDavid Gibson { 107991067db1SAlexey Kardashevskiy target_ulong ov_table; /* Working address in data buffer */ 108080c33d34SDavid Gibson uint32_t cas_pvr; 108186962462SGreg Kurz SpaprOptionVector *ov1_guest, *ov5_guest; 108280c33d34SDavid Gibson bool guest_radix; 1083cc7b35b1SGreg Kurz bool raw_mode_supported = false; 108421bde1ecSAlexey Kardashevskiy bool guest_xive; 108512b3868eSGreg Kurz CPUState *cs; 1086087820e3SGreg Kurz void *fdt; 1087121afbe4SGreg Kurz uint32_t max_compat = spapr->max_compat_pvr; 108812b3868eSGreg Kurz 108912b3868eSGreg Kurz /* CAS is supposed to be called early when only the boot vCPU is active. */ 109012b3868eSGreg Kurz CPU_FOREACH(cs) { 109112b3868eSGreg Kurz if (cs == CPU(cpu)) { 109212b3868eSGreg Kurz continue; 109312b3868eSGreg Kurz } 109412b3868eSGreg Kurz if (!cs->halted) { 109512b3868eSGreg Kurz warn_report("guest has multiple active vCPUs at CAS, which is not allowed"); 109612b3868eSGreg Kurz return H_MULTI_THREADS_ACTIVE; 109712b3868eSGreg Kurz } 109812b3868eSGreg Kurz } 10993794d548SAlexey Kardashevskiy 1100121afbe4SGreg Kurz cas_pvr = cas_check_pvr(cpu, max_compat, &vec, &raw_mode_supported); 1101121afbe4SGreg Kurz if (!cas_pvr && (!raw_mode_supported || max_compat)) { 1102121afbe4SGreg Kurz /* 1103121afbe4SGreg Kurz * We couldn't find a suitable compatibility mode, and either 1104121afbe4SGreg Kurz * the guest doesn't support "raw" mode for this CPU, or "raw" 1105121afbe4SGreg Kurz * mode is disabled because a maximum compat mode is set. 1106121afbe4SGreg Kurz */ 1107121afbe4SGreg Kurz error_report("Couldn't negotiate a suitable PVR during CAS"); 110880c33d34SDavid Gibson return H_HARDWARE; 110980c33d34SDavid Gibson } 111080c33d34SDavid Gibson 111180c33d34SDavid Gibson /* Update CPUs */ 111280c33d34SDavid Gibson if (cpu->compat_pvr != cas_pvr) { 11137e92da81SGreg Kurz Error *local_err = NULL; 11147e92da81SGreg Kurz 11157e92da81SGreg Kurz if (ppc_set_compat_all(cas_pvr, &local_err) < 0) { 1116cc7b35b1SGreg Kurz /* We fail to set compat mode (likely because running with KVM PR), 1117cc7b35b1SGreg Kurz * but maybe we can fallback to raw mode if the guest supports it. 1118cc7b35b1SGreg Kurz */ 1119cc7b35b1SGreg Kurz if (!raw_mode_supported) { 1120f6f242c7SDavid Gibson error_report_err(local_err); 11213794d548SAlexey Kardashevskiy return H_HARDWARE; 11223794d548SAlexey Kardashevskiy } 11232c9dfdacSGreg Kurz error_free(local_err); 1124cc7b35b1SGreg Kurz } 11253794d548SAlexey Kardashevskiy } 11263794d548SAlexey Kardashevskiy 112703d196b7SBharata B Rao /* For the future use: here @ov_table points to the first option vector */ 112891067db1SAlexey Kardashevskiy ov_table = vec; 112903d196b7SBharata B Rao 1130e957f6a9SSam Bobroff ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1131cbd0d7f3SGreg Kurz if (!ov1_guest) { 1132cbd0d7f3SGreg Kurz warn_report("guest didn't provide option vector 1"); 1133cbd0d7f3SGreg Kurz return H_PARAMETER; 1134cbd0d7f3SGreg Kurz } 1135facdb8b6SMichael Roth ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1136cbd0d7f3SGreg Kurz if (!ov5_guest) { 1137ce05fa0fSGreg Kurz spapr_ovec_cleanup(ov1_guest); 1138cbd0d7f3SGreg Kurz warn_report("guest didn't provide option vector 5"); 1139cbd0d7f3SGreg Kurz return H_PARAMETER; 1140cbd0d7f3SGreg Kurz } 11419fb4541fSSam Bobroff if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 11429fb4541fSSam Bobroff error_report("guest requested hash and radix MMU, which is invalid."); 11439fb4541fSSam Bobroff exit(EXIT_FAILURE); 11449fb4541fSSam Bobroff } 1145e7f78db9SGreg Kurz if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { 1146e7f78db9SGreg Kurz error_report("guest requested an invalid interrupt mode"); 1147e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1148e7f78db9SGreg Kurz } 1149e7f78db9SGreg Kurz 11509fb4541fSSam Bobroff guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 11512a6593cbSAlexey Kardashevskiy 1152e7f78db9SGreg Kurz guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); 1153e7f78db9SGreg Kurz 11542772cf6bSDavid Gibson /* 11552772cf6bSDavid Gibson * HPT resizing is a bit of a special case, because when enabled 11562772cf6bSDavid Gibson * we assume an HPT guest will support it until it says it 11572772cf6bSDavid Gibson * doesn't, instead of assuming it won't support it until it says 11582772cf6bSDavid Gibson * it does. Strictly speaking that approach could break for 11592772cf6bSDavid Gibson * guests which don't make a CAS call, but those are so old we 11602772cf6bSDavid Gibson * don't care about them. Without that assumption we'd have to 11612772cf6bSDavid Gibson * make at least a temporary allocation of an HPT sized for max 11622772cf6bSDavid Gibson * memory, which could be impossibly difficult under KVM HV if 11632772cf6bSDavid Gibson * maxram is large. 11642772cf6bSDavid Gibson */ 11652772cf6bSDavid Gibson if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 11662772cf6bSDavid Gibson int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 11672772cf6bSDavid Gibson 11682772cf6bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 11692772cf6bSDavid Gibson error_report( 11702772cf6bSDavid Gibson "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 11712772cf6bSDavid Gibson exit(1); 11722772cf6bSDavid Gibson } 11732772cf6bSDavid Gibson 11742772cf6bSDavid Gibson if (spapr->htab_shift < maxshift) { 11752772cf6bSDavid Gibson /* Guest doesn't know about HPT resizing, so we 11762772cf6bSDavid Gibson * pre-emptively resize for the maximum permitted RAM. At 11772772cf6bSDavid Gibson * the point this is called, nothing should have been 11782772cf6bSDavid Gibson * entered into the existing HPT */ 11792772cf6bSDavid Gibson spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 11801ec26c75SGreg Kurz push_sregs_to_kvm_pr(spapr); 1181b55d295eSDavid Gibson } 11822772cf6bSDavid Gibson } 11832772cf6bSDavid Gibson 1184facdb8b6SMichael Roth /* NOTE: there are actually a number of ov5 bits where input from the 1185facdb8b6SMichael Roth * guest is always zero, and the platform/QEMU enables them independently 1186facdb8b6SMichael Roth * of guest input. To model these properly we'd want some sort of mask, 1187facdb8b6SMichael Roth * but since they only currently apply to memory migration as defined 1188facdb8b6SMichael Roth * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 11896787d27bSMichael Roth * to worry about this for now. 1190facdb8b6SMichael Roth */ 119130bf9ed1SCédric Le Goater 11926787d27bSMichael Roth /* full range of negotiated ov5 capabilities */ 1193facdb8b6SMichael Roth spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1194facdb8b6SMichael Roth spapr_ovec_cleanup(ov5_guest); 1195b4b83312SGreg Kurz 1196068479e1SFabiano Rosas spapr_check_mmu_mode(guest_radix); 1197068479e1SFabiano Rosas 1198daa36379SDavid Gibson spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00); 119900005f22SShivaprasad G Bhat spapr_ovec_cleanup(ov1_guest); 120013db0cd9SCédric Le Goater 120113db0cd9SCédric Le Goater /* 1202*5dab5abeSDaniel Henrique Barboza * Check for NUMA affinity conditions now that we know which NUMA 1203*5dab5abeSDaniel Henrique Barboza * affinity the guest will use. 1204*5dab5abeSDaniel Henrique Barboza */ 1205*5dab5abeSDaniel Henrique Barboza spapr_numa_associativity_check(spapr); 1206*5dab5abeSDaniel Henrique Barboza 1207*5dab5abeSDaniel Henrique Barboza /* 12088deb8019SDavid Gibson * Ensure the guest asks for an interrupt mode we support; 12098deb8019SDavid Gibson * otherwise terminate the boot. 1210e7f78db9SGreg Kurz */ 1211e7f78db9SGreg Kurz if (guest_xive) { 1212ca62823bSDavid Gibson if (!spapr->irq->xive) { 121375de5941SGreg Kurz error_report( 121475de5941SGreg Kurz "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property"); 1215e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1216e7f78db9SGreg Kurz } 1217e7f78db9SGreg Kurz } else { 1218ca62823bSDavid Gibson if (!spapr->irq->xics) { 121975de5941SGreg Kurz error_report( 122075de5941SGreg Kurz "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual"); 1221e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1222e7f78db9SGreg Kurz } 1223e7f78db9SGreg Kurz } 1224e7f78db9SGreg Kurz 12258deb8019SDavid Gibson spapr_irq_update_active_intc(spapr); 12268deb8019SDavid Gibson 1227babb819fSGreg Kurz /* 1228babb819fSGreg Kurz * Process all pending hot-plug/unplug requests now. An updated full 1229babb819fSGreg Kurz * rendered FDT will be returned to the guest. 1230babb819fSGreg Kurz */ 1231babb819fSGreg Kurz spapr_drc_reset_all(spapr); 1232babb819fSGreg Kurz spapr_clear_pending_hotplug_events(spapr); 12330c21e073SDavid Gibson 1234087820e3SGreg Kurz /* 1235087820e3SGreg Kurz * If spapr_machine_reset() did not set up a HPT but one is necessary 1236087820e3SGreg Kurz * (because the guest isn't going to use radix) then set it up here. 1237087820e3SGreg Kurz */ 12388deb8019SDavid Gibson if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { 12398deb8019SDavid Gibson /* legacy hash or new hash: */ 12408897ea5aSDavid Gibson spapr_setup_hpt(spapr); 12418deb8019SDavid Gibson } 12420c21e073SDavid Gibson 124321bde1ecSAlexey Kardashevskiy fdt = spapr_build_fdt(spapr, spapr->vof != NULL, fdt_bufsize); 12440c21e073SDavid Gibson g_free(spapr->fdt_blob); 12450c21e073SDavid Gibson spapr->fdt_size = fdt_totalsize(fdt); 12460c21e073SDavid Gibson spapr->fdt_initial_size = spapr->fdt_size; 12470c21e073SDavid Gibson spapr->fdt_blob = fdt; 12482a6593cbSAlexey Kardashevskiy 12492a6593cbSAlexey Kardashevskiy return H_SUCCESS; 12502a6593cbSAlexey Kardashevskiy } 12512a6593cbSAlexey Kardashevskiy 125291067db1SAlexey Kardashevskiy static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 125391067db1SAlexey Kardashevskiy SpaprMachineState *spapr, 125491067db1SAlexey Kardashevskiy target_ulong opcode, 125591067db1SAlexey Kardashevskiy target_ulong *args) 125691067db1SAlexey Kardashevskiy { 125791067db1SAlexey Kardashevskiy target_ulong vec = ppc64_phys_to_real(args[0]); 125891067db1SAlexey Kardashevskiy target_ulong fdt_buf = args[1]; 125991067db1SAlexey Kardashevskiy target_ulong fdt_bufsize = args[2]; 126091067db1SAlexey Kardashevskiy target_ulong ret; 126191067db1SAlexey Kardashevskiy SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 126291067db1SAlexey Kardashevskiy 126391067db1SAlexey Kardashevskiy if (fdt_bufsize < sizeof(hdr)) { 126491067db1SAlexey Kardashevskiy error_report("SLOF provided insufficient CAS buffer " 126591067db1SAlexey Kardashevskiy TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr)); 126691067db1SAlexey Kardashevskiy exit(EXIT_FAILURE); 126791067db1SAlexey Kardashevskiy } 126891067db1SAlexey Kardashevskiy 126991067db1SAlexey Kardashevskiy fdt_bufsize -= sizeof(hdr); 127091067db1SAlexey Kardashevskiy 127191067db1SAlexey Kardashevskiy ret = do_client_architecture_support(cpu, spapr, vec, fdt_bufsize); 127291067db1SAlexey Kardashevskiy if (ret == H_SUCCESS) { 127391067db1SAlexey Kardashevskiy _FDT((fdt_pack(spapr->fdt_blob))); 127491067db1SAlexey Kardashevskiy spapr->fdt_size = fdt_totalsize(spapr->fdt_blob); 127591067db1SAlexey Kardashevskiy spapr->fdt_initial_size = spapr->fdt_size; 127691067db1SAlexey Kardashevskiy 127791067db1SAlexey Kardashevskiy cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr)); 127891067db1SAlexey Kardashevskiy cpu_physical_memory_write(fdt_buf + sizeof(hdr), spapr->fdt_blob, 127991067db1SAlexey Kardashevskiy spapr->fdt_size); 128091067db1SAlexey Kardashevskiy trace_spapr_cas_continue(spapr->fdt_size + sizeof(hdr)); 128191067db1SAlexey Kardashevskiy } 128291067db1SAlexey Kardashevskiy 128391067db1SAlexey Kardashevskiy return ret; 128491067db1SAlexey Kardashevskiy } 128591067db1SAlexey Kardashevskiy 1286fc8c745dSAlexey Kardashevskiy target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1287fc8c745dSAlexey Kardashevskiy CPUState *cs, 1288fc8c745dSAlexey Kardashevskiy target_ulong ovec_addr) 1289fc8c745dSAlexey Kardashevskiy { 1290fc8c745dSAlexey Kardashevskiy SpaprMachineState *spapr = SPAPR_MACHINE(ms); 1291fc8c745dSAlexey Kardashevskiy 1292fc8c745dSAlexey Kardashevskiy target_ulong ret = do_client_architecture_support(POWERPC_CPU(cs), spapr, 1293fc8c745dSAlexey Kardashevskiy ovec_addr, FDT_MAX_SIZE); 1294fc8c745dSAlexey Kardashevskiy 1295fc8c745dSAlexey Kardashevskiy /* 1296fc8c745dSAlexey Kardashevskiy * This adds stdout and generates phandles for boottime and CAS FDTs. 1297fc8c745dSAlexey Kardashevskiy * It is alright to update the FDT here as do_client_architecture_support() 1298fc8c745dSAlexey Kardashevskiy * does not pack it. 1299fc8c745dSAlexey Kardashevskiy */ 1300fc8c745dSAlexey Kardashevskiy spapr_vof_client_dt_finalize(spapr, spapr->fdt_blob); 1301fc8c745dSAlexey Kardashevskiy 1302fc8c745dSAlexey Kardashevskiy return ret; 1303fc8c745dSAlexey Kardashevskiy } 1304fc8c745dSAlexey Kardashevskiy 1305c59704b2SSuraj Jitindar Singh static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1306ce2918cbSDavid Gibson SpaprMachineState *spapr, 1307c59704b2SSuraj Jitindar Singh target_ulong opcode, 1308c59704b2SSuraj Jitindar Singh target_ulong *args) 1309c59704b2SSuraj Jitindar Singh { 1310c59704b2SSuraj Jitindar Singh uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1311c59704b2SSuraj Jitindar Singh ~H_CPU_CHAR_THR_RECONF_TRIG; 1312c59704b2SSuraj Jitindar Singh uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1313c59704b2SSuraj Jitindar Singh uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1314c59704b2SSuraj Jitindar Singh uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1315c59704b2SSuraj Jitindar Singh uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 13168ff43ee4SSuraj Jitindar Singh uint8_t count_cache_flush_assist = spapr_get_cap(spapr, 13178ff43ee4SSuraj Jitindar Singh SPAPR_CAP_CCF_ASSIST); 1318c59704b2SSuraj Jitindar Singh 1319c59704b2SSuraj Jitindar Singh switch (safe_cache) { 1320c59704b2SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1321c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1322c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1323c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1324c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1325c59704b2SSuraj Jitindar Singh break; 1326c59704b2SSuraj Jitindar Singh case SPAPR_CAP_FIXED: 132717fd09c0SNicholas Piggin behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY; 132817fd09c0SNicholas Piggin behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS; 1329c59704b2SSuraj Jitindar Singh break; 1330c59704b2SSuraj Jitindar Singh default: /* broken */ 1331c59704b2SSuraj Jitindar Singh assert(safe_cache == SPAPR_CAP_BROKEN); 1332c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1333c59704b2SSuraj Jitindar Singh break; 1334c59704b2SSuraj Jitindar Singh } 1335c59704b2SSuraj Jitindar Singh 1336c59704b2SSuraj Jitindar Singh switch (safe_bounds_check) { 1337c59704b2SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1338c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1339c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1340c59704b2SSuraj Jitindar Singh break; 1341c59704b2SSuraj Jitindar Singh case SPAPR_CAP_FIXED: 1342c59704b2SSuraj Jitindar Singh break; 1343c59704b2SSuraj Jitindar Singh default: /* broken */ 1344c59704b2SSuraj Jitindar Singh assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1345c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1346c59704b2SSuraj Jitindar Singh break; 1347c59704b2SSuraj Jitindar Singh } 1348c59704b2SSuraj Jitindar Singh 1349c59704b2SSuraj Jitindar Singh switch (safe_indirect_branch) { 1350399b2896SSuraj Jitindar Singh case SPAPR_CAP_FIXED_NA: 1351399b2896SSuraj Jitindar Singh break; 1352c76c0d30SSuraj Jitindar Singh case SPAPR_CAP_FIXED_CCD: 1353c76c0d30SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; 1354c76c0d30SSuraj Jitindar Singh break; 1355c76c0d30SSuraj Jitindar Singh case SPAPR_CAP_FIXED_IBS: 1356c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1357fa86f592SGreg Kurz break; 1358399b2896SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1359399b2896SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE; 13608ff43ee4SSuraj Jitindar Singh if (count_cache_flush_assist) { 13618ff43ee4SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST; 13628ff43ee4SSuraj Jitindar Singh } 1363399b2896SSuraj Jitindar Singh break; 1364c59704b2SSuraj Jitindar Singh default: /* broken */ 1365c59704b2SSuraj Jitindar Singh assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1366c59704b2SSuraj Jitindar Singh break; 1367c59704b2SSuraj Jitindar Singh } 1368c59704b2SSuraj Jitindar Singh 1369c59704b2SSuraj Jitindar Singh args[0] = characteristics; 1370c59704b2SSuraj Jitindar Singh args[1] = behaviour; 1371fea35ca4SAlexey Kardashevskiy return H_SUCCESS; 1372fea35ca4SAlexey Kardashevskiy } 1373fea35ca4SAlexey Kardashevskiy 1374ce2918cbSDavid Gibson static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, 1375fea35ca4SAlexey Kardashevskiy target_ulong opcode, target_ulong *args) 1376fea35ca4SAlexey Kardashevskiy { 1377fea35ca4SAlexey Kardashevskiy target_ulong dt = ppc64_phys_to_real(args[0]); 1378fea35ca4SAlexey Kardashevskiy struct fdt_header hdr = { 0 }; 1379fea35ca4SAlexey Kardashevskiy unsigned cb; 1380ce2918cbSDavid Gibson SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1381fea35ca4SAlexey Kardashevskiy void *fdt; 1382fea35ca4SAlexey Kardashevskiy 1383fea35ca4SAlexey Kardashevskiy cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); 1384fea35ca4SAlexey Kardashevskiy cb = fdt32_to_cpu(hdr.totalsize); 1385fea35ca4SAlexey Kardashevskiy 1386fea35ca4SAlexey Kardashevskiy if (!smc->update_dt_enabled) { 1387fea35ca4SAlexey Kardashevskiy return H_SUCCESS; 1388fea35ca4SAlexey Kardashevskiy } 1389fea35ca4SAlexey Kardashevskiy 1390fea35ca4SAlexey Kardashevskiy /* Check that the fdt did not grow out of proportion */ 1391fea35ca4SAlexey Kardashevskiy if (cb > spapr->fdt_initial_size * 2) { 1392fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, 1393fea35ca4SAlexey Kardashevskiy fdt32_to_cpu(hdr.magic)); 1394fea35ca4SAlexey Kardashevskiy return H_PARAMETER; 1395fea35ca4SAlexey Kardashevskiy } 1396fea35ca4SAlexey Kardashevskiy 1397fea35ca4SAlexey Kardashevskiy fdt = g_malloc0(cb); 1398fea35ca4SAlexey Kardashevskiy cpu_physical_memory_read(dt, fdt, cb); 1399fea35ca4SAlexey Kardashevskiy 1400fea35ca4SAlexey Kardashevskiy /* Check the fdt consistency */ 1401fea35ca4SAlexey Kardashevskiy if (fdt_check_full(fdt, cb)) { 1402fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, 1403fea35ca4SAlexey Kardashevskiy fdt32_to_cpu(hdr.magic)); 1404fea35ca4SAlexey Kardashevskiy return H_PARAMETER; 1405fea35ca4SAlexey Kardashevskiy } 1406fea35ca4SAlexey Kardashevskiy 1407fea35ca4SAlexey Kardashevskiy g_free(spapr->fdt_blob); 1408fea35ca4SAlexey Kardashevskiy spapr->fdt_size = cb; 1409fea35ca4SAlexey Kardashevskiy spapr->fdt_blob = fdt; 1410fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt(cb); 1411c59704b2SSuraj Jitindar Singh 1412c59704b2SSuraj Jitindar Singh return H_SUCCESS; 1413c59704b2SSuraj Jitindar Singh } 1414c59704b2SSuraj Jitindar Singh 14159f64bd8aSPaolo Bonzini static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 14169f64bd8aSPaolo Bonzini static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 14170fb6bd07SMichael Roth static spapr_hcall_fn svm_hypercall_table[(SVM_HCALL_MAX - SVM_HCALL_BASE) / 4 + 1]; 14189f64bd8aSPaolo Bonzini 14199f64bd8aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 14209f64bd8aSPaolo Bonzini { 14219f64bd8aSPaolo Bonzini spapr_hcall_fn *slot; 14229f64bd8aSPaolo Bonzini 14239f64bd8aSPaolo Bonzini if (opcode <= MAX_HCALL_OPCODE) { 14249f64bd8aSPaolo Bonzini assert((opcode & 0x3) == 0); 14259f64bd8aSPaolo Bonzini 14269f64bd8aSPaolo Bonzini slot = &papr_hypercall_table[opcode / 4]; 14270fb6bd07SMichael Roth } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { 14280fb6bd07SMichael Roth /* we only have SVM-related hcall numbers assigned in multiples of 4 */ 14290fb6bd07SMichael Roth assert((opcode & 0x3) == 0); 14300fb6bd07SMichael Roth 14310fb6bd07SMichael Roth slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 14329f64bd8aSPaolo Bonzini } else { 14339f64bd8aSPaolo Bonzini assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 14349f64bd8aSPaolo Bonzini 14359f64bd8aSPaolo Bonzini slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 14369f64bd8aSPaolo Bonzini } 14379f64bd8aSPaolo Bonzini 14389f64bd8aSPaolo Bonzini assert(!(*slot)); 14399f64bd8aSPaolo Bonzini *slot = fn; 14409f64bd8aSPaolo Bonzini } 14419f64bd8aSPaolo Bonzini 14429f64bd8aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 14439f64bd8aSPaolo Bonzini target_ulong *args) 14449f64bd8aSPaolo Bonzini { 1445ce2918cbSDavid Gibson SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 144628e02042SDavid Gibson 14479f64bd8aSPaolo Bonzini if ((opcode <= MAX_HCALL_OPCODE) 14489f64bd8aSPaolo Bonzini && ((opcode & 0x3) == 0)) { 14499f64bd8aSPaolo Bonzini spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 14509f64bd8aSPaolo Bonzini 14519f64bd8aSPaolo Bonzini if (fn) { 14529f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 14539f64bd8aSPaolo Bonzini } 14540fb6bd07SMichael Roth } else if ((opcode >= SVM_HCALL_BASE) && 14550fb6bd07SMichael Roth (opcode <= SVM_HCALL_MAX)) { 14560fb6bd07SMichael Roth spapr_hcall_fn fn = svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 14570fb6bd07SMichael Roth 14580fb6bd07SMichael Roth if (fn) { 14590fb6bd07SMichael Roth return fn(cpu, spapr, opcode, args); 14600fb6bd07SMichael Roth } 14619f64bd8aSPaolo Bonzini } else if ((opcode >= KVMPPC_HCALL_BASE) && 14629f64bd8aSPaolo Bonzini (opcode <= KVMPPC_HCALL_MAX)) { 14639f64bd8aSPaolo Bonzini spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 14649f64bd8aSPaolo Bonzini 14659f64bd8aSPaolo Bonzini if (fn) { 14669f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 14679f64bd8aSPaolo Bonzini } 14689f64bd8aSPaolo Bonzini } 14699f64bd8aSPaolo Bonzini 1470aaf87c66SThomas Huth qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1471aaf87c66SThomas Huth opcode); 14729f64bd8aSPaolo Bonzini return H_FUNCTION; 14739f64bd8aSPaolo Bonzini } 14749f64bd8aSPaolo Bonzini 1475962104f0SLucas Mateus Castro (alqotel) #ifndef CONFIG_TCG 1476962104f0SLucas Mateus Castro (alqotel) static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr, 1477962104f0SLucas Mateus Castro (alqotel) target_ulong opcode, target_ulong *args) 1478962104f0SLucas Mateus Castro (alqotel) { 1479962104f0SLucas Mateus Castro (alqotel) g_assert_not_reached(); 1480962104f0SLucas Mateus Castro (alqotel) } 1481962104f0SLucas Mateus Castro (alqotel) 1482962104f0SLucas Mateus Castro (alqotel) static void hypercall_register_softmmu(void) 14839f64bd8aSPaolo Bonzini { 14849f64bd8aSPaolo Bonzini /* hcall-pft */ 1485962104f0SLucas Mateus Castro (alqotel) spapr_register_hypercall(H_ENTER, h_softmmu); 1486962104f0SLucas Mateus Castro (alqotel) spapr_register_hypercall(H_REMOVE, h_softmmu); 1487962104f0SLucas Mateus Castro (alqotel) spapr_register_hypercall(H_PROTECT, h_softmmu); 1488962104f0SLucas Mateus Castro (alqotel) spapr_register_hypercall(H_READ, h_softmmu); 14899f64bd8aSPaolo Bonzini 14909f64bd8aSPaolo Bonzini /* hcall-bulk */ 1491962104f0SLucas Mateus Castro (alqotel) spapr_register_hypercall(H_BULK_REMOVE, h_softmmu); 1492962104f0SLucas Mateus Castro (alqotel) } 1493962104f0SLucas Mateus Castro (alqotel) #else 1494962104f0SLucas Mateus Castro (alqotel) static void hypercall_register_softmmu(void) 1495962104f0SLucas Mateus Castro (alqotel) { 1496962104f0SLucas Mateus Castro (alqotel) /* DO NOTHING */ 1497962104f0SLucas Mateus Castro (alqotel) } 1498962104f0SLucas Mateus Castro (alqotel) #endif 1499962104f0SLucas Mateus Castro (alqotel) 1500962104f0SLucas Mateus Castro (alqotel) static void hypercall_register_types(void) 1501962104f0SLucas Mateus Castro (alqotel) { 1502962104f0SLucas Mateus Castro (alqotel) hypercall_register_softmmu(); 15039f64bd8aSPaolo Bonzini 150430f4b05bSDavid Gibson /* hcall-hpt-resize */ 150530f4b05bSDavid Gibson spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 150630f4b05bSDavid Gibson spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 150730f4b05bSDavid Gibson 15089f64bd8aSPaolo Bonzini /* hcall-splpar */ 15099f64bd8aSPaolo Bonzini spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 15109f64bd8aSPaolo Bonzini spapr_register_hypercall(H_CEDE, h_cede); 1511e8ce0e40SNicholas Piggin spapr_register_hypercall(H_CONFER, h_confer); 15123a6e6224SNicholas Piggin spapr_register_hypercall(H_PROD, h_prod); 15133a6e6224SNicholas Piggin 151410741314SNicholas Piggin /* hcall-join */ 151510741314SNicholas Piggin spapr_register_hypercall(H_JOIN, h_join); 151610741314SNicholas Piggin 15171c7ad77eSNicholas Piggin spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 15189f64bd8aSPaolo Bonzini 1519423576f7SThomas Huth /* processor register resource access h-calls */ 1520423576f7SThomas Huth spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1521af08a58fSThomas Huth spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1522e49ff266SThomas Huth spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 15233240dd9aSThomas Huth spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1524423576f7SThomas Huth spapr_register_hypercall(H_SET_MODE, h_set_mode); 1525423576f7SThomas Huth 1526d77a98b0SSuraj Jitindar Singh /* In Memory Table MMU h-calls */ 1527d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1528d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1529d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1530d77a98b0SSuraj Jitindar Singh 1531c59704b2SSuraj Jitindar Singh /* hcall-get-cpu-characteristics */ 1532c59704b2SSuraj Jitindar Singh spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 1533c59704b2SSuraj Jitindar Singh h_get_cpu_characteristics); 1534c59704b2SSuraj Jitindar Singh 15359f64bd8aSPaolo Bonzini /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 15369f64bd8aSPaolo Bonzini * here between the "CI" and the "CACHE" variants, they will use whatever 15379f64bd8aSPaolo Bonzini * mapping attributes qemu is using. When using KVM, the kernel will 15389f64bd8aSPaolo Bonzini * enforce the attributes more strongly 15399f64bd8aSPaolo Bonzini */ 15409f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 15419f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 15429f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 15439f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 15449f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 15459f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 15469f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 15479f64bd8aSPaolo Bonzini 15489f64bd8aSPaolo Bonzini /* qemu/KVM-PPC specific hcalls */ 15499f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 155042561bf2SAnton Blanchard 15512a6593cbSAlexey Kardashevskiy /* ibm,client-architecture-support support */ 15522a6593cbSAlexey Kardashevskiy spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1553c24ba3d0SLaurent Vivier 1554fea35ca4SAlexey Kardashevskiy spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); 15559f64bd8aSPaolo Bonzini } 15569f64bd8aSPaolo Bonzini 15579f64bd8aSPaolo Bonzini type_init(hypercall_register_types) 1558