10d75590dSPeter Maydell #include "qemu/osdep.h" 20c21e073SDavid Gibson #include "qemu/cutils.h" 3da34e65cSMarkus Armbruster #include "qapi/error.h" 4b3946626SVincent Palatin #include "sysemu/hw_accel.h" 554d31236SMarkus Armbruster #include "sysemu/runstate.h" 603dd024fSPaolo Bonzini #include "qemu/log.h" 7db725815SMarkus Armbruster #include "qemu/main-loop.h" 80b8fa32fSMarkus Armbruster #include "qemu/module.h" 90b0b8310SDavid Gibson #include "qemu/error-report.h" 109f64bd8aSPaolo Bonzini #include "cpu.h" 1163c91552SPaolo Bonzini #include "exec/exec-all.h" 129f64bd8aSPaolo Bonzini #include "helper_regs.h" 130d09e41aSPaolo Bonzini #include "hw/ppc/spapr.h" 147388efafSDavid Gibson #include "hw/ppc/spapr_cpu_core.h" 15d5aea6f3SDavid Gibson #include "mmu-hash64.h" 163794d548SAlexey Kardashevskiy #include "cpu-models.h" 173794d548SAlexey Kardashevskiy #include "trace.h" 183794d548SAlexey Kardashevskiy #include "kvm_ppc.h" 190c21e073SDavid Gibson #include "hw/ppc/fdt.h" 20facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 21b4db5413SSuraj Jitindar Singh #include "mmu-book3s-v3.h" 222cc0e2e8SDavid Hildenbrand #include "hw/mem/memory-device.h" 239f64bd8aSPaolo Bonzini 24af08a58fSThomas Huth static bool has_spr(PowerPCCPU *cpu, int spr) 25af08a58fSThomas Huth { 26af08a58fSThomas Huth /* We can test whether the SPR is defined by checking for a valid name */ 27af08a58fSThomas Huth return cpu->env.spr_cb[spr].name != NULL; 28af08a58fSThomas Huth } 29af08a58fSThomas Huth 30c6404adeSDavid Gibson static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) 31f3c75d42SAneesh Kumar K.V { 32f3c75d42SAneesh Kumar K.V /* 3336778660SDavid Gibson * hash value/pteg group index is normalized by HPT mask 34f3c75d42SAneesh Kumar K.V */ 3536778660SDavid Gibson if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { 36f3c75d42SAneesh Kumar K.V return false; 37f3c75d42SAneesh Kumar K.V } 38f3c75d42SAneesh Kumar K.V return true; 39f3c75d42SAneesh Kumar K.V } 40f3c75d42SAneesh Kumar K.V 41ce2918cbSDavid Gibson static bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) 42ecbc25faSDavid Gibson { 43ecbc25faSDavid Gibson MachineState *machine = MACHINE(spapr); 44e017da37SDavid Hildenbrand DeviceMemoryState *dms = machine->device_memory; 45ecbc25faSDavid Gibson 46ecbc25faSDavid Gibson if (addr < machine->ram_size) { 47ecbc25faSDavid Gibson return true; 48ecbc25faSDavid Gibson } 49e017da37SDavid Hildenbrand if ((addr >= dms->base) 50e017da37SDavid Hildenbrand && ((addr - dms->base) < memory_region_size(&dms->mr))) { 51ecbc25faSDavid Gibson return true; 52ecbc25faSDavid Gibson } 53ecbc25faSDavid Gibson 54ecbc25faSDavid Gibson return false; 55ecbc25faSDavid Gibson } 56ecbc25faSDavid Gibson 57ce2918cbSDavid Gibson static target_ulong h_enter(PowerPCCPU *cpu, SpaprMachineState *spapr, 589f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 599f64bd8aSPaolo Bonzini { 609f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 61c6404adeSDavid Gibson target_ulong ptex = args[1]; 629f64bd8aSPaolo Bonzini target_ulong pteh = args[2]; 639f64bd8aSPaolo Bonzini target_ulong ptel = args[3]; 641f0252e6SCédric Le Goater unsigned apshift; 659f64bd8aSPaolo Bonzini target_ulong raddr; 66c6404adeSDavid Gibson target_ulong slot; 677222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 689f64bd8aSPaolo Bonzini 691f0252e6SCédric Le Goater apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); 701114e712SDavid Gibson if (!apshift) { 711114e712SDavid Gibson /* Bad page size encoding */ 729f64bd8aSPaolo Bonzini return H_PARAMETER; 739f64bd8aSPaolo Bonzini } 749f64bd8aSPaolo Bonzini 751114e712SDavid Gibson raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); 769f64bd8aSPaolo Bonzini 77ecbc25faSDavid Gibson if (is_ram_address(spapr, raddr)) { 789f64bd8aSPaolo Bonzini /* Regular RAM - should have WIMG=0010 */ 79d5aea6f3SDavid Gibson if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 809f64bd8aSPaolo Bonzini return H_PARAMETER; 819f64bd8aSPaolo Bonzini } 829f64bd8aSPaolo Bonzini } else { 83c1175907SAneesh Kumar K.V target_ulong wimg_flags; 849f64bd8aSPaolo Bonzini /* Looks like an IO address */ 859f64bd8aSPaolo Bonzini /* FIXME: What WIMG combinations could be sensible for IO? 869f64bd8aSPaolo Bonzini * For now we allow WIMG=010x, but are there others? */ 879f64bd8aSPaolo Bonzini /* FIXME: Should we check against registered IO addresses? */ 88c1175907SAneesh Kumar K.V wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); 89c1175907SAneesh Kumar K.V 90c1175907SAneesh Kumar K.V if (wimg_flags != HPTE64_R_I && 91c1175907SAneesh Kumar K.V wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { 929f64bd8aSPaolo Bonzini return H_PARAMETER; 939f64bd8aSPaolo Bonzini } 949f64bd8aSPaolo Bonzini } 959f64bd8aSPaolo Bonzini 969f64bd8aSPaolo Bonzini pteh &= ~0x60ULL; 979f64bd8aSPaolo Bonzini 98c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 999f64bd8aSPaolo Bonzini return H_PARAMETER; 1009f64bd8aSPaolo Bonzini } 1017c43bca0SAneesh Kumar K.V 102c6404adeSDavid Gibson slot = ptex & 7ULL; 103c6404adeSDavid Gibson ptex = ptex & ~7ULL; 104c6404adeSDavid Gibson 1059f64bd8aSPaolo Bonzini if (likely((flags & H_EXACT) == 0)) { 1067222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 107c6404adeSDavid Gibson for (slot = 0; slot < 8; slot++) { 1087222b94aSDavid Gibson if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { 1099f64bd8aSPaolo Bonzini break; 1109f64bd8aSPaolo Bonzini } 1117aaf4957SAneesh Kumar K.V } 1127222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 113c6404adeSDavid Gibson if (slot == 8) { 1147aaf4957SAneesh Kumar K.V return H_PTEG_FULL; 1157aaf4957SAneesh Kumar K.V } 1169f64bd8aSPaolo Bonzini } else { 1177222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); 1187222b94aSDavid Gibson if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { 1197222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); 1209f64bd8aSPaolo Bonzini return H_PTEG_FULL; 1219f64bd8aSPaolo Bonzini } 1227222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 1239f64bd8aSPaolo Bonzini } 1247c43bca0SAneesh Kumar K.V 125a2dd4e83SBenjamin Herrenschmidt spapr_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); 1269f64bd8aSPaolo Bonzini 127c6404adeSDavid Gibson args[0] = ptex + slot; 1289f64bd8aSPaolo Bonzini return H_SUCCESS; 1299f64bd8aSPaolo Bonzini } 1309f64bd8aSPaolo Bonzini 131a3801402SStefan Weil typedef enum { 1329f64bd8aSPaolo Bonzini REMOVE_SUCCESS = 0, 1339f64bd8aSPaolo Bonzini REMOVE_NOT_FOUND = 1, 1349f64bd8aSPaolo Bonzini REMOVE_PARM = 2, 1359f64bd8aSPaolo Bonzini REMOVE_HW = 3, 136a3801402SStefan Weil } RemoveResult; 1379f64bd8aSPaolo Bonzini 138a2dd4e83SBenjamin Herrenschmidt static RemoveResult remove_hpte(PowerPCCPU *cpu 139a2dd4e83SBenjamin Herrenschmidt , target_ulong ptex, 1409f64bd8aSPaolo Bonzini target_ulong avpn, 1419f64bd8aSPaolo Bonzini target_ulong flags, 1429f64bd8aSPaolo Bonzini target_ulong *vp, target_ulong *rp) 1439f64bd8aSPaolo Bonzini { 1447222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 14561a36c9bSDavid Gibson target_ulong v, r; 1469f64bd8aSPaolo Bonzini 147c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 1489f64bd8aSPaolo Bonzini return REMOVE_PARM; 1499f64bd8aSPaolo Bonzini } 1509f64bd8aSPaolo Bonzini 1517222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 1527222b94aSDavid Gibson v = ppc_hash64_hpte0(cpu, hptes, 0); 1537222b94aSDavid Gibson r = ppc_hash64_hpte1(cpu, hptes, 0); 1547222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 1559f64bd8aSPaolo Bonzini 156d5aea6f3SDavid Gibson if ((v & HPTE64_V_VALID) == 0 || 1579f64bd8aSPaolo Bonzini ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 1589f64bd8aSPaolo Bonzini ((flags & H_ANDCOND) && (v & avpn) != 0)) { 1599f64bd8aSPaolo Bonzini return REMOVE_NOT_FOUND; 1609f64bd8aSPaolo Bonzini } 1619f64bd8aSPaolo Bonzini *vp = v; 1629f64bd8aSPaolo Bonzini *rp = r; 163a2dd4e83SBenjamin Herrenschmidt spapr_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); 16461a36c9bSDavid Gibson ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 1659f64bd8aSPaolo Bonzini return REMOVE_SUCCESS; 1669f64bd8aSPaolo Bonzini } 1679f64bd8aSPaolo Bonzini 168ce2918cbSDavid Gibson static target_ulong h_remove(PowerPCCPU *cpu, SpaprMachineState *spapr, 1699f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 1709f64bd8aSPaolo Bonzini { 171cd0c6f47SBenjamin Herrenschmidt CPUPPCState *env = &cpu->env; 1729f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 173c6404adeSDavid Gibson target_ulong ptex = args[1]; 1749f64bd8aSPaolo Bonzini target_ulong avpn = args[2]; 175a3801402SStefan Weil RemoveResult ret; 1769f64bd8aSPaolo Bonzini 177c6404adeSDavid Gibson ret = remove_hpte(cpu, ptex, avpn, flags, 1789f64bd8aSPaolo Bonzini &args[0], &args[1]); 1799f64bd8aSPaolo Bonzini 1809f64bd8aSPaolo Bonzini switch (ret) { 1819f64bd8aSPaolo Bonzini case REMOVE_SUCCESS: 182e3cffe6fSNikunj A Dadhania check_tlb_flush(env, true); 1839f64bd8aSPaolo Bonzini return H_SUCCESS; 1849f64bd8aSPaolo Bonzini 1859f64bd8aSPaolo Bonzini case REMOVE_NOT_FOUND: 1869f64bd8aSPaolo Bonzini return H_NOT_FOUND; 1879f64bd8aSPaolo Bonzini 1889f64bd8aSPaolo Bonzini case REMOVE_PARM: 1899f64bd8aSPaolo Bonzini return H_PARAMETER; 1909f64bd8aSPaolo Bonzini 1919f64bd8aSPaolo Bonzini case REMOVE_HW: 1929f64bd8aSPaolo Bonzini return H_HARDWARE; 1939f64bd8aSPaolo Bonzini } 1949f64bd8aSPaolo Bonzini 1959a39970dSStefan Weil g_assert_not_reached(); 1969f64bd8aSPaolo Bonzini } 1979f64bd8aSPaolo Bonzini 1989f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 1999f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 2009f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 2019f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_END 0xc000000000000000ULL 2029f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 2039f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 2049f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 2059f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 2069f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_HW 0x3000000000000000ULL 2079f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 2089f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 2099f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 2109f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 2119f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 2129f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 2139f64bd8aSPaolo Bonzini 2149f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_MAX_BATCH 4 2159f64bd8aSPaolo Bonzini 216ce2918cbSDavid Gibson static target_ulong h_bulk_remove(PowerPCCPU *cpu, SpaprMachineState *spapr, 2179f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 2189f64bd8aSPaolo Bonzini { 219cd0c6f47SBenjamin Herrenschmidt CPUPPCState *env = &cpu->env; 2209f64bd8aSPaolo Bonzini int i; 221cd0c6f47SBenjamin Herrenschmidt target_ulong rc = H_SUCCESS; 2229f64bd8aSPaolo Bonzini 2239f64bd8aSPaolo Bonzini for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 2249f64bd8aSPaolo Bonzini target_ulong *tsh = &args[i*2]; 2259f64bd8aSPaolo Bonzini target_ulong tsl = args[i*2 + 1]; 2269f64bd8aSPaolo Bonzini target_ulong v, r, ret; 2279f64bd8aSPaolo Bonzini 2289f64bd8aSPaolo Bonzini if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 2299f64bd8aSPaolo Bonzini break; 2309f64bd8aSPaolo Bonzini } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 2319f64bd8aSPaolo Bonzini return H_PARAMETER; 2329f64bd8aSPaolo Bonzini } 2339f64bd8aSPaolo Bonzini 2349f64bd8aSPaolo Bonzini *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 2359f64bd8aSPaolo Bonzini *tsh |= H_BULK_REMOVE_RESPONSE; 2369f64bd8aSPaolo Bonzini 2379f64bd8aSPaolo Bonzini if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 2389f64bd8aSPaolo Bonzini *tsh |= H_BULK_REMOVE_PARM; 2399f64bd8aSPaolo Bonzini return H_PARAMETER; 2409f64bd8aSPaolo Bonzini } 2419f64bd8aSPaolo Bonzini 2427ef23068SDavid Gibson ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, 2439f64bd8aSPaolo Bonzini (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 2449f64bd8aSPaolo Bonzini &v, &r); 2459f64bd8aSPaolo Bonzini 2469f64bd8aSPaolo Bonzini *tsh |= ret << 60; 2479f64bd8aSPaolo Bonzini 2489f64bd8aSPaolo Bonzini switch (ret) { 2499f64bd8aSPaolo Bonzini case REMOVE_SUCCESS: 250d5aea6f3SDavid Gibson *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 2519f64bd8aSPaolo Bonzini break; 2529f64bd8aSPaolo Bonzini 2539f64bd8aSPaolo Bonzini case REMOVE_PARM: 254cd0c6f47SBenjamin Herrenschmidt rc = H_PARAMETER; 255cd0c6f47SBenjamin Herrenschmidt goto exit; 2569f64bd8aSPaolo Bonzini 2579f64bd8aSPaolo Bonzini case REMOVE_HW: 258cd0c6f47SBenjamin Herrenschmidt rc = H_HARDWARE; 259cd0c6f47SBenjamin Herrenschmidt goto exit; 2609f64bd8aSPaolo Bonzini } 2619f64bd8aSPaolo Bonzini } 262cd0c6f47SBenjamin Herrenschmidt exit: 263e3cffe6fSNikunj A Dadhania check_tlb_flush(env, true); 2649f64bd8aSPaolo Bonzini 265cd0c6f47SBenjamin Herrenschmidt return rc; 2669f64bd8aSPaolo Bonzini } 2679f64bd8aSPaolo Bonzini 268ce2918cbSDavid Gibson static target_ulong h_protect(PowerPCCPU *cpu, SpaprMachineState *spapr, 2699f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 2709f64bd8aSPaolo Bonzini { 2719f64bd8aSPaolo Bonzini CPUPPCState *env = &cpu->env; 2729f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 273c6404adeSDavid Gibson target_ulong ptex = args[1]; 2749f64bd8aSPaolo Bonzini target_ulong avpn = args[2]; 2757222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 27661a36c9bSDavid Gibson target_ulong v, r; 2779f64bd8aSPaolo Bonzini 278c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 2799f64bd8aSPaolo Bonzini return H_PARAMETER; 2809f64bd8aSPaolo Bonzini } 2819f64bd8aSPaolo Bonzini 2827222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 2837222b94aSDavid Gibson v = ppc_hash64_hpte0(cpu, hptes, 0); 2847222b94aSDavid Gibson r = ppc_hash64_hpte1(cpu, hptes, 0); 2857222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 2869f64bd8aSPaolo Bonzini 287d5aea6f3SDavid Gibson if ((v & HPTE64_V_VALID) == 0 || 2889f64bd8aSPaolo Bonzini ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 2899f64bd8aSPaolo Bonzini return H_NOT_FOUND; 2909f64bd8aSPaolo Bonzini } 2919f64bd8aSPaolo Bonzini 292d5aea6f3SDavid Gibson r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 293d5aea6f3SDavid Gibson HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 294d5aea6f3SDavid Gibson r |= (flags << 55) & HPTE64_R_PP0; 295d5aea6f3SDavid Gibson r |= (flags << 48) & HPTE64_R_KEY_HI; 296d5aea6f3SDavid Gibson r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 297a2dd4e83SBenjamin Herrenschmidt spapr_store_hpte(cpu, ptex, 2983f94170bSAneesh Kumar K.V (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); 299c6404adeSDavid Gibson ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 300d76ab5e1SNikunj A Dadhania /* Flush the tlb */ 301d76ab5e1SNikunj A Dadhania check_tlb_flush(env, true); 3029f64bd8aSPaolo Bonzini /* Don't need a memory barrier, due to qemu's global lock */ 303a2dd4e83SBenjamin Herrenschmidt spapr_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); 3049f64bd8aSPaolo Bonzini return H_SUCCESS; 3059f64bd8aSPaolo Bonzini } 3069f64bd8aSPaolo Bonzini 307ce2918cbSDavid Gibson static target_ulong h_read(PowerPCCPU *cpu, SpaprMachineState *spapr, 308fa388916SAnthony Liguori target_ulong opcode, target_ulong *args) 309fa388916SAnthony Liguori { 310fa388916SAnthony Liguori target_ulong flags = args[0]; 311c6404adeSDavid Gibson target_ulong ptex = args[1]; 312fa388916SAnthony Liguori int i, ridx, n_entries = 1; 313993aaf0cSBenjamin Herrenschmidt const ppc_hash_pte64_t *hptes; 314fa388916SAnthony Liguori 315c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 316fa388916SAnthony Liguori return H_PARAMETER; 317fa388916SAnthony Liguori } 318fa388916SAnthony Liguori 319fa388916SAnthony Liguori if (flags & H_READ_4) { 320fa388916SAnthony Liguori /* Clear the two low order bits */ 321c6404adeSDavid Gibson ptex &= ~(3ULL); 322fa388916SAnthony Liguori n_entries = 4; 323fa388916SAnthony Liguori } 324fa388916SAnthony Liguori 325993aaf0cSBenjamin Herrenschmidt hptes = ppc_hash64_map_hptes(cpu, ptex, n_entries); 326fa388916SAnthony Liguori for (i = 0, ridx = 0; i < n_entries; i++) { 327993aaf0cSBenjamin Herrenschmidt args[ridx++] = ppc_hash64_hpte0(cpu, hptes, i); 328993aaf0cSBenjamin Herrenschmidt args[ridx++] = ppc_hash64_hpte1(cpu, hptes, i); 329fa388916SAnthony Liguori } 330993aaf0cSBenjamin Herrenschmidt ppc_hash64_unmap_hptes(cpu, hptes, ptex, n_entries); 331fa388916SAnthony Liguori 332fa388916SAnthony Liguori return H_SUCCESS; 333fa388916SAnthony Liguori } 334fa388916SAnthony Liguori 335ce2918cbSDavid Gibson struct SpaprPendingHpt { 3360b0b8310SDavid Gibson /* These fields are read-only after initialization */ 3370b0b8310SDavid Gibson int shift; 3380b0b8310SDavid Gibson QemuThread thread; 3390b0b8310SDavid Gibson 3400b0b8310SDavid Gibson /* These fields are protected by the BQL */ 3410b0b8310SDavid Gibson bool complete; 3420b0b8310SDavid Gibson 3430b0b8310SDavid Gibson /* These fields are private to the preparation thread if 3440b0b8310SDavid Gibson * !complete, otherwise protected by the BQL */ 3450b0b8310SDavid Gibson int ret; 3460b0b8310SDavid Gibson void *hpt; 3470b0b8310SDavid Gibson }; 3480b0b8310SDavid Gibson 349ce2918cbSDavid Gibson static void free_pending_hpt(SpaprPendingHpt *pending) 3500b0b8310SDavid Gibson { 3510b0b8310SDavid Gibson if (pending->hpt) { 3520b0b8310SDavid Gibson qemu_vfree(pending->hpt); 3530b0b8310SDavid Gibson } 3540b0b8310SDavid Gibson 3550b0b8310SDavid Gibson g_free(pending); 3560b0b8310SDavid Gibson } 3570b0b8310SDavid Gibson 3580b0b8310SDavid Gibson static void *hpt_prepare_thread(void *opaque) 3590b0b8310SDavid Gibson { 360ce2918cbSDavid Gibson SpaprPendingHpt *pending = opaque; 3610b0b8310SDavid Gibson size_t size = 1ULL << pending->shift; 3620b0b8310SDavid Gibson 3630b0b8310SDavid Gibson pending->hpt = qemu_memalign(size, size); 3640b0b8310SDavid Gibson if (pending->hpt) { 3650b0b8310SDavid Gibson memset(pending->hpt, 0, size); 3660b0b8310SDavid Gibson pending->ret = H_SUCCESS; 3670b0b8310SDavid Gibson } else { 3680b0b8310SDavid Gibson pending->ret = H_NO_MEM; 3690b0b8310SDavid Gibson } 3700b0b8310SDavid Gibson 3710b0b8310SDavid Gibson qemu_mutex_lock_iothread(); 3720b0b8310SDavid Gibson 3730b0b8310SDavid Gibson if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) { 3740b0b8310SDavid Gibson /* Ready to go */ 3750b0b8310SDavid Gibson pending->complete = true; 3760b0b8310SDavid Gibson } else { 3770b0b8310SDavid Gibson /* We've been cancelled, clean ourselves up */ 3780b0b8310SDavid Gibson free_pending_hpt(pending); 3790b0b8310SDavid Gibson } 3800b0b8310SDavid Gibson 3810b0b8310SDavid Gibson qemu_mutex_unlock_iothread(); 3820b0b8310SDavid Gibson return NULL; 3830b0b8310SDavid Gibson } 3840b0b8310SDavid Gibson 3850b0b8310SDavid Gibson /* Must be called with BQL held */ 386ce2918cbSDavid Gibson static void cancel_hpt_prepare(SpaprMachineState *spapr) 3870b0b8310SDavid Gibson { 388ce2918cbSDavid Gibson SpaprPendingHpt *pending = spapr->pending_hpt; 3890b0b8310SDavid Gibson 3900b0b8310SDavid Gibson /* Let the thread know it's cancelled */ 3910b0b8310SDavid Gibson spapr->pending_hpt = NULL; 3920b0b8310SDavid Gibson 3930b0b8310SDavid Gibson if (!pending) { 3940b0b8310SDavid Gibson /* Nothing to do */ 3950b0b8310SDavid Gibson return; 3960b0b8310SDavid Gibson } 3970b0b8310SDavid Gibson 3980b0b8310SDavid Gibson if (!pending->complete) { 3990b0b8310SDavid Gibson /* thread will clean itself up */ 4000b0b8310SDavid Gibson return; 4010b0b8310SDavid Gibson } 4020b0b8310SDavid Gibson 4030b0b8310SDavid Gibson free_pending_hpt(pending); 4040b0b8310SDavid Gibson } 4050b0b8310SDavid Gibson 406b55d295eSDavid Gibson /* Convert a return code from the KVM ioctl()s implementing resize HPT 407b55d295eSDavid Gibson * into a PAPR hypercall return code */ 408b55d295eSDavid Gibson static target_ulong resize_hpt_convert_rc(int ret) 409b55d295eSDavid Gibson { 410b55d295eSDavid Gibson if (ret >= 100000) { 411b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_100_SEC; 412b55d295eSDavid Gibson } else if (ret >= 10000) { 413b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_10_SEC; 414b55d295eSDavid Gibson } else if (ret >= 1000) { 415b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_1_SEC; 416b55d295eSDavid Gibson } else if (ret >= 100) { 417b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 418b55d295eSDavid Gibson } else if (ret >= 10) { 419b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_10_MSEC; 420b55d295eSDavid Gibson } else if (ret > 0) { 421b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_1_MSEC; 422b55d295eSDavid Gibson } 423b55d295eSDavid Gibson 424b55d295eSDavid Gibson switch (ret) { 425b55d295eSDavid Gibson case 0: 426b55d295eSDavid Gibson return H_SUCCESS; 427b55d295eSDavid Gibson case -EPERM: 428b55d295eSDavid Gibson return H_AUTHORITY; 429b55d295eSDavid Gibson case -EINVAL: 430b55d295eSDavid Gibson return H_PARAMETER; 431b55d295eSDavid Gibson case -ENXIO: 432b55d295eSDavid Gibson return H_CLOSED; 433b55d295eSDavid Gibson case -ENOSPC: 434b55d295eSDavid Gibson return H_PTEG_FULL; 435b55d295eSDavid Gibson case -EBUSY: 436b55d295eSDavid Gibson return H_BUSY; 437b55d295eSDavid Gibson case -ENOMEM: 438b55d295eSDavid Gibson return H_NO_MEM; 439b55d295eSDavid Gibson default: 440b55d295eSDavid Gibson return H_HARDWARE; 441b55d295eSDavid Gibson } 442b55d295eSDavid Gibson } 443b55d295eSDavid Gibson 44430f4b05bSDavid Gibson static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 445ce2918cbSDavid Gibson SpaprMachineState *spapr, 44630f4b05bSDavid Gibson target_ulong opcode, 44730f4b05bSDavid Gibson target_ulong *args) 44830f4b05bSDavid Gibson { 44930f4b05bSDavid Gibson target_ulong flags = args[0]; 4500b0b8310SDavid Gibson int shift = args[1]; 451ce2918cbSDavid Gibson SpaprPendingHpt *pending = spapr->pending_hpt; 452db50f280SDavid Gibson uint64_t current_ram_size; 453b55d295eSDavid Gibson int rc; 45430f4b05bSDavid Gibson 45530f4b05bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 45630f4b05bSDavid Gibson return H_AUTHORITY; 45730f4b05bSDavid Gibson } 45830f4b05bSDavid Gibson 4590b0b8310SDavid Gibson if (!spapr->htab_shift) { 4600b0b8310SDavid Gibson /* Radix guest, no HPT */ 4610b0b8310SDavid Gibson return H_NOT_AVAILABLE; 4620b0b8310SDavid Gibson } 4630b0b8310SDavid Gibson 46430f4b05bSDavid Gibson trace_spapr_h_resize_hpt_prepare(flags, shift); 4650b0b8310SDavid Gibson 4660b0b8310SDavid Gibson if (flags != 0) { 4670b0b8310SDavid Gibson return H_PARAMETER; 4680b0b8310SDavid Gibson } 4690b0b8310SDavid Gibson 4700b0b8310SDavid Gibson if (shift && ((shift < 18) || (shift > 46))) { 4710b0b8310SDavid Gibson return H_PARAMETER; 4720b0b8310SDavid Gibson } 4730b0b8310SDavid Gibson 474db50f280SDavid Gibson current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 4750b0b8310SDavid Gibson 4760b0b8310SDavid Gibson /* We only allow the guest to allocate an HPT one order above what 4770b0b8310SDavid Gibson * we'd normally give them (to stop a small guest claiming a huge 4780b0b8310SDavid Gibson * chunk of resources in the HPT */ 4790b0b8310SDavid Gibson if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 4800b0b8310SDavid Gibson return H_RESOURCE; 4810b0b8310SDavid Gibson } 4820b0b8310SDavid Gibson 483b55d295eSDavid Gibson rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 484b55d295eSDavid Gibson if (rc != -ENOSYS) { 485b55d295eSDavid Gibson return resize_hpt_convert_rc(rc); 486b55d295eSDavid Gibson } 487b55d295eSDavid Gibson 4880b0b8310SDavid Gibson if (pending) { 4890b0b8310SDavid Gibson /* something already in progress */ 4900b0b8310SDavid Gibson if (pending->shift == shift) { 4910b0b8310SDavid Gibson /* and it's suitable */ 4920b0b8310SDavid Gibson if (pending->complete) { 4930b0b8310SDavid Gibson return pending->ret; 4940b0b8310SDavid Gibson } else { 4950b0b8310SDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 4960b0b8310SDavid Gibson } 4970b0b8310SDavid Gibson } 4980b0b8310SDavid Gibson 4990b0b8310SDavid Gibson /* not suitable, cancel and replace */ 5000b0b8310SDavid Gibson cancel_hpt_prepare(spapr); 5010b0b8310SDavid Gibson } 5020b0b8310SDavid Gibson 5030b0b8310SDavid Gibson if (!shift) { 5040b0b8310SDavid Gibson /* nothing to do */ 5050b0b8310SDavid Gibson return H_SUCCESS; 5060b0b8310SDavid Gibson } 5070b0b8310SDavid Gibson 5080b0b8310SDavid Gibson /* start new prepare */ 5090b0b8310SDavid Gibson 510ce2918cbSDavid Gibson pending = g_new0(SpaprPendingHpt, 1); 5110b0b8310SDavid Gibson pending->shift = shift; 5120b0b8310SDavid Gibson pending->ret = H_HARDWARE; 5130b0b8310SDavid Gibson 5140b0b8310SDavid Gibson qemu_thread_create(&pending->thread, "sPAPR HPT prepare", 5150b0b8310SDavid Gibson hpt_prepare_thread, pending, QEMU_THREAD_DETACHED); 5160b0b8310SDavid Gibson 5170b0b8310SDavid Gibson spapr->pending_hpt = pending; 5180b0b8310SDavid Gibson 5190b0b8310SDavid Gibson /* In theory we could estimate the time more accurately based on 5200b0b8310SDavid Gibson * the new size, but there's not much point */ 5210b0b8310SDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 5220b0b8310SDavid Gibson } 5230b0b8310SDavid Gibson 5240b0b8310SDavid Gibson static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot) 5250b0b8310SDavid Gibson { 5260b0b8310SDavid Gibson uint8_t *addr = htab; 5270b0b8310SDavid Gibson 5280b0b8310SDavid Gibson addr += pteg * HASH_PTEG_SIZE_64; 5290b0b8310SDavid Gibson addr += slot * HASH_PTE_SIZE_64; 5300b0b8310SDavid Gibson return ldq_p(addr); 5310b0b8310SDavid Gibson } 5320b0b8310SDavid Gibson 5330b0b8310SDavid Gibson static void new_hpte_store(void *htab, uint64_t pteg, int slot, 5340b0b8310SDavid Gibson uint64_t pte0, uint64_t pte1) 5350b0b8310SDavid Gibson { 5360b0b8310SDavid Gibson uint8_t *addr = htab; 5370b0b8310SDavid Gibson 5380b0b8310SDavid Gibson addr += pteg * HASH_PTEG_SIZE_64; 5390b0b8310SDavid Gibson addr += slot * HASH_PTE_SIZE_64; 5400b0b8310SDavid Gibson 5410b0b8310SDavid Gibson stq_p(addr, pte0); 5420b0b8310SDavid Gibson stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1); 5430b0b8310SDavid Gibson } 5440b0b8310SDavid Gibson 5450b0b8310SDavid Gibson static int rehash_hpte(PowerPCCPU *cpu, 5460b0b8310SDavid Gibson const ppc_hash_pte64_t *hptes, 5470b0b8310SDavid Gibson void *old_hpt, uint64_t oldsize, 5480b0b8310SDavid Gibson void *new_hpt, uint64_t newsize, 5490b0b8310SDavid Gibson uint64_t pteg, int slot) 5500b0b8310SDavid Gibson { 5510b0b8310SDavid Gibson uint64_t old_hash_mask = (oldsize >> 7) - 1; 5520b0b8310SDavid Gibson uint64_t new_hash_mask = (newsize >> 7) - 1; 5530b0b8310SDavid Gibson target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot); 5540b0b8310SDavid Gibson target_ulong pte1; 5550b0b8310SDavid Gibson uint64_t avpn; 5560b0b8310SDavid Gibson unsigned base_pg_shift; 5570b0b8310SDavid Gibson uint64_t hash, new_pteg, replace_pte0; 5580b0b8310SDavid Gibson 5590b0b8310SDavid Gibson if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) { 5600b0b8310SDavid Gibson return H_SUCCESS; 5610b0b8310SDavid Gibson } 5620b0b8310SDavid Gibson 5630b0b8310SDavid Gibson pte1 = ppc_hash64_hpte1(cpu, hptes, slot); 5640b0b8310SDavid Gibson 5650b0b8310SDavid Gibson base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1); 5660b0b8310SDavid Gibson assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */ 5670b0b8310SDavid Gibson avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23); 5680b0b8310SDavid Gibson 5690b0b8310SDavid Gibson if (pte0 & HPTE64_V_SECONDARY) { 5700b0b8310SDavid Gibson pteg = ~pteg; 5710b0b8310SDavid Gibson } 5720b0b8310SDavid Gibson 5730b0b8310SDavid Gibson if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) { 5740b0b8310SDavid Gibson uint64_t offset, vsid; 5750b0b8310SDavid Gibson 5760b0b8310SDavid Gibson /* We only have 28 - 23 bits of offset in avpn */ 5770b0b8310SDavid Gibson offset = (avpn & 0x1f) << 23; 5780b0b8310SDavid Gibson vsid = avpn >> 5; 5790b0b8310SDavid Gibson /* We can find more bits from the pteg value */ 5800b0b8310SDavid Gibson if (base_pg_shift < 23) { 5810b0b8310SDavid Gibson offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift; 5820b0b8310SDavid Gibson } 5830b0b8310SDavid Gibson 5840b0b8310SDavid Gibson hash = vsid ^ (offset >> base_pg_shift); 5850b0b8310SDavid Gibson } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) { 5860b0b8310SDavid Gibson uint64_t offset, vsid; 5870b0b8310SDavid Gibson 5880b0b8310SDavid Gibson /* We only have 40 - 23 bits of seg_off in avpn */ 5890b0b8310SDavid Gibson offset = (avpn & 0x1ffff) << 23; 5900b0b8310SDavid Gibson vsid = avpn >> 17; 5910b0b8310SDavid Gibson if (base_pg_shift < 23) { 5920b0b8310SDavid Gibson offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask) 5930b0b8310SDavid Gibson << base_pg_shift; 5940b0b8310SDavid Gibson } 5950b0b8310SDavid Gibson 5960b0b8310SDavid Gibson hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift); 5970b0b8310SDavid Gibson } else { 5980b0b8310SDavid Gibson error_report("rehash_pte: Bad segment size in HPTE"); 59930f4b05bSDavid Gibson return H_HARDWARE; 60030f4b05bSDavid Gibson } 60130f4b05bSDavid Gibson 6020b0b8310SDavid Gibson new_pteg = hash & new_hash_mask; 6030b0b8310SDavid Gibson if (pte0 & HPTE64_V_SECONDARY) { 6040b0b8310SDavid Gibson assert(~pteg == (hash & old_hash_mask)); 6050b0b8310SDavid Gibson new_pteg = ~new_pteg; 6060b0b8310SDavid Gibson } else { 6070b0b8310SDavid Gibson assert(pteg == (hash & old_hash_mask)); 6080b0b8310SDavid Gibson } 6090b0b8310SDavid Gibson assert((oldsize != newsize) || (pteg == new_pteg)); 6100b0b8310SDavid Gibson replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot); 6110b0b8310SDavid Gibson /* 6120b0b8310SDavid Gibson * Strictly speaking, we don't need all these tests, since we only 6130b0b8310SDavid Gibson * ever rehash bolted HPTEs. We might in future handle non-bolted 6140b0b8310SDavid Gibson * HPTEs, though so make the logic correct for those cases as 6150b0b8310SDavid Gibson * well. 6160b0b8310SDavid Gibson */ 6170b0b8310SDavid Gibson if (replace_pte0 & HPTE64_V_VALID) { 6180b0b8310SDavid Gibson assert(newsize < oldsize); 6190b0b8310SDavid Gibson if (replace_pte0 & HPTE64_V_BOLTED) { 6200b0b8310SDavid Gibson if (pte0 & HPTE64_V_BOLTED) { 6210b0b8310SDavid Gibson /* Bolted collision, nothing we can do */ 6220b0b8310SDavid Gibson return H_PTEG_FULL; 6230b0b8310SDavid Gibson } else { 6240b0b8310SDavid Gibson /* Discard this hpte */ 6250b0b8310SDavid Gibson return H_SUCCESS; 6260b0b8310SDavid Gibson } 6270b0b8310SDavid Gibson } 6280b0b8310SDavid Gibson } 6290b0b8310SDavid Gibson 6300b0b8310SDavid Gibson new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1); 6310b0b8310SDavid Gibson return H_SUCCESS; 6320b0b8310SDavid Gibson } 6330b0b8310SDavid Gibson 6340b0b8310SDavid Gibson static int rehash_hpt(PowerPCCPU *cpu, 6350b0b8310SDavid Gibson void *old_hpt, uint64_t oldsize, 6360b0b8310SDavid Gibson void *new_hpt, uint64_t newsize) 6370b0b8310SDavid Gibson { 6380b0b8310SDavid Gibson uint64_t n_ptegs = oldsize >> 7; 6390b0b8310SDavid Gibson uint64_t pteg; 6400b0b8310SDavid Gibson int slot; 6410b0b8310SDavid Gibson int rc; 6420b0b8310SDavid Gibson 6430b0b8310SDavid Gibson for (pteg = 0; pteg < n_ptegs; pteg++) { 6440b0b8310SDavid Gibson hwaddr ptex = pteg * HPTES_PER_GROUP; 6450b0b8310SDavid Gibson const ppc_hash_pte64_t *hptes 6460b0b8310SDavid Gibson = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 6470b0b8310SDavid Gibson 6480b0b8310SDavid Gibson if (!hptes) { 6490b0b8310SDavid Gibson return H_HARDWARE; 6500b0b8310SDavid Gibson } 6510b0b8310SDavid Gibson 6520b0b8310SDavid Gibson for (slot = 0; slot < HPTES_PER_GROUP; slot++) { 6530b0b8310SDavid Gibson rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize, 6540b0b8310SDavid Gibson pteg, slot); 6550b0b8310SDavid Gibson if (rc != H_SUCCESS) { 6560b0b8310SDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 6570b0b8310SDavid Gibson return rc; 6580b0b8310SDavid Gibson } 6590b0b8310SDavid Gibson } 6600b0b8310SDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 6610b0b8310SDavid Gibson } 6620b0b8310SDavid Gibson 6630b0b8310SDavid Gibson return H_SUCCESS; 6640b0b8310SDavid Gibson } 6650b0b8310SDavid Gibson 6661ec26c75SGreg Kurz static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 6671ec26c75SGreg Kurz { 6681ec26c75SGreg Kurz int ret; 6691ec26c75SGreg Kurz 6701ec26c75SGreg Kurz cpu_synchronize_state(cs); 6711ec26c75SGreg Kurz 6721ec26c75SGreg Kurz ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 6731ec26c75SGreg Kurz if (ret < 0) { 6741ec26c75SGreg Kurz error_report("failed to push sregs to KVM: %s", strerror(-ret)); 6751ec26c75SGreg Kurz exit(1); 6761ec26c75SGreg Kurz } 6771ec26c75SGreg Kurz } 6781ec26c75SGreg Kurz 679ce2918cbSDavid Gibson static void push_sregs_to_kvm_pr(SpaprMachineState *spapr) 6801ec26c75SGreg Kurz { 6811ec26c75SGreg Kurz CPUState *cs; 6821ec26c75SGreg Kurz 6831ec26c75SGreg Kurz /* 6841ec26c75SGreg Kurz * This is a hack for the benefit of KVM PR - it abuses the SDR1 6851ec26c75SGreg Kurz * slot in kvm_sregs to communicate the userspace address of the 6861ec26c75SGreg Kurz * HPT 6871ec26c75SGreg Kurz */ 6881ec26c75SGreg Kurz if (!kvm_enabled() || !spapr->htab) { 6891ec26c75SGreg Kurz return; 6901ec26c75SGreg Kurz } 6911ec26c75SGreg Kurz 6921ec26c75SGreg Kurz CPU_FOREACH(cs) { 6931ec26c75SGreg Kurz run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 6941ec26c75SGreg Kurz } 6951ec26c75SGreg Kurz } 6961ec26c75SGreg Kurz 69730f4b05bSDavid Gibson static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 698ce2918cbSDavid Gibson SpaprMachineState *spapr, 69930f4b05bSDavid Gibson target_ulong opcode, 70030f4b05bSDavid Gibson target_ulong *args) 70130f4b05bSDavid Gibson { 70230f4b05bSDavid Gibson target_ulong flags = args[0]; 70330f4b05bSDavid Gibson target_ulong shift = args[1]; 704ce2918cbSDavid Gibson SpaprPendingHpt *pending = spapr->pending_hpt; 7050b0b8310SDavid Gibson int rc; 7060b0b8310SDavid Gibson size_t newsize; 70730f4b05bSDavid Gibson 70830f4b05bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 70930f4b05bSDavid Gibson return H_AUTHORITY; 71030f4b05bSDavid Gibson } 71130f4b05bSDavid Gibson 71294789567SDaniel Henrique Barboza if (!spapr->htab_shift) { 71394789567SDaniel Henrique Barboza /* Radix guest, no HPT */ 71494789567SDaniel Henrique Barboza return H_NOT_AVAILABLE; 71594789567SDaniel Henrique Barboza } 71694789567SDaniel Henrique Barboza 71730f4b05bSDavid Gibson trace_spapr_h_resize_hpt_commit(flags, shift); 7180b0b8310SDavid Gibson 719b55d295eSDavid Gibson rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 720b55d295eSDavid Gibson if (rc != -ENOSYS) { 72194789567SDaniel Henrique Barboza rc = resize_hpt_convert_rc(rc); 72294789567SDaniel Henrique Barboza if (rc == H_SUCCESS) { 72394789567SDaniel Henrique Barboza /* Need to set the new htab_shift in the machine state */ 72494789567SDaniel Henrique Barboza spapr->htab_shift = shift; 72594789567SDaniel Henrique Barboza } 72694789567SDaniel Henrique Barboza return rc; 727b55d295eSDavid Gibson } 728b55d295eSDavid Gibson 7290b0b8310SDavid Gibson if (flags != 0) { 7300b0b8310SDavid Gibson return H_PARAMETER; 7310b0b8310SDavid Gibson } 7320b0b8310SDavid Gibson 7330b0b8310SDavid Gibson if (!pending || (pending->shift != shift)) { 7340b0b8310SDavid Gibson /* no matching prepare */ 7350b0b8310SDavid Gibson return H_CLOSED; 7360b0b8310SDavid Gibson } 7370b0b8310SDavid Gibson 7380b0b8310SDavid Gibson if (!pending->complete) { 7390b0b8310SDavid Gibson /* prepare has not completed */ 7400b0b8310SDavid Gibson return H_BUSY; 7410b0b8310SDavid Gibson } 7420b0b8310SDavid Gibson 7430b0b8310SDavid Gibson /* Shouldn't have got past PREPARE without an HPT */ 7440b0b8310SDavid Gibson g_assert(spapr->htab_shift); 7450b0b8310SDavid Gibson 7460b0b8310SDavid Gibson newsize = 1ULL << pending->shift; 7470b0b8310SDavid Gibson rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr), 7480b0b8310SDavid Gibson pending->hpt, newsize); 7490b0b8310SDavid Gibson if (rc == H_SUCCESS) { 7500b0b8310SDavid Gibson qemu_vfree(spapr->htab); 7510b0b8310SDavid Gibson spapr->htab = pending->hpt; 7520b0b8310SDavid Gibson spapr->htab_shift = pending->shift; 7530b0b8310SDavid Gibson 7541ec26c75SGreg Kurz push_sregs_to_kvm_pr(spapr); 755b55d295eSDavid Gibson 7560b0b8310SDavid Gibson pending->hpt = NULL; /* so it's not free()d */ 7570b0b8310SDavid Gibson } 7580b0b8310SDavid Gibson 7590b0b8310SDavid Gibson /* Clean up */ 7600b0b8310SDavid Gibson spapr->pending_hpt = NULL; 7610b0b8310SDavid Gibson free_pending_hpt(pending); 7620b0b8310SDavid Gibson 7630b0b8310SDavid Gibson return rc; 76430f4b05bSDavid Gibson } 76530f4b05bSDavid Gibson 766ce2918cbSDavid Gibson static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, 767423576f7SThomas Huth target_ulong opcode, target_ulong *args) 768423576f7SThomas Huth { 769423576f7SThomas Huth cpu_synchronize_state(CPU(cpu)); 770423576f7SThomas Huth cpu->env.spr[SPR_SPRG0] = args[0]; 771423576f7SThomas Huth 772423576f7SThomas Huth return H_SUCCESS; 773423576f7SThomas Huth } 774423576f7SThomas Huth 775ce2918cbSDavid Gibson static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 7769f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 7779f64bd8aSPaolo Bonzini { 778af08a58fSThomas Huth if (!has_spr(cpu, SPR_DABR)) { 779af08a58fSThomas Huth return H_HARDWARE; /* DABR register not available */ 780af08a58fSThomas Huth } 781af08a58fSThomas Huth cpu_synchronize_state(CPU(cpu)); 782af08a58fSThomas Huth 783af08a58fSThomas Huth if (has_spr(cpu, SPR_DABRX)) { 784af08a58fSThomas Huth cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 785af08a58fSThomas Huth } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 786af08a58fSThomas Huth return H_RESERVED_DABR; 787af08a58fSThomas Huth } 788af08a58fSThomas Huth 789af08a58fSThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 790af08a58fSThomas Huth return H_SUCCESS; 7919f64bd8aSPaolo Bonzini } 7929f64bd8aSPaolo Bonzini 793ce2918cbSDavid Gibson static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 794e49ff266SThomas Huth target_ulong opcode, target_ulong *args) 795e49ff266SThomas Huth { 796e49ff266SThomas Huth target_ulong dabrx = args[1]; 797e49ff266SThomas Huth 798e49ff266SThomas Huth if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { 799e49ff266SThomas Huth return H_HARDWARE; 800e49ff266SThomas Huth } 801e49ff266SThomas Huth 802e49ff266SThomas Huth if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 803e49ff266SThomas Huth || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 804e49ff266SThomas Huth return H_PARAMETER; 805e49ff266SThomas Huth } 806e49ff266SThomas Huth 807e49ff266SThomas Huth cpu_synchronize_state(CPU(cpu)); 808e49ff266SThomas Huth cpu->env.spr[SPR_DABRX] = dabrx; 809e49ff266SThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 810e49ff266SThomas Huth 811e49ff266SThomas Huth return H_SUCCESS; 812e49ff266SThomas Huth } 813e49ff266SThomas Huth 814ce2918cbSDavid Gibson static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, 8153240dd9aSThomas Huth target_ulong opcode, target_ulong *args) 8163240dd9aSThomas Huth { 8173240dd9aSThomas Huth target_ulong flags = args[0]; 8183240dd9aSThomas Huth hwaddr dst = args[1]; 8193240dd9aSThomas Huth hwaddr src = args[2]; 8203240dd9aSThomas Huth hwaddr len = TARGET_PAGE_SIZE; 8213240dd9aSThomas Huth uint8_t *pdst, *psrc; 8223240dd9aSThomas Huth target_long ret = H_SUCCESS; 8233240dd9aSThomas Huth 8243240dd9aSThomas Huth if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 8253240dd9aSThomas Huth | H_COPY_PAGE | H_ZERO_PAGE)) { 8263240dd9aSThomas Huth qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 8273240dd9aSThomas Huth flags); 8283240dd9aSThomas Huth return H_PARAMETER; 8293240dd9aSThomas Huth } 8303240dd9aSThomas Huth 8313240dd9aSThomas Huth /* Map-in destination */ 8323240dd9aSThomas Huth if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 8333240dd9aSThomas Huth return H_PARAMETER; 8343240dd9aSThomas Huth } 8353240dd9aSThomas Huth pdst = cpu_physical_memory_map(dst, &len, 1); 8363240dd9aSThomas Huth if (!pdst || len != TARGET_PAGE_SIZE) { 8373240dd9aSThomas Huth return H_PARAMETER; 8383240dd9aSThomas Huth } 8393240dd9aSThomas Huth 8403240dd9aSThomas Huth if (flags & H_COPY_PAGE) { 8413240dd9aSThomas Huth /* Map-in source, copy to destination, and unmap source again */ 8423240dd9aSThomas Huth if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 8433240dd9aSThomas Huth ret = H_PARAMETER; 8443240dd9aSThomas Huth goto unmap_out; 8453240dd9aSThomas Huth } 8463240dd9aSThomas Huth psrc = cpu_physical_memory_map(src, &len, 0); 8473240dd9aSThomas Huth if (!psrc || len != TARGET_PAGE_SIZE) { 8483240dd9aSThomas Huth ret = H_PARAMETER; 8493240dd9aSThomas Huth goto unmap_out; 8503240dd9aSThomas Huth } 8513240dd9aSThomas Huth memcpy(pdst, psrc, len); 8523240dd9aSThomas Huth cpu_physical_memory_unmap(psrc, len, 0, len); 8533240dd9aSThomas Huth } else if (flags & H_ZERO_PAGE) { 8543240dd9aSThomas Huth memset(pdst, 0, len); /* Just clear the destination page */ 8553240dd9aSThomas Huth } 8563240dd9aSThomas Huth 8573240dd9aSThomas Huth if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 8583240dd9aSThomas Huth kvmppc_dcbst_range(cpu, pdst, len); 8593240dd9aSThomas Huth } 8603240dd9aSThomas Huth if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 8613240dd9aSThomas Huth if (kvm_enabled()) { 8623240dd9aSThomas Huth kvmppc_icbi_range(cpu, pdst, len); 8633240dd9aSThomas Huth } else { 8643240dd9aSThomas Huth tb_flush(CPU(cpu)); 8653240dd9aSThomas Huth } 8663240dd9aSThomas Huth } 8673240dd9aSThomas Huth 8683240dd9aSThomas Huth unmap_out: 8693240dd9aSThomas Huth cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 8703240dd9aSThomas Huth return ret; 8713240dd9aSThomas Huth } 8723240dd9aSThomas Huth 8739f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 8749f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 8759f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 8769f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 8779f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 8789f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 8799f64bd8aSPaolo Bonzini 8807388efafSDavid Gibson static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) 8819f64bd8aSPaolo Bonzini { 8827388efafSDavid Gibson CPUState *cs = CPU(cpu); 8837388efafSDavid Gibson CPUPPCState *env = &cpu->env; 884ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 8859f64bd8aSPaolo Bonzini uint16_t size; 8869f64bd8aSPaolo Bonzini uint8_t tmp; 8879f64bd8aSPaolo Bonzini 8889f64bd8aSPaolo Bonzini if (vpa == 0) { 8899f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 8909f64bd8aSPaolo Bonzini return H_HARDWARE; 8919f64bd8aSPaolo Bonzini } 8929f64bd8aSPaolo Bonzini 8939f64bd8aSPaolo Bonzini if (vpa % env->dcache_line_size) { 8949f64bd8aSPaolo Bonzini return H_PARAMETER; 8959f64bd8aSPaolo Bonzini } 8969f64bd8aSPaolo Bonzini /* FIXME: bounds check the address */ 8979f64bd8aSPaolo Bonzini 89841701aa4SEdgar E. Iglesias size = lduw_be_phys(cs->as, vpa + 0x4); 8999f64bd8aSPaolo Bonzini 9009f64bd8aSPaolo Bonzini if (size < VPA_MIN_SIZE) { 9019f64bd8aSPaolo Bonzini return H_PARAMETER; 9029f64bd8aSPaolo Bonzini } 9039f64bd8aSPaolo Bonzini 9049f64bd8aSPaolo Bonzini /* VPA is not allowed to cross a page boundary */ 9059f64bd8aSPaolo Bonzini if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 9069f64bd8aSPaolo Bonzini return H_PARAMETER; 9079f64bd8aSPaolo Bonzini } 9089f64bd8aSPaolo Bonzini 9097388efafSDavid Gibson spapr_cpu->vpa_addr = vpa; 9109f64bd8aSPaolo Bonzini 9117388efafSDavid Gibson tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET); 9129f64bd8aSPaolo Bonzini tmp |= VPA_SHARED_PROC_VAL; 9137388efafSDavid Gibson stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 9149f64bd8aSPaolo Bonzini 9159f64bd8aSPaolo Bonzini return H_SUCCESS; 9169f64bd8aSPaolo Bonzini } 9179f64bd8aSPaolo Bonzini 9187388efafSDavid Gibson static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) 9199f64bd8aSPaolo Bonzini { 920ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 9217388efafSDavid Gibson 9227388efafSDavid Gibson if (spapr_cpu->slb_shadow_addr) { 9239f64bd8aSPaolo Bonzini return H_RESOURCE; 9249f64bd8aSPaolo Bonzini } 9259f64bd8aSPaolo Bonzini 9267388efafSDavid Gibson if (spapr_cpu->dtl_addr) { 9279f64bd8aSPaolo Bonzini return H_RESOURCE; 9289f64bd8aSPaolo Bonzini } 9299f64bd8aSPaolo Bonzini 9307388efafSDavid Gibson spapr_cpu->vpa_addr = 0; 9319f64bd8aSPaolo Bonzini return H_SUCCESS; 9329f64bd8aSPaolo Bonzini } 9339f64bd8aSPaolo Bonzini 9347388efafSDavid Gibson static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 9359f64bd8aSPaolo Bonzini { 936ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 9379f64bd8aSPaolo Bonzini uint32_t size; 9389f64bd8aSPaolo Bonzini 9399f64bd8aSPaolo Bonzini if (addr == 0) { 9409f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 9419f64bd8aSPaolo Bonzini return H_HARDWARE; 9429f64bd8aSPaolo Bonzini } 9439f64bd8aSPaolo Bonzini 9447388efafSDavid Gibson size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 9459f64bd8aSPaolo Bonzini if (size < 0x8) { 9469f64bd8aSPaolo Bonzini return H_PARAMETER; 9479f64bd8aSPaolo Bonzini } 9489f64bd8aSPaolo Bonzini 9499f64bd8aSPaolo Bonzini if ((addr / 4096) != ((addr + size - 1) / 4096)) { 9509f64bd8aSPaolo Bonzini return H_PARAMETER; 9519f64bd8aSPaolo Bonzini } 9529f64bd8aSPaolo Bonzini 9537388efafSDavid Gibson if (!spapr_cpu->vpa_addr) { 9549f64bd8aSPaolo Bonzini return H_RESOURCE; 9559f64bd8aSPaolo Bonzini } 9569f64bd8aSPaolo Bonzini 9577388efafSDavid Gibson spapr_cpu->slb_shadow_addr = addr; 9587388efafSDavid Gibson spapr_cpu->slb_shadow_size = size; 9599f64bd8aSPaolo Bonzini 9609f64bd8aSPaolo Bonzini return H_SUCCESS; 9619f64bd8aSPaolo Bonzini } 9629f64bd8aSPaolo Bonzini 9637388efafSDavid Gibson static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 9649f64bd8aSPaolo Bonzini { 965ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 9667388efafSDavid Gibson 9677388efafSDavid Gibson spapr_cpu->slb_shadow_addr = 0; 9687388efafSDavid Gibson spapr_cpu->slb_shadow_size = 0; 9699f64bd8aSPaolo Bonzini return H_SUCCESS; 9709f64bd8aSPaolo Bonzini } 9719f64bd8aSPaolo Bonzini 9727388efafSDavid Gibson static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) 9739f64bd8aSPaolo Bonzini { 974ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 9759f64bd8aSPaolo Bonzini uint32_t size; 9769f64bd8aSPaolo Bonzini 9779f64bd8aSPaolo Bonzini if (addr == 0) { 9789f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with DTL at logical 0\n"); 9799f64bd8aSPaolo Bonzini return H_HARDWARE; 9809f64bd8aSPaolo Bonzini } 9819f64bd8aSPaolo Bonzini 9827388efafSDavid Gibson size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 9839f64bd8aSPaolo Bonzini 9849f64bd8aSPaolo Bonzini if (size < 48) { 9859f64bd8aSPaolo Bonzini return H_PARAMETER; 9869f64bd8aSPaolo Bonzini } 9879f64bd8aSPaolo Bonzini 9887388efafSDavid Gibson if (!spapr_cpu->vpa_addr) { 9899f64bd8aSPaolo Bonzini return H_RESOURCE; 9909f64bd8aSPaolo Bonzini } 9919f64bd8aSPaolo Bonzini 9927388efafSDavid Gibson spapr_cpu->dtl_addr = addr; 9937388efafSDavid Gibson spapr_cpu->dtl_size = size; 9949f64bd8aSPaolo Bonzini 9959f64bd8aSPaolo Bonzini return H_SUCCESS; 9969f64bd8aSPaolo Bonzini } 9979f64bd8aSPaolo Bonzini 9987388efafSDavid Gibson static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) 9999f64bd8aSPaolo Bonzini { 1000ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 10017388efafSDavid Gibson 10027388efafSDavid Gibson spapr_cpu->dtl_addr = 0; 10037388efafSDavid Gibson spapr_cpu->dtl_size = 0; 10049f64bd8aSPaolo Bonzini 10059f64bd8aSPaolo Bonzini return H_SUCCESS; 10069f64bd8aSPaolo Bonzini } 10079f64bd8aSPaolo Bonzini 1008ce2918cbSDavid Gibson static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr, 10099f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 10109f64bd8aSPaolo Bonzini { 10119f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 10129f64bd8aSPaolo Bonzini target_ulong procno = args[1]; 10139f64bd8aSPaolo Bonzini target_ulong vpa = args[2]; 10149f64bd8aSPaolo Bonzini target_ulong ret = H_PARAMETER; 10150f20ba62SAlexey Kardashevskiy PowerPCCPU *tcpu; 10169f64bd8aSPaolo Bonzini 10172e886fb3SSam Bobroff tcpu = spapr_find_cpu(procno); 10189f64bd8aSPaolo Bonzini if (!tcpu) { 10199f64bd8aSPaolo Bonzini return H_PARAMETER; 10209f64bd8aSPaolo Bonzini } 10219f64bd8aSPaolo Bonzini 10229f64bd8aSPaolo Bonzini switch (flags) { 10239f64bd8aSPaolo Bonzini case FLAGS_REGISTER_VPA: 10247388efafSDavid Gibson ret = register_vpa(tcpu, vpa); 10259f64bd8aSPaolo Bonzini break; 10269f64bd8aSPaolo Bonzini 10279f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_VPA: 10287388efafSDavid Gibson ret = deregister_vpa(tcpu, vpa); 10299f64bd8aSPaolo Bonzini break; 10309f64bd8aSPaolo Bonzini 10319f64bd8aSPaolo Bonzini case FLAGS_REGISTER_SLBSHADOW: 10327388efafSDavid Gibson ret = register_slb_shadow(tcpu, vpa); 10339f64bd8aSPaolo Bonzini break; 10349f64bd8aSPaolo Bonzini 10359f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_SLBSHADOW: 10367388efafSDavid Gibson ret = deregister_slb_shadow(tcpu, vpa); 10379f64bd8aSPaolo Bonzini break; 10389f64bd8aSPaolo Bonzini 10399f64bd8aSPaolo Bonzini case FLAGS_REGISTER_DTL: 10407388efafSDavid Gibson ret = register_dtl(tcpu, vpa); 10419f64bd8aSPaolo Bonzini break; 10429f64bd8aSPaolo Bonzini 10439f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_DTL: 10447388efafSDavid Gibson ret = deregister_dtl(tcpu, vpa); 10459f64bd8aSPaolo Bonzini break; 10469f64bd8aSPaolo Bonzini } 10479f64bd8aSPaolo Bonzini 10489f64bd8aSPaolo Bonzini return ret; 10499f64bd8aSPaolo Bonzini } 10509f64bd8aSPaolo Bonzini 1051ce2918cbSDavid Gibson static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, 10529f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 10539f64bd8aSPaolo Bonzini { 10549f64bd8aSPaolo Bonzini CPUPPCState *env = &cpu->env; 10559f64bd8aSPaolo Bonzini CPUState *cs = CPU(cpu); 10563a6e6224SNicholas Piggin SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 10579f64bd8aSPaolo Bonzini 10589f64bd8aSPaolo Bonzini env->msr |= (1ULL << MSR_EE); 10599f64bd8aSPaolo Bonzini hreg_compute_hflags(env); 10603a6e6224SNicholas Piggin 10613a6e6224SNicholas Piggin if (spapr_cpu->prod) { 10623a6e6224SNicholas Piggin spapr_cpu->prod = false; 10633a6e6224SNicholas Piggin return H_SUCCESS; 10643a6e6224SNicholas Piggin } 10653a6e6224SNicholas Piggin 10669f64bd8aSPaolo Bonzini if (!cpu_has_work(cs)) { 1067259186a7SAndreas Färber cs->halted = 1; 106827103424SAndreas Färber cs->exception_index = EXCP_HLT; 10699f64bd8aSPaolo Bonzini cs->exit_request = 1; 10709f64bd8aSPaolo Bonzini } 10713a6e6224SNicholas Piggin 10723a6e6224SNicholas Piggin return H_SUCCESS; 10733a6e6224SNicholas Piggin } 10743a6e6224SNicholas Piggin 107510741314SNicholas Piggin /* 107610741314SNicholas Piggin * Confer to self, aka join. Cede could use the same pattern as well, if 107710741314SNicholas Piggin * EXCP_HLT can be changed to ECXP_HALTED. 107810741314SNicholas Piggin */ 107910741314SNicholas Piggin static target_ulong h_confer_self(PowerPCCPU *cpu) 108010741314SNicholas Piggin { 108110741314SNicholas Piggin CPUState *cs = CPU(cpu); 108210741314SNicholas Piggin SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 108310741314SNicholas Piggin 108410741314SNicholas Piggin if (spapr_cpu->prod) { 108510741314SNicholas Piggin spapr_cpu->prod = false; 108610741314SNicholas Piggin return H_SUCCESS; 108710741314SNicholas Piggin } 108810741314SNicholas Piggin cs->halted = 1; 108910741314SNicholas Piggin cs->exception_index = EXCP_HALTED; 109010741314SNicholas Piggin cs->exit_request = 1; 109110741314SNicholas Piggin 109210741314SNicholas Piggin return H_SUCCESS; 109310741314SNicholas Piggin } 109410741314SNicholas Piggin 109510741314SNicholas Piggin static target_ulong h_join(PowerPCCPU *cpu, SpaprMachineState *spapr, 109610741314SNicholas Piggin target_ulong opcode, target_ulong *args) 109710741314SNicholas Piggin { 109810741314SNicholas Piggin CPUPPCState *env = &cpu->env; 109910741314SNicholas Piggin CPUState *cs; 110010741314SNicholas Piggin bool last_unjoined = true; 110110741314SNicholas Piggin 110210741314SNicholas Piggin if (env->msr & (1ULL << MSR_EE)) { 110310741314SNicholas Piggin return H_BAD_MODE; 110410741314SNicholas Piggin } 110510741314SNicholas Piggin 110610741314SNicholas Piggin /* 110710741314SNicholas Piggin * Must not join the last CPU running. Interestingly, no such restriction 110810741314SNicholas Piggin * for H_CONFER-to-self, but that is probably not intended to be used 110910741314SNicholas Piggin * when H_JOIN is available. 111010741314SNicholas Piggin */ 111110741314SNicholas Piggin CPU_FOREACH(cs) { 111210741314SNicholas Piggin PowerPCCPU *c = POWERPC_CPU(cs); 111310741314SNicholas Piggin CPUPPCState *e = &c->env; 111410741314SNicholas Piggin if (c == cpu) { 111510741314SNicholas Piggin continue; 111610741314SNicholas Piggin } 111710741314SNicholas Piggin 111810741314SNicholas Piggin /* Don't have a way to indicate joined, so use halted && MSR[EE]=0 */ 111910741314SNicholas Piggin if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { 112010741314SNicholas Piggin last_unjoined = false; 112110741314SNicholas Piggin break; 112210741314SNicholas Piggin } 112310741314SNicholas Piggin } 112410741314SNicholas Piggin if (last_unjoined) { 112510741314SNicholas Piggin return H_CONTINUE; 112610741314SNicholas Piggin } 112710741314SNicholas Piggin 112810741314SNicholas Piggin return h_confer_self(cpu); 112910741314SNicholas Piggin } 113010741314SNicholas Piggin 1131e8ce0e40SNicholas Piggin static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr, 1132e8ce0e40SNicholas Piggin target_ulong opcode, target_ulong *args) 1133e8ce0e40SNicholas Piggin { 1134e8ce0e40SNicholas Piggin target_long target = args[0]; 1135e8ce0e40SNicholas Piggin uint32_t dispatch = args[1]; 1136e8ce0e40SNicholas Piggin CPUState *cs = CPU(cpu); 1137e8ce0e40SNicholas Piggin SpaprCpuState *spapr_cpu; 1138e8ce0e40SNicholas Piggin 1139e8ce0e40SNicholas Piggin /* 1140e8ce0e40SNicholas Piggin * -1 means confer to all other CPUs without dispatch counter check, 1141e8ce0e40SNicholas Piggin * otherwise it's a targeted confer. 1142e8ce0e40SNicholas Piggin */ 1143e8ce0e40SNicholas Piggin if (target != -1) { 1144e8ce0e40SNicholas Piggin PowerPCCPU *target_cpu = spapr_find_cpu(target); 1145e8ce0e40SNicholas Piggin uint32_t target_dispatch; 1146e8ce0e40SNicholas Piggin 1147e8ce0e40SNicholas Piggin if (!target_cpu) { 1148e8ce0e40SNicholas Piggin return H_PARAMETER; 1149e8ce0e40SNicholas Piggin } 1150e8ce0e40SNicholas Piggin 1151e8ce0e40SNicholas Piggin /* 1152e8ce0e40SNicholas Piggin * target == self is a special case, we wait until prodded, without 1153e8ce0e40SNicholas Piggin * dispatch counter check. 1154e8ce0e40SNicholas Piggin */ 1155e8ce0e40SNicholas Piggin if (cpu == target_cpu) { 115610741314SNicholas Piggin return h_confer_self(cpu); 1157e8ce0e40SNicholas Piggin } 1158e8ce0e40SNicholas Piggin 115910741314SNicholas Piggin spapr_cpu = spapr_cpu_state(target_cpu); 1160e8ce0e40SNicholas Piggin if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) { 1161e8ce0e40SNicholas Piggin return H_SUCCESS; 1162e8ce0e40SNicholas Piggin } 1163e8ce0e40SNicholas Piggin 1164e8ce0e40SNicholas Piggin target_dispatch = ldl_be_phys(cs->as, 1165e8ce0e40SNicholas Piggin spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 1166e8ce0e40SNicholas Piggin if (target_dispatch != dispatch) { 1167e8ce0e40SNicholas Piggin return H_SUCCESS; 1168e8ce0e40SNicholas Piggin } 1169e8ce0e40SNicholas Piggin 1170e8ce0e40SNicholas Piggin /* 1171e8ce0e40SNicholas Piggin * The targeted confer does not do anything special beyond yielding 1172e8ce0e40SNicholas Piggin * the current vCPU, but even this should be better than nothing. 1173e8ce0e40SNicholas Piggin * At least for single-threaded tcg, it gives the target a chance to 1174e8ce0e40SNicholas Piggin * run before we run again. Multi-threaded tcg does not really do 1175e8ce0e40SNicholas Piggin * anything with EXCP_YIELD yet. 1176e8ce0e40SNicholas Piggin */ 1177e8ce0e40SNicholas Piggin } 1178e8ce0e40SNicholas Piggin 1179e8ce0e40SNicholas Piggin cs->exception_index = EXCP_YIELD; 1180e8ce0e40SNicholas Piggin cs->exit_request = 1; 1181e8ce0e40SNicholas Piggin cpu_loop_exit(cs); 1182e8ce0e40SNicholas Piggin 1183e8ce0e40SNicholas Piggin return H_SUCCESS; 1184e8ce0e40SNicholas Piggin } 1185e8ce0e40SNicholas Piggin 11863a6e6224SNicholas Piggin static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr, 11873a6e6224SNicholas Piggin target_ulong opcode, target_ulong *args) 11883a6e6224SNicholas Piggin { 11893a6e6224SNicholas Piggin target_long target = args[0]; 11903a6e6224SNicholas Piggin PowerPCCPU *tcpu; 11913a6e6224SNicholas Piggin CPUState *cs; 11923a6e6224SNicholas Piggin SpaprCpuState *spapr_cpu; 11933a6e6224SNicholas Piggin 11943a6e6224SNicholas Piggin tcpu = spapr_find_cpu(target); 11953a6e6224SNicholas Piggin cs = CPU(tcpu); 11963a6e6224SNicholas Piggin if (!cs) { 11973a6e6224SNicholas Piggin return H_PARAMETER; 11983a6e6224SNicholas Piggin } 11993a6e6224SNicholas Piggin 12003a6e6224SNicholas Piggin spapr_cpu = spapr_cpu_state(tcpu); 12013a6e6224SNicholas Piggin spapr_cpu->prod = true; 12023a6e6224SNicholas Piggin cs->halted = 0; 12033a6e6224SNicholas Piggin qemu_cpu_kick(cs); 12043a6e6224SNicholas Piggin 12059f64bd8aSPaolo Bonzini return H_SUCCESS; 12069f64bd8aSPaolo Bonzini } 12079f64bd8aSPaolo Bonzini 1208ce2918cbSDavid Gibson static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, 12099f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 12109f64bd8aSPaolo Bonzini { 12119f64bd8aSPaolo Bonzini target_ulong rtas_r3 = args[0]; 12124fe822e0SAlexey Kardashevskiy uint32_t token = rtas_ld(rtas_r3, 0); 12134fe822e0SAlexey Kardashevskiy uint32_t nargs = rtas_ld(rtas_r3, 1); 12144fe822e0SAlexey Kardashevskiy uint32_t nret = rtas_ld(rtas_r3, 2); 12159f64bd8aSPaolo Bonzini 1216210b580bSAnthony Liguori return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 12179f64bd8aSPaolo Bonzini nret, rtas_r3 + 12 + 4*nargs); 12189f64bd8aSPaolo Bonzini } 12199f64bd8aSPaolo Bonzini 1220ce2918cbSDavid Gibson static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr, 12219f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 12229f64bd8aSPaolo Bonzini { 1223fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 12249f64bd8aSPaolo Bonzini target_ulong size = args[0]; 12259f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 12269f64bd8aSPaolo Bonzini 12279f64bd8aSPaolo Bonzini switch (size) { 12289f64bd8aSPaolo Bonzini case 1: 12292c17449bSEdgar E. Iglesias args[0] = ldub_phys(cs->as, addr); 12309f64bd8aSPaolo Bonzini return H_SUCCESS; 12319f64bd8aSPaolo Bonzini case 2: 123241701aa4SEdgar E. Iglesias args[0] = lduw_phys(cs->as, addr); 12339f64bd8aSPaolo Bonzini return H_SUCCESS; 12349f64bd8aSPaolo Bonzini case 4: 1235fdfba1a2SEdgar E. Iglesias args[0] = ldl_phys(cs->as, addr); 12369f64bd8aSPaolo Bonzini return H_SUCCESS; 12379f64bd8aSPaolo Bonzini case 8: 12382c17449bSEdgar E. Iglesias args[0] = ldq_phys(cs->as, addr); 12399f64bd8aSPaolo Bonzini return H_SUCCESS; 12409f64bd8aSPaolo Bonzini } 12419f64bd8aSPaolo Bonzini return H_PARAMETER; 12429f64bd8aSPaolo Bonzini } 12439f64bd8aSPaolo Bonzini 1244ce2918cbSDavid Gibson static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr, 12459f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 12469f64bd8aSPaolo Bonzini { 1247f606604fSEdgar E. Iglesias CPUState *cs = CPU(cpu); 1248f606604fSEdgar E. Iglesias 12499f64bd8aSPaolo Bonzini target_ulong size = args[0]; 12509f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 12519f64bd8aSPaolo Bonzini target_ulong val = args[2]; 12529f64bd8aSPaolo Bonzini 12539f64bd8aSPaolo Bonzini switch (size) { 12549f64bd8aSPaolo Bonzini case 1: 1255db3be60dSEdgar E. Iglesias stb_phys(cs->as, addr, val); 12569f64bd8aSPaolo Bonzini return H_SUCCESS; 12579f64bd8aSPaolo Bonzini case 2: 12585ce5944dSEdgar E. Iglesias stw_phys(cs->as, addr, val); 12599f64bd8aSPaolo Bonzini return H_SUCCESS; 12609f64bd8aSPaolo Bonzini case 4: 1261ab1da857SEdgar E. Iglesias stl_phys(cs->as, addr, val); 12629f64bd8aSPaolo Bonzini return H_SUCCESS; 12639f64bd8aSPaolo Bonzini case 8: 1264f606604fSEdgar E. Iglesias stq_phys(cs->as, addr, val); 12659f64bd8aSPaolo Bonzini return H_SUCCESS; 12669f64bd8aSPaolo Bonzini } 12679f64bd8aSPaolo Bonzini return H_PARAMETER; 12689f64bd8aSPaolo Bonzini } 12699f64bd8aSPaolo Bonzini 1270ce2918cbSDavid Gibson static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr, 12719f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 12729f64bd8aSPaolo Bonzini { 1273fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 1274fdfba1a2SEdgar E. Iglesias 12759f64bd8aSPaolo Bonzini target_ulong dst = args[0]; /* Destination address */ 12769f64bd8aSPaolo Bonzini target_ulong src = args[1]; /* Source address */ 12779f64bd8aSPaolo Bonzini target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 12789f64bd8aSPaolo Bonzini target_ulong count = args[3]; /* Element count */ 12799f64bd8aSPaolo Bonzini target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 12809f64bd8aSPaolo Bonzini uint64_t tmp; 12819f64bd8aSPaolo Bonzini unsigned int mask = (1 << esize) - 1; 12829f64bd8aSPaolo Bonzini int step = 1 << esize; 12839f64bd8aSPaolo Bonzini 12849f64bd8aSPaolo Bonzini if (count > 0x80000000) { 12859f64bd8aSPaolo Bonzini return H_PARAMETER; 12869f64bd8aSPaolo Bonzini } 12879f64bd8aSPaolo Bonzini 12889f64bd8aSPaolo Bonzini if ((dst & mask) || (src & mask) || (op > 1)) { 12899f64bd8aSPaolo Bonzini return H_PARAMETER; 12909f64bd8aSPaolo Bonzini } 12919f64bd8aSPaolo Bonzini 12929f64bd8aSPaolo Bonzini if (dst >= src && dst < (src + (count << esize))) { 12939f64bd8aSPaolo Bonzini dst = dst + ((count - 1) << esize); 12949f64bd8aSPaolo Bonzini src = src + ((count - 1) << esize); 12959f64bd8aSPaolo Bonzini step = -step; 12969f64bd8aSPaolo Bonzini } 12979f64bd8aSPaolo Bonzini 12989f64bd8aSPaolo Bonzini while (count--) { 12999f64bd8aSPaolo Bonzini switch (esize) { 13009f64bd8aSPaolo Bonzini case 0: 13012c17449bSEdgar E. Iglesias tmp = ldub_phys(cs->as, src); 13029f64bd8aSPaolo Bonzini break; 13039f64bd8aSPaolo Bonzini case 1: 130441701aa4SEdgar E. Iglesias tmp = lduw_phys(cs->as, src); 13059f64bd8aSPaolo Bonzini break; 13069f64bd8aSPaolo Bonzini case 2: 1307fdfba1a2SEdgar E. Iglesias tmp = ldl_phys(cs->as, src); 13089f64bd8aSPaolo Bonzini break; 13099f64bd8aSPaolo Bonzini case 3: 13102c17449bSEdgar E. Iglesias tmp = ldq_phys(cs->as, src); 13119f64bd8aSPaolo Bonzini break; 13129f64bd8aSPaolo Bonzini default: 13139f64bd8aSPaolo Bonzini return H_PARAMETER; 13149f64bd8aSPaolo Bonzini } 13159f64bd8aSPaolo Bonzini if (op == 1) { 13169f64bd8aSPaolo Bonzini tmp = ~tmp; 13179f64bd8aSPaolo Bonzini } 13189f64bd8aSPaolo Bonzini switch (esize) { 13199f64bd8aSPaolo Bonzini case 0: 1320db3be60dSEdgar E. Iglesias stb_phys(cs->as, dst, tmp); 13219f64bd8aSPaolo Bonzini break; 13229f64bd8aSPaolo Bonzini case 1: 13235ce5944dSEdgar E. Iglesias stw_phys(cs->as, dst, tmp); 13249f64bd8aSPaolo Bonzini break; 13259f64bd8aSPaolo Bonzini case 2: 1326ab1da857SEdgar E. Iglesias stl_phys(cs->as, dst, tmp); 13279f64bd8aSPaolo Bonzini break; 13289f64bd8aSPaolo Bonzini case 3: 1329f606604fSEdgar E. Iglesias stq_phys(cs->as, dst, tmp); 13309f64bd8aSPaolo Bonzini break; 13319f64bd8aSPaolo Bonzini } 13329f64bd8aSPaolo Bonzini dst = dst + step; 13339f64bd8aSPaolo Bonzini src = src + step; 13349f64bd8aSPaolo Bonzini } 13359f64bd8aSPaolo Bonzini 13369f64bd8aSPaolo Bonzini return H_SUCCESS; 13379f64bd8aSPaolo Bonzini } 13389f64bd8aSPaolo Bonzini 1339ce2918cbSDavid Gibson static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr, 13409f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 13419f64bd8aSPaolo Bonzini { 13429f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 13439f64bd8aSPaolo Bonzini return H_SUCCESS; 13449f64bd8aSPaolo Bonzini } 13459f64bd8aSPaolo Bonzini 1346ce2918cbSDavid Gibson static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, 13479f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 13489f64bd8aSPaolo Bonzini { 13499f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 13509f64bd8aSPaolo Bonzini return H_SUCCESS; 13519f64bd8aSPaolo Bonzini } 13529f64bd8aSPaolo Bonzini 13537d0cd464SPeter Maydell static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 1354c4015bbdSAlexey Kardashevskiy target_ulong mflags, 1355c4015bbdSAlexey Kardashevskiy target_ulong value1, 1356c4015bbdSAlexey Kardashevskiy target_ulong value2) 135742561bf2SAnton Blanchard { 135842561bf2SAnton Blanchard if (value1) { 1359c4015bbdSAlexey Kardashevskiy return H_P3; 136042561bf2SAnton Blanchard } 136142561bf2SAnton Blanchard if (value2) { 1362c4015bbdSAlexey Kardashevskiy return H_P4; 136342561bf2SAnton Blanchard } 1364c4015bbdSAlexey Kardashevskiy 136542561bf2SAnton Blanchard switch (mflags) { 136642561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_BIG: 136700fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(0, LPCR_ILE); 1368eefaccc0SDavid Gibson spapr_pci_switch_vga(true); 1369c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 137042561bf2SAnton Blanchard 137142561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_LITTLE: 137200fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); 1373eefaccc0SDavid Gibson spapr_pci_switch_vga(false); 1374c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 1375c4015bbdSAlexey Kardashevskiy } 1376c4015bbdSAlexey Kardashevskiy 1377c4015bbdSAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 1378c4015bbdSAlexey Kardashevskiy } 1379c4015bbdSAlexey Kardashevskiy 13807d0cd464SPeter Maydell static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 1381d5ac4f54SAlexey Kardashevskiy target_ulong mflags, 1382d5ac4f54SAlexey Kardashevskiy target_ulong value1, 1383d5ac4f54SAlexey Kardashevskiy target_ulong value2) 1384d5ac4f54SAlexey Kardashevskiy { 1385d5ac4f54SAlexey Kardashevskiy PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 1386d5ac4f54SAlexey Kardashevskiy 1387d5ac4f54SAlexey Kardashevskiy if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 1388d5ac4f54SAlexey Kardashevskiy return H_P2; 1389d5ac4f54SAlexey Kardashevskiy } 1390d5ac4f54SAlexey Kardashevskiy if (value1) { 1391d5ac4f54SAlexey Kardashevskiy return H_P3; 1392d5ac4f54SAlexey Kardashevskiy } 1393d5ac4f54SAlexey Kardashevskiy if (value2) { 1394d5ac4f54SAlexey Kardashevskiy return H_P4; 1395d5ac4f54SAlexey Kardashevskiy } 1396d5ac4f54SAlexey Kardashevskiy 13975c94b2a5SCédric Le Goater if (mflags == AIL_RESERVED) { 1398d5ac4f54SAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 1399d5ac4f54SAlexey Kardashevskiy } 1400d5ac4f54SAlexey Kardashevskiy 140100fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); 1402d5ac4f54SAlexey Kardashevskiy 1403d5ac4f54SAlexey Kardashevskiy return H_SUCCESS; 1404d5ac4f54SAlexey Kardashevskiy } 1405d5ac4f54SAlexey Kardashevskiy 1406ce2918cbSDavid Gibson static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, 1407c4015bbdSAlexey Kardashevskiy target_ulong opcode, target_ulong *args) 1408c4015bbdSAlexey Kardashevskiy { 1409c4015bbdSAlexey Kardashevskiy target_ulong resource = args[1]; 1410c4015bbdSAlexey Kardashevskiy target_ulong ret = H_P2; 1411c4015bbdSAlexey Kardashevskiy 1412c4015bbdSAlexey Kardashevskiy switch (resource) { 1413c4015bbdSAlexey Kardashevskiy case H_SET_MODE_RESOURCE_LE: 14147d0cd464SPeter Maydell ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); 141542561bf2SAnton Blanchard break; 1416d5ac4f54SAlexey Kardashevskiy case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 14177d0cd464SPeter Maydell ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 1418d5ac4f54SAlexey Kardashevskiy args[2], args[3]); 1419d5ac4f54SAlexey Kardashevskiy break; 142042561bf2SAnton Blanchard } 142142561bf2SAnton Blanchard 142242561bf2SAnton Blanchard return ret; 142342561bf2SAnton Blanchard } 142442561bf2SAnton Blanchard 1425ce2918cbSDavid Gibson static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, 1426d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 1427d77a98b0SSuraj Jitindar Singh { 1428d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1429d77a98b0SSuraj Jitindar Singh opcode, " (H_CLEAN_SLB)"); 1430d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 1431d77a98b0SSuraj Jitindar Singh } 1432d77a98b0SSuraj Jitindar Singh 1433ce2918cbSDavid Gibson static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr, 1434d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 1435d77a98b0SSuraj Jitindar Singh { 1436d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1437d77a98b0SSuraj Jitindar Singh opcode, " (H_INVALIDATE_PID)"); 1438d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 1439d77a98b0SSuraj Jitindar Singh } 1440d77a98b0SSuraj Jitindar Singh 1441ce2918cbSDavid Gibson static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, 1442b4db5413SSuraj Jitindar Singh uint64_t patbe_old, uint64_t patbe_new) 1443b4db5413SSuraj Jitindar Singh { 1444b4db5413SSuraj Jitindar Singh /* 1445b4db5413SSuraj Jitindar Singh * We have 4 Options: 1446b4db5413SSuraj Jitindar Singh * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 1447b4db5413SSuraj Jitindar Singh * HASH->RADIX : Free HPT 1448b4db5413SSuraj Jitindar Singh * RADIX->HASH : Allocate HPT 1449b4db5413SSuraj Jitindar Singh * NOTHING->HASH : Allocate HPT 1450b4db5413SSuraj Jitindar Singh * Note: NOTHING implies the case where we said the guest could choose 1451b4db5413SSuraj Jitindar Singh * later and so assumed radix and now it's called H_REG_PROC_TBL 1452b4db5413SSuraj Jitindar Singh */ 1453b4db5413SSuraj Jitindar Singh 145479825f4dSBenjamin Herrenschmidt if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) { 1455b4db5413SSuraj Jitindar Singh /* We assume RADIX, so this catches all the "Do Nothing" cases */ 145679825f4dSBenjamin Herrenschmidt } else if (!(patbe_old & PATE1_GR)) { 1457b4db5413SSuraj Jitindar Singh /* HASH->RADIX : Free HPT */ 145806ec79e8SBharata B Rao spapr_free_hpt(spapr); 145979825f4dSBenjamin Herrenschmidt } else if (!(patbe_new & PATE1_GR)) { 1460b4db5413SSuraj Jitindar Singh /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 1461b4db5413SSuraj Jitindar Singh spapr_setup_hpt_and_vrma(spapr); 1462b4db5413SSuraj Jitindar Singh } 1463b4db5413SSuraj Jitindar Singh return; 1464b4db5413SSuraj Jitindar Singh } 1465b4db5413SSuraj Jitindar Singh 1466b4db5413SSuraj Jitindar Singh #define FLAGS_MASK 0x01FULL 1467b4db5413SSuraj Jitindar Singh #define FLAG_MODIFY 0x10 1468b4db5413SSuraj Jitindar Singh #define FLAG_REGISTER 0x08 1469b4db5413SSuraj Jitindar Singh #define FLAG_RADIX 0x04 1470b4db5413SSuraj Jitindar Singh #define FLAG_HASH_PROC_TBL 0x02 1471b4db5413SSuraj Jitindar Singh #define FLAG_GTSE 0x01 1472b4db5413SSuraj Jitindar Singh 1473d77a98b0SSuraj Jitindar Singh static target_ulong h_register_process_table(PowerPCCPU *cpu, 1474ce2918cbSDavid Gibson SpaprMachineState *spapr, 1475d77a98b0SSuraj Jitindar Singh target_ulong opcode, 1476d77a98b0SSuraj Jitindar Singh target_ulong *args) 1477d77a98b0SSuraj Jitindar Singh { 1478b4db5413SSuraj Jitindar Singh target_ulong flags = args[0]; 1479b4db5413SSuraj Jitindar Singh target_ulong proc_tbl = args[1]; 1480b4db5413SSuraj Jitindar Singh target_ulong page_size = args[2]; 1481b4db5413SSuraj Jitindar Singh target_ulong table_size = args[3]; 1482176dcceeSSuraj Jitindar Singh target_ulong update_lpcr = 0; 1483b4db5413SSuraj Jitindar Singh uint64_t cproc; 1484b4db5413SSuraj Jitindar Singh 1485b4db5413SSuraj Jitindar Singh if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 1486b4db5413SSuraj Jitindar Singh return H_PARAMETER; 1487b4db5413SSuraj Jitindar Singh } 1488b4db5413SSuraj Jitindar Singh if (flags & FLAG_MODIFY) { 1489b4db5413SSuraj Jitindar Singh if (flags & FLAG_REGISTER) { 1490b4db5413SSuraj Jitindar Singh if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 1491b4db5413SSuraj Jitindar Singh if (proc_tbl & 0xfff || proc_tbl >> 60) { 1492b4db5413SSuraj Jitindar Singh return H_P2; 1493b4db5413SSuraj Jitindar Singh } else if (page_size) { 1494b4db5413SSuraj Jitindar Singh return H_P3; 1495b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 1496b4db5413SSuraj Jitindar Singh return H_P4; 1497b4db5413SSuraj Jitindar Singh } 149879825f4dSBenjamin Herrenschmidt cproc = PATE1_GR | proc_tbl | table_size; 1499b4db5413SSuraj Jitindar Singh } else { /* Register new HPT process table */ 1500b4db5413SSuraj Jitindar Singh if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 1501b4db5413SSuraj Jitindar Singh /* TODO - Not Supported */ 1502b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 1503b4db5413SSuraj Jitindar Singh return H_PARAMETER; 1504b4db5413SSuraj Jitindar Singh } else { /* Hash with SLB */ 1505b4db5413SSuraj Jitindar Singh if (proc_tbl >> 38) { 1506b4db5413SSuraj Jitindar Singh return H_P2; 1507b4db5413SSuraj Jitindar Singh } else if (page_size & ~0x7) { 1508b4db5413SSuraj Jitindar Singh return H_P3; 1509b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 1510b4db5413SSuraj Jitindar Singh return H_P4; 1511b4db5413SSuraj Jitindar Singh } 1512b4db5413SSuraj Jitindar Singh } 1513b4db5413SSuraj Jitindar Singh cproc = (proc_tbl << 25) | page_size << 5 | table_size; 1514b4db5413SSuraj Jitindar Singh } 1515b4db5413SSuraj Jitindar Singh 1516b4db5413SSuraj Jitindar Singh } else { /* Deregister current process table */ 151779825f4dSBenjamin Herrenschmidt /* 151879825f4dSBenjamin Herrenschmidt * Set to benign value: (current GR) | 0. This allows 151979825f4dSBenjamin Herrenschmidt * deregistration in KVM to succeed even if the radix bit 152079825f4dSBenjamin Herrenschmidt * in flags doesn't match the radix bit in the old PATE. 152179825f4dSBenjamin Herrenschmidt */ 152279825f4dSBenjamin Herrenschmidt cproc = spapr->patb_entry & PATE1_GR; 1523b4db5413SSuraj Jitindar Singh } 1524b4db5413SSuraj Jitindar Singh } else { /* Maintain current registration */ 152579825f4dSBenjamin Herrenschmidt if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) { 1526b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 1527b4db5413SSuraj Jitindar Singh return H_PARAMETER; /* Existing Process Table Mismatch */ 1528b4db5413SSuraj Jitindar Singh } 1529b4db5413SSuraj Jitindar Singh cproc = spapr->patb_entry; 1530b4db5413SSuraj Jitindar Singh } 1531b4db5413SSuraj Jitindar Singh 1532b4db5413SSuraj Jitindar Singh /* Check if we need to setup OR free the hpt */ 1533b4db5413SSuraj Jitindar Singh spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 1534b4db5413SSuraj Jitindar Singh 1535b4db5413SSuraj Jitindar Singh spapr->patb_entry = cproc; /* Save new process table */ 15366de83307SSuraj Jitindar Singh 153700fd075eSBenjamin Herrenschmidt /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ 1538176dcceeSSuraj Jitindar Singh if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */ 1539176dcceeSSuraj Jitindar Singh update_lpcr |= (LPCR_UPRT | LPCR_HR); 1540176dcceeSSuraj Jitindar Singh else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ 1541176dcceeSSuraj Jitindar Singh update_lpcr |= LPCR_UPRT; 1542176dcceeSSuraj Jitindar Singh if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ 154349e9fdd7SDavid Gibson update_lpcr |= LPCR_GTSE; 154449e9fdd7SDavid Gibson 1545176dcceeSSuraj Jitindar Singh spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); 1546b4db5413SSuraj Jitindar Singh 1547b4db5413SSuraj Jitindar Singh if (kvm_enabled()) { 1548b4db5413SSuraj Jitindar Singh return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1549b4db5413SSuraj Jitindar Singh flags & FLAG_GTSE, cproc); 1550b4db5413SSuraj Jitindar Singh } 1551b4db5413SSuraj Jitindar Singh return H_SUCCESS; 1552d77a98b0SSuraj Jitindar Singh } 1553d77a98b0SSuraj Jitindar Singh 15541c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALL -1 15551c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 15561c7ad77eSNicholas Piggin 15571c7ad77eSNicholas Piggin static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1558ce2918cbSDavid Gibson SpaprMachineState *spapr, 15591c7ad77eSNicholas Piggin target_ulong opcode, target_ulong *args) 15601c7ad77eSNicholas Piggin { 15611c7ad77eSNicholas Piggin target_long target = args[0]; 15621c7ad77eSNicholas Piggin CPUState *cs; 15631c7ad77eSNicholas Piggin 15641c7ad77eSNicholas Piggin if (target < 0) { 15651c7ad77eSNicholas Piggin /* Broadcast */ 15661c7ad77eSNicholas Piggin if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 15671c7ad77eSNicholas Piggin return H_PARAMETER; 15681c7ad77eSNicholas Piggin } 15691c7ad77eSNicholas Piggin 15701c7ad77eSNicholas Piggin CPU_FOREACH(cs) { 15711c7ad77eSNicholas Piggin PowerPCCPU *c = POWERPC_CPU(cs); 15721c7ad77eSNicholas Piggin 15731c7ad77eSNicholas Piggin if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 15741c7ad77eSNicholas Piggin if (c == cpu) { 15751c7ad77eSNicholas Piggin continue; 15761c7ad77eSNicholas Piggin } 15771c7ad77eSNicholas Piggin } 15781c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 15791c7ad77eSNicholas Piggin } 15801c7ad77eSNicholas Piggin return H_SUCCESS; 15811c7ad77eSNicholas Piggin 15821c7ad77eSNicholas Piggin } else { 15831c7ad77eSNicholas Piggin /* Unicast */ 15842e886fb3SSam Bobroff cs = CPU(spapr_find_cpu(target)); 1585f57467e3SSam Bobroff if (cs) { 15861c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 15871c7ad77eSNicholas Piggin return H_SUCCESS; 15881c7ad77eSNicholas Piggin } 15891c7ad77eSNicholas Piggin return H_PARAMETER; 15901c7ad77eSNicholas Piggin } 15911c7ad77eSNicholas Piggin } 15921c7ad77eSNicholas Piggin 1593ce2918cbSDavid Gibson static uint32_t cas_check_pvr(SpaprMachineState *spapr, PowerPCCPU *cpu, 1594cc7b35b1SGreg Kurz target_ulong *addr, bool *raw_mode_supported, 1595cc7b35b1SGreg Kurz Error **errp) 15962a6593cbSAlexey Kardashevskiy { 1597152ef803SDavid Gibson bool explicit_match = false; /* Matched the CPU's real PVR */ 15987843c0d6SDavid Gibson uint32_t max_compat = spapr->max_compat_pvr; 1599152ef803SDavid Gibson uint32_t best_compat = 0; 1600152ef803SDavid Gibson int i; 16013794d548SAlexey Kardashevskiy 1602152ef803SDavid Gibson /* 1603152ef803SDavid Gibson * We scan the supplied table of PVRs looking for two things 1604152ef803SDavid Gibson * 1. Is our real CPU PVR in the list? 1605152ef803SDavid Gibson * 2. What's the "best" listed logical PVR 1606152ef803SDavid Gibson */ 1607152ef803SDavid Gibson for (i = 0; i < 512; ++i) { 16083794d548SAlexey Kardashevskiy uint32_t pvr, pvr_mask; 16093794d548SAlexey Kardashevskiy 161080c33d34SDavid Gibson pvr_mask = ldl_be_phys(&address_space_memory, *addr); 161180c33d34SDavid Gibson pvr = ldl_be_phys(&address_space_memory, *addr + 4); 161280c33d34SDavid Gibson *addr += 8; 16133794d548SAlexey Kardashevskiy 16143794d548SAlexey Kardashevskiy if (~pvr_mask & pvr) { 1615152ef803SDavid Gibson break; /* Terminator record */ 16163794d548SAlexey Kardashevskiy } 1617152ef803SDavid Gibson 1618152ef803SDavid Gibson if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1619152ef803SDavid Gibson explicit_match = true; 1620152ef803SDavid Gibson } else { 1621152ef803SDavid Gibson if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1622152ef803SDavid Gibson best_compat = pvr; 1623152ef803SDavid Gibson } 1624152ef803SDavid Gibson } 1625152ef803SDavid Gibson } 1626152ef803SDavid Gibson 1627152ef803SDavid Gibson if ((best_compat == 0) && (!explicit_match || max_compat)) { 1628152ef803SDavid Gibson /* We couldn't find a suitable compatibility mode, and either 1629152ef803SDavid Gibson * the guest doesn't support "raw" mode for this CPU, or raw 1630152ef803SDavid Gibson * mode is disabled because a maximum compat mode is set */ 163180c33d34SDavid Gibson error_setg(errp, "Couldn't negotiate a suitable PVR during CAS"); 163280c33d34SDavid Gibson return 0; 16333794d548SAlexey Kardashevskiy } 16343794d548SAlexey Kardashevskiy 1635cc7b35b1SGreg Kurz *raw_mode_supported = explicit_match; 1636cc7b35b1SGreg Kurz 16373794d548SAlexey Kardashevskiy /* Parsing finished */ 1638152ef803SDavid Gibson trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 16393794d548SAlexey Kardashevskiy 164080c33d34SDavid Gibson return best_compat; 164180c33d34SDavid Gibson } 164280c33d34SDavid Gibson 1643*4b63db12SGreg Kurz static bool spapr_transient_dev_before_cas(void) 16440c21e073SDavid Gibson { 1645*4b63db12SGreg Kurz Object *drc_container; 16460c21e073SDavid Gibson ObjectProperty *prop; 16470c21e073SDavid Gibson ObjectPropertyIterator iter; 16480c21e073SDavid Gibson 16490c21e073SDavid Gibson drc_container = container_get(object_get_root(), "/dr-connector"); 16500c21e073SDavid Gibson object_property_iter_init(&iter, drc_container); 16510c21e073SDavid Gibson while ((prop = object_property_iter_next(&iter))) { 1652*4b63db12SGreg Kurz SpaprDrc *drc; 1653*4b63db12SGreg Kurz 16540c21e073SDavid Gibson if (!strstart(prop->type, "link<", NULL)) { 16550c21e073SDavid Gibson continue; 16560c21e073SDavid Gibson } 1657*4b63db12SGreg Kurz drc = SPAPR_DR_CONNECTOR(object_property_get_link(drc_container, 1658*4b63db12SGreg Kurz prop->name, NULL)); 1659*4b63db12SGreg Kurz 1660*4b63db12SGreg Kurz if (spapr_drc_transient(drc)) { 16610c21e073SDavid Gibson return true; 16620c21e073SDavid Gibson } 16630c21e073SDavid Gibson } 16640c21e073SDavid Gibson return false; 16650c21e073SDavid Gibson } 16660c21e073SDavid Gibson 166780c33d34SDavid Gibson static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1668ce2918cbSDavid Gibson SpaprMachineState *spapr, 166980c33d34SDavid Gibson target_ulong opcode, 167080c33d34SDavid Gibson target_ulong *args) 167180c33d34SDavid Gibson { 167280c33d34SDavid Gibson /* Working address in data buffer */ 167380c33d34SDavid Gibson target_ulong addr = ppc64_phys_to_real(args[0]); 16740c21e073SDavid Gibson target_ulong fdt_buf = args[1]; 16750c21e073SDavid Gibson target_ulong fdt_bufsize = args[2]; 167680c33d34SDavid Gibson target_ulong ov_table; 167780c33d34SDavid Gibson uint32_t cas_pvr; 1678d1d32d62SDavid Gibson SpaprOptionVector *ov1_guest, *ov5_guest, *ov5_cas_old; 167980c33d34SDavid Gibson bool guest_radix; 1680f6f242c7SDavid Gibson Error *local_err = NULL; 1681cc7b35b1SGreg Kurz bool raw_mode_supported = false; 1682e7f78db9SGreg Kurz bool guest_xive; 168312b3868eSGreg Kurz CPUState *cs; 168412b3868eSGreg Kurz 168512b3868eSGreg Kurz /* CAS is supposed to be called early when only the boot vCPU is active. */ 168612b3868eSGreg Kurz CPU_FOREACH(cs) { 168712b3868eSGreg Kurz if (cs == CPU(cpu)) { 168812b3868eSGreg Kurz continue; 168912b3868eSGreg Kurz } 169012b3868eSGreg Kurz if (!cs->halted) { 169112b3868eSGreg Kurz warn_report("guest has multiple active vCPUs at CAS, which is not allowed"); 169212b3868eSGreg Kurz return H_MULTI_THREADS_ACTIVE; 169312b3868eSGreg Kurz } 169412b3868eSGreg Kurz } 16953794d548SAlexey Kardashevskiy 1696cc7b35b1SGreg Kurz cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err); 169780c33d34SDavid Gibson if (local_err) { 169880c33d34SDavid Gibson error_report_err(local_err); 169980c33d34SDavid Gibson return H_HARDWARE; 170080c33d34SDavid Gibson } 170180c33d34SDavid Gibson 170280c33d34SDavid Gibson /* Update CPUs */ 170380c33d34SDavid Gibson if (cpu->compat_pvr != cas_pvr) { 170480c33d34SDavid Gibson ppc_set_compat_all(cas_pvr, &local_err); 1705f6f242c7SDavid Gibson if (local_err) { 1706cc7b35b1SGreg Kurz /* We fail to set compat mode (likely because running with KVM PR), 1707cc7b35b1SGreg Kurz * but maybe we can fallback to raw mode if the guest supports it. 1708cc7b35b1SGreg Kurz */ 1709cc7b35b1SGreg Kurz if (!raw_mode_supported) { 1710f6f242c7SDavid Gibson error_report_err(local_err); 17113794d548SAlexey Kardashevskiy return H_HARDWARE; 17123794d548SAlexey Kardashevskiy } 17132c9dfdacSGreg Kurz error_free(local_err); 1714cc7b35b1SGreg Kurz local_err = NULL; 1715cc7b35b1SGreg Kurz } 17163794d548SAlexey Kardashevskiy } 17173794d548SAlexey Kardashevskiy 171803d196b7SBharata B Rao /* For the future use: here @ov_table points to the first option vector */ 171980c33d34SDavid Gibson ov_table = addr; 172003d196b7SBharata B Rao 1721e957f6a9SSam Bobroff ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1722cbd0d7f3SGreg Kurz if (!ov1_guest) { 1723cbd0d7f3SGreg Kurz warn_report("guest didn't provide option vector 1"); 1724cbd0d7f3SGreg Kurz return H_PARAMETER; 1725cbd0d7f3SGreg Kurz } 1726facdb8b6SMichael Roth ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1727cbd0d7f3SGreg Kurz if (!ov5_guest) { 1728cbd0d7f3SGreg Kurz warn_report("guest didn't provide option vector 5"); 1729cbd0d7f3SGreg Kurz return H_PARAMETER; 1730cbd0d7f3SGreg Kurz } 17319fb4541fSSam Bobroff if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 17329fb4541fSSam Bobroff error_report("guest requested hash and radix MMU, which is invalid."); 17339fb4541fSSam Bobroff exit(EXIT_FAILURE); 17349fb4541fSSam Bobroff } 1735e7f78db9SGreg Kurz if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { 1736e7f78db9SGreg Kurz error_report("guest requested an invalid interrupt mode"); 1737e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1738e7f78db9SGreg Kurz } 1739e7f78db9SGreg Kurz 17409fb4541fSSam Bobroff /* The radix/hash bit in byte 24 requires special handling: */ 17419fb4541fSSam Bobroff guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 17429fb4541fSSam Bobroff spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300); 17432a6593cbSAlexey Kardashevskiy 1744e7f78db9SGreg Kurz guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); 1745e7f78db9SGreg Kurz 17462772cf6bSDavid Gibson /* 17472772cf6bSDavid Gibson * HPT resizing is a bit of a special case, because when enabled 17482772cf6bSDavid Gibson * we assume an HPT guest will support it until it says it 17492772cf6bSDavid Gibson * doesn't, instead of assuming it won't support it until it says 17502772cf6bSDavid Gibson * it does. Strictly speaking that approach could break for 17512772cf6bSDavid Gibson * guests which don't make a CAS call, but those are so old we 17522772cf6bSDavid Gibson * don't care about them. Without that assumption we'd have to 17532772cf6bSDavid Gibson * make at least a temporary allocation of an HPT sized for max 17542772cf6bSDavid Gibson * memory, which could be impossibly difficult under KVM HV if 17552772cf6bSDavid Gibson * maxram is large. 17562772cf6bSDavid Gibson */ 17572772cf6bSDavid Gibson if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 17582772cf6bSDavid Gibson int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 17592772cf6bSDavid Gibson 17602772cf6bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 17612772cf6bSDavid Gibson error_report( 17622772cf6bSDavid Gibson "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 17632772cf6bSDavid Gibson exit(1); 17642772cf6bSDavid Gibson } 17652772cf6bSDavid Gibson 17662772cf6bSDavid Gibson if (spapr->htab_shift < maxshift) { 17672772cf6bSDavid Gibson /* Guest doesn't know about HPT resizing, so we 17682772cf6bSDavid Gibson * pre-emptively resize for the maximum permitted RAM. At 17692772cf6bSDavid Gibson * the point this is called, nothing should have been 17702772cf6bSDavid Gibson * entered into the existing HPT */ 17712772cf6bSDavid Gibson spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 17721ec26c75SGreg Kurz push_sregs_to_kvm_pr(spapr); 1773b55d295eSDavid Gibson } 17742772cf6bSDavid Gibson } 17752772cf6bSDavid Gibson 1776facdb8b6SMichael Roth /* NOTE: there are actually a number of ov5 bits where input from the 1777facdb8b6SMichael Roth * guest is always zero, and the platform/QEMU enables them independently 1778facdb8b6SMichael Roth * of guest input. To model these properly we'd want some sort of mask, 1779facdb8b6SMichael Roth * but since they only currently apply to memory migration as defined 1780facdb8b6SMichael Roth * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 17816787d27bSMichael Roth * to worry about this for now. 1782facdb8b6SMichael Roth */ 17836787d27bSMichael Roth ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); 178430bf9ed1SCédric Le Goater 178530bf9ed1SCédric Le Goater /* also clear the radix/hash bit from the current ov5_cas bits to 178630bf9ed1SCédric Le Goater * be in sync with the newly ov5 bits. Else the radix bit will be 178730bf9ed1SCédric Le Goater * seen as being removed and this will generate a reset loop 178830bf9ed1SCédric Le Goater */ 178930bf9ed1SCédric Le Goater spapr_ovec_clear(ov5_cas_old, OV5_MMU_RADIX_300); 179030bf9ed1SCédric Le Goater 17916787d27bSMichael Roth /* full range of negotiated ov5 capabilities */ 1792facdb8b6SMichael Roth spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1793facdb8b6SMichael Roth spapr_ovec_cleanup(ov5_guest); 17946787d27bSMichael Roth /* capabilities that have been added since CAS-generated guest reset. 17956787d27bSMichael Roth * if capabilities have since been removed, generate another reset 17966787d27bSMichael Roth */ 1797d1d32d62SDavid Gibson spapr->cas_reboot = !spapr_ovec_subset(ov5_cas_old, spapr->ov5_cas); 179800005f22SShivaprasad G Bhat spapr_ovec_cleanup(ov5_cas_old); 17999fb4541fSSam Bobroff /* Now that processing is finished, set the radix/hash bit for the 18009fb4541fSSam Bobroff * guest if it requested a valid mode; otherwise terminate the boot. */ 18019fb4541fSSam Bobroff if (guest_radix) { 18029fb4541fSSam Bobroff if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 18039fb4541fSSam Bobroff error_report("Guest requested unavailable MMU mode (radix)."); 18049fb4541fSSam Bobroff exit(EXIT_FAILURE); 18059fb4541fSSam Bobroff } 18069fb4541fSSam Bobroff spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300); 18079fb4541fSSam Bobroff } else { 18089fb4541fSSam Bobroff if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 18099fb4541fSSam Bobroff && !kvmppc_has_cap_mmu_hash_v3()) { 18109fb4541fSSam Bobroff error_report("Guest requested unavailable MMU mode (hash)."); 18119fb4541fSSam Bobroff exit(EXIT_FAILURE); 18129fb4541fSSam Bobroff } 18139fb4541fSSam Bobroff } 1814daa36379SDavid Gibson spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00); 181500005f22SShivaprasad G Bhat spapr_ovec_cleanup(ov1_guest); 181613db0cd9SCédric Le Goater 181713db0cd9SCédric Le Goater /* 18188deb8019SDavid Gibson * Ensure the guest asks for an interrupt mode we support; 18198deb8019SDavid Gibson * otherwise terminate the boot. 1820e7f78db9SGreg Kurz */ 1821e7f78db9SGreg Kurz if (guest_xive) { 1822ca62823bSDavid Gibson if (!spapr->irq->xive) { 182375de5941SGreg Kurz error_report( 182475de5941SGreg Kurz "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property"); 1825e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1826e7f78db9SGreg Kurz } 1827e7f78db9SGreg Kurz } else { 1828ca62823bSDavid Gibson if (!spapr->irq->xics) { 182975de5941SGreg Kurz error_report( 183075de5941SGreg Kurz "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual"); 1831e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1832e7f78db9SGreg Kurz } 1833e7f78db9SGreg Kurz } 1834e7f78db9SGreg Kurz 18358deb8019SDavid Gibson spapr_irq_update_active_intc(spapr); 18368deb8019SDavid Gibson 1837*4b63db12SGreg Kurz if (spapr_transient_dev_before_cas()) { 18380c21e073SDavid Gibson spapr->cas_reboot = true; 18390c21e073SDavid Gibson } 18400c21e073SDavid Gibson 184113db0cd9SCédric Le Goater if (!spapr->cas_reboot) { 18420c21e073SDavid Gibson void *fdt; 18430c21e073SDavid Gibson SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 18440c21e073SDavid Gibson 18458deb8019SDavid Gibson /* If spapr_machine_reset() did not set up a HPT but one is necessary 18468deb8019SDavid Gibson * (because the guest isn't going to use radix) then set it up here. */ 18478deb8019SDavid Gibson if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { 18488deb8019SDavid Gibson /* legacy hash or new hash: */ 18498deb8019SDavid Gibson spapr_setup_hpt_and_vrma(spapr); 18508deb8019SDavid Gibson } 18510c21e073SDavid Gibson 18520c21e073SDavid Gibson if (fdt_bufsize < sizeof(hdr)) { 18530c21e073SDavid Gibson error_report("SLOF provided insufficient CAS buffer " 18540c21e073SDavid Gibson TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr)); 18550c21e073SDavid Gibson exit(EXIT_FAILURE); 18560c21e073SDavid Gibson } 18570c21e073SDavid Gibson 18580c21e073SDavid Gibson fdt_bufsize -= sizeof(hdr); 18590c21e073SDavid Gibson 18600c21e073SDavid Gibson fdt = spapr_build_fdt(spapr, false, fdt_bufsize); 18610c21e073SDavid Gibson _FDT((fdt_pack(fdt))); 18620c21e073SDavid Gibson 18630c21e073SDavid Gibson cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr)); 18640c21e073SDavid Gibson cpu_physical_memory_write(fdt_buf + sizeof(hdr), fdt, 18650c21e073SDavid Gibson fdt_totalsize(fdt)); 18660c21e073SDavid Gibson trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 18670c21e073SDavid Gibson 18680c21e073SDavid Gibson g_free(spapr->fdt_blob); 18690c21e073SDavid Gibson spapr->fdt_size = fdt_totalsize(fdt); 18700c21e073SDavid Gibson spapr->fdt_initial_size = spapr->fdt_size; 18710c21e073SDavid Gibson spapr->fdt_blob = fdt; 187213db0cd9SCédric Le Goater } 187313db0cd9SCédric Le Goater 18746787d27bSMichael Roth if (spapr->cas_reboot) { 18759146206eSDavid Gibson qemu_system_reset_request(SHUTDOWN_CAUSE_SUBSYSTEM_RESET); 18762a6593cbSAlexey Kardashevskiy } 18772a6593cbSAlexey Kardashevskiy 18782a6593cbSAlexey Kardashevskiy return H_SUCCESS; 18792a6593cbSAlexey Kardashevskiy } 18802a6593cbSAlexey Kardashevskiy 1881c24ba3d0SLaurent Vivier static target_ulong h_home_node_associativity(PowerPCCPU *cpu, 1882ce2918cbSDavid Gibson SpaprMachineState *spapr, 1883c24ba3d0SLaurent Vivier target_ulong opcode, 1884c24ba3d0SLaurent Vivier target_ulong *args) 1885c24ba3d0SLaurent Vivier { 1886c24ba3d0SLaurent Vivier target_ulong flags = args[0]; 1887c24ba3d0SLaurent Vivier target_ulong procno = args[1]; 1888c24ba3d0SLaurent Vivier PowerPCCPU *tcpu; 1889c24ba3d0SLaurent Vivier int idx; 1890c24ba3d0SLaurent Vivier 1891c24ba3d0SLaurent Vivier /* only support procno from H_REGISTER_VPA */ 1892c24ba3d0SLaurent Vivier if (flags != 0x1) { 1893c24ba3d0SLaurent Vivier return H_FUNCTION; 1894c24ba3d0SLaurent Vivier } 1895c24ba3d0SLaurent Vivier 1896c24ba3d0SLaurent Vivier tcpu = spapr_find_cpu(procno); 1897c24ba3d0SLaurent Vivier if (tcpu == NULL) { 1898c24ba3d0SLaurent Vivier return H_P2; 1899c24ba3d0SLaurent Vivier } 1900c24ba3d0SLaurent Vivier 1901c24ba3d0SLaurent Vivier /* sequence is the same as in the "ibm,associativity" property */ 1902c24ba3d0SLaurent Vivier 1903c24ba3d0SLaurent Vivier idx = 0; 1904c24ba3d0SLaurent Vivier #define ASSOCIATIVITY(a, b) (((uint64_t)(a) << 32) | \ 1905c24ba3d0SLaurent Vivier ((uint64_t)(b) & 0xffffffff)) 1906c24ba3d0SLaurent Vivier args[idx++] = ASSOCIATIVITY(0, 0); 1907c24ba3d0SLaurent Vivier args[idx++] = ASSOCIATIVITY(0, tcpu->node_id); 1908c24ba3d0SLaurent Vivier args[idx++] = ASSOCIATIVITY(procno, -1); 1909c24ba3d0SLaurent Vivier for ( ; idx < 6; idx++) { 1910c24ba3d0SLaurent Vivier args[idx] = -1; 1911c24ba3d0SLaurent Vivier } 1912c24ba3d0SLaurent Vivier #undef ASSOCIATIVITY 1913c24ba3d0SLaurent Vivier 1914c24ba3d0SLaurent Vivier return H_SUCCESS; 1915c24ba3d0SLaurent Vivier } 1916c24ba3d0SLaurent Vivier 1917c59704b2SSuraj Jitindar Singh static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1918ce2918cbSDavid Gibson SpaprMachineState *spapr, 1919c59704b2SSuraj Jitindar Singh target_ulong opcode, 1920c59704b2SSuraj Jitindar Singh target_ulong *args) 1921c59704b2SSuraj Jitindar Singh { 1922c59704b2SSuraj Jitindar Singh uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1923c59704b2SSuraj Jitindar Singh ~H_CPU_CHAR_THR_RECONF_TRIG; 1924c59704b2SSuraj Jitindar Singh uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1925c59704b2SSuraj Jitindar Singh uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1926c59704b2SSuraj Jitindar Singh uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1927c59704b2SSuraj Jitindar Singh uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 19288ff43ee4SSuraj Jitindar Singh uint8_t count_cache_flush_assist = spapr_get_cap(spapr, 19298ff43ee4SSuraj Jitindar Singh SPAPR_CAP_CCF_ASSIST); 1930c59704b2SSuraj Jitindar Singh 1931c59704b2SSuraj Jitindar Singh switch (safe_cache) { 1932c59704b2SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1933c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1934c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1935c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1936c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1937c59704b2SSuraj Jitindar Singh break; 1938c59704b2SSuraj Jitindar Singh case SPAPR_CAP_FIXED: 1939c59704b2SSuraj Jitindar Singh break; 1940c59704b2SSuraj Jitindar Singh default: /* broken */ 1941c59704b2SSuraj Jitindar Singh assert(safe_cache == SPAPR_CAP_BROKEN); 1942c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1943c59704b2SSuraj Jitindar Singh break; 1944c59704b2SSuraj Jitindar Singh } 1945c59704b2SSuraj Jitindar Singh 1946c59704b2SSuraj Jitindar Singh switch (safe_bounds_check) { 1947c59704b2SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1948c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1949c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1950c59704b2SSuraj Jitindar Singh break; 1951c59704b2SSuraj Jitindar Singh case SPAPR_CAP_FIXED: 1952c59704b2SSuraj Jitindar Singh break; 1953c59704b2SSuraj Jitindar Singh default: /* broken */ 1954c59704b2SSuraj Jitindar Singh assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1955c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1956c59704b2SSuraj Jitindar Singh break; 1957c59704b2SSuraj Jitindar Singh } 1958c59704b2SSuraj Jitindar Singh 1959c59704b2SSuraj Jitindar Singh switch (safe_indirect_branch) { 1960399b2896SSuraj Jitindar Singh case SPAPR_CAP_FIXED_NA: 1961399b2896SSuraj Jitindar Singh break; 1962c76c0d30SSuraj Jitindar Singh case SPAPR_CAP_FIXED_CCD: 1963c76c0d30SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; 1964c76c0d30SSuraj Jitindar Singh break; 1965c76c0d30SSuraj Jitindar Singh case SPAPR_CAP_FIXED_IBS: 1966c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1967fa86f592SGreg Kurz break; 1968399b2896SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1969399b2896SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE; 19708ff43ee4SSuraj Jitindar Singh if (count_cache_flush_assist) { 19718ff43ee4SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST; 19728ff43ee4SSuraj Jitindar Singh } 1973399b2896SSuraj Jitindar Singh break; 1974c59704b2SSuraj Jitindar Singh default: /* broken */ 1975c59704b2SSuraj Jitindar Singh assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1976c59704b2SSuraj Jitindar Singh break; 1977c59704b2SSuraj Jitindar Singh } 1978c59704b2SSuraj Jitindar Singh 1979c59704b2SSuraj Jitindar Singh args[0] = characteristics; 1980c59704b2SSuraj Jitindar Singh args[1] = behaviour; 1981fea35ca4SAlexey Kardashevskiy return H_SUCCESS; 1982fea35ca4SAlexey Kardashevskiy } 1983fea35ca4SAlexey Kardashevskiy 1984ce2918cbSDavid Gibson static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, 1985fea35ca4SAlexey Kardashevskiy target_ulong opcode, target_ulong *args) 1986fea35ca4SAlexey Kardashevskiy { 1987fea35ca4SAlexey Kardashevskiy target_ulong dt = ppc64_phys_to_real(args[0]); 1988fea35ca4SAlexey Kardashevskiy struct fdt_header hdr = { 0 }; 1989fea35ca4SAlexey Kardashevskiy unsigned cb; 1990ce2918cbSDavid Gibson SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1991fea35ca4SAlexey Kardashevskiy void *fdt; 1992fea35ca4SAlexey Kardashevskiy 1993fea35ca4SAlexey Kardashevskiy cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); 1994fea35ca4SAlexey Kardashevskiy cb = fdt32_to_cpu(hdr.totalsize); 1995fea35ca4SAlexey Kardashevskiy 1996fea35ca4SAlexey Kardashevskiy if (!smc->update_dt_enabled) { 1997fea35ca4SAlexey Kardashevskiy return H_SUCCESS; 1998fea35ca4SAlexey Kardashevskiy } 1999fea35ca4SAlexey Kardashevskiy 2000fea35ca4SAlexey Kardashevskiy /* Check that the fdt did not grow out of proportion */ 2001fea35ca4SAlexey Kardashevskiy if (cb > spapr->fdt_initial_size * 2) { 2002fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, 2003fea35ca4SAlexey Kardashevskiy fdt32_to_cpu(hdr.magic)); 2004fea35ca4SAlexey Kardashevskiy return H_PARAMETER; 2005fea35ca4SAlexey Kardashevskiy } 2006fea35ca4SAlexey Kardashevskiy 2007fea35ca4SAlexey Kardashevskiy fdt = g_malloc0(cb); 2008fea35ca4SAlexey Kardashevskiy cpu_physical_memory_read(dt, fdt, cb); 2009fea35ca4SAlexey Kardashevskiy 2010fea35ca4SAlexey Kardashevskiy /* Check the fdt consistency */ 2011fea35ca4SAlexey Kardashevskiy if (fdt_check_full(fdt, cb)) { 2012fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, 2013fea35ca4SAlexey Kardashevskiy fdt32_to_cpu(hdr.magic)); 2014fea35ca4SAlexey Kardashevskiy return H_PARAMETER; 2015fea35ca4SAlexey Kardashevskiy } 2016fea35ca4SAlexey Kardashevskiy 2017fea35ca4SAlexey Kardashevskiy g_free(spapr->fdt_blob); 2018fea35ca4SAlexey Kardashevskiy spapr->fdt_size = cb; 2019fea35ca4SAlexey Kardashevskiy spapr->fdt_blob = fdt; 2020fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt(cb); 2021c59704b2SSuraj Jitindar Singh 2022c59704b2SSuraj Jitindar Singh return H_SUCCESS; 2023c59704b2SSuraj Jitindar Singh } 2024c59704b2SSuraj Jitindar Singh 20259f64bd8aSPaolo Bonzini static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 20269f64bd8aSPaolo Bonzini static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 20270fb6bd07SMichael Roth static spapr_hcall_fn svm_hypercall_table[(SVM_HCALL_MAX - SVM_HCALL_BASE) / 4 + 1]; 20289f64bd8aSPaolo Bonzini 20299f64bd8aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 20309f64bd8aSPaolo Bonzini { 20319f64bd8aSPaolo Bonzini spapr_hcall_fn *slot; 20329f64bd8aSPaolo Bonzini 20339f64bd8aSPaolo Bonzini if (opcode <= MAX_HCALL_OPCODE) { 20349f64bd8aSPaolo Bonzini assert((opcode & 0x3) == 0); 20359f64bd8aSPaolo Bonzini 20369f64bd8aSPaolo Bonzini slot = &papr_hypercall_table[opcode / 4]; 20370fb6bd07SMichael Roth } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { 20380fb6bd07SMichael Roth /* we only have SVM-related hcall numbers assigned in multiples of 4 */ 20390fb6bd07SMichael Roth assert((opcode & 0x3) == 0); 20400fb6bd07SMichael Roth 20410fb6bd07SMichael Roth slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 20429f64bd8aSPaolo Bonzini } else { 20439f64bd8aSPaolo Bonzini assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 20449f64bd8aSPaolo Bonzini 20459f64bd8aSPaolo Bonzini slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 20469f64bd8aSPaolo Bonzini } 20479f64bd8aSPaolo Bonzini 20489f64bd8aSPaolo Bonzini assert(!(*slot)); 20499f64bd8aSPaolo Bonzini *slot = fn; 20509f64bd8aSPaolo Bonzini } 20519f64bd8aSPaolo Bonzini 20529f64bd8aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 20539f64bd8aSPaolo Bonzini target_ulong *args) 20549f64bd8aSPaolo Bonzini { 2055ce2918cbSDavid Gibson SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 205628e02042SDavid Gibson 20579f64bd8aSPaolo Bonzini if ((opcode <= MAX_HCALL_OPCODE) 20589f64bd8aSPaolo Bonzini && ((opcode & 0x3) == 0)) { 20599f64bd8aSPaolo Bonzini spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 20609f64bd8aSPaolo Bonzini 20619f64bd8aSPaolo Bonzini if (fn) { 20629f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 20639f64bd8aSPaolo Bonzini } 20640fb6bd07SMichael Roth } else if ((opcode >= SVM_HCALL_BASE) && 20650fb6bd07SMichael Roth (opcode <= SVM_HCALL_MAX)) { 20660fb6bd07SMichael Roth spapr_hcall_fn fn = svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 20670fb6bd07SMichael Roth 20680fb6bd07SMichael Roth if (fn) { 20690fb6bd07SMichael Roth return fn(cpu, spapr, opcode, args); 20700fb6bd07SMichael Roth } 20719f64bd8aSPaolo Bonzini } else if ((opcode >= KVMPPC_HCALL_BASE) && 20729f64bd8aSPaolo Bonzini (opcode <= KVMPPC_HCALL_MAX)) { 20739f64bd8aSPaolo Bonzini spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 20749f64bd8aSPaolo Bonzini 20759f64bd8aSPaolo Bonzini if (fn) { 20769f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 20779f64bd8aSPaolo Bonzini } 20789f64bd8aSPaolo Bonzini } 20799f64bd8aSPaolo Bonzini 2080aaf87c66SThomas Huth qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 2081aaf87c66SThomas Huth opcode); 20829f64bd8aSPaolo Bonzini return H_FUNCTION; 20839f64bd8aSPaolo Bonzini } 20849f64bd8aSPaolo Bonzini 20859f64bd8aSPaolo Bonzini static void hypercall_register_types(void) 20869f64bd8aSPaolo Bonzini { 20879f64bd8aSPaolo Bonzini /* hcall-pft */ 20889f64bd8aSPaolo Bonzini spapr_register_hypercall(H_ENTER, h_enter); 20899f64bd8aSPaolo Bonzini spapr_register_hypercall(H_REMOVE, h_remove); 20909f64bd8aSPaolo Bonzini spapr_register_hypercall(H_PROTECT, h_protect); 2091fa388916SAnthony Liguori spapr_register_hypercall(H_READ, h_read); 20929f64bd8aSPaolo Bonzini 20939f64bd8aSPaolo Bonzini /* hcall-bulk */ 20949f64bd8aSPaolo Bonzini spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 20959f64bd8aSPaolo Bonzini 209630f4b05bSDavid Gibson /* hcall-hpt-resize */ 209730f4b05bSDavid Gibson spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 209830f4b05bSDavid Gibson spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 209930f4b05bSDavid Gibson 21009f64bd8aSPaolo Bonzini /* hcall-splpar */ 21019f64bd8aSPaolo Bonzini spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 21029f64bd8aSPaolo Bonzini spapr_register_hypercall(H_CEDE, h_cede); 2103e8ce0e40SNicholas Piggin spapr_register_hypercall(H_CONFER, h_confer); 21043a6e6224SNicholas Piggin spapr_register_hypercall(H_PROD, h_prod); 21053a6e6224SNicholas Piggin 210610741314SNicholas Piggin /* hcall-join */ 210710741314SNicholas Piggin spapr_register_hypercall(H_JOIN, h_join); 210810741314SNicholas Piggin 21091c7ad77eSNicholas Piggin spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 21109f64bd8aSPaolo Bonzini 2111423576f7SThomas Huth /* processor register resource access h-calls */ 2112423576f7SThomas Huth spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 2113af08a58fSThomas Huth spapr_register_hypercall(H_SET_DABR, h_set_dabr); 2114e49ff266SThomas Huth spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 21153240dd9aSThomas Huth spapr_register_hypercall(H_PAGE_INIT, h_page_init); 2116423576f7SThomas Huth spapr_register_hypercall(H_SET_MODE, h_set_mode); 2117423576f7SThomas Huth 2118d77a98b0SSuraj Jitindar Singh /* In Memory Table MMU h-calls */ 2119d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 2120d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 2121d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 2122d77a98b0SSuraj Jitindar Singh 2123c59704b2SSuraj Jitindar Singh /* hcall-get-cpu-characteristics */ 2124c59704b2SSuraj Jitindar Singh spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 2125c59704b2SSuraj Jitindar Singh h_get_cpu_characteristics); 2126c59704b2SSuraj Jitindar Singh 21279f64bd8aSPaolo Bonzini /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 21289f64bd8aSPaolo Bonzini * here between the "CI" and the "CACHE" variants, they will use whatever 21299f64bd8aSPaolo Bonzini * mapping attributes qemu is using. When using KVM, the kernel will 21309f64bd8aSPaolo Bonzini * enforce the attributes more strongly 21319f64bd8aSPaolo Bonzini */ 21329f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 21339f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 21349f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 21359f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 21369f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 21379f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 21389f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 21399f64bd8aSPaolo Bonzini 21409f64bd8aSPaolo Bonzini /* qemu/KVM-PPC specific hcalls */ 21419f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 214242561bf2SAnton Blanchard 21432a6593cbSAlexey Kardashevskiy /* ibm,client-architecture-support support */ 21442a6593cbSAlexey Kardashevskiy spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 2145c24ba3d0SLaurent Vivier 2146fea35ca4SAlexey Kardashevskiy spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); 2147fea35ca4SAlexey Kardashevskiy 2148c24ba3d0SLaurent Vivier /* Virtual Processor Home Node */ 2149c24ba3d0SLaurent Vivier spapr_register_hypercall(H_HOME_NODE_ASSOCIATIVITY, 2150c24ba3d0SLaurent Vivier h_home_node_associativity); 21519f64bd8aSPaolo Bonzini } 21529f64bd8aSPaolo Bonzini 21539f64bd8aSPaolo Bonzini type_init(hypercall_register_types) 2154