10d75590dSPeter Maydell #include "qemu/osdep.h" 2da34e65cSMarkus Armbruster #include "qapi/error.h" 3b3946626SVincent Palatin #include "sysemu/hw_accel.h" 49f64bd8aSPaolo Bonzini #include "sysemu/sysemu.h" 503dd024fSPaolo Bonzini #include "qemu/log.h" 60b0b8310SDavid Gibson #include "qemu/error-report.h" 79f64bd8aSPaolo Bonzini #include "cpu.h" 863c91552SPaolo Bonzini #include "exec/exec-all.h" 99f64bd8aSPaolo Bonzini #include "helper_regs.h" 100d09e41aSPaolo Bonzini #include "hw/ppc/spapr.h" 11d5aea6f3SDavid Gibson #include "mmu-hash64.h" 123794d548SAlexey Kardashevskiy #include "cpu-models.h" 133794d548SAlexey Kardashevskiy #include "trace.h" 143794d548SAlexey Kardashevskiy #include "kvm_ppc.h" 15facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 16b4db5413SSuraj Jitindar Singh #include "qemu/error-report.h" 17b4db5413SSuraj Jitindar Singh #include "mmu-book3s-v3.h" 189f64bd8aSPaolo Bonzini 19a46622fdSAlexey Kardashevskiy struct SPRSyncState { 20a46622fdSAlexey Kardashevskiy int spr; 21a46622fdSAlexey Kardashevskiy target_ulong value; 22a46622fdSAlexey Kardashevskiy target_ulong mask; 23a46622fdSAlexey Kardashevskiy }; 24a46622fdSAlexey Kardashevskiy 2514e6fe12SPaolo Bonzini static void do_spr_sync(CPUState *cs, run_on_cpu_data arg) 26a46622fdSAlexey Kardashevskiy { 2714e6fe12SPaolo Bonzini struct SPRSyncState *s = arg.host_ptr; 28e0eeb4a2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 29a46622fdSAlexey Kardashevskiy CPUPPCState *env = &cpu->env; 30a46622fdSAlexey Kardashevskiy 31e0eeb4a2SAlex Bennée cpu_synchronize_state(cs); 32a46622fdSAlexey Kardashevskiy env->spr[s->spr] &= ~s->mask; 33a46622fdSAlexey Kardashevskiy env->spr[s->spr] |= s->value; 34a46622fdSAlexey Kardashevskiy } 35a46622fdSAlexey Kardashevskiy 36a46622fdSAlexey Kardashevskiy static void set_spr(CPUState *cs, int spr, target_ulong value, 37a46622fdSAlexey Kardashevskiy target_ulong mask) 38a46622fdSAlexey Kardashevskiy { 39a46622fdSAlexey Kardashevskiy struct SPRSyncState s = { 40a46622fdSAlexey Kardashevskiy .spr = spr, 41a46622fdSAlexey Kardashevskiy .value = value, 42a46622fdSAlexey Kardashevskiy .mask = mask 43a46622fdSAlexey Kardashevskiy }; 4414e6fe12SPaolo Bonzini run_on_cpu(cs, do_spr_sync, RUN_ON_CPU_HOST_PTR(&s)); 45a46622fdSAlexey Kardashevskiy } 46a46622fdSAlexey Kardashevskiy 47af08a58fSThomas Huth static bool has_spr(PowerPCCPU *cpu, int spr) 48af08a58fSThomas Huth { 49af08a58fSThomas Huth /* We can test whether the SPR is defined by checking for a valid name */ 50af08a58fSThomas Huth return cpu->env.spr_cb[spr].name != NULL; 51af08a58fSThomas Huth } 52af08a58fSThomas Huth 53c6404adeSDavid Gibson static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) 54f3c75d42SAneesh Kumar K.V { 55f3c75d42SAneesh Kumar K.V /* 5636778660SDavid Gibson * hash value/pteg group index is normalized by HPT mask 57f3c75d42SAneesh Kumar K.V */ 5836778660SDavid Gibson if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { 59f3c75d42SAneesh Kumar K.V return false; 60f3c75d42SAneesh Kumar K.V } 61f3c75d42SAneesh Kumar K.V return true; 62f3c75d42SAneesh Kumar K.V } 63f3c75d42SAneesh Kumar K.V 64ecbc25faSDavid Gibson static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr) 65ecbc25faSDavid Gibson { 66ecbc25faSDavid Gibson MachineState *machine = MACHINE(spapr); 67ecbc25faSDavid Gibson MemoryHotplugState *hpms = &spapr->hotplug_memory; 68ecbc25faSDavid Gibson 69ecbc25faSDavid Gibson if (addr < machine->ram_size) { 70ecbc25faSDavid Gibson return true; 71ecbc25faSDavid Gibson } 72ecbc25faSDavid Gibson if ((addr >= hpms->base) 73ecbc25faSDavid Gibson && ((addr - hpms->base) < memory_region_size(&hpms->mr))) { 74ecbc25faSDavid Gibson return true; 75ecbc25faSDavid Gibson } 76ecbc25faSDavid Gibson 77ecbc25faSDavid Gibson return false; 78ecbc25faSDavid Gibson } 79ecbc25faSDavid Gibson 8028e02042SDavid Gibson static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, 819f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 829f64bd8aSPaolo Bonzini { 839f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 84c6404adeSDavid Gibson target_ulong ptex = args[1]; 859f64bd8aSPaolo Bonzini target_ulong pteh = args[2]; 869f64bd8aSPaolo Bonzini target_ulong ptel = args[3]; 871f0252e6SCédric Le Goater unsigned apshift; 889f64bd8aSPaolo Bonzini target_ulong raddr; 89c6404adeSDavid Gibson target_ulong slot; 907222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 919f64bd8aSPaolo Bonzini 921f0252e6SCédric Le Goater apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); 931114e712SDavid Gibson if (!apshift) { 941114e712SDavid Gibson /* Bad page size encoding */ 959f64bd8aSPaolo Bonzini return H_PARAMETER; 969f64bd8aSPaolo Bonzini } 979f64bd8aSPaolo Bonzini 981114e712SDavid Gibson raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); 999f64bd8aSPaolo Bonzini 100ecbc25faSDavid Gibson if (is_ram_address(spapr, raddr)) { 1019f64bd8aSPaolo Bonzini /* Regular RAM - should have WIMG=0010 */ 102d5aea6f3SDavid Gibson if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 1039f64bd8aSPaolo Bonzini return H_PARAMETER; 1049f64bd8aSPaolo Bonzini } 1059f64bd8aSPaolo Bonzini } else { 106c1175907SAneesh Kumar K.V target_ulong wimg_flags; 1079f64bd8aSPaolo Bonzini /* Looks like an IO address */ 1089f64bd8aSPaolo Bonzini /* FIXME: What WIMG combinations could be sensible for IO? 1099f64bd8aSPaolo Bonzini * For now we allow WIMG=010x, but are there others? */ 1109f64bd8aSPaolo Bonzini /* FIXME: Should we check against registered IO addresses? */ 111c1175907SAneesh Kumar K.V wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); 112c1175907SAneesh Kumar K.V 113c1175907SAneesh Kumar K.V if (wimg_flags != HPTE64_R_I && 114c1175907SAneesh Kumar K.V wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { 1159f64bd8aSPaolo Bonzini return H_PARAMETER; 1169f64bd8aSPaolo Bonzini } 1179f64bd8aSPaolo Bonzini } 1189f64bd8aSPaolo Bonzini 1199f64bd8aSPaolo Bonzini pteh &= ~0x60ULL; 1209f64bd8aSPaolo Bonzini 121c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 1229f64bd8aSPaolo Bonzini return H_PARAMETER; 1239f64bd8aSPaolo Bonzini } 1247c43bca0SAneesh Kumar K.V 125c6404adeSDavid Gibson slot = ptex & 7ULL; 126c6404adeSDavid Gibson ptex = ptex & ~7ULL; 127c6404adeSDavid Gibson 1289f64bd8aSPaolo Bonzini if (likely((flags & H_EXACT) == 0)) { 1297222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 130c6404adeSDavid Gibson for (slot = 0; slot < 8; slot++) { 1317222b94aSDavid Gibson if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { 1329f64bd8aSPaolo Bonzini break; 1339f64bd8aSPaolo Bonzini } 1347aaf4957SAneesh Kumar K.V } 1357222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 136c6404adeSDavid Gibson if (slot == 8) { 1377aaf4957SAneesh Kumar K.V return H_PTEG_FULL; 1387aaf4957SAneesh Kumar K.V } 1399f64bd8aSPaolo Bonzini } else { 1407222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); 1417222b94aSDavid Gibson if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { 1427222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); 1439f64bd8aSPaolo Bonzini return H_PTEG_FULL; 1449f64bd8aSPaolo Bonzini } 1457222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 1469f64bd8aSPaolo Bonzini } 1477c43bca0SAneesh Kumar K.V 148c6404adeSDavid Gibson ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); 1499f64bd8aSPaolo Bonzini 150c6404adeSDavid Gibson args[0] = ptex + slot; 1519f64bd8aSPaolo Bonzini return H_SUCCESS; 1529f64bd8aSPaolo Bonzini } 1539f64bd8aSPaolo Bonzini 154a3801402SStefan Weil typedef enum { 1559f64bd8aSPaolo Bonzini REMOVE_SUCCESS = 0, 1569f64bd8aSPaolo Bonzini REMOVE_NOT_FOUND = 1, 1579f64bd8aSPaolo Bonzini REMOVE_PARM = 2, 1589f64bd8aSPaolo Bonzini REMOVE_HW = 3, 159a3801402SStefan Weil } RemoveResult; 1609f64bd8aSPaolo Bonzini 1617ef23068SDavid Gibson static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, 1629f64bd8aSPaolo Bonzini target_ulong avpn, 1639f64bd8aSPaolo Bonzini target_ulong flags, 1649f64bd8aSPaolo Bonzini target_ulong *vp, target_ulong *rp) 1659f64bd8aSPaolo Bonzini { 1667222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 16761a36c9bSDavid Gibson target_ulong v, r; 1689f64bd8aSPaolo Bonzini 169c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 1709f64bd8aSPaolo Bonzini return REMOVE_PARM; 1719f64bd8aSPaolo Bonzini } 1729f64bd8aSPaolo Bonzini 1737222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 1747222b94aSDavid Gibson v = ppc_hash64_hpte0(cpu, hptes, 0); 1757222b94aSDavid Gibson r = ppc_hash64_hpte1(cpu, hptes, 0); 1767222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 1779f64bd8aSPaolo Bonzini 178d5aea6f3SDavid Gibson if ((v & HPTE64_V_VALID) == 0 || 1799f64bd8aSPaolo Bonzini ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 1809f64bd8aSPaolo Bonzini ((flags & H_ANDCOND) && (v & avpn) != 0)) { 1819f64bd8aSPaolo Bonzini return REMOVE_NOT_FOUND; 1829f64bd8aSPaolo Bonzini } 1839f64bd8aSPaolo Bonzini *vp = v; 1849f64bd8aSPaolo Bonzini *rp = r; 1857ef23068SDavid Gibson ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); 18661a36c9bSDavid Gibson ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 1879f64bd8aSPaolo Bonzini return REMOVE_SUCCESS; 1889f64bd8aSPaolo Bonzini } 1899f64bd8aSPaolo Bonzini 19028e02042SDavid Gibson static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1919f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 1929f64bd8aSPaolo Bonzini { 193cd0c6f47SBenjamin Herrenschmidt CPUPPCState *env = &cpu->env; 1949f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 195c6404adeSDavid Gibson target_ulong ptex = args[1]; 1969f64bd8aSPaolo Bonzini target_ulong avpn = args[2]; 197a3801402SStefan Weil RemoveResult ret; 1989f64bd8aSPaolo Bonzini 199c6404adeSDavid Gibson ret = remove_hpte(cpu, ptex, avpn, flags, 2009f64bd8aSPaolo Bonzini &args[0], &args[1]); 2019f64bd8aSPaolo Bonzini 2029f64bd8aSPaolo Bonzini switch (ret) { 2039f64bd8aSPaolo Bonzini case REMOVE_SUCCESS: 204e3cffe6fSNikunj A Dadhania check_tlb_flush(env, true); 2059f64bd8aSPaolo Bonzini return H_SUCCESS; 2069f64bd8aSPaolo Bonzini 2079f64bd8aSPaolo Bonzini case REMOVE_NOT_FOUND: 2089f64bd8aSPaolo Bonzini return H_NOT_FOUND; 2099f64bd8aSPaolo Bonzini 2109f64bd8aSPaolo Bonzini case REMOVE_PARM: 2119f64bd8aSPaolo Bonzini return H_PARAMETER; 2129f64bd8aSPaolo Bonzini 2139f64bd8aSPaolo Bonzini case REMOVE_HW: 2149f64bd8aSPaolo Bonzini return H_HARDWARE; 2159f64bd8aSPaolo Bonzini } 2169f64bd8aSPaolo Bonzini 2179a39970dSStefan Weil g_assert_not_reached(); 2189f64bd8aSPaolo Bonzini } 2199f64bd8aSPaolo Bonzini 2209f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 2219f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 2229f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 2239f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_END 0xc000000000000000ULL 2249f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 2259f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 2269f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 2279f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 2289f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_HW 0x3000000000000000ULL 2299f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 2309f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 2319f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 2329f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 2339f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 2349f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 2359f64bd8aSPaolo Bonzini 2369f64bd8aSPaolo Bonzini #define H_BULK_REMOVE_MAX_BATCH 4 2379f64bd8aSPaolo Bonzini 23828e02042SDavid Gibson static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 2399f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 2409f64bd8aSPaolo Bonzini { 241cd0c6f47SBenjamin Herrenschmidt CPUPPCState *env = &cpu->env; 2429f64bd8aSPaolo Bonzini int i; 243cd0c6f47SBenjamin Herrenschmidt target_ulong rc = H_SUCCESS; 2449f64bd8aSPaolo Bonzini 2459f64bd8aSPaolo Bonzini for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 2469f64bd8aSPaolo Bonzini target_ulong *tsh = &args[i*2]; 2479f64bd8aSPaolo Bonzini target_ulong tsl = args[i*2 + 1]; 2489f64bd8aSPaolo Bonzini target_ulong v, r, ret; 2499f64bd8aSPaolo Bonzini 2509f64bd8aSPaolo Bonzini if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 2519f64bd8aSPaolo Bonzini break; 2529f64bd8aSPaolo Bonzini } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 2539f64bd8aSPaolo Bonzini return H_PARAMETER; 2549f64bd8aSPaolo Bonzini } 2559f64bd8aSPaolo Bonzini 2569f64bd8aSPaolo Bonzini *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 2579f64bd8aSPaolo Bonzini *tsh |= H_BULK_REMOVE_RESPONSE; 2589f64bd8aSPaolo Bonzini 2599f64bd8aSPaolo Bonzini if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 2609f64bd8aSPaolo Bonzini *tsh |= H_BULK_REMOVE_PARM; 2619f64bd8aSPaolo Bonzini return H_PARAMETER; 2629f64bd8aSPaolo Bonzini } 2639f64bd8aSPaolo Bonzini 2647ef23068SDavid Gibson ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, 2659f64bd8aSPaolo Bonzini (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 2669f64bd8aSPaolo Bonzini &v, &r); 2679f64bd8aSPaolo Bonzini 2689f64bd8aSPaolo Bonzini *tsh |= ret << 60; 2699f64bd8aSPaolo Bonzini 2709f64bd8aSPaolo Bonzini switch (ret) { 2719f64bd8aSPaolo Bonzini case REMOVE_SUCCESS: 272d5aea6f3SDavid Gibson *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 2739f64bd8aSPaolo Bonzini break; 2749f64bd8aSPaolo Bonzini 2759f64bd8aSPaolo Bonzini case REMOVE_PARM: 276cd0c6f47SBenjamin Herrenschmidt rc = H_PARAMETER; 277cd0c6f47SBenjamin Herrenschmidt goto exit; 2789f64bd8aSPaolo Bonzini 2799f64bd8aSPaolo Bonzini case REMOVE_HW: 280cd0c6f47SBenjamin Herrenschmidt rc = H_HARDWARE; 281cd0c6f47SBenjamin Herrenschmidt goto exit; 2829f64bd8aSPaolo Bonzini } 2839f64bd8aSPaolo Bonzini } 284cd0c6f47SBenjamin Herrenschmidt exit: 285e3cffe6fSNikunj A Dadhania check_tlb_flush(env, true); 2869f64bd8aSPaolo Bonzini 287cd0c6f47SBenjamin Herrenschmidt return rc; 2889f64bd8aSPaolo Bonzini } 2899f64bd8aSPaolo Bonzini 29028e02042SDavid Gibson static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr, 2919f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 2929f64bd8aSPaolo Bonzini { 2939f64bd8aSPaolo Bonzini CPUPPCState *env = &cpu->env; 2949f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 295c6404adeSDavid Gibson target_ulong ptex = args[1]; 2969f64bd8aSPaolo Bonzini target_ulong avpn = args[2]; 2977222b94aSDavid Gibson const ppc_hash_pte64_t *hptes; 29861a36c9bSDavid Gibson target_ulong v, r; 2999f64bd8aSPaolo Bonzini 300c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 3019f64bd8aSPaolo Bonzini return H_PARAMETER; 3029f64bd8aSPaolo Bonzini } 3039f64bd8aSPaolo Bonzini 3047222b94aSDavid Gibson hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 3057222b94aSDavid Gibson v = ppc_hash64_hpte0(cpu, hptes, 0); 3067222b94aSDavid Gibson r = ppc_hash64_hpte1(cpu, hptes, 0); 3077222b94aSDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 3089f64bd8aSPaolo Bonzini 309d5aea6f3SDavid Gibson if ((v & HPTE64_V_VALID) == 0 || 3109f64bd8aSPaolo Bonzini ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 3119f64bd8aSPaolo Bonzini return H_NOT_FOUND; 3129f64bd8aSPaolo Bonzini } 3139f64bd8aSPaolo Bonzini 314d5aea6f3SDavid Gibson r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 315d5aea6f3SDavid Gibson HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 316d5aea6f3SDavid Gibson r |= (flags << 55) & HPTE64_R_PP0; 317d5aea6f3SDavid Gibson r |= (flags << 48) & HPTE64_R_KEY_HI; 318d5aea6f3SDavid Gibson r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 319c6404adeSDavid Gibson ppc_hash64_store_hpte(cpu, ptex, 3203f94170bSAneesh Kumar K.V (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); 321c6404adeSDavid Gibson ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 322d76ab5e1SNikunj A Dadhania /* Flush the tlb */ 323d76ab5e1SNikunj A Dadhania check_tlb_flush(env, true); 3249f64bd8aSPaolo Bonzini /* Don't need a memory barrier, due to qemu's global lock */ 325c6404adeSDavid Gibson ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); 3269f64bd8aSPaolo Bonzini return H_SUCCESS; 3279f64bd8aSPaolo Bonzini } 3289f64bd8aSPaolo Bonzini 32928e02042SDavid Gibson static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr, 330fa388916SAnthony Liguori target_ulong opcode, target_ulong *args) 331fa388916SAnthony Liguori { 332fa388916SAnthony Liguori target_ulong flags = args[0]; 333c6404adeSDavid Gibson target_ulong ptex = args[1]; 334fa388916SAnthony Liguori uint8_t *hpte; 335fa388916SAnthony Liguori int i, ridx, n_entries = 1; 336fa388916SAnthony Liguori 337c6404adeSDavid Gibson if (!valid_ptex(cpu, ptex)) { 338fa388916SAnthony Liguori return H_PARAMETER; 339fa388916SAnthony Liguori } 340fa388916SAnthony Liguori 341fa388916SAnthony Liguori if (flags & H_READ_4) { 342fa388916SAnthony Liguori /* Clear the two low order bits */ 343c6404adeSDavid Gibson ptex &= ~(3ULL); 344fa388916SAnthony Liguori n_entries = 4; 345fa388916SAnthony Liguori } 346fa388916SAnthony Liguori 347e57ca75cSDavid Gibson hpte = spapr->htab + (ptex * HASH_PTE_SIZE_64); 348fa388916SAnthony Liguori 349fa388916SAnthony Liguori for (i = 0, ridx = 0; i < n_entries; i++) { 350fa388916SAnthony Liguori args[ridx++] = ldq_p(hpte); 351fa388916SAnthony Liguori args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); 352fa388916SAnthony Liguori hpte += HASH_PTE_SIZE_64; 353fa388916SAnthony Liguori } 354fa388916SAnthony Liguori 355fa388916SAnthony Liguori return H_SUCCESS; 356fa388916SAnthony Liguori } 357fa388916SAnthony Liguori 3580b0b8310SDavid Gibson struct sPAPRPendingHPT { 3590b0b8310SDavid Gibson /* These fields are read-only after initialization */ 3600b0b8310SDavid Gibson int shift; 3610b0b8310SDavid Gibson QemuThread thread; 3620b0b8310SDavid Gibson 3630b0b8310SDavid Gibson /* These fields are protected by the BQL */ 3640b0b8310SDavid Gibson bool complete; 3650b0b8310SDavid Gibson 3660b0b8310SDavid Gibson /* These fields are private to the preparation thread if 3670b0b8310SDavid Gibson * !complete, otherwise protected by the BQL */ 3680b0b8310SDavid Gibson int ret; 3690b0b8310SDavid Gibson void *hpt; 3700b0b8310SDavid Gibson }; 3710b0b8310SDavid Gibson 3720b0b8310SDavid Gibson static void free_pending_hpt(sPAPRPendingHPT *pending) 3730b0b8310SDavid Gibson { 3740b0b8310SDavid Gibson if (pending->hpt) { 3750b0b8310SDavid Gibson qemu_vfree(pending->hpt); 3760b0b8310SDavid Gibson } 3770b0b8310SDavid Gibson 3780b0b8310SDavid Gibson g_free(pending); 3790b0b8310SDavid Gibson } 3800b0b8310SDavid Gibson 3810b0b8310SDavid Gibson static void *hpt_prepare_thread(void *opaque) 3820b0b8310SDavid Gibson { 3830b0b8310SDavid Gibson sPAPRPendingHPT *pending = opaque; 3840b0b8310SDavid Gibson size_t size = 1ULL << pending->shift; 3850b0b8310SDavid Gibson 3860b0b8310SDavid Gibson pending->hpt = qemu_memalign(size, size); 3870b0b8310SDavid Gibson if (pending->hpt) { 3880b0b8310SDavid Gibson memset(pending->hpt, 0, size); 3890b0b8310SDavid Gibson pending->ret = H_SUCCESS; 3900b0b8310SDavid Gibson } else { 3910b0b8310SDavid Gibson pending->ret = H_NO_MEM; 3920b0b8310SDavid Gibson } 3930b0b8310SDavid Gibson 3940b0b8310SDavid Gibson qemu_mutex_lock_iothread(); 3950b0b8310SDavid Gibson 3960b0b8310SDavid Gibson if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) { 3970b0b8310SDavid Gibson /* Ready to go */ 3980b0b8310SDavid Gibson pending->complete = true; 3990b0b8310SDavid Gibson } else { 4000b0b8310SDavid Gibson /* We've been cancelled, clean ourselves up */ 4010b0b8310SDavid Gibson free_pending_hpt(pending); 4020b0b8310SDavid Gibson } 4030b0b8310SDavid Gibson 4040b0b8310SDavid Gibson qemu_mutex_unlock_iothread(); 4050b0b8310SDavid Gibson return NULL; 4060b0b8310SDavid Gibson } 4070b0b8310SDavid Gibson 4080b0b8310SDavid Gibson /* Must be called with BQL held */ 4090b0b8310SDavid Gibson static void cancel_hpt_prepare(sPAPRMachineState *spapr) 4100b0b8310SDavid Gibson { 4110b0b8310SDavid Gibson sPAPRPendingHPT *pending = spapr->pending_hpt; 4120b0b8310SDavid Gibson 4130b0b8310SDavid Gibson /* Let the thread know it's cancelled */ 4140b0b8310SDavid Gibson spapr->pending_hpt = NULL; 4150b0b8310SDavid Gibson 4160b0b8310SDavid Gibson if (!pending) { 4170b0b8310SDavid Gibson /* Nothing to do */ 4180b0b8310SDavid Gibson return; 4190b0b8310SDavid Gibson } 4200b0b8310SDavid Gibson 4210b0b8310SDavid Gibson if (!pending->complete) { 4220b0b8310SDavid Gibson /* thread will clean itself up */ 4230b0b8310SDavid Gibson return; 4240b0b8310SDavid Gibson } 4250b0b8310SDavid Gibson 4260b0b8310SDavid Gibson free_pending_hpt(pending); 4270b0b8310SDavid Gibson } 4280b0b8310SDavid Gibson 429b55d295eSDavid Gibson /* Convert a return code from the KVM ioctl()s implementing resize HPT 430b55d295eSDavid Gibson * into a PAPR hypercall return code */ 431b55d295eSDavid Gibson static target_ulong resize_hpt_convert_rc(int ret) 432b55d295eSDavid Gibson { 433b55d295eSDavid Gibson if (ret >= 100000) { 434b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_100_SEC; 435b55d295eSDavid Gibson } else if (ret >= 10000) { 436b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_10_SEC; 437b55d295eSDavid Gibson } else if (ret >= 1000) { 438b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_1_SEC; 439b55d295eSDavid Gibson } else if (ret >= 100) { 440b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 441b55d295eSDavid Gibson } else if (ret >= 10) { 442b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_10_MSEC; 443b55d295eSDavid Gibson } else if (ret > 0) { 444b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_1_MSEC; 445b55d295eSDavid Gibson } 446b55d295eSDavid Gibson 447b55d295eSDavid Gibson switch (ret) { 448b55d295eSDavid Gibson case 0: 449b55d295eSDavid Gibson return H_SUCCESS; 450b55d295eSDavid Gibson case -EPERM: 451b55d295eSDavid Gibson return H_AUTHORITY; 452b55d295eSDavid Gibson case -EINVAL: 453b55d295eSDavid Gibson return H_PARAMETER; 454b55d295eSDavid Gibson case -ENXIO: 455b55d295eSDavid Gibson return H_CLOSED; 456b55d295eSDavid Gibson case -ENOSPC: 457b55d295eSDavid Gibson return H_PTEG_FULL; 458b55d295eSDavid Gibson case -EBUSY: 459b55d295eSDavid Gibson return H_BUSY; 460b55d295eSDavid Gibson case -ENOMEM: 461b55d295eSDavid Gibson return H_NO_MEM; 462b55d295eSDavid Gibson default: 463b55d295eSDavid Gibson return H_HARDWARE; 464b55d295eSDavid Gibson } 465b55d295eSDavid Gibson } 466b55d295eSDavid Gibson 46730f4b05bSDavid Gibson static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 46830f4b05bSDavid Gibson sPAPRMachineState *spapr, 46930f4b05bSDavid Gibson target_ulong opcode, 47030f4b05bSDavid Gibson target_ulong *args) 47130f4b05bSDavid Gibson { 47230f4b05bSDavid Gibson target_ulong flags = args[0]; 4730b0b8310SDavid Gibson int shift = args[1]; 4740b0b8310SDavid Gibson sPAPRPendingHPT *pending = spapr->pending_hpt; 4750b0b8310SDavid Gibson uint64_t current_ram_size = MACHINE(spapr)->ram_size; 476b55d295eSDavid Gibson int rc; 47730f4b05bSDavid Gibson 47830f4b05bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 47930f4b05bSDavid Gibson return H_AUTHORITY; 48030f4b05bSDavid Gibson } 48130f4b05bSDavid Gibson 4820b0b8310SDavid Gibson if (!spapr->htab_shift) { 4830b0b8310SDavid Gibson /* Radix guest, no HPT */ 4840b0b8310SDavid Gibson return H_NOT_AVAILABLE; 4850b0b8310SDavid Gibson } 4860b0b8310SDavid Gibson 48730f4b05bSDavid Gibson trace_spapr_h_resize_hpt_prepare(flags, shift); 4880b0b8310SDavid Gibson 4890b0b8310SDavid Gibson if (flags != 0) { 4900b0b8310SDavid Gibson return H_PARAMETER; 4910b0b8310SDavid Gibson } 4920b0b8310SDavid Gibson 4930b0b8310SDavid Gibson if (shift && ((shift < 18) || (shift > 46))) { 4940b0b8310SDavid Gibson return H_PARAMETER; 4950b0b8310SDavid Gibson } 4960b0b8310SDavid Gibson 4970b0b8310SDavid Gibson current_ram_size = pc_existing_dimms_capacity(&error_fatal); 4980b0b8310SDavid Gibson 4990b0b8310SDavid Gibson /* We only allow the guest to allocate an HPT one order above what 5000b0b8310SDavid Gibson * we'd normally give them (to stop a small guest claiming a huge 5010b0b8310SDavid Gibson * chunk of resources in the HPT */ 5020b0b8310SDavid Gibson if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 5030b0b8310SDavid Gibson return H_RESOURCE; 5040b0b8310SDavid Gibson } 5050b0b8310SDavid Gibson 506b55d295eSDavid Gibson rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 507b55d295eSDavid Gibson if (rc != -ENOSYS) { 508b55d295eSDavid Gibson return resize_hpt_convert_rc(rc); 509b55d295eSDavid Gibson } 510b55d295eSDavid Gibson 5110b0b8310SDavid Gibson if (pending) { 5120b0b8310SDavid Gibson /* something already in progress */ 5130b0b8310SDavid Gibson if (pending->shift == shift) { 5140b0b8310SDavid Gibson /* and it's suitable */ 5150b0b8310SDavid Gibson if (pending->complete) { 5160b0b8310SDavid Gibson return pending->ret; 5170b0b8310SDavid Gibson } else { 5180b0b8310SDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 5190b0b8310SDavid Gibson } 5200b0b8310SDavid Gibson } 5210b0b8310SDavid Gibson 5220b0b8310SDavid Gibson /* not suitable, cancel and replace */ 5230b0b8310SDavid Gibson cancel_hpt_prepare(spapr); 5240b0b8310SDavid Gibson } 5250b0b8310SDavid Gibson 5260b0b8310SDavid Gibson if (!shift) { 5270b0b8310SDavid Gibson /* nothing to do */ 5280b0b8310SDavid Gibson return H_SUCCESS; 5290b0b8310SDavid Gibson } 5300b0b8310SDavid Gibson 5310b0b8310SDavid Gibson /* start new prepare */ 5320b0b8310SDavid Gibson 5330b0b8310SDavid Gibson pending = g_new0(sPAPRPendingHPT, 1); 5340b0b8310SDavid Gibson pending->shift = shift; 5350b0b8310SDavid Gibson pending->ret = H_HARDWARE; 5360b0b8310SDavid Gibson 5370b0b8310SDavid Gibson qemu_thread_create(&pending->thread, "sPAPR HPT prepare", 5380b0b8310SDavid Gibson hpt_prepare_thread, pending, QEMU_THREAD_DETACHED); 5390b0b8310SDavid Gibson 5400b0b8310SDavid Gibson spapr->pending_hpt = pending; 5410b0b8310SDavid Gibson 5420b0b8310SDavid Gibson /* In theory we could estimate the time more accurately based on 5430b0b8310SDavid Gibson * the new size, but there's not much point */ 5440b0b8310SDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 5450b0b8310SDavid Gibson } 5460b0b8310SDavid Gibson 5470b0b8310SDavid Gibson static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot) 5480b0b8310SDavid Gibson { 5490b0b8310SDavid Gibson uint8_t *addr = htab; 5500b0b8310SDavid Gibson 5510b0b8310SDavid Gibson addr += pteg * HASH_PTEG_SIZE_64; 5520b0b8310SDavid Gibson addr += slot * HASH_PTE_SIZE_64; 5530b0b8310SDavid Gibson return ldq_p(addr); 5540b0b8310SDavid Gibson } 5550b0b8310SDavid Gibson 5560b0b8310SDavid Gibson static void new_hpte_store(void *htab, uint64_t pteg, int slot, 5570b0b8310SDavid Gibson uint64_t pte0, uint64_t pte1) 5580b0b8310SDavid Gibson { 5590b0b8310SDavid Gibson uint8_t *addr = htab; 5600b0b8310SDavid Gibson 5610b0b8310SDavid Gibson addr += pteg * HASH_PTEG_SIZE_64; 5620b0b8310SDavid Gibson addr += slot * HASH_PTE_SIZE_64; 5630b0b8310SDavid Gibson 5640b0b8310SDavid Gibson stq_p(addr, pte0); 5650b0b8310SDavid Gibson stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1); 5660b0b8310SDavid Gibson } 5670b0b8310SDavid Gibson 5680b0b8310SDavid Gibson static int rehash_hpte(PowerPCCPU *cpu, 5690b0b8310SDavid Gibson const ppc_hash_pte64_t *hptes, 5700b0b8310SDavid Gibson void *old_hpt, uint64_t oldsize, 5710b0b8310SDavid Gibson void *new_hpt, uint64_t newsize, 5720b0b8310SDavid Gibson uint64_t pteg, int slot) 5730b0b8310SDavid Gibson { 5740b0b8310SDavid Gibson uint64_t old_hash_mask = (oldsize >> 7) - 1; 5750b0b8310SDavid Gibson uint64_t new_hash_mask = (newsize >> 7) - 1; 5760b0b8310SDavid Gibson target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot); 5770b0b8310SDavid Gibson target_ulong pte1; 5780b0b8310SDavid Gibson uint64_t avpn; 5790b0b8310SDavid Gibson unsigned base_pg_shift; 5800b0b8310SDavid Gibson uint64_t hash, new_pteg, replace_pte0; 5810b0b8310SDavid Gibson 5820b0b8310SDavid Gibson if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) { 5830b0b8310SDavid Gibson return H_SUCCESS; 5840b0b8310SDavid Gibson } 5850b0b8310SDavid Gibson 5860b0b8310SDavid Gibson pte1 = ppc_hash64_hpte1(cpu, hptes, slot); 5870b0b8310SDavid Gibson 5880b0b8310SDavid Gibson base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1); 5890b0b8310SDavid Gibson assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */ 5900b0b8310SDavid Gibson avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23); 5910b0b8310SDavid Gibson 5920b0b8310SDavid Gibson if (pte0 & HPTE64_V_SECONDARY) { 5930b0b8310SDavid Gibson pteg = ~pteg; 5940b0b8310SDavid Gibson } 5950b0b8310SDavid Gibson 5960b0b8310SDavid Gibson if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) { 5970b0b8310SDavid Gibson uint64_t offset, vsid; 5980b0b8310SDavid Gibson 5990b0b8310SDavid Gibson /* We only have 28 - 23 bits of offset in avpn */ 6000b0b8310SDavid Gibson offset = (avpn & 0x1f) << 23; 6010b0b8310SDavid Gibson vsid = avpn >> 5; 6020b0b8310SDavid Gibson /* We can find more bits from the pteg value */ 6030b0b8310SDavid Gibson if (base_pg_shift < 23) { 6040b0b8310SDavid Gibson offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift; 6050b0b8310SDavid Gibson } 6060b0b8310SDavid Gibson 6070b0b8310SDavid Gibson hash = vsid ^ (offset >> base_pg_shift); 6080b0b8310SDavid Gibson } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) { 6090b0b8310SDavid Gibson uint64_t offset, vsid; 6100b0b8310SDavid Gibson 6110b0b8310SDavid Gibson /* We only have 40 - 23 bits of seg_off in avpn */ 6120b0b8310SDavid Gibson offset = (avpn & 0x1ffff) << 23; 6130b0b8310SDavid Gibson vsid = avpn >> 17; 6140b0b8310SDavid Gibson if (base_pg_shift < 23) { 6150b0b8310SDavid Gibson offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask) 6160b0b8310SDavid Gibson << base_pg_shift; 6170b0b8310SDavid Gibson } 6180b0b8310SDavid Gibson 6190b0b8310SDavid Gibson hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift); 6200b0b8310SDavid Gibson } else { 6210b0b8310SDavid Gibson error_report("rehash_pte: Bad segment size in HPTE"); 62230f4b05bSDavid Gibson return H_HARDWARE; 62330f4b05bSDavid Gibson } 62430f4b05bSDavid Gibson 6250b0b8310SDavid Gibson new_pteg = hash & new_hash_mask; 6260b0b8310SDavid Gibson if (pte0 & HPTE64_V_SECONDARY) { 6270b0b8310SDavid Gibson assert(~pteg == (hash & old_hash_mask)); 6280b0b8310SDavid Gibson new_pteg = ~new_pteg; 6290b0b8310SDavid Gibson } else { 6300b0b8310SDavid Gibson assert(pteg == (hash & old_hash_mask)); 6310b0b8310SDavid Gibson } 6320b0b8310SDavid Gibson assert((oldsize != newsize) || (pteg == new_pteg)); 6330b0b8310SDavid Gibson replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot); 6340b0b8310SDavid Gibson /* 6350b0b8310SDavid Gibson * Strictly speaking, we don't need all these tests, since we only 6360b0b8310SDavid Gibson * ever rehash bolted HPTEs. We might in future handle non-bolted 6370b0b8310SDavid Gibson * HPTEs, though so make the logic correct for those cases as 6380b0b8310SDavid Gibson * well. 6390b0b8310SDavid Gibson */ 6400b0b8310SDavid Gibson if (replace_pte0 & HPTE64_V_VALID) { 6410b0b8310SDavid Gibson assert(newsize < oldsize); 6420b0b8310SDavid Gibson if (replace_pte0 & HPTE64_V_BOLTED) { 6430b0b8310SDavid Gibson if (pte0 & HPTE64_V_BOLTED) { 6440b0b8310SDavid Gibson /* Bolted collision, nothing we can do */ 6450b0b8310SDavid Gibson return H_PTEG_FULL; 6460b0b8310SDavid Gibson } else { 6470b0b8310SDavid Gibson /* Discard this hpte */ 6480b0b8310SDavid Gibson return H_SUCCESS; 6490b0b8310SDavid Gibson } 6500b0b8310SDavid Gibson } 6510b0b8310SDavid Gibson } 6520b0b8310SDavid Gibson 6530b0b8310SDavid Gibson new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1); 6540b0b8310SDavid Gibson return H_SUCCESS; 6550b0b8310SDavid Gibson } 6560b0b8310SDavid Gibson 6570b0b8310SDavid Gibson static int rehash_hpt(PowerPCCPU *cpu, 6580b0b8310SDavid Gibson void *old_hpt, uint64_t oldsize, 6590b0b8310SDavid Gibson void *new_hpt, uint64_t newsize) 6600b0b8310SDavid Gibson { 6610b0b8310SDavid Gibson uint64_t n_ptegs = oldsize >> 7; 6620b0b8310SDavid Gibson uint64_t pteg; 6630b0b8310SDavid Gibson int slot; 6640b0b8310SDavid Gibson int rc; 6650b0b8310SDavid Gibson 6660b0b8310SDavid Gibson for (pteg = 0; pteg < n_ptegs; pteg++) { 6670b0b8310SDavid Gibson hwaddr ptex = pteg * HPTES_PER_GROUP; 6680b0b8310SDavid Gibson const ppc_hash_pte64_t *hptes 6690b0b8310SDavid Gibson = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 6700b0b8310SDavid Gibson 6710b0b8310SDavid Gibson if (!hptes) { 6720b0b8310SDavid Gibson return H_HARDWARE; 6730b0b8310SDavid Gibson } 6740b0b8310SDavid Gibson 6750b0b8310SDavid Gibson for (slot = 0; slot < HPTES_PER_GROUP; slot++) { 6760b0b8310SDavid Gibson rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize, 6770b0b8310SDavid Gibson pteg, slot); 6780b0b8310SDavid Gibson if (rc != H_SUCCESS) { 6790b0b8310SDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 6800b0b8310SDavid Gibson return rc; 6810b0b8310SDavid Gibson } 6820b0b8310SDavid Gibson } 6830b0b8310SDavid Gibson ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 6840b0b8310SDavid Gibson } 6850b0b8310SDavid Gibson 6860b0b8310SDavid Gibson return H_SUCCESS; 6870b0b8310SDavid Gibson } 6880b0b8310SDavid Gibson 68930f4b05bSDavid Gibson static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 69030f4b05bSDavid Gibson sPAPRMachineState *spapr, 69130f4b05bSDavid Gibson target_ulong opcode, 69230f4b05bSDavid Gibson target_ulong *args) 69330f4b05bSDavid Gibson { 69430f4b05bSDavid Gibson target_ulong flags = args[0]; 69530f4b05bSDavid Gibson target_ulong shift = args[1]; 6960b0b8310SDavid Gibson sPAPRPendingHPT *pending = spapr->pending_hpt; 6970b0b8310SDavid Gibson int rc; 6980b0b8310SDavid Gibson size_t newsize; 69930f4b05bSDavid Gibson 70030f4b05bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 70130f4b05bSDavid Gibson return H_AUTHORITY; 70230f4b05bSDavid Gibson } 70330f4b05bSDavid Gibson 70430f4b05bSDavid Gibson trace_spapr_h_resize_hpt_commit(flags, shift); 7050b0b8310SDavid Gibson 706b55d295eSDavid Gibson rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 707b55d295eSDavid Gibson if (rc != -ENOSYS) { 708b55d295eSDavid Gibson return resize_hpt_convert_rc(rc); 709b55d295eSDavid Gibson } 710b55d295eSDavid Gibson 7110b0b8310SDavid Gibson if (flags != 0) { 7120b0b8310SDavid Gibson return H_PARAMETER; 7130b0b8310SDavid Gibson } 7140b0b8310SDavid Gibson 7150b0b8310SDavid Gibson if (!pending || (pending->shift != shift)) { 7160b0b8310SDavid Gibson /* no matching prepare */ 7170b0b8310SDavid Gibson return H_CLOSED; 7180b0b8310SDavid Gibson } 7190b0b8310SDavid Gibson 7200b0b8310SDavid Gibson if (!pending->complete) { 7210b0b8310SDavid Gibson /* prepare has not completed */ 7220b0b8310SDavid Gibson return H_BUSY; 7230b0b8310SDavid Gibson } 7240b0b8310SDavid Gibson 7250b0b8310SDavid Gibson /* Shouldn't have got past PREPARE without an HPT */ 7260b0b8310SDavid Gibson g_assert(spapr->htab_shift); 7270b0b8310SDavid Gibson 7280b0b8310SDavid Gibson newsize = 1ULL << pending->shift; 7290b0b8310SDavid Gibson rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr), 7300b0b8310SDavid Gibson pending->hpt, newsize); 7310b0b8310SDavid Gibson if (rc == H_SUCCESS) { 7320b0b8310SDavid Gibson qemu_vfree(spapr->htab); 7330b0b8310SDavid Gibson spapr->htab = pending->hpt; 7340b0b8310SDavid Gibson spapr->htab_shift = pending->shift; 7350b0b8310SDavid Gibson 736b55d295eSDavid Gibson if (kvm_enabled()) { 737b55d295eSDavid Gibson /* For KVM PR, update the HPT pointer */ 738b55d295eSDavid Gibson target_ulong sdr1 = (target_ulong)(uintptr_t)spapr->htab 739b55d295eSDavid Gibson | (spapr->htab_shift - 18); 740b55d295eSDavid Gibson kvmppc_update_sdr1(sdr1); 741b55d295eSDavid Gibson } 742b55d295eSDavid Gibson 7430b0b8310SDavid Gibson pending->hpt = NULL; /* so it's not free()d */ 7440b0b8310SDavid Gibson } 7450b0b8310SDavid Gibson 7460b0b8310SDavid Gibson /* Clean up */ 7470b0b8310SDavid Gibson spapr->pending_hpt = NULL; 7480b0b8310SDavid Gibson free_pending_hpt(pending); 7490b0b8310SDavid Gibson 7500b0b8310SDavid Gibson return rc; 75130f4b05bSDavid Gibson } 75230f4b05bSDavid Gibson 753423576f7SThomas Huth static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr, 754423576f7SThomas Huth target_ulong opcode, target_ulong *args) 755423576f7SThomas Huth { 756423576f7SThomas Huth cpu_synchronize_state(CPU(cpu)); 757423576f7SThomas Huth cpu->env.spr[SPR_SPRG0] = args[0]; 758423576f7SThomas Huth 759423576f7SThomas Huth return H_SUCCESS; 760423576f7SThomas Huth } 761423576f7SThomas Huth 76228e02042SDavid Gibson static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 7639f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 7649f64bd8aSPaolo Bonzini { 765af08a58fSThomas Huth if (!has_spr(cpu, SPR_DABR)) { 766af08a58fSThomas Huth return H_HARDWARE; /* DABR register not available */ 767af08a58fSThomas Huth } 768af08a58fSThomas Huth cpu_synchronize_state(CPU(cpu)); 769af08a58fSThomas Huth 770af08a58fSThomas Huth if (has_spr(cpu, SPR_DABRX)) { 771af08a58fSThomas Huth cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 772af08a58fSThomas Huth } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 773af08a58fSThomas Huth return H_RESERVED_DABR; 774af08a58fSThomas Huth } 775af08a58fSThomas Huth 776af08a58fSThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 777af08a58fSThomas Huth return H_SUCCESS; 7789f64bd8aSPaolo Bonzini } 7799f64bd8aSPaolo Bonzini 780e49ff266SThomas Huth static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 781e49ff266SThomas Huth target_ulong opcode, target_ulong *args) 782e49ff266SThomas Huth { 783e49ff266SThomas Huth target_ulong dabrx = args[1]; 784e49ff266SThomas Huth 785e49ff266SThomas Huth if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { 786e49ff266SThomas Huth return H_HARDWARE; 787e49ff266SThomas Huth } 788e49ff266SThomas Huth 789e49ff266SThomas Huth if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 790e49ff266SThomas Huth || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 791e49ff266SThomas Huth return H_PARAMETER; 792e49ff266SThomas Huth } 793e49ff266SThomas Huth 794e49ff266SThomas Huth cpu_synchronize_state(CPU(cpu)); 795e49ff266SThomas Huth cpu->env.spr[SPR_DABRX] = dabrx; 796e49ff266SThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 797e49ff266SThomas Huth 798e49ff266SThomas Huth return H_SUCCESS; 799e49ff266SThomas Huth } 800e49ff266SThomas Huth 8013240dd9aSThomas Huth static target_ulong h_page_init(PowerPCCPU *cpu, sPAPRMachineState *spapr, 8023240dd9aSThomas Huth target_ulong opcode, target_ulong *args) 8033240dd9aSThomas Huth { 8043240dd9aSThomas Huth target_ulong flags = args[0]; 8053240dd9aSThomas Huth hwaddr dst = args[1]; 8063240dd9aSThomas Huth hwaddr src = args[2]; 8073240dd9aSThomas Huth hwaddr len = TARGET_PAGE_SIZE; 8083240dd9aSThomas Huth uint8_t *pdst, *psrc; 8093240dd9aSThomas Huth target_long ret = H_SUCCESS; 8103240dd9aSThomas Huth 8113240dd9aSThomas Huth if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 8123240dd9aSThomas Huth | H_COPY_PAGE | H_ZERO_PAGE)) { 8133240dd9aSThomas Huth qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 8143240dd9aSThomas Huth flags); 8153240dd9aSThomas Huth return H_PARAMETER; 8163240dd9aSThomas Huth } 8173240dd9aSThomas Huth 8183240dd9aSThomas Huth /* Map-in destination */ 8193240dd9aSThomas Huth if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 8203240dd9aSThomas Huth return H_PARAMETER; 8213240dd9aSThomas Huth } 8223240dd9aSThomas Huth pdst = cpu_physical_memory_map(dst, &len, 1); 8233240dd9aSThomas Huth if (!pdst || len != TARGET_PAGE_SIZE) { 8243240dd9aSThomas Huth return H_PARAMETER; 8253240dd9aSThomas Huth } 8263240dd9aSThomas Huth 8273240dd9aSThomas Huth if (flags & H_COPY_PAGE) { 8283240dd9aSThomas Huth /* Map-in source, copy to destination, and unmap source again */ 8293240dd9aSThomas Huth if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 8303240dd9aSThomas Huth ret = H_PARAMETER; 8313240dd9aSThomas Huth goto unmap_out; 8323240dd9aSThomas Huth } 8333240dd9aSThomas Huth psrc = cpu_physical_memory_map(src, &len, 0); 8343240dd9aSThomas Huth if (!psrc || len != TARGET_PAGE_SIZE) { 8353240dd9aSThomas Huth ret = H_PARAMETER; 8363240dd9aSThomas Huth goto unmap_out; 8373240dd9aSThomas Huth } 8383240dd9aSThomas Huth memcpy(pdst, psrc, len); 8393240dd9aSThomas Huth cpu_physical_memory_unmap(psrc, len, 0, len); 8403240dd9aSThomas Huth } else if (flags & H_ZERO_PAGE) { 8413240dd9aSThomas Huth memset(pdst, 0, len); /* Just clear the destination page */ 8423240dd9aSThomas Huth } 8433240dd9aSThomas Huth 8443240dd9aSThomas Huth if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 8453240dd9aSThomas Huth kvmppc_dcbst_range(cpu, pdst, len); 8463240dd9aSThomas Huth } 8473240dd9aSThomas Huth if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 8483240dd9aSThomas Huth if (kvm_enabled()) { 8493240dd9aSThomas Huth kvmppc_icbi_range(cpu, pdst, len); 8503240dd9aSThomas Huth } else { 8513240dd9aSThomas Huth tb_flush(CPU(cpu)); 8523240dd9aSThomas Huth } 8533240dd9aSThomas Huth } 8543240dd9aSThomas Huth 8553240dd9aSThomas Huth unmap_out: 8563240dd9aSThomas Huth cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 8573240dd9aSThomas Huth return ret; 8583240dd9aSThomas Huth } 8593240dd9aSThomas Huth 8609f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 8619f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 8629f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 8639f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 8649f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 8659f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 8669f64bd8aSPaolo Bonzini 8679f64bd8aSPaolo Bonzini #define VPA_MIN_SIZE 640 8689f64bd8aSPaolo Bonzini #define VPA_SIZE_OFFSET 0x4 8699f64bd8aSPaolo Bonzini #define VPA_SHARED_PROC_OFFSET 0x9 8709f64bd8aSPaolo Bonzini #define VPA_SHARED_PROC_VAL 0x2 8719f64bd8aSPaolo Bonzini 8729f64bd8aSPaolo Bonzini static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) 8739f64bd8aSPaolo Bonzini { 87433276f1bSAndreas Färber CPUState *cs = CPU(ppc_env_get_cpu(env)); 8759f64bd8aSPaolo Bonzini uint16_t size; 8769f64bd8aSPaolo Bonzini uint8_t tmp; 8779f64bd8aSPaolo Bonzini 8789f64bd8aSPaolo Bonzini if (vpa == 0) { 8799f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 8809f64bd8aSPaolo Bonzini return H_HARDWARE; 8819f64bd8aSPaolo Bonzini } 8829f64bd8aSPaolo Bonzini 8839f64bd8aSPaolo Bonzini if (vpa % env->dcache_line_size) { 8849f64bd8aSPaolo Bonzini return H_PARAMETER; 8859f64bd8aSPaolo Bonzini } 8869f64bd8aSPaolo Bonzini /* FIXME: bounds check the address */ 8879f64bd8aSPaolo Bonzini 88841701aa4SEdgar E. Iglesias size = lduw_be_phys(cs->as, vpa + 0x4); 8899f64bd8aSPaolo Bonzini 8909f64bd8aSPaolo Bonzini if (size < VPA_MIN_SIZE) { 8919f64bd8aSPaolo Bonzini return H_PARAMETER; 8929f64bd8aSPaolo Bonzini } 8939f64bd8aSPaolo Bonzini 8949f64bd8aSPaolo Bonzini /* VPA is not allowed to cross a page boundary */ 8959f64bd8aSPaolo Bonzini if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 8969f64bd8aSPaolo Bonzini return H_PARAMETER; 8979f64bd8aSPaolo Bonzini } 8989f64bd8aSPaolo Bonzini 8999f64bd8aSPaolo Bonzini env->vpa_addr = vpa; 9009f64bd8aSPaolo Bonzini 9012c17449bSEdgar E. Iglesias tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); 9029f64bd8aSPaolo Bonzini tmp |= VPA_SHARED_PROC_VAL; 903db3be60dSEdgar E. Iglesias stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 9049f64bd8aSPaolo Bonzini 9059f64bd8aSPaolo Bonzini return H_SUCCESS; 9069f64bd8aSPaolo Bonzini } 9079f64bd8aSPaolo Bonzini 9089f64bd8aSPaolo Bonzini static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) 9099f64bd8aSPaolo Bonzini { 9109f64bd8aSPaolo Bonzini if (env->slb_shadow_addr) { 9119f64bd8aSPaolo Bonzini return H_RESOURCE; 9129f64bd8aSPaolo Bonzini } 9139f64bd8aSPaolo Bonzini 9149f64bd8aSPaolo Bonzini if (env->dtl_addr) { 9159f64bd8aSPaolo Bonzini return H_RESOURCE; 9169f64bd8aSPaolo Bonzini } 9179f64bd8aSPaolo Bonzini 9189f64bd8aSPaolo Bonzini env->vpa_addr = 0; 9199f64bd8aSPaolo Bonzini return H_SUCCESS; 9209f64bd8aSPaolo Bonzini } 9219f64bd8aSPaolo Bonzini 9229f64bd8aSPaolo Bonzini static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) 9239f64bd8aSPaolo Bonzini { 92433276f1bSAndreas Färber CPUState *cs = CPU(ppc_env_get_cpu(env)); 9259f64bd8aSPaolo Bonzini uint32_t size; 9269f64bd8aSPaolo Bonzini 9279f64bd8aSPaolo Bonzini if (addr == 0) { 9289f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 9299f64bd8aSPaolo Bonzini return H_HARDWARE; 9309f64bd8aSPaolo Bonzini } 9319f64bd8aSPaolo Bonzini 932fdfba1a2SEdgar E. Iglesias size = ldl_be_phys(cs->as, addr + 0x4); 9339f64bd8aSPaolo Bonzini if (size < 0x8) { 9349f64bd8aSPaolo Bonzini return H_PARAMETER; 9359f64bd8aSPaolo Bonzini } 9369f64bd8aSPaolo Bonzini 9379f64bd8aSPaolo Bonzini if ((addr / 4096) != ((addr + size - 1) / 4096)) { 9389f64bd8aSPaolo Bonzini return H_PARAMETER; 9399f64bd8aSPaolo Bonzini } 9409f64bd8aSPaolo Bonzini 9419f64bd8aSPaolo Bonzini if (!env->vpa_addr) { 9429f64bd8aSPaolo Bonzini return H_RESOURCE; 9439f64bd8aSPaolo Bonzini } 9449f64bd8aSPaolo Bonzini 9459f64bd8aSPaolo Bonzini env->slb_shadow_addr = addr; 9469f64bd8aSPaolo Bonzini env->slb_shadow_size = size; 9479f64bd8aSPaolo Bonzini 9489f64bd8aSPaolo Bonzini return H_SUCCESS; 9499f64bd8aSPaolo Bonzini } 9509f64bd8aSPaolo Bonzini 9519f64bd8aSPaolo Bonzini static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) 9529f64bd8aSPaolo Bonzini { 9539f64bd8aSPaolo Bonzini env->slb_shadow_addr = 0; 9549f64bd8aSPaolo Bonzini env->slb_shadow_size = 0; 9559f64bd8aSPaolo Bonzini return H_SUCCESS; 9569f64bd8aSPaolo Bonzini } 9579f64bd8aSPaolo Bonzini 9589f64bd8aSPaolo Bonzini static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) 9599f64bd8aSPaolo Bonzini { 96033276f1bSAndreas Färber CPUState *cs = CPU(ppc_env_get_cpu(env)); 9619f64bd8aSPaolo Bonzini uint32_t size; 9629f64bd8aSPaolo Bonzini 9639f64bd8aSPaolo Bonzini if (addr == 0) { 9649f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with DTL at logical 0\n"); 9659f64bd8aSPaolo Bonzini return H_HARDWARE; 9669f64bd8aSPaolo Bonzini } 9679f64bd8aSPaolo Bonzini 968fdfba1a2SEdgar E. Iglesias size = ldl_be_phys(cs->as, addr + 0x4); 9699f64bd8aSPaolo Bonzini 9709f64bd8aSPaolo Bonzini if (size < 48) { 9719f64bd8aSPaolo Bonzini return H_PARAMETER; 9729f64bd8aSPaolo Bonzini } 9739f64bd8aSPaolo Bonzini 9749f64bd8aSPaolo Bonzini if (!env->vpa_addr) { 9759f64bd8aSPaolo Bonzini return H_RESOURCE; 9769f64bd8aSPaolo Bonzini } 9779f64bd8aSPaolo Bonzini 9789f64bd8aSPaolo Bonzini env->dtl_addr = addr; 9799f64bd8aSPaolo Bonzini env->dtl_size = size; 9809f64bd8aSPaolo Bonzini 9819f64bd8aSPaolo Bonzini return H_SUCCESS; 9829f64bd8aSPaolo Bonzini } 9839f64bd8aSPaolo Bonzini 9849f64bd8aSPaolo Bonzini static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) 9859f64bd8aSPaolo Bonzini { 9869f64bd8aSPaolo Bonzini env->dtl_addr = 0; 9879f64bd8aSPaolo Bonzini env->dtl_size = 0; 9889f64bd8aSPaolo Bonzini 9899f64bd8aSPaolo Bonzini return H_SUCCESS; 9909f64bd8aSPaolo Bonzini } 9919f64bd8aSPaolo Bonzini 99228e02042SDavid Gibson static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr, 9939f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 9949f64bd8aSPaolo Bonzini { 9959f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 9969f64bd8aSPaolo Bonzini target_ulong procno = args[1]; 9979f64bd8aSPaolo Bonzini target_ulong vpa = args[2]; 9989f64bd8aSPaolo Bonzini target_ulong ret = H_PARAMETER; 9999f64bd8aSPaolo Bonzini CPUPPCState *tenv; 10000f20ba62SAlexey Kardashevskiy PowerPCCPU *tcpu; 10019f64bd8aSPaolo Bonzini 10022e886fb3SSam Bobroff tcpu = spapr_find_cpu(procno); 10039f64bd8aSPaolo Bonzini if (!tcpu) { 10049f64bd8aSPaolo Bonzini return H_PARAMETER; 10059f64bd8aSPaolo Bonzini } 10060f20ba62SAlexey Kardashevskiy tenv = &tcpu->env; 10079f64bd8aSPaolo Bonzini 10089f64bd8aSPaolo Bonzini switch (flags) { 10099f64bd8aSPaolo Bonzini case FLAGS_REGISTER_VPA: 10109f64bd8aSPaolo Bonzini ret = register_vpa(tenv, vpa); 10119f64bd8aSPaolo Bonzini break; 10129f64bd8aSPaolo Bonzini 10139f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_VPA: 10149f64bd8aSPaolo Bonzini ret = deregister_vpa(tenv, vpa); 10159f64bd8aSPaolo Bonzini break; 10169f64bd8aSPaolo Bonzini 10179f64bd8aSPaolo Bonzini case FLAGS_REGISTER_SLBSHADOW: 10189f64bd8aSPaolo Bonzini ret = register_slb_shadow(tenv, vpa); 10199f64bd8aSPaolo Bonzini break; 10209f64bd8aSPaolo Bonzini 10219f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_SLBSHADOW: 10229f64bd8aSPaolo Bonzini ret = deregister_slb_shadow(tenv, vpa); 10239f64bd8aSPaolo Bonzini break; 10249f64bd8aSPaolo Bonzini 10259f64bd8aSPaolo Bonzini case FLAGS_REGISTER_DTL: 10269f64bd8aSPaolo Bonzini ret = register_dtl(tenv, vpa); 10279f64bd8aSPaolo Bonzini break; 10289f64bd8aSPaolo Bonzini 10299f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_DTL: 10309f64bd8aSPaolo Bonzini ret = deregister_dtl(tenv, vpa); 10319f64bd8aSPaolo Bonzini break; 10329f64bd8aSPaolo Bonzini } 10339f64bd8aSPaolo Bonzini 10349f64bd8aSPaolo Bonzini return ret; 10359f64bd8aSPaolo Bonzini } 10369f64bd8aSPaolo Bonzini 103728e02042SDavid Gibson static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr, 10389f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 10399f64bd8aSPaolo Bonzini { 10409f64bd8aSPaolo Bonzini CPUPPCState *env = &cpu->env; 10419f64bd8aSPaolo Bonzini CPUState *cs = CPU(cpu); 10429f64bd8aSPaolo Bonzini 10439f64bd8aSPaolo Bonzini env->msr |= (1ULL << MSR_EE); 10449f64bd8aSPaolo Bonzini hreg_compute_hflags(env); 10459f64bd8aSPaolo Bonzini if (!cpu_has_work(cs)) { 1046259186a7SAndreas Färber cs->halted = 1; 104727103424SAndreas Färber cs->exception_index = EXCP_HLT; 10489f64bd8aSPaolo Bonzini cs->exit_request = 1; 10499f64bd8aSPaolo Bonzini } 10509f64bd8aSPaolo Bonzini return H_SUCCESS; 10519f64bd8aSPaolo Bonzini } 10529f64bd8aSPaolo Bonzini 105328e02042SDavid Gibson static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr, 10549f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 10559f64bd8aSPaolo Bonzini { 10569f64bd8aSPaolo Bonzini target_ulong rtas_r3 = args[0]; 10574fe822e0SAlexey Kardashevskiy uint32_t token = rtas_ld(rtas_r3, 0); 10584fe822e0SAlexey Kardashevskiy uint32_t nargs = rtas_ld(rtas_r3, 1); 10594fe822e0SAlexey Kardashevskiy uint32_t nret = rtas_ld(rtas_r3, 2); 10609f64bd8aSPaolo Bonzini 1061210b580bSAnthony Liguori return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 10629f64bd8aSPaolo Bonzini nret, rtas_r3 + 12 + 4*nargs); 10639f64bd8aSPaolo Bonzini } 10649f64bd8aSPaolo Bonzini 106528e02042SDavid Gibson static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr, 10669f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 10679f64bd8aSPaolo Bonzini { 1068fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 10699f64bd8aSPaolo Bonzini target_ulong size = args[0]; 10709f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 10719f64bd8aSPaolo Bonzini 10729f64bd8aSPaolo Bonzini switch (size) { 10739f64bd8aSPaolo Bonzini case 1: 10742c17449bSEdgar E. Iglesias args[0] = ldub_phys(cs->as, addr); 10759f64bd8aSPaolo Bonzini return H_SUCCESS; 10769f64bd8aSPaolo Bonzini case 2: 107741701aa4SEdgar E. Iglesias args[0] = lduw_phys(cs->as, addr); 10789f64bd8aSPaolo Bonzini return H_SUCCESS; 10799f64bd8aSPaolo Bonzini case 4: 1080fdfba1a2SEdgar E. Iglesias args[0] = ldl_phys(cs->as, addr); 10819f64bd8aSPaolo Bonzini return H_SUCCESS; 10829f64bd8aSPaolo Bonzini case 8: 10832c17449bSEdgar E. Iglesias args[0] = ldq_phys(cs->as, addr); 10849f64bd8aSPaolo Bonzini return H_SUCCESS; 10859f64bd8aSPaolo Bonzini } 10869f64bd8aSPaolo Bonzini return H_PARAMETER; 10879f64bd8aSPaolo Bonzini } 10889f64bd8aSPaolo Bonzini 108928e02042SDavid Gibson static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, 10909f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 10919f64bd8aSPaolo Bonzini { 1092f606604fSEdgar E. Iglesias CPUState *cs = CPU(cpu); 1093f606604fSEdgar E. Iglesias 10949f64bd8aSPaolo Bonzini target_ulong size = args[0]; 10959f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 10969f64bd8aSPaolo Bonzini target_ulong val = args[2]; 10979f64bd8aSPaolo Bonzini 10989f64bd8aSPaolo Bonzini switch (size) { 10999f64bd8aSPaolo Bonzini case 1: 1100db3be60dSEdgar E. Iglesias stb_phys(cs->as, addr, val); 11019f64bd8aSPaolo Bonzini return H_SUCCESS; 11029f64bd8aSPaolo Bonzini case 2: 11035ce5944dSEdgar E. Iglesias stw_phys(cs->as, addr, val); 11049f64bd8aSPaolo Bonzini return H_SUCCESS; 11059f64bd8aSPaolo Bonzini case 4: 1106ab1da857SEdgar E. Iglesias stl_phys(cs->as, addr, val); 11079f64bd8aSPaolo Bonzini return H_SUCCESS; 11089f64bd8aSPaolo Bonzini case 8: 1109f606604fSEdgar E. Iglesias stq_phys(cs->as, addr, val); 11109f64bd8aSPaolo Bonzini return H_SUCCESS; 11119f64bd8aSPaolo Bonzini } 11129f64bd8aSPaolo Bonzini return H_PARAMETER; 11139f64bd8aSPaolo Bonzini } 11149f64bd8aSPaolo Bonzini 111528e02042SDavid Gibson static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr, 11169f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 11179f64bd8aSPaolo Bonzini { 1118fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 1119fdfba1a2SEdgar E. Iglesias 11209f64bd8aSPaolo Bonzini target_ulong dst = args[0]; /* Destination address */ 11219f64bd8aSPaolo Bonzini target_ulong src = args[1]; /* Source address */ 11229f64bd8aSPaolo Bonzini target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 11239f64bd8aSPaolo Bonzini target_ulong count = args[3]; /* Element count */ 11249f64bd8aSPaolo Bonzini target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 11259f64bd8aSPaolo Bonzini uint64_t tmp; 11269f64bd8aSPaolo Bonzini unsigned int mask = (1 << esize) - 1; 11279f64bd8aSPaolo Bonzini int step = 1 << esize; 11289f64bd8aSPaolo Bonzini 11299f64bd8aSPaolo Bonzini if (count > 0x80000000) { 11309f64bd8aSPaolo Bonzini return H_PARAMETER; 11319f64bd8aSPaolo Bonzini } 11329f64bd8aSPaolo Bonzini 11339f64bd8aSPaolo Bonzini if ((dst & mask) || (src & mask) || (op > 1)) { 11349f64bd8aSPaolo Bonzini return H_PARAMETER; 11359f64bd8aSPaolo Bonzini } 11369f64bd8aSPaolo Bonzini 11379f64bd8aSPaolo Bonzini if (dst >= src && dst < (src + (count << esize))) { 11389f64bd8aSPaolo Bonzini dst = dst + ((count - 1) << esize); 11399f64bd8aSPaolo Bonzini src = src + ((count - 1) << esize); 11409f64bd8aSPaolo Bonzini step = -step; 11419f64bd8aSPaolo Bonzini } 11429f64bd8aSPaolo Bonzini 11439f64bd8aSPaolo Bonzini while (count--) { 11449f64bd8aSPaolo Bonzini switch (esize) { 11459f64bd8aSPaolo Bonzini case 0: 11462c17449bSEdgar E. Iglesias tmp = ldub_phys(cs->as, src); 11479f64bd8aSPaolo Bonzini break; 11489f64bd8aSPaolo Bonzini case 1: 114941701aa4SEdgar E. Iglesias tmp = lduw_phys(cs->as, src); 11509f64bd8aSPaolo Bonzini break; 11519f64bd8aSPaolo Bonzini case 2: 1152fdfba1a2SEdgar E. Iglesias tmp = ldl_phys(cs->as, src); 11539f64bd8aSPaolo Bonzini break; 11549f64bd8aSPaolo Bonzini case 3: 11552c17449bSEdgar E. Iglesias tmp = ldq_phys(cs->as, src); 11569f64bd8aSPaolo Bonzini break; 11579f64bd8aSPaolo Bonzini default: 11589f64bd8aSPaolo Bonzini return H_PARAMETER; 11599f64bd8aSPaolo Bonzini } 11609f64bd8aSPaolo Bonzini if (op == 1) { 11619f64bd8aSPaolo Bonzini tmp = ~tmp; 11629f64bd8aSPaolo Bonzini } 11639f64bd8aSPaolo Bonzini switch (esize) { 11649f64bd8aSPaolo Bonzini case 0: 1165db3be60dSEdgar E. Iglesias stb_phys(cs->as, dst, tmp); 11669f64bd8aSPaolo Bonzini break; 11679f64bd8aSPaolo Bonzini case 1: 11685ce5944dSEdgar E. Iglesias stw_phys(cs->as, dst, tmp); 11699f64bd8aSPaolo Bonzini break; 11709f64bd8aSPaolo Bonzini case 2: 1171ab1da857SEdgar E. Iglesias stl_phys(cs->as, dst, tmp); 11729f64bd8aSPaolo Bonzini break; 11739f64bd8aSPaolo Bonzini case 3: 1174f606604fSEdgar E. Iglesias stq_phys(cs->as, dst, tmp); 11759f64bd8aSPaolo Bonzini break; 11769f64bd8aSPaolo Bonzini } 11779f64bd8aSPaolo Bonzini dst = dst + step; 11789f64bd8aSPaolo Bonzini src = src + step; 11799f64bd8aSPaolo Bonzini } 11809f64bd8aSPaolo Bonzini 11819f64bd8aSPaolo Bonzini return H_SUCCESS; 11829f64bd8aSPaolo Bonzini } 11839f64bd8aSPaolo Bonzini 118428e02042SDavid Gibson static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 11859f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 11869f64bd8aSPaolo Bonzini { 11879f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 11889f64bd8aSPaolo Bonzini return H_SUCCESS; 11899f64bd8aSPaolo Bonzini } 11909f64bd8aSPaolo Bonzini 119128e02042SDavid Gibson static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr, 11929f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 11939f64bd8aSPaolo Bonzini { 11949f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 11959f64bd8aSPaolo Bonzini return H_SUCCESS; 11969f64bd8aSPaolo Bonzini } 11979f64bd8aSPaolo Bonzini 11987d0cd464SPeter Maydell static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 1199c4015bbdSAlexey Kardashevskiy target_ulong mflags, 1200c4015bbdSAlexey Kardashevskiy target_ulong value1, 1201c4015bbdSAlexey Kardashevskiy target_ulong value2) 120242561bf2SAnton Blanchard { 120342561bf2SAnton Blanchard CPUState *cs; 120442561bf2SAnton Blanchard 120542561bf2SAnton Blanchard if (value1) { 1206c4015bbdSAlexey Kardashevskiy return H_P3; 120742561bf2SAnton Blanchard } 120842561bf2SAnton Blanchard if (value2) { 1209c4015bbdSAlexey Kardashevskiy return H_P4; 121042561bf2SAnton Blanchard } 1211c4015bbdSAlexey Kardashevskiy 121242561bf2SAnton Blanchard switch (mflags) { 121342561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_BIG: 1214bdc44640SAndreas Färber CPU_FOREACH(cs) { 1215a46622fdSAlexey Kardashevskiy set_spr(cs, SPR_LPCR, 0, LPCR_ILE); 121642561bf2SAnton Blanchard } 1217eefaccc0SDavid Gibson spapr_pci_switch_vga(true); 1218c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 121942561bf2SAnton Blanchard 122042561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_LITTLE: 1221bdc44640SAndreas Färber CPU_FOREACH(cs) { 1222a46622fdSAlexey Kardashevskiy set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE); 122342561bf2SAnton Blanchard } 1224eefaccc0SDavid Gibson spapr_pci_switch_vga(false); 1225c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 1226c4015bbdSAlexey Kardashevskiy } 1227c4015bbdSAlexey Kardashevskiy 1228c4015bbdSAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 1229c4015bbdSAlexey Kardashevskiy } 1230c4015bbdSAlexey Kardashevskiy 12317d0cd464SPeter Maydell static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 1232d5ac4f54SAlexey Kardashevskiy target_ulong mflags, 1233d5ac4f54SAlexey Kardashevskiy target_ulong value1, 1234d5ac4f54SAlexey Kardashevskiy target_ulong value2) 1235d5ac4f54SAlexey Kardashevskiy { 1236d5ac4f54SAlexey Kardashevskiy CPUState *cs; 1237d5ac4f54SAlexey Kardashevskiy PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 1238d5ac4f54SAlexey Kardashevskiy 1239d5ac4f54SAlexey Kardashevskiy if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 1240d5ac4f54SAlexey Kardashevskiy return H_P2; 1241d5ac4f54SAlexey Kardashevskiy } 1242d5ac4f54SAlexey Kardashevskiy if (value1) { 1243d5ac4f54SAlexey Kardashevskiy return H_P3; 1244d5ac4f54SAlexey Kardashevskiy } 1245d5ac4f54SAlexey Kardashevskiy if (value2) { 1246d5ac4f54SAlexey Kardashevskiy return H_P4; 1247d5ac4f54SAlexey Kardashevskiy } 1248d5ac4f54SAlexey Kardashevskiy 12495c94b2a5SCédric Le Goater if (mflags == AIL_RESERVED) { 1250d5ac4f54SAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 1251d5ac4f54SAlexey Kardashevskiy } 1252d5ac4f54SAlexey Kardashevskiy 1253d5ac4f54SAlexey Kardashevskiy CPU_FOREACH(cs) { 1254d5ac4f54SAlexey Kardashevskiy set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL); 1255d5ac4f54SAlexey Kardashevskiy } 1256d5ac4f54SAlexey Kardashevskiy 1257d5ac4f54SAlexey Kardashevskiy return H_SUCCESS; 1258d5ac4f54SAlexey Kardashevskiy } 1259d5ac4f54SAlexey Kardashevskiy 126028e02042SDavid Gibson static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1261c4015bbdSAlexey Kardashevskiy target_ulong opcode, target_ulong *args) 1262c4015bbdSAlexey Kardashevskiy { 1263c4015bbdSAlexey Kardashevskiy target_ulong resource = args[1]; 1264c4015bbdSAlexey Kardashevskiy target_ulong ret = H_P2; 1265c4015bbdSAlexey Kardashevskiy 1266c4015bbdSAlexey Kardashevskiy switch (resource) { 1267c4015bbdSAlexey Kardashevskiy case H_SET_MODE_RESOURCE_LE: 12687d0cd464SPeter Maydell ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); 126942561bf2SAnton Blanchard break; 1270d5ac4f54SAlexey Kardashevskiy case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 12717d0cd464SPeter Maydell ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 1272d5ac4f54SAlexey Kardashevskiy args[2], args[3]); 1273d5ac4f54SAlexey Kardashevskiy break; 127442561bf2SAnton Blanchard } 127542561bf2SAnton Blanchard 127642561bf2SAnton Blanchard return ret; 127742561bf2SAnton Blanchard } 127842561bf2SAnton Blanchard 1279d77a98b0SSuraj Jitindar Singh static target_ulong h_clean_slb(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1280d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 1281d77a98b0SSuraj Jitindar Singh { 1282d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1283d77a98b0SSuraj Jitindar Singh opcode, " (H_CLEAN_SLB)"); 1284d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 1285d77a98b0SSuraj Jitindar Singh } 1286d77a98b0SSuraj Jitindar Singh 1287d77a98b0SSuraj Jitindar Singh static target_ulong h_invalidate_pid(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1288d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 1289d77a98b0SSuraj Jitindar Singh { 1290d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1291d77a98b0SSuraj Jitindar Singh opcode, " (H_INVALIDATE_PID)"); 1292d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 1293d77a98b0SSuraj Jitindar Singh } 1294d77a98b0SSuraj Jitindar Singh 1295b4db5413SSuraj Jitindar Singh static void spapr_check_setup_free_hpt(sPAPRMachineState *spapr, 1296b4db5413SSuraj Jitindar Singh uint64_t patbe_old, uint64_t patbe_new) 1297b4db5413SSuraj Jitindar Singh { 1298b4db5413SSuraj Jitindar Singh /* 1299b4db5413SSuraj Jitindar Singh * We have 4 Options: 1300b4db5413SSuraj Jitindar Singh * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 1301b4db5413SSuraj Jitindar Singh * HASH->RADIX : Free HPT 1302b4db5413SSuraj Jitindar Singh * RADIX->HASH : Allocate HPT 1303b4db5413SSuraj Jitindar Singh * NOTHING->HASH : Allocate HPT 1304b4db5413SSuraj Jitindar Singh * Note: NOTHING implies the case where we said the guest could choose 1305b4db5413SSuraj Jitindar Singh * later and so assumed radix and now it's called H_REG_PROC_TBL 1306b4db5413SSuraj Jitindar Singh */ 1307b4db5413SSuraj Jitindar Singh 1308b4db5413SSuraj Jitindar Singh if ((patbe_old & PATBE1_GR) == (patbe_new & PATBE1_GR)) { 1309b4db5413SSuraj Jitindar Singh /* We assume RADIX, so this catches all the "Do Nothing" cases */ 1310b4db5413SSuraj Jitindar Singh } else if (!(patbe_old & PATBE1_GR)) { 1311b4db5413SSuraj Jitindar Singh /* HASH->RADIX : Free HPT */ 131206ec79e8SBharata B Rao spapr_free_hpt(spapr); 1313b4db5413SSuraj Jitindar Singh } else if (!(patbe_new & PATBE1_GR)) { 1314b4db5413SSuraj Jitindar Singh /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 1315b4db5413SSuraj Jitindar Singh spapr_setup_hpt_and_vrma(spapr); 1316b4db5413SSuraj Jitindar Singh } 1317b4db5413SSuraj Jitindar Singh return; 1318b4db5413SSuraj Jitindar Singh } 1319b4db5413SSuraj Jitindar Singh 1320b4db5413SSuraj Jitindar Singh #define FLAGS_MASK 0x01FULL 1321b4db5413SSuraj Jitindar Singh #define FLAG_MODIFY 0x10 1322b4db5413SSuraj Jitindar Singh #define FLAG_REGISTER 0x08 1323b4db5413SSuraj Jitindar Singh #define FLAG_RADIX 0x04 1324b4db5413SSuraj Jitindar Singh #define FLAG_HASH_PROC_TBL 0x02 1325b4db5413SSuraj Jitindar Singh #define FLAG_GTSE 0x01 1326b4db5413SSuraj Jitindar Singh 1327d77a98b0SSuraj Jitindar Singh static target_ulong h_register_process_table(PowerPCCPU *cpu, 1328d77a98b0SSuraj Jitindar Singh sPAPRMachineState *spapr, 1329d77a98b0SSuraj Jitindar Singh target_ulong opcode, 1330d77a98b0SSuraj Jitindar Singh target_ulong *args) 1331d77a98b0SSuraj Jitindar Singh { 13326de83307SSuraj Jitindar Singh CPUState *cs; 1333b4db5413SSuraj Jitindar Singh target_ulong flags = args[0]; 1334b4db5413SSuraj Jitindar Singh target_ulong proc_tbl = args[1]; 1335b4db5413SSuraj Jitindar Singh target_ulong page_size = args[2]; 1336b4db5413SSuraj Jitindar Singh target_ulong table_size = args[3]; 1337b4db5413SSuraj Jitindar Singh uint64_t cproc; 1338b4db5413SSuraj Jitindar Singh 1339b4db5413SSuraj Jitindar Singh if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 1340b4db5413SSuraj Jitindar Singh return H_PARAMETER; 1341b4db5413SSuraj Jitindar Singh } 1342b4db5413SSuraj Jitindar Singh if (flags & FLAG_MODIFY) { 1343b4db5413SSuraj Jitindar Singh if (flags & FLAG_REGISTER) { 1344b4db5413SSuraj Jitindar Singh if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 1345b4db5413SSuraj Jitindar Singh if (proc_tbl & 0xfff || proc_tbl >> 60) { 1346b4db5413SSuraj Jitindar Singh return H_P2; 1347b4db5413SSuraj Jitindar Singh } else if (page_size) { 1348b4db5413SSuraj Jitindar Singh return H_P3; 1349b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 1350b4db5413SSuraj Jitindar Singh return H_P4; 1351b4db5413SSuraj Jitindar Singh } 1352b4db5413SSuraj Jitindar Singh cproc = PATBE1_GR | proc_tbl | table_size; 1353b4db5413SSuraj Jitindar Singh } else { /* Register new HPT process table */ 1354b4db5413SSuraj Jitindar Singh if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 1355b4db5413SSuraj Jitindar Singh /* TODO - Not Supported */ 1356b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 1357b4db5413SSuraj Jitindar Singh return H_PARAMETER; 1358b4db5413SSuraj Jitindar Singh } else { /* Hash with SLB */ 1359b4db5413SSuraj Jitindar Singh if (proc_tbl >> 38) { 1360b4db5413SSuraj Jitindar Singh return H_P2; 1361b4db5413SSuraj Jitindar Singh } else if (page_size & ~0x7) { 1362b4db5413SSuraj Jitindar Singh return H_P3; 1363b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 1364b4db5413SSuraj Jitindar Singh return H_P4; 1365b4db5413SSuraj Jitindar Singh } 1366b4db5413SSuraj Jitindar Singh } 1367b4db5413SSuraj Jitindar Singh cproc = (proc_tbl << 25) | page_size << 5 | table_size; 1368b4db5413SSuraj Jitindar Singh } 1369b4db5413SSuraj Jitindar Singh 1370b4db5413SSuraj Jitindar Singh } else { /* Deregister current process table */ 1371b4db5413SSuraj Jitindar Singh /* Set to benign value: (current GR) | 0. This allows 1372b4db5413SSuraj Jitindar Singh * deregistration in KVM to succeed even if the radix bit in flags 1373b4db5413SSuraj Jitindar Singh * doesn't match the radix bit in the old PATB. */ 1374b4db5413SSuraj Jitindar Singh cproc = spapr->patb_entry & PATBE1_GR; 1375b4db5413SSuraj Jitindar Singh } 1376b4db5413SSuraj Jitindar Singh } else { /* Maintain current registration */ 1377b4db5413SSuraj Jitindar Singh if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATBE1_GR)) { 1378b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 1379b4db5413SSuraj Jitindar Singh return H_PARAMETER; /* Existing Process Table Mismatch */ 1380b4db5413SSuraj Jitindar Singh } 1381b4db5413SSuraj Jitindar Singh cproc = spapr->patb_entry; 1382b4db5413SSuraj Jitindar Singh } 1383b4db5413SSuraj Jitindar Singh 1384b4db5413SSuraj Jitindar Singh /* Check if we need to setup OR free the hpt */ 1385b4db5413SSuraj Jitindar Singh spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 1386b4db5413SSuraj Jitindar Singh 1387b4db5413SSuraj Jitindar Singh spapr->patb_entry = cproc; /* Save new process table */ 13886de83307SSuraj Jitindar Singh 13896de83307SSuraj Jitindar Singh /* Update the UPRT and GTSE bits in the LPCR for all cpus */ 13906de83307SSuraj Jitindar Singh CPU_FOREACH(cs) { 139160694bc6SSuraj Jitindar Singh set_spr(cs, SPR_LPCR, 13926de83307SSuraj Jitindar Singh ((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT : 0) | 139360694bc6SSuraj Jitindar Singh ((flags & FLAG_GTSE) ? LPCR_GTSE : 0), 139460694bc6SSuraj Jitindar Singh LPCR_UPRT | LPCR_GTSE); 1395b4db5413SSuraj Jitindar Singh } 1396b4db5413SSuraj Jitindar Singh 1397b4db5413SSuraj Jitindar Singh if (kvm_enabled()) { 1398b4db5413SSuraj Jitindar Singh return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1399b4db5413SSuraj Jitindar Singh flags & FLAG_GTSE, cproc); 1400b4db5413SSuraj Jitindar Singh } 1401b4db5413SSuraj Jitindar Singh return H_SUCCESS; 1402d77a98b0SSuraj Jitindar Singh } 1403d77a98b0SSuraj Jitindar Singh 14041c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALL -1 14051c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 14061c7ad77eSNicholas Piggin 14071c7ad77eSNicholas Piggin static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 14081c7ad77eSNicholas Piggin sPAPRMachineState *spapr, 14091c7ad77eSNicholas Piggin target_ulong opcode, target_ulong *args) 14101c7ad77eSNicholas Piggin { 14111c7ad77eSNicholas Piggin target_long target = args[0]; 14121c7ad77eSNicholas Piggin CPUState *cs; 14131c7ad77eSNicholas Piggin 14141c7ad77eSNicholas Piggin if (target < 0) { 14151c7ad77eSNicholas Piggin /* Broadcast */ 14161c7ad77eSNicholas Piggin if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 14171c7ad77eSNicholas Piggin return H_PARAMETER; 14181c7ad77eSNicholas Piggin } 14191c7ad77eSNicholas Piggin 14201c7ad77eSNicholas Piggin CPU_FOREACH(cs) { 14211c7ad77eSNicholas Piggin PowerPCCPU *c = POWERPC_CPU(cs); 14221c7ad77eSNicholas Piggin 14231c7ad77eSNicholas Piggin if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 14241c7ad77eSNicholas Piggin if (c == cpu) { 14251c7ad77eSNicholas Piggin continue; 14261c7ad77eSNicholas Piggin } 14271c7ad77eSNicholas Piggin } 14281c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 14291c7ad77eSNicholas Piggin } 14301c7ad77eSNicholas Piggin return H_SUCCESS; 14311c7ad77eSNicholas Piggin 14321c7ad77eSNicholas Piggin } else { 14331c7ad77eSNicholas Piggin /* Unicast */ 14342e886fb3SSam Bobroff cs = CPU(spapr_find_cpu(target)); 1435f57467e3SSam Bobroff if (cs) { 14361c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 14371c7ad77eSNicholas Piggin return H_SUCCESS; 14381c7ad77eSNicholas Piggin } 14391c7ad77eSNicholas Piggin return H_PARAMETER; 14401c7ad77eSNicholas Piggin } 14411c7ad77eSNicholas Piggin } 14421c7ad77eSNicholas Piggin 14437843c0d6SDavid Gibson static uint32_t cas_check_pvr(sPAPRMachineState *spapr, PowerPCCPU *cpu, 1444cc7b35b1SGreg Kurz target_ulong *addr, bool *raw_mode_supported, 1445cc7b35b1SGreg Kurz Error **errp) 14462a6593cbSAlexey Kardashevskiy { 1447152ef803SDavid Gibson bool explicit_match = false; /* Matched the CPU's real PVR */ 14487843c0d6SDavid Gibson uint32_t max_compat = spapr->max_compat_pvr; 1449152ef803SDavid Gibson uint32_t best_compat = 0; 1450152ef803SDavid Gibson int i; 14513794d548SAlexey Kardashevskiy 1452152ef803SDavid Gibson /* 1453152ef803SDavid Gibson * We scan the supplied table of PVRs looking for two things 1454152ef803SDavid Gibson * 1. Is our real CPU PVR in the list? 1455152ef803SDavid Gibson * 2. What's the "best" listed logical PVR 1456152ef803SDavid Gibson */ 1457152ef803SDavid Gibson for (i = 0; i < 512; ++i) { 14583794d548SAlexey Kardashevskiy uint32_t pvr, pvr_mask; 14593794d548SAlexey Kardashevskiy 146080c33d34SDavid Gibson pvr_mask = ldl_be_phys(&address_space_memory, *addr); 146180c33d34SDavid Gibson pvr = ldl_be_phys(&address_space_memory, *addr + 4); 146280c33d34SDavid Gibson *addr += 8; 14633794d548SAlexey Kardashevskiy 14643794d548SAlexey Kardashevskiy if (~pvr_mask & pvr) { 1465152ef803SDavid Gibson break; /* Terminator record */ 14663794d548SAlexey Kardashevskiy } 1467152ef803SDavid Gibson 1468152ef803SDavid Gibson if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1469152ef803SDavid Gibson explicit_match = true; 1470152ef803SDavid Gibson } else { 1471152ef803SDavid Gibson if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1472152ef803SDavid Gibson best_compat = pvr; 1473152ef803SDavid Gibson } 1474152ef803SDavid Gibson } 1475152ef803SDavid Gibson } 1476152ef803SDavid Gibson 1477152ef803SDavid Gibson if ((best_compat == 0) && (!explicit_match || max_compat)) { 1478152ef803SDavid Gibson /* We couldn't find a suitable compatibility mode, and either 1479152ef803SDavid Gibson * the guest doesn't support "raw" mode for this CPU, or raw 1480152ef803SDavid Gibson * mode is disabled because a maximum compat mode is set */ 148180c33d34SDavid Gibson error_setg(errp, "Couldn't negotiate a suitable PVR during CAS"); 148280c33d34SDavid Gibson return 0; 14833794d548SAlexey Kardashevskiy } 14843794d548SAlexey Kardashevskiy 1485cc7b35b1SGreg Kurz *raw_mode_supported = explicit_match; 1486cc7b35b1SGreg Kurz 14873794d548SAlexey Kardashevskiy /* Parsing finished */ 1488152ef803SDavid Gibson trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 14893794d548SAlexey Kardashevskiy 149080c33d34SDavid Gibson return best_compat; 149180c33d34SDavid Gibson } 149280c33d34SDavid Gibson 149380c33d34SDavid Gibson static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 149480c33d34SDavid Gibson sPAPRMachineState *spapr, 149580c33d34SDavid Gibson target_ulong opcode, 149680c33d34SDavid Gibson target_ulong *args) 149780c33d34SDavid Gibson { 149880c33d34SDavid Gibson /* Working address in data buffer */ 149980c33d34SDavid Gibson target_ulong addr = ppc64_phys_to_real(args[0]); 150080c33d34SDavid Gibson target_ulong ov_table; 150180c33d34SDavid Gibson uint32_t cas_pvr; 150280c33d34SDavid Gibson sPAPROptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates; 150380c33d34SDavid Gibson bool guest_radix; 1504f6f242c7SDavid Gibson Error *local_err = NULL; 1505cc7b35b1SGreg Kurz bool raw_mode_supported = false; 15063794d548SAlexey Kardashevskiy 1507cc7b35b1SGreg Kurz cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err); 150880c33d34SDavid Gibson if (local_err) { 150980c33d34SDavid Gibson error_report_err(local_err); 151080c33d34SDavid Gibson return H_HARDWARE; 151180c33d34SDavid Gibson } 151280c33d34SDavid Gibson 151380c33d34SDavid Gibson /* Update CPUs */ 151480c33d34SDavid Gibson if (cpu->compat_pvr != cas_pvr) { 151580c33d34SDavid Gibson ppc_set_compat_all(cas_pvr, &local_err); 1516f6f242c7SDavid Gibson if (local_err) { 1517cc7b35b1SGreg Kurz /* We fail to set compat mode (likely because running with KVM PR), 1518cc7b35b1SGreg Kurz * but maybe we can fallback to raw mode if the guest supports it. 1519cc7b35b1SGreg Kurz */ 1520cc7b35b1SGreg Kurz if (!raw_mode_supported) { 1521f6f242c7SDavid Gibson error_report_err(local_err); 15223794d548SAlexey Kardashevskiy return H_HARDWARE; 15233794d548SAlexey Kardashevskiy } 1524cc7b35b1SGreg Kurz local_err = NULL; 1525cc7b35b1SGreg Kurz } 15263794d548SAlexey Kardashevskiy } 15273794d548SAlexey Kardashevskiy 152803d196b7SBharata B Rao /* For the future use: here @ov_table points to the first option vector */ 152980c33d34SDavid Gibson ov_table = addr; 153003d196b7SBharata B Rao 1531e957f6a9SSam Bobroff ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1532facdb8b6SMichael Roth ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 15339fb4541fSSam Bobroff if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 15349fb4541fSSam Bobroff error_report("guest requested hash and radix MMU, which is invalid."); 15359fb4541fSSam Bobroff exit(EXIT_FAILURE); 15369fb4541fSSam Bobroff } 15379fb4541fSSam Bobroff /* The radix/hash bit in byte 24 requires special handling: */ 15389fb4541fSSam Bobroff guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 15399fb4541fSSam Bobroff spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300); 15402a6593cbSAlexey Kardashevskiy 15412772cf6bSDavid Gibson /* 15422772cf6bSDavid Gibson * HPT resizing is a bit of a special case, because when enabled 15432772cf6bSDavid Gibson * we assume an HPT guest will support it until it says it 15442772cf6bSDavid Gibson * doesn't, instead of assuming it won't support it until it says 15452772cf6bSDavid Gibson * it does. Strictly speaking that approach could break for 15462772cf6bSDavid Gibson * guests which don't make a CAS call, but those are so old we 15472772cf6bSDavid Gibson * don't care about them. Without that assumption we'd have to 15482772cf6bSDavid Gibson * make at least a temporary allocation of an HPT sized for max 15492772cf6bSDavid Gibson * memory, which could be impossibly difficult under KVM HV if 15502772cf6bSDavid Gibson * maxram is large. 15512772cf6bSDavid Gibson */ 15522772cf6bSDavid Gibson if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 15532772cf6bSDavid Gibson int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 15542772cf6bSDavid Gibson 15552772cf6bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 15562772cf6bSDavid Gibson error_report( 15572772cf6bSDavid Gibson "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 15582772cf6bSDavid Gibson exit(1); 15592772cf6bSDavid Gibson } 15602772cf6bSDavid Gibson 15612772cf6bSDavid Gibson if (spapr->htab_shift < maxshift) { 15622772cf6bSDavid Gibson /* Guest doesn't know about HPT resizing, so we 15632772cf6bSDavid Gibson * pre-emptively resize for the maximum permitted RAM. At 15642772cf6bSDavid Gibson * the point this is called, nothing should have been 15652772cf6bSDavid Gibson * entered into the existing HPT */ 15662772cf6bSDavid Gibson spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 1567b55d295eSDavid Gibson if (kvm_enabled()) { 1568b55d295eSDavid Gibson /* For KVM PR, update the HPT pointer */ 1569b55d295eSDavid Gibson target_ulong sdr1 = (target_ulong)(uintptr_t)spapr->htab 1570b55d295eSDavid Gibson | (spapr->htab_shift - 18); 1571b55d295eSDavid Gibson kvmppc_update_sdr1(sdr1); 1572b55d295eSDavid Gibson } 1573b55d295eSDavid Gibson } 15742772cf6bSDavid Gibson } 15752772cf6bSDavid Gibson 1576facdb8b6SMichael Roth /* NOTE: there are actually a number of ov5 bits where input from the 1577facdb8b6SMichael Roth * guest is always zero, and the platform/QEMU enables them independently 1578facdb8b6SMichael Roth * of guest input. To model these properly we'd want some sort of mask, 1579facdb8b6SMichael Roth * but since they only currently apply to memory migration as defined 1580facdb8b6SMichael Roth * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 15816787d27bSMichael Roth * to worry about this for now. 1582facdb8b6SMichael Roth */ 15836787d27bSMichael Roth ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); 1584*30bf9ed1SCédric Le Goater 1585*30bf9ed1SCédric Le Goater /* also clear the radix/hash bit from the current ov5_cas bits to 1586*30bf9ed1SCédric Le Goater * be in sync with the newly ov5 bits. Else the radix bit will be 1587*30bf9ed1SCédric Le Goater * seen as being removed and this will generate a reset loop 1588*30bf9ed1SCédric Le Goater */ 1589*30bf9ed1SCédric Le Goater spapr_ovec_clear(ov5_cas_old, OV5_MMU_RADIX_300); 1590*30bf9ed1SCédric Le Goater 15916787d27bSMichael Roth /* full range of negotiated ov5 capabilities */ 1592facdb8b6SMichael Roth spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1593facdb8b6SMichael Roth spapr_ovec_cleanup(ov5_guest); 15946787d27bSMichael Roth /* capabilities that have been added since CAS-generated guest reset. 15956787d27bSMichael Roth * if capabilities have since been removed, generate another reset 15966787d27bSMichael Roth */ 15976787d27bSMichael Roth ov5_updates = spapr_ovec_new(); 15986787d27bSMichael Roth spapr->cas_reboot = spapr_ovec_diff(ov5_updates, 15996787d27bSMichael Roth ov5_cas_old, spapr->ov5_cas); 16009fb4541fSSam Bobroff /* Now that processing is finished, set the radix/hash bit for the 16019fb4541fSSam Bobroff * guest if it requested a valid mode; otherwise terminate the boot. */ 16029fb4541fSSam Bobroff if (guest_radix) { 16039fb4541fSSam Bobroff if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 16049fb4541fSSam Bobroff error_report("Guest requested unavailable MMU mode (radix)."); 16059fb4541fSSam Bobroff exit(EXIT_FAILURE); 16069fb4541fSSam Bobroff } 16079fb4541fSSam Bobroff spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300); 16089fb4541fSSam Bobroff } else { 16099fb4541fSSam Bobroff if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 16109fb4541fSSam Bobroff && !kvmppc_has_cap_mmu_hash_v3()) { 16119fb4541fSSam Bobroff error_report("Guest requested unavailable MMU mode (hash)."); 16129fb4541fSSam Bobroff exit(EXIT_FAILURE); 16139fb4541fSSam Bobroff } 16149fb4541fSSam Bobroff } 1615e957f6a9SSam Bobroff spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest, 1616e957f6a9SSam Bobroff OV1_PPC_3_00); 16176787d27bSMichael Roth if (!spapr->cas_reboot) { 16186787d27bSMichael Roth spapr->cas_reboot = 16195b120785SDavid Gibson (spapr_h_cas_compose_response(spapr, args[1], args[2], 16206787d27bSMichael Roth ov5_updates) != 0); 16216787d27bSMichael Roth } 16226787d27bSMichael Roth spapr_ovec_cleanup(ov5_updates); 16236787d27bSMichael Roth 16246787d27bSMichael Roth if (spapr->cas_reboot) { 1625cf83f140SEric Blake qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 16269fb4541fSSam Bobroff } else { 16279fb4541fSSam Bobroff /* If ppc_spapr_reset() did not set up a HPT but one is necessary 16289fb4541fSSam Bobroff * (because the guest isn't going to use radix) then set it up here. */ 16299fb4541fSSam Bobroff if ((spapr->patb_entry & PATBE1_GR) && !guest_radix) { 16309fb4541fSSam Bobroff /* legacy hash or new hash: */ 16319fb4541fSSam Bobroff spapr_setup_hpt_and_vrma(spapr); 16329fb4541fSSam Bobroff } 16332a6593cbSAlexey Kardashevskiy } 16342a6593cbSAlexey Kardashevskiy 16352a6593cbSAlexey Kardashevskiy return H_SUCCESS; 16362a6593cbSAlexey Kardashevskiy } 16372a6593cbSAlexey Kardashevskiy 16389f64bd8aSPaolo Bonzini static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 16399f64bd8aSPaolo Bonzini static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 16409f64bd8aSPaolo Bonzini 16419f64bd8aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 16429f64bd8aSPaolo Bonzini { 16439f64bd8aSPaolo Bonzini spapr_hcall_fn *slot; 16449f64bd8aSPaolo Bonzini 16459f64bd8aSPaolo Bonzini if (opcode <= MAX_HCALL_OPCODE) { 16469f64bd8aSPaolo Bonzini assert((opcode & 0x3) == 0); 16479f64bd8aSPaolo Bonzini 16489f64bd8aSPaolo Bonzini slot = &papr_hypercall_table[opcode / 4]; 16499f64bd8aSPaolo Bonzini } else { 16509f64bd8aSPaolo Bonzini assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 16519f64bd8aSPaolo Bonzini 16529f64bd8aSPaolo Bonzini slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 16539f64bd8aSPaolo Bonzini } 16549f64bd8aSPaolo Bonzini 16559f64bd8aSPaolo Bonzini assert(!(*slot)); 16569f64bd8aSPaolo Bonzini *slot = fn; 16579f64bd8aSPaolo Bonzini } 16589f64bd8aSPaolo Bonzini 16599f64bd8aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 16609f64bd8aSPaolo Bonzini target_ulong *args) 16619f64bd8aSPaolo Bonzini { 166228e02042SDavid Gibson sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 166328e02042SDavid Gibson 16649f64bd8aSPaolo Bonzini if ((opcode <= MAX_HCALL_OPCODE) 16659f64bd8aSPaolo Bonzini && ((opcode & 0x3) == 0)) { 16669f64bd8aSPaolo Bonzini spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 16679f64bd8aSPaolo Bonzini 16689f64bd8aSPaolo Bonzini if (fn) { 16699f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 16709f64bd8aSPaolo Bonzini } 16719f64bd8aSPaolo Bonzini } else if ((opcode >= KVMPPC_HCALL_BASE) && 16729f64bd8aSPaolo Bonzini (opcode <= KVMPPC_HCALL_MAX)) { 16739f64bd8aSPaolo Bonzini spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 16749f64bd8aSPaolo Bonzini 16759f64bd8aSPaolo Bonzini if (fn) { 16769f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 16779f64bd8aSPaolo Bonzini } 16789f64bd8aSPaolo Bonzini } 16799f64bd8aSPaolo Bonzini 1680aaf87c66SThomas Huth qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1681aaf87c66SThomas Huth opcode); 16829f64bd8aSPaolo Bonzini return H_FUNCTION; 16839f64bd8aSPaolo Bonzini } 16849f64bd8aSPaolo Bonzini 16859f64bd8aSPaolo Bonzini static void hypercall_register_types(void) 16869f64bd8aSPaolo Bonzini { 16879f64bd8aSPaolo Bonzini /* hcall-pft */ 16889f64bd8aSPaolo Bonzini spapr_register_hypercall(H_ENTER, h_enter); 16899f64bd8aSPaolo Bonzini spapr_register_hypercall(H_REMOVE, h_remove); 16909f64bd8aSPaolo Bonzini spapr_register_hypercall(H_PROTECT, h_protect); 1691fa388916SAnthony Liguori spapr_register_hypercall(H_READ, h_read); 16929f64bd8aSPaolo Bonzini 16939f64bd8aSPaolo Bonzini /* hcall-bulk */ 16949f64bd8aSPaolo Bonzini spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 16959f64bd8aSPaolo Bonzini 169630f4b05bSDavid Gibson /* hcall-hpt-resize */ 169730f4b05bSDavid Gibson spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 169830f4b05bSDavid Gibson spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 169930f4b05bSDavid Gibson 17009f64bd8aSPaolo Bonzini /* hcall-splpar */ 17019f64bd8aSPaolo Bonzini spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 17029f64bd8aSPaolo Bonzini spapr_register_hypercall(H_CEDE, h_cede); 17031c7ad77eSNicholas Piggin spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 17049f64bd8aSPaolo Bonzini 1705423576f7SThomas Huth /* processor register resource access h-calls */ 1706423576f7SThomas Huth spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1707af08a58fSThomas Huth spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1708e49ff266SThomas Huth spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 17093240dd9aSThomas Huth spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1710423576f7SThomas Huth spapr_register_hypercall(H_SET_MODE, h_set_mode); 1711423576f7SThomas Huth 1712d77a98b0SSuraj Jitindar Singh /* In Memory Table MMU h-calls */ 1713d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1714d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1715d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1716d77a98b0SSuraj Jitindar Singh 17179f64bd8aSPaolo Bonzini /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 17189f64bd8aSPaolo Bonzini * here between the "CI" and the "CACHE" variants, they will use whatever 17199f64bd8aSPaolo Bonzini * mapping attributes qemu is using. When using KVM, the kernel will 17209f64bd8aSPaolo Bonzini * enforce the attributes more strongly 17219f64bd8aSPaolo Bonzini */ 17229f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 17239f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 17249f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 17259f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 17269f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 17279f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 17289f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 17299f64bd8aSPaolo Bonzini 17309f64bd8aSPaolo Bonzini /* qemu/KVM-PPC specific hcalls */ 17319f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 173242561bf2SAnton Blanchard 17332a6593cbSAlexey Kardashevskiy /* ibm,client-architecture-support support */ 17342a6593cbSAlexey Kardashevskiy spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 17359f64bd8aSPaolo Bonzini } 17369f64bd8aSPaolo Bonzini 17379f64bd8aSPaolo Bonzini type_init(hypercall_register_types) 1738