10d75590dSPeter Maydell #include "qemu/osdep.h" 20c21e073SDavid Gibson #include "qemu/cutils.h" 3da34e65cSMarkus Armbruster #include "qapi/error.h" 4b3946626SVincent Palatin #include "sysemu/hw_accel.h" 554d31236SMarkus Armbruster #include "sysemu/runstate.h" 603dd024fSPaolo Bonzini #include "qemu/log.h" 7db725815SMarkus Armbruster #include "qemu/main-loop.h" 80b8fa32fSMarkus Armbruster #include "qemu/module.h" 90b0b8310SDavid Gibson #include "qemu/error-report.h" 1063c91552SPaolo Bonzini #include "exec/exec-all.h" 119f64bd8aSPaolo Bonzini #include "helper_regs.h" 12*120f738aSNicholas Piggin #include "hw/ppc/ppc.h" 130d09e41aSPaolo Bonzini #include "hw/ppc/spapr.h" 147388efafSDavid Gibson #include "hw/ppc/spapr_cpu_core.h" 15d5aea6f3SDavid Gibson #include "mmu-hash64.h" 163794d548SAlexey Kardashevskiy #include "cpu-models.h" 173794d548SAlexey Kardashevskiy #include "trace.h" 183794d548SAlexey Kardashevskiy #include "kvm_ppc.h" 190c21e073SDavid Gibson #include "hw/ppc/fdt.h" 20facdb8b6SMichael Roth #include "hw/ppc/spapr_ovec.h" 21a165ac67SDaniel Henrique Barboza #include "hw/ppc/spapr_numa.h" 22b4db5413SSuraj Jitindar Singh #include "mmu-book3s-v3.h" 232cc0e2e8SDavid Hildenbrand #include "hw/mem/memory-device.h" 249f64bd8aSPaolo Bonzini 25962104f0SLucas Mateus Castro (alqotel) bool is_ram_address(SpaprMachineState *spapr, hwaddr addr) 26ecbc25faSDavid Gibson { 27ecbc25faSDavid Gibson MachineState *machine = MACHINE(spapr); 28e017da37SDavid Hildenbrand DeviceMemoryState *dms = machine->device_memory; 29ecbc25faSDavid Gibson 30ecbc25faSDavid Gibson if (addr < machine->ram_size) { 31ecbc25faSDavid Gibson return true; 32ecbc25faSDavid Gibson } 33e017da37SDavid Hildenbrand if ((addr >= dms->base) 34e017da37SDavid Hildenbrand && ((addr - dms->base) < memory_region_size(&dms->mr))) { 35ecbc25faSDavid Gibson return true; 36ecbc25faSDavid Gibson } 37ecbc25faSDavid Gibson 38ecbc25faSDavid Gibson return false; 39ecbc25faSDavid Gibson } 40ecbc25faSDavid Gibson 41b55d295eSDavid Gibson /* Convert a return code from the KVM ioctl()s implementing resize HPT 42b55d295eSDavid Gibson * into a PAPR hypercall return code */ 43b55d295eSDavid Gibson static target_ulong resize_hpt_convert_rc(int ret) 44b55d295eSDavid Gibson { 45b55d295eSDavid Gibson if (ret >= 100000) { 46b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_100_SEC; 47b55d295eSDavid Gibson } else if (ret >= 10000) { 48b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_10_SEC; 49b55d295eSDavid Gibson } else if (ret >= 1000) { 50b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_1_SEC; 51b55d295eSDavid Gibson } else if (ret >= 100) { 52b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_100_MSEC; 53b55d295eSDavid Gibson } else if (ret >= 10) { 54b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_10_MSEC; 55b55d295eSDavid Gibson } else if (ret > 0) { 56b55d295eSDavid Gibson return H_LONG_BUSY_ORDER_1_MSEC; 57b55d295eSDavid Gibson } 58b55d295eSDavid Gibson 59b55d295eSDavid Gibson switch (ret) { 60b55d295eSDavid Gibson case 0: 61b55d295eSDavid Gibson return H_SUCCESS; 62b55d295eSDavid Gibson case -EPERM: 63b55d295eSDavid Gibson return H_AUTHORITY; 64b55d295eSDavid Gibson case -EINVAL: 65b55d295eSDavid Gibson return H_PARAMETER; 66b55d295eSDavid Gibson case -ENXIO: 67b55d295eSDavid Gibson return H_CLOSED; 68b55d295eSDavid Gibson case -ENOSPC: 69b55d295eSDavid Gibson return H_PTEG_FULL; 70b55d295eSDavid Gibson case -EBUSY: 71b55d295eSDavid Gibson return H_BUSY; 72b55d295eSDavid Gibson case -ENOMEM: 73b55d295eSDavid Gibson return H_NO_MEM; 74b55d295eSDavid Gibson default: 75b55d295eSDavid Gibson return H_HARDWARE; 76b55d295eSDavid Gibson } 77b55d295eSDavid Gibson } 78b55d295eSDavid Gibson 7930f4b05bSDavid Gibson static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 80ce2918cbSDavid Gibson SpaprMachineState *spapr, 8130f4b05bSDavid Gibson target_ulong opcode, 8230f4b05bSDavid Gibson target_ulong *args) 8330f4b05bSDavid Gibson { 8430f4b05bSDavid Gibson target_ulong flags = args[0]; 850b0b8310SDavid Gibson int shift = args[1]; 86db50f280SDavid Gibson uint64_t current_ram_size; 87b55d295eSDavid Gibson int rc; 8830f4b05bSDavid Gibson 8930f4b05bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 9030f4b05bSDavid Gibson return H_AUTHORITY; 9130f4b05bSDavid Gibson } 9230f4b05bSDavid Gibson 930b0b8310SDavid Gibson if (!spapr->htab_shift) { 940b0b8310SDavid Gibson /* Radix guest, no HPT */ 950b0b8310SDavid Gibson return H_NOT_AVAILABLE; 960b0b8310SDavid Gibson } 970b0b8310SDavid Gibson 9830f4b05bSDavid Gibson trace_spapr_h_resize_hpt_prepare(flags, shift); 990b0b8310SDavid Gibson 1000b0b8310SDavid Gibson if (flags != 0) { 1010b0b8310SDavid Gibson return H_PARAMETER; 1020b0b8310SDavid Gibson } 1030b0b8310SDavid Gibson 1040b0b8310SDavid Gibson if (shift && ((shift < 18) || (shift > 46))) { 1050b0b8310SDavid Gibson return H_PARAMETER; 1060b0b8310SDavid Gibson } 1070b0b8310SDavid Gibson 108db50f280SDavid Gibson current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1090b0b8310SDavid Gibson 1100b0b8310SDavid Gibson /* We only allow the guest to allocate an HPT one order above what 1110b0b8310SDavid Gibson * we'd normally give them (to stop a small guest claiming a huge 1120b0b8310SDavid Gibson * chunk of resources in the HPT */ 1130b0b8310SDavid Gibson if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 1140b0b8310SDavid Gibson return H_RESOURCE; 1150b0b8310SDavid Gibson } 1160b0b8310SDavid Gibson 117b55d295eSDavid Gibson rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 118b55d295eSDavid Gibson if (rc != -ENOSYS) { 119b55d295eSDavid Gibson return resize_hpt_convert_rc(rc); 120b55d295eSDavid Gibson } 121b55d295eSDavid Gibson 122962104f0SLucas Mateus Castro (alqotel) if (kvm_enabled()) { 12330f4b05bSDavid Gibson return H_HARDWARE; 12430f4b05bSDavid Gibson } 12530f4b05bSDavid Gibson 126962104f0SLucas Mateus Castro (alqotel) return softmmu_resize_hpt_prepare(cpu, spapr, shift); 1270b0b8310SDavid Gibson } 1280b0b8310SDavid Gibson 1291ec26c75SGreg Kurz static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 1301ec26c75SGreg Kurz { 1311ec26c75SGreg Kurz int ret; 1321ec26c75SGreg Kurz 1331ec26c75SGreg Kurz cpu_synchronize_state(cs); 1341ec26c75SGreg Kurz 1351ec26c75SGreg Kurz ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 1361ec26c75SGreg Kurz if (ret < 0) { 1371ec26c75SGreg Kurz error_report("failed to push sregs to KVM: %s", strerror(-ret)); 1381ec26c75SGreg Kurz exit(1); 1391ec26c75SGreg Kurz } 1401ec26c75SGreg Kurz } 1411ec26c75SGreg Kurz 142962104f0SLucas Mateus Castro (alqotel) void push_sregs_to_kvm_pr(SpaprMachineState *spapr) 1431ec26c75SGreg Kurz { 1441ec26c75SGreg Kurz CPUState *cs; 1451ec26c75SGreg Kurz 1461ec26c75SGreg Kurz /* 1471ec26c75SGreg Kurz * This is a hack for the benefit of KVM PR - it abuses the SDR1 1481ec26c75SGreg Kurz * slot in kvm_sregs to communicate the userspace address of the 1491ec26c75SGreg Kurz * HPT 1501ec26c75SGreg Kurz */ 1511ec26c75SGreg Kurz if (!kvm_enabled() || !spapr->htab) { 1521ec26c75SGreg Kurz return; 1531ec26c75SGreg Kurz } 1541ec26c75SGreg Kurz 1551ec26c75SGreg Kurz CPU_FOREACH(cs) { 1561ec26c75SGreg Kurz run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 1571ec26c75SGreg Kurz } 1581ec26c75SGreg Kurz } 1591ec26c75SGreg Kurz 16030f4b05bSDavid Gibson static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 161ce2918cbSDavid Gibson SpaprMachineState *spapr, 16230f4b05bSDavid Gibson target_ulong opcode, 16330f4b05bSDavid Gibson target_ulong *args) 16430f4b05bSDavid Gibson { 16530f4b05bSDavid Gibson target_ulong flags = args[0]; 16630f4b05bSDavid Gibson target_ulong shift = args[1]; 1670b0b8310SDavid Gibson int rc; 16830f4b05bSDavid Gibson 16930f4b05bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 17030f4b05bSDavid Gibson return H_AUTHORITY; 17130f4b05bSDavid Gibson } 17230f4b05bSDavid Gibson 17394789567SDaniel Henrique Barboza if (!spapr->htab_shift) { 17494789567SDaniel Henrique Barboza /* Radix guest, no HPT */ 17594789567SDaniel Henrique Barboza return H_NOT_AVAILABLE; 17694789567SDaniel Henrique Barboza } 17794789567SDaniel Henrique Barboza 17830f4b05bSDavid Gibson trace_spapr_h_resize_hpt_commit(flags, shift); 1790b0b8310SDavid Gibson 180b55d295eSDavid Gibson rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 181b55d295eSDavid Gibson if (rc != -ENOSYS) { 18294789567SDaniel Henrique Barboza rc = resize_hpt_convert_rc(rc); 18394789567SDaniel Henrique Barboza if (rc == H_SUCCESS) { 18494789567SDaniel Henrique Barboza /* Need to set the new htab_shift in the machine state */ 18594789567SDaniel Henrique Barboza spapr->htab_shift = shift; 18694789567SDaniel Henrique Barboza } 18794789567SDaniel Henrique Barboza return rc; 188b55d295eSDavid Gibson } 189b55d295eSDavid Gibson 190962104f0SLucas Mateus Castro (alqotel) if (kvm_enabled()) { 191962104f0SLucas Mateus Castro (alqotel) return H_HARDWARE; 1920b0b8310SDavid Gibson } 1930b0b8310SDavid Gibson 194962104f0SLucas Mateus Castro (alqotel) return softmmu_resize_hpt_commit(cpu, spapr, flags, shift); 1950b0b8310SDavid Gibson } 1960b0b8310SDavid Gibson 1970b0b8310SDavid Gibson 19830f4b05bSDavid Gibson 199ce2918cbSDavid Gibson static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr, 200423576f7SThomas Huth target_ulong opcode, target_ulong *args) 201423576f7SThomas Huth { 202423576f7SThomas Huth cpu_synchronize_state(CPU(cpu)); 203423576f7SThomas Huth cpu->env.spr[SPR_SPRG0] = args[0]; 204423576f7SThomas Huth 205423576f7SThomas Huth return H_SUCCESS; 206423576f7SThomas Huth } 207423576f7SThomas Huth 208ce2918cbSDavid Gibson static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 2099f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 2109f64bd8aSPaolo Bonzini { 21103282a3aSLucas Mateus Castro (alqotel) if (!ppc_has_spr(cpu, SPR_DABR)) { 212af08a58fSThomas Huth return H_HARDWARE; /* DABR register not available */ 213af08a58fSThomas Huth } 214af08a58fSThomas Huth cpu_synchronize_state(CPU(cpu)); 215af08a58fSThomas Huth 21603282a3aSLucas Mateus Castro (alqotel) if (ppc_has_spr(cpu, SPR_DABRX)) { 217af08a58fSThomas Huth cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 218af08a58fSThomas Huth } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 219af08a58fSThomas Huth return H_RESERVED_DABR; 220af08a58fSThomas Huth } 221af08a58fSThomas Huth 222af08a58fSThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 223af08a58fSThomas Huth return H_SUCCESS; 2249f64bd8aSPaolo Bonzini } 2259f64bd8aSPaolo Bonzini 226ce2918cbSDavid Gibson static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr, 227e49ff266SThomas Huth target_ulong opcode, target_ulong *args) 228e49ff266SThomas Huth { 229e49ff266SThomas Huth target_ulong dabrx = args[1]; 230e49ff266SThomas Huth 23103282a3aSLucas Mateus Castro (alqotel) if (!ppc_has_spr(cpu, SPR_DABR) || !ppc_has_spr(cpu, SPR_DABRX)) { 232e49ff266SThomas Huth return H_HARDWARE; 233e49ff266SThomas Huth } 234e49ff266SThomas Huth 235e49ff266SThomas Huth if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 236e49ff266SThomas Huth || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 237e49ff266SThomas Huth return H_PARAMETER; 238e49ff266SThomas Huth } 239e49ff266SThomas Huth 240e49ff266SThomas Huth cpu_synchronize_state(CPU(cpu)); 241e49ff266SThomas Huth cpu->env.spr[SPR_DABRX] = dabrx; 242e49ff266SThomas Huth cpu->env.spr[SPR_DABR] = args[0]; 243e49ff266SThomas Huth 244e49ff266SThomas Huth return H_SUCCESS; 245e49ff266SThomas Huth } 246e49ff266SThomas Huth 247ce2918cbSDavid Gibson static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, 2483240dd9aSThomas Huth target_ulong opcode, target_ulong *args) 2493240dd9aSThomas Huth { 2503240dd9aSThomas Huth target_ulong flags = args[0]; 2513240dd9aSThomas Huth hwaddr dst = args[1]; 2523240dd9aSThomas Huth hwaddr src = args[2]; 2533240dd9aSThomas Huth hwaddr len = TARGET_PAGE_SIZE; 2543240dd9aSThomas Huth uint8_t *pdst, *psrc; 2553240dd9aSThomas Huth target_long ret = H_SUCCESS; 2563240dd9aSThomas Huth 2573240dd9aSThomas Huth if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 2583240dd9aSThomas Huth | H_COPY_PAGE | H_ZERO_PAGE)) { 2593240dd9aSThomas Huth qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 2603240dd9aSThomas Huth flags); 2613240dd9aSThomas Huth return H_PARAMETER; 2623240dd9aSThomas Huth } 2633240dd9aSThomas Huth 2643240dd9aSThomas Huth /* Map-in destination */ 2653240dd9aSThomas Huth if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 2663240dd9aSThomas Huth return H_PARAMETER; 2673240dd9aSThomas Huth } 26885eb7c18SPhilippe Mathieu-Daudé pdst = cpu_physical_memory_map(dst, &len, true); 2693240dd9aSThomas Huth if (!pdst || len != TARGET_PAGE_SIZE) { 2703240dd9aSThomas Huth return H_PARAMETER; 2713240dd9aSThomas Huth } 2723240dd9aSThomas Huth 2733240dd9aSThomas Huth if (flags & H_COPY_PAGE) { 2743240dd9aSThomas Huth /* Map-in source, copy to destination, and unmap source again */ 2753240dd9aSThomas Huth if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 2763240dd9aSThomas Huth ret = H_PARAMETER; 2773240dd9aSThomas Huth goto unmap_out; 2783240dd9aSThomas Huth } 27985eb7c18SPhilippe Mathieu-Daudé psrc = cpu_physical_memory_map(src, &len, false); 2803240dd9aSThomas Huth if (!psrc || len != TARGET_PAGE_SIZE) { 2813240dd9aSThomas Huth ret = H_PARAMETER; 2823240dd9aSThomas Huth goto unmap_out; 2833240dd9aSThomas Huth } 2843240dd9aSThomas Huth memcpy(pdst, psrc, len); 2853240dd9aSThomas Huth cpu_physical_memory_unmap(psrc, len, 0, len); 2863240dd9aSThomas Huth } else if (flags & H_ZERO_PAGE) { 2873240dd9aSThomas Huth memset(pdst, 0, len); /* Just clear the destination page */ 2883240dd9aSThomas Huth } 2893240dd9aSThomas Huth 2903240dd9aSThomas Huth if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 2913240dd9aSThomas Huth kvmppc_dcbst_range(cpu, pdst, len); 2923240dd9aSThomas Huth } 2933240dd9aSThomas Huth if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 2943240dd9aSThomas Huth if (kvm_enabled()) { 2953240dd9aSThomas Huth kvmppc_icbi_range(cpu, pdst, len); 2963240dd9aSThomas Huth } else { 2973240dd9aSThomas Huth tb_flush(CPU(cpu)); 2983240dd9aSThomas Huth } 2993240dd9aSThomas Huth } 3003240dd9aSThomas Huth 3013240dd9aSThomas Huth unmap_out: 3023240dd9aSThomas Huth cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 3033240dd9aSThomas Huth return ret; 3043240dd9aSThomas Huth } 3053240dd9aSThomas Huth 3069f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 3079f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 3089f64bd8aSPaolo Bonzini #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 3099f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 3109f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 3119f64bd8aSPaolo Bonzini #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 3129f64bd8aSPaolo Bonzini 3137388efafSDavid Gibson static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa) 3149f64bd8aSPaolo Bonzini { 3157388efafSDavid Gibson CPUState *cs = CPU(cpu); 3167388efafSDavid Gibson CPUPPCState *env = &cpu->env; 317ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 3189f64bd8aSPaolo Bonzini uint16_t size; 3199f64bd8aSPaolo Bonzini uint8_t tmp; 3209f64bd8aSPaolo Bonzini 3219f64bd8aSPaolo Bonzini if (vpa == 0) { 3229f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 3239f64bd8aSPaolo Bonzini return H_HARDWARE; 3249f64bd8aSPaolo Bonzini } 3259f64bd8aSPaolo Bonzini 3269f64bd8aSPaolo Bonzini if (vpa % env->dcache_line_size) { 3279f64bd8aSPaolo Bonzini return H_PARAMETER; 3289f64bd8aSPaolo Bonzini } 3299f64bd8aSPaolo Bonzini /* FIXME: bounds check the address */ 3309f64bd8aSPaolo Bonzini 33141701aa4SEdgar E. Iglesias size = lduw_be_phys(cs->as, vpa + 0x4); 3329f64bd8aSPaolo Bonzini 3339f64bd8aSPaolo Bonzini if (size < VPA_MIN_SIZE) { 3349f64bd8aSPaolo Bonzini return H_PARAMETER; 3359f64bd8aSPaolo Bonzini } 3369f64bd8aSPaolo Bonzini 3379f64bd8aSPaolo Bonzini /* VPA is not allowed to cross a page boundary */ 3389f64bd8aSPaolo Bonzini if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 3399f64bd8aSPaolo Bonzini return H_PARAMETER; 3409f64bd8aSPaolo Bonzini } 3419f64bd8aSPaolo Bonzini 3427388efafSDavid Gibson spapr_cpu->vpa_addr = vpa; 3439f64bd8aSPaolo Bonzini 3447388efafSDavid Gibson tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET); 3459f64bd8aSPaolo Bonzini tmp |= VPA_SHARED_PROC_VAL; 3467388efafSDavid Gibson stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 3479f64bd8aSPaolo Bonzini 3489f64bd8aSPaolo Bonzini return H_SUCCESS; 3499f64bd8aSPaolo Bonzini } 3509f64bd8aSPaolo Bonzini 3517388efafSDavid Gibson static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa) 3529f64bd8aSPaolo Bonzini { 353ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 3547388efafSDavid Gibson 3557388efafSDavid Gibson if (spapr_cpu->slb_shadow_addr) { 3569f64bd8aSPaolo Bonzini return H_RESOURCE; 3579f64bd8aSPaolo Bonzini } 3589f64bd8aSPaolo Bonzini 3597388efafSDavid Gibson if (spapr_cpu->dtl_addr) { 3609f64bd8aSPaolo Bonzini return H_RESOURCE; 3619f64bd8aSPaolo Bonzini } 3629f64bd8aSPaolo Bonzini 3637388efafSDavid Gibson spapr_cpu->vpa_addr = 0; 3649f64bd8aSPaolo Bonzini return H_SUCCESS; 3659f64bd8aSPaolo Bonzini } 3669f64bd8aSPaolo Bonzini 3677388efafSDavid Gibson static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 3689f64bd8aSPaolo Bonzini { 369ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 3709f64bd8aSPaolo Bonzini uint32_t size; 3719f64bd8aSPaolo Bonzini 3729f64bd8aSPaolo Bonzini if (addr == 0) { 3739f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 3749f64bd8aSPaolo Bonzini return H_HARDWARE; 3759f64bd8aSPaolo Bonzini } 3769f64bd8aSPaolo Bonzini 3777388efafSDavid Gibson size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 3789f64bd8aSPaolo Bonzini if (size < 0x8) { 3799f64bd8aSPaolo Bonzini return H_PARAMETER; 3809f64bd8aSPaolo Bonzini } 3819f64bd8aSPaolo Bonzini 3829f64bd8aSPaolo Bonzini if ((addr / 4096) != ((addr + size - 1) / 4096)) { 3839f64bd8aSPaolo Bonzini return H_PARAMETER; 3849f64bd8aSPaolo Bonzini } 3859f64bd8aSPaolo Bonzini 3867388efafSDavid Gibson if (!spapr_cpu->vpa_addr) { 3879f64bd8aSPaolo Bonzini return H_RESOURCE; 3889f64bd8aSPaolo Bonzini } 3899f64bd8aSPaolo Bonzini 3907388efafSDavid Gibson spapr_cpu->slb_shadow_addr = addr; 3917388efafSDavid Gibson spapr_cpu->slb_shadow_size = size; 3929f64bd8aSPaolo Bonzini 3939f64bd8aSPaolo Bonzini return H_SUCCESS; 3949f64bd8aSPaolo Bonzini } 3959f64bd8aSPaolo Bonzini 3967388efafSDavid Gibson static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr) 3979f64bd8aSPaolo Bonzini { 398ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 3997388efafSDavid Gibson 4007388efafSDavid Gibson spapr_cpu->slb_shadow_addr = 0; 4017388efafSDavid Gibson spapr_cpu->slb_shadow_size = 0; 4029f64bd8aSPaolo Bonzini return H_SUCCESS; 4039f64bd8aSPaolo Bonzini } 4049f64bd8aSPaolo Bonzini 4057388efafSDavid Gibson static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr) 4069f64bd8aSPaolo Bonzini { 407ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4089f64bd8aSPaolo Bonzini uint32_t size; 4099f64bd8aSPaolo Bonzini 4109f64bd8aSPaolo Bonzini if (addr == 0) { 4119f64bd8aSPaolo Bonzini hcall_dprintf("Can't cope with DTL at logical 0\n"); 4129f64bd8aSPaolo Bonzini return H_HARDWARE; 4139f64bd8aSPaolo Bonzini } 4149f64bd8aSPaolo Bonzini 4157388efafSDavid Gibson size = ldl_be_phys(CPU(cpu)->as, addr + 0x4); 4169f64bd8aSPaolo Bonzini 4179f64bd8aSPaolo Bonzini if (size < 48) { 4189f64bd8aSPaolo Bonzini return H_PARAMETER; 4199f64bd8aSPaolo Bonzini } 4209f64bd8aSPaolo Bonzini 4217388efafSDavid Gibson if (!spapr_cpu->vpa_addr) { 4229f64bd8aSPaolo Bonzini return H_RESOURCE; 4239f64bd8aSPaolo Bonzini } 4249f64bd8aSPaolo Bonzini 4257388efafSDavid Gibson spapr_cpu->dtl_addr = addr; 4267388efafSDavid Gibson spapr_cpu->dtl_size = size; 4279f64bd8aSPaolo Bonzini 4289f64bd8aSPaolo Bonzini return H_SUCCESS; 4299f64bd8aSPaolo Bonzini } 4309f64bd8aSPaolo Bonzini 4317388efafSDavid Gibson static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr) 4329f64bd8aSPaolo Bonzini { 433ce2918cbSDavid Gibson SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4347388efafSDavid Gibson 4357388efafSDavid Gibson spapr_cpu->dtl_addr = 0; 4367388efafSDavid Gibson spapr_cpu->dtl_size = 0; 4379f64bd8aSPaolo Bonzini 4389f64bd8aSPaolo Bonzini return H_SUCCESS; 4399f64bd8aSPaolo Bonzini } 4409f64bd8aSPaolo Bonzini 441ce2918cbSDavid Gibson static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr, 4429f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 4439f64bd8aSPaolo Bonzini { 4449f64bd8aSPaolo Bonzini target_ulong flags = args[0]; 4459f64bd8aSPaolo Bonzini target_ulong procno = args[1]; 4469f64bd8aSPaolo Bonzini target_ulong vpa = args[2]; 4479f64bd8aSPaolo Bonzini target_ulong ret = H_PARAMETER; 4480f20ba62SAlexey Kardashevskiy PowerPCCPU *tcpu; 4499f64bd8aSPaolo Bonzini 4502e886fb3SSam Bobroff tcpu = spapr_find_cpu(procno); 4519f64bd8aSPaolo Bonzini if (!tcpu) { 4529f64bd8aSPaolo Bonzini return H_PARAMETER; 4539f64bd8aSPaolo Bonzini } 4549f64bd8aSPaolo Bonzini 4559f64bd8aSPaolo Bonzini switch (flags) { 4569f64bd8aSPaolo Bonzini case FLAGS_REGISTER_VPA: 4577388efafSDavid Gibson ret = register_vpa(tcpu, vpa); 4589f64bd8aSPaolo Bonzini break; 4599f64bd8aSPaolo Bonzini 4609f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_VPA: 4617388efafSDavid Gibson ret = deregister_vpa(tcpu, vpa); 4629f64bd8aSPaolo Bonzini break; 4639f64bd8aSPaolo Bonzini 4649f64bd8aSPaolo Bonzini case FLAGS_REGISTER_SLBSHADOW: 4657388efafSDavid Gibson ret = register_slb_shadow(tcpu, vpa); 4669f64bd8aSPaolo Bonzini break; 4679f64bd8aSPaolo Bonzini 4689f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_SLBSHADOW: 4697388efafSDavid Gibson ret = deregister_slb_shadow(tcpu, vpa); 4709f64bd8aSPaolo Bonzini break; 4719f64bd8aSPaolo Bonzini 4729f64bd8aSPaolo Bonzini case FLAGS_REGISTER_DTL: 4737388efafSDavid Gibson ret = register_dtl(tcpu, vpa); 4749f64bd8aSPaolo Bonzini break; 4759f64bd8aSPaolo Bonzini 4769f64bd8aSPaolo Bonzini case FLAGS_DEREGISTER_DTL: 4777388efafSDavid Gibson ret = deregister_dtl(tcpu, vpa); 4789f64bd8aSPaolo Bonzini break; 4799f64bd8aSPaolo Bonzini } 4809f64bd8aSPaolo Bonzini 4819f64bd8aSPaolo Bonzini return ret; 4829f64bd8aSPaolo Bonzini } 4839f64bd8aSPaolo Bonzini 484ce2918cbSDavid Gibson static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, 4859f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 4869f64bd8aSPaolo Bonzini { 4879f64bd8aSPaolo Bonzini CPUPPCState *env = &cpu->env; 4889f64bd8aSPaolo Bonzini CPUState *cs = CPU(cpu); 4893a6e6224SNicholas Piggin SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4909f64bd8aSPaolo Bonzini 4919f64bd8aSPaolo Bonzini env->msr |= (1ULL << MSR_EE); 4929f64bd8aSPaolo Bonzini hreg_compute_hflags(env); 4933a6e6224SNicholas Piggin 4943a6e6224SNicholas Piggin if (spapr_cpu->prod) { 4953a6e6224SNicholas Piggin spapr_cpu->prod = false; 4963a6e6224SNicholas Piggin return H_SUCCESS; 4973a6e6224SNicholas Piggin } 4983a6e6224SNicholas Piggin 4999f64bd8aSPaolo Bonzini if (!cpu_has_work(cs)) { 500259186a7SAndreas Färber cs->halted = 1; 50127103424SAndreas Färber cs->exception_index = EXCP_HLT; 5029f64bd8aSPaolo Bonzini cs->exit_request = 1; 5039f64bd8aSPaolo Bonzini } 5043a6e6224SNicholas Piggin 5053a6e6224SNicholas Piggin return H_SUCCESS; 5063a6e6224SNicholas Piggin } 5073a6e6224SNicholas Piggin 50810741314SNicholas Piggin /* 50910741314SNicholas Piggin * Confer to self, aka join. Cede could use the same pattern as well, if 51010741314SNicholas Piggin * EXCP_HLT can be changed to ECXP_HALTED. 51110741314SNicholas Piggin */ 51210741314SNicholas Piggin static target_ulong h_confer_self(PowerPCCPU *cpu) 51310741314SNicholas Piggin { 51410741314SNicholas Piggin CPUState *cs = CPU(cpu); 51510741314SNicholas Piggin SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 51610741314SNicholas Piggin 51710741314SNicholas Piggin if (spapr_cpu->prod) { 51810741314SNicholas Piggin spapr_cpu->prod = false; 51910741314SNicholas Piggin return H_SUCCESS; 52010741314SNicholas Piggin } 52110741314SNicholas Piggin cs->halted = 1; 52210741314SNicholas Piggin cs->exception_index = EXCP_HALTED; 52310741314SNicholas Piggin cs->exit_request = 1; 52410741314SNicholas Piggin 52510741314SNicholas Piggin return H_SUCCESS; 52610741314SNicholas Piggin } 52710741314SNicholas Piggin 52810741314SNicholas Piggin static target_ulong h_join(PowerPCCPU *cpu, SpaprMachineState *spapr, 52910741314SNicholas Piggin target_ulong opcode, target_ulong *args) 53010741314SNicholas Piggin { 53110741314SNicholas Piggin CPUPPCState *env = &cpu->env; 53210741314SNicholas Piggin CPUState *cs; 53310741314SNicholas Piggin bool last_unjoined = true; 53410741314SNicholas Piggin 53510741314SNicholas Piggin if (env->msr & (1ULL << MSR_EE)) { 53610741314SNicholas Piggin return H_BAD_MODE; 53710741314SNicholas Piggin } 53810741314SNicholas Piggin 53910741314SNicholas Piggin /* 54010741314SNicholas Piggin * Must not join the last CPU running. Interestingly, no such restriction 54110741314SNicholas Piggin * for H_CONFER-to-self, but that is probably not intended to be used 54210741314SNicholas Piggin * when H_JOIN is available. 54310741314SNicholas Piggin */ 54410741314SNicholas Piggin CPU_FOREACH(cs) { 54510741314SNicholas Piggin PowerPCCPU *c = POWERPC_CPU(cs); 54610741314SNicholas Piggin CPUPPCState *e = &c->env; 54710741314SNicholas Piggin if (c == cpu) { 54810741314SNicholas Piggin continue; 54910741314SNicholas Piggin } 55010741314SNicholas Piggin 55110741314SNicholas Piggin /* Don't have a way to indicate joined, so use halted && MSR[EE]=0 */ 55210741314SNicholas Piggin if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { 55310741314SNicholas Piggin last_unjoined = false; 55410741314SNicholas Piggin break; 55510741314SNicholas Piggin } 55610741314SNicholas Piggin } 55710741314SNicholas Piggin if (last_unjoined) { 55810741314SNicholas Piggin return H_CONTINUE; 55910741314SNicholas Piggin } 56010741314SNicholas Piggin 56110741314SNicholas Piggin return h_confer_self(cpu); 56210741314SNicholas Piggin } 56310741314SNicholas Piggin 564e8ce0e40SNicholas Piggin static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr, 565e8ce0e40SNicholas Piggin target_ulong opcode, target_ulong *args) 566e8ce0e40SNicholas Piggin { 567e8ce0e40SNicholas Piggin target_long target = args[0]; 568e8ce0e40SNicholas Piggin uint32_t dispatch = args[1]; 569e8ce0e40SNicholas Piggin CPUState *cs = CPU(cpu); 570e8ce0e40SNicholas Piggin SpaprCpuState *spapr_cpu; 571e8ce0e40SNicholas Piggin 572e8ce0e40SNicholas Piggin /* 573e8ce0e40SNicholas Piggin * -1 means confer to all other CPUs without dispatch counter check, 574e8ce0e40SNicholas Piggin * otherwise it's a targeted confer. 575e8ce0e40SNicholas Piggin */ 576e8ce0e40SNicholas Piggin if (target != -1) { 577e8ce0e40SNicholas Piggin PowerPCCPU *target_cpu = spapr_find_cpu(target); 578e8ce0e40SNicholas Piggin uint32_t target_dispatch; 579e8ce0e40SNicholas Piggin 580e8ce0e40SNicholas Piggin if (!target_cpu) { 581e8ce0e40SNicholas Piggin return H_PARAMETER; 582e8ce0e40SNicholas Piggin } 583e8ce0e40SNicholas Piggin 584e8ce0e40SNicholas Piggin /* 585e8ce0e40SNicholas Piggin * target == self is a special case, we wait until prodded, without 586e8ce0e40SNicholas Piggin * dispatch counter check. 587e8ce0e40SNicholas Piggin */ 588e8ce0e40SNicholas Piggin if (cpu == target_cpu) { 58910741314SNicholas Piggin return h_confer_self(cpu); 590e8ce0e40SNicholas Piggin } 591e8ce0e40SNicholas Piggin 59210741314SNicholas Piggin spapr_cpu = spapr_cpu_state(target_cpu); 593e8ce0e40SNicholas Piggin if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) { 594e8ce0e40SNicholas Piggin return H_SUCCESS; 595e8ce0e40SNicholas Piggin } 596e8ce0e40SNicholas Piggin 597e8ce0e40SNicholas Piggin target_dispatch = ldl_be_phys(cs->as, 598e8ce0e40SNicholas Piggin spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 599e8ce0e40SNicholas Piggin if (target_dispatch != dispatch) { 600e8ce0e40SNicholas Piggin return H_SUCCESS; 601e8ce0e40SNicholas Piggin } 602e8ce0e40SNicholas Piggin 603e8ce0e40SNicholas Piggin /* 604e8ce0e40SNicholas Piggin * The targeted confer does not do anything special beyond yielding 605e8ce0e40SNicholas Piggin * the current vCPU, but even this should be better than nothing. 606e8ce0e40SNicholas Piggin * At least for single-threaded tcg, it gives the target a chance to 607e8ce0e40SNicholas Piggin * run before we run again. Multi-threaded tcg does not really do 608e8ce0e40SNicholas Piggin * anything with EXCP_YIELD yet. 609e8ce0e40SNicholas Piggin */ 610e8ce0e40SNicholas Piggin } 611e8ce0e40SNicholas Piggin 612e8ce0e40SNicholas Piggin cs->exception_index = EXCP_YIELD; 613e8ce0e40SNicholas Piggin cs->exit_request = 1; 614e8ce0e40SNicholas Piggin cpu_loop_exit(cs); 615e8ce0e40SNicholas Piggin 616e8ce0e40SNicholas Piggin return H_SUCCESS; 617e8ce0e40SNicholas Piggin } 618e8ce0e40SNicholas Piggin 6193a6e6224SNicholas Piggin static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr, 6203a6e6224SNicholas Piggin target_ulong opcode, target_ulong *args) 6213a6e6224SNicholas Piggin { 6223a6e6224SNicholas Piggin target_long target = args[0]; 6233a6e6224SNicholas Piggin PowerPCCPU *tcpu; 6243a6e6224SNicholas Piggin CPUState *cs; 6253a6e6224SNicholas Piggin SpaprCpuState *spapr_cpu; 6263a6e6224SNicholas Piggin 6273a6e6224SNicholas Piggin tcpu = spapr_find_cpu(target); 6283a6e6224SNicholas Piggin cs = CPU(tcpu); 6293a6e6224SNicholas Piggin if (!cs) { 6303a6e6224SNicholas Piggin return H_PARAMETER; 6313a6e6224SNicholas Piggin } 6323a6e6224SNicholas Piggin 6333a6e6224SNicholas Piggin spapr_cpu = spapr_cpu_state(tcpu); 6343a6e6224SNicholas Piggin spapr_cpu->prod = true; 6353a6e6224SNicholas Piggin cs->halted = 0; 6363a6e6224SNicholas Piggin qemu_cpu_kick(cs); 6373a6e6224SNicholas Piggin 6389f64bd8aSPaolo Bonzini return H_SUCCESS; 6399f64bd8aSPaolo Bonzini } 6409f64bd8aSPaolo Bonzini 641ce2918cbSDavid Gibson static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr, 6429f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 6439f64bd8aSPaolo Bonzini { 6449f64bd8aSPaolo Bonzini target_ulong rtas_r3 = args[0]; 6454fe822e0SAlexey Kardashevskiy uint32_t token = rtas_ld(rtas_r3, 0); 6464fe822e0SAlexey Kardashevskiy uint32_t nargs = rtas_ld(rtas_r3, 1); 6474fe822e0SAlexey Kardashevskiy uint32_t nret = rtas_ld(rtas_r3, 2); 6489f64bd8aSPaolo Bonzini 649210b580bSAnthony Liguori return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 6509f64bd8aSPaolo Bonzini nret, rtas_r3 + 12 + 4*nargs); 6519f64bd8aSPaolo Bonzini } 6529f64bd8aSPaolo Bonzini 653ce2918cbSDavid Gibson static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr, 6549f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 6559f64bd8aSPaolo Bonzini { 656fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 6579f64bd8aSPaolo Bonzini target_ulong size = args[0]; 6589f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 6599f64bd8aSPaolo Bonzini 6609f64bd8aSPaolo Bonzini switch (size) { 6619f64bd8aSPaolo Bonzini case 1: 6622c17449bSEdgar E. Iglesias args[0] = ldub_phys(cs->as, addr); 6639f64bd8aSPaolo Bonzini return H_SUCCESS; 6649f64bd8aSPaolo Bonzini case 2: 66541701aa4SEdgar E. Iglesias args[0] = lduw_phys(cs->as, addr); 6669f64bd8aSPaolo Bonzini return H_SUCCESS; 6679f64bd8aSPaolo Bonzini case 4: 668fdfba1a2SEdgar E. Iglesias args[0] = ldl_phys(cs->as, addr); 6699f64bd8aSPaolo Bonzini return H_SUCCESS; 6709f64bd8aSPaolo Bonzini case 8: 6712c17449bSEdgar E. Iglesias args[0] = ldq_phys(cs->as, addr); 6729f64bd8aSPaolo Bonzini return H_SUCCESS; 6739f64bd8aSPaolo Bonzini } 6749f64bd8aSPaolo Bonzini return H_PARAMETER; 6759f64bd8aSPaolo Bonzini } 6769f64bd8aSPaolo Bonzini 677ce2918cbSDavid Gibson static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr, 6789f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 6799f64bd8aSPaolo Bonzini { 680f606604fSEdgar E. Iglesias CPUState *cs = CPU(cpu); 681f606604fSEdgar E. Iglesias 6829f64bd8aSPaolo Bonzini target_ulong size = args[0]; 6839f64bd8aSPaolo Bonzini target_ulong addr = args[1]; 6849f64bd8aSPaolo Bonzini target_ulong val = args[2]; 6859f64bd8aSPaolo Bonzini 6869f64bd8aSPaolo Bonzini switch (size) { 6879f64bd8aSPaolo Bonzini case 1: 688db3be60dSEdgar E. Iglesias stb_phys(cs->as, addr, val); 6899f64bd8aSPaolo Bonzini return H_SUCCESS; 6909f64bd8aSPaolo Bonzini case 2: 6915ce5944dSEdgar E. Iglesias stw_phys(cs->as, addr, val); 6929f64bd8aSPaolo Bonzini return H_SUCCESS; 6939f64bd8aSPaolo Bonzini case 4: 694ab1da857SEdgar E. Iglesias stl_phys(cs->as, addr, val); 6959f64bd8aSPaolo Bonzini return H_SUCCESS; 6969f64bd8aSPaolo Bonzini case 8: 697f606604fSEdgar E. Iglesias stq_phys(cs->as, addr, val); 6989f64bd8aSPaolo Bonzini return H_SUCCESS; 6999f64bd8aSPaolo Bonzini } 7009f64bd8aSPaolo Bonzini return H_PARAMETER; 7019f64bd8aSPaolo Bonzini } 7029f64bd8aSPaolo Bonzini 703ce2918cbSDavid Gibson static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr, 7049f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 7059f64bd8aSPaolo Bonzini { 706fdfba1a2SEdgar E. Iglesias CPUState *cs = CPU(cpu); 707fdfba1a2SEdgar E. Iglesias 7089f64bd8aSPaolo Bonzini target_ulong dst = args[0]; /* Destination address */ 7099f64bd8aSPaolo Bonzini target_ulong src = args[1]; /* Source address */ 7109f64bd8aSPaolo Bonzini target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 7119f64bd8aSPaolo Bonzini target_ulong count = args[3]; /* Element count */ 7129f64bd8aSPaolo Bonzini target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 7139f64bd8aSPaolo Bonzini uint64_t tmp; 7149f64bd8aSPaolo Bonzini unsigned int mask = (1 << esize) - 1; 7159f64bd8aSPaolo Bonzini int step = 1 << esize; 7169f64bd8aSPaolo Bonzini 7179f64bd8aSPaolo Bonzini if (count > 0x80000000) { 7189f64bd8aSPaolo Bonzini return H_PARAMETER; 7199f64bd8aSPaolo Bonzini } 7209f64bd8aSPaolo Bonzini 7219f64bd8aSPaolo Bonzini if ((dst & mask) || (src & mask) || (op > 1)) { 7229f64bd8aSPaolo Bonzini return H_PARAMETER; 7239f64bd8aSPaolo Bonzini } 7249f64bd8aSPaolo Bonzini 7259f64bd8aSPaolo Bonzini if (dst >= src && dst < (src + (count << esize))) { 7269f64bd8aSPaolo Bonzini dst = dst + ((count - 1) << esize); 7279f64bd8aSPaolo Bonzini src = src + ((count - 1) << esize); 7289f64bd8aSPaolo Bonzini step = -step; 7299f64bd8aSPaolo Bonzini } 7309f64bd8aSPaolo Bonzini 7319f64bd8aSPaolo Bonzini while (count--) { 7329f64bd8aSPaolo Bonzini switch (esize) { 7339f64bd8aSPaolo Bonzini case 0: 7342c17449bSEdgar E. Iglesias tmp = ldub_phys(cs->as, src); 7359f64bd8aSPaolo Bonzini break; 7369f64bd8aSPaolo Bonzini case 1: 73741701aa4SEdgar E. Iglesias tmp = lduw_phys(cs->as, src); 7389f64bd8aSPaolo Bonzini break; 7399f64bd8aSPaolo Bonzini case 2: 740fdfba1a2SEdgar E. Iglesias tmp = ldl_phys(cs->as, src); 7419f64bd8aSPaolo Bonzini break; 7429f64bd8aSPaolo Bonzini case 3: 7432c17449bSEdgar E. Iglesias tmp = ldq_phys(cs->as, src); 7449f64bd8aSPaolo Bonzini break; 7459f64bd8aSPaolo Bonzini default: 7469f64bd8aSPaolo Bonzini return H_PARAMETER; 7479f64bd8aSPaolo Bonzini } 7489f64bd8aSPaolo Bonzini if (op == 1) { 7499f64bd8aSPaolo Bonzini tmp = ~tmp; 7509f64bd8aSPaolo Bonzini } 7519f64bd8aSPaolo Bonzini switch (esize) { 7529f64bd8aSPaolo Bonzini case 0: 753db3be60dSEdgar E. Iglesias stb_phys(cs->as, dst, tmp); 7549f64bd8aSPaolo Bonzini break; 7559f64bd8aSPaolo Bonzini case 1: 7565ce5944dSEdgar E. Iglesias stw_phys(cs->as, dst, tmp); 7579f64bd8aSPaolo Bonzini break; 7589f64bd8aSPaolo Bonzini case 2: 759ab1da857SEdgar E. Iglesias stl_phys(cs->as, dst, tmp); 7609f64bd8aSPaolo Bonzini break; 7619f64bd8aSPaolo Bonzini case 3: 762f606604fSEdgar E. Iglesias stq_phys(cs->as, dst, tmp); 7639f64bd8aSPaolo Bonzini break; 7649f64bd8aSPaolo Bonzini } 7659f64bd8aSPaolo Bonzini dst = dst + step; 7669f64bd8aSPaolo Bonzini src = src + step; 7679f64bd8aSPaolo Bonzini } 7689f64bd8aSPaolo Bonzini 7699f64bd8aSPaolo Bonzini return H_SUCCESS; 7709f64bd8aSPaolo Bonzini } 7719f64bd8aSPaolo Bonzini 772ce2918cbSDavid Gibson static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr, 7739f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 7749f64bd8aSPaolo Bonzini { 7759f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 7769f64bd8aSPaolo Bonzini return H_SUCCESS; 7779f64bd8aSPaolo Bonzini } 7789f64bd8aSPaolo Bonzini 779ce2918cbSDavid Gibson static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, 7809f64bd8aSPaolo Bonzini target_ulong opcode, target_ulong *args) 7819f64bd8aSPaolo Bonzini { 7829f64bd8aSPaolo Bonzini /* Nothing to do on emulation, KVM will trap this in the kernel */ 7839f64bd8aSPaolo Bonzini return H_SUCCESS; 7849f64bd8aSPaolo Bonzini } 7859f64bd8aSPaolo Bonzini 7867d0cd464SPeter Maydell static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 787c4c81d7dSGreg Kurz SpaprMachineState *spapr, 788c4015bbdSAlexey Kardashevskiy target_ulong mflags, 789c4015bbdSAlexey Kardashevskiy target_ulong value1, 790c4015bbdSAlexey Kardashevskiy target_ulong value2) 79142561bf2SAnton Blanchard { 79242561bf2SAnton Blanchard if (value1) { 793c4015bbdSAlexey Kardashevskiy return H_P3; 79442561bf2SAnton Blanchard } 79542561bf2SAnton Blanchard if (value2) { 796c4015bbdSAlexey Kardashevskiy return H_P4; 79742561bf2SAnton Blanchard } 798c4015bbdSAlexey Kardashevskiy 79942561bf2SAnton Blanchard switch (mflags) { 80042561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_BIG: 80100fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(0, LPCR_ILE); 802c4c81d7dSGreg Kurz spapr_pci_switch_vga(spapr, true); 803c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 80442561bf2SAnton Blanchard 80542561bf2SAnton Blanchard case H_SET_MODE_ENDIAN_LITTLE: 80600fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE); 807c4c81d7dSGreg Kurz spapr_pci_switch_vga(spapr, false); 808c4015bbdSAlexey Kardashevskiy return H_SUCCESS; 809c4015bbdSAlexey Kardashevskiy } 810c4015bbdSAlexey Kardashevskiy 811c4015bbdSAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 812c4015bbdSAlexey Kardashevskiy } 813c4015bbdSAlexey Kardashevskiy 8147d0cd464SPeter Maydell static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 815d5ac4f54SAlexey Kardashevskiy target_ulong mflags, 816d5ac4f54SAlexey Kardashevskiy target_ulong value1, 817d5ac4f54SAlexey Kardashevskiy target_ulong value2) 818d5ac4f54SAlexey Kardashevskiy { 819d5ac4f54SAlexey Kardashevskiy PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 820d5ac4f54SAlexey Kardashevskiy 821d5ac4f54SAlexey Kardashevskiy if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 822d5ac4f54SAlexey Kardashevskiy return H_P2; 823d5ac4f54SAlexey Kardashevskiy } 824d5ac4f54SAlexey Kardashevskiy if (value1) { 825d5ac4f54SAlexey Kardashevskiy return H_P3; 826d5ac4f54SAlexey Kardashevskiy } 827d5ac4f54SAlexey Kardashevskiy if (value2) { 828d5ac4f54SAlexey Kardashevskiy return H_P4; 829d5ac4f54SAlexey Kardashevskiy } 830d5ac4f54SAlexey Kardashevskiy 8318b7e6b07SNicholas Piggin if (mflags == 1) { 832526cdce7SNicholas Piggin /* AIL=1 is reserved in POWER8/POWER9/POWER10 */ 833526cdce7SNicholas Piggin return H_UNSUPPORTED_FLAG; 834526cdce7SNicholas Piggin } 835526cdce7SNicholas Piggin 836526cdce7SNicholas Piggin if (mflags == 2 && (pcc->insns_flags2 & PPC2_ISA310)) { 837526cdce7SNicholas Piggin /* AIL=2 is reserved in POWER10 (ISA v3.1) */ 838d5ac4f54SAlexey Kardashevskiy return H_UNSUPPORTED_FLAG; 839d5ac4f54SAlexey Kardashevskiy } 840d5ac4f54SAlexey Kardashevskiy 84100fd075eSBenjamin Herrenschmidt spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL); 842d5ac4f54SAlexey Kardashevskiy 843d5ac4f54SAlexey Kardashevskiy return H_SUCCESS; 844d5ac4f54SAlexey Kardashevskiy } 845d5ac4f54SAlexey Kardashevskiy 846ce2918cbSDavid Gibson static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, 847c4015bbdSAlexey Kardashevskiy target_ulong opcode, target_ulong *args) 848c4015bbdSAlexey Kardashevskiy { 849c4015bbdSAlexey Kardashevskiy target_ulong resource = args[1]; 850c4015bbdSAlexey Kardashevskiy target_ulong ret = H_P2; 851c4015bbdSAlexey Kardashevskiy 852c4015bbdSAlexey Kardashevskiy switch (resource) { 853c4015bbdSAlexey Kardashevskiy case H_SET_MODE_RESOURCE_LE: 854c4c81d7dSGreg Kurz ret = h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[3]); 85542561bf2SAnton Blanchard break; 856d5ac4f54SAlexey Kardashevskiy case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 8577d0cd464SPeter Maydell ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 858d5ac4f54SAlexey Kardashevskiy args[2], args[3]); 859d5ac4f54SAlexey Kardashevskiy break; 86042561bf2SAnton Blanchard } 86142561bf2SAnton Blanchard 86242561bf2SAnton Blanchard return ret; 86342561bf2SAnton Blanchard } 86442561bf2SAnton Blanchard 865ce2918cbSDavid Gibson static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr, 866d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 867d77a98b0SSuraj Jitindar Singh { 868d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 869d77a98b0SSuraj Jitindar Singh opcode, " (H_CLEAN_SLB)"); 870d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 871d77a98b0SSuraj Jitindar Singh } 872d77a98b0SSuraj Jitindar Singh 873ce2918cbSDavid Gibson static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr, 874d77a98b0SSuraj Jitindar Singh target_ulong opcode, target_ulong *args) 875d77a98b0SSuraj Jitindar Singh { 876d77a98b0SSuraj Jitindar Singh qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 877d77a98b0SSuraj Jitindar Singh opcode, " (H_INVALIDATE_PID)"); 878d77a98b0SSuraj Jitindar Singh return H_FUNCTION; 879d77a98b0SSuraj Jitindar Singh } 880d77a98b0SSuraj Jitindar Singh 881ce2918cbSDavid Gibson static void spapr_check_setup_free_hpt(SpaprMachineState *spapr, 882b4db5413SSuraj Jitindar Singh uint64_t patbe_old, uint64_t patbe_new) 883b4db5413SSuraj Jitindar Singh { 884b4db5413SSuraj Jitindar Singh /* 885b4db5413SSuraj Jitindar Singh * We have 4 Options: 886b4db5413SSuraj Jitindar Singh * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 887b4db5413SSuraj Jitindar Singh * HASH->RADIX : Free HPT 888b4db5413SSuraj Jitindar Singh * RADIX->HASH : Allocate HPT 889b4db5413SSuraj Jitindar Singh * NOTHING->HASH : Allocate HPT 890b4db5413SSuraj Jitindar Singh * Note: NOTHING implies the case where we said the guest could choose 891b4db5413SSuraj Jitindar Singh * later and so assumed radix and now it's called H_REG_PROC_TBL 892b4db5413SSuraj Jitindar Singh */ 893b4db5413SSuraj Jitindar Singh 89479825f4dSBenjamin Herrenschmidt if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) { 895b4db5413SSuraj Jitindar Singh /* We assume RADIX, so this catches all the "Do Nothing" cases */ 89679825f4dSBenjamin Herrenschmidt } else if (!(patbe_old & PATE1_GR)) { 897b4db5413SSuraj Jitindar Singh /* HASH->RADIX : Free HPT */ 89806ec79e8SBharata B Rao spapr_free_hpt(spapr); 89979825f4dSBenjamin Herrenschmidt } else if (!(patbe_new & PATE1_GR)) { 900b4db5413SSuraj Jitindar Singh /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 9018897ea5aSDavid Gibson spapr_setup_hpt(spapr); 902b4db5413SSuraj Jitindar Singh } 903b4db5413SSuraj Jitindar Singh return; 904b4db5413SSuraj Jitindar Singh } 905b4db5413SSuraj Jitindar Singh 906b4db5413SSuraj Jitindar Singh #define FLAGS_MASK 0x01FULL 907b4db5413SSuraj Jitindar Singh #define FLAG_MODIFY 0x10 908b4db5413SSuraj Jitindar Singh #define FLAG_REGISTER 0x08 909b4db5413SSuraj Jitindar Singh #define FLAG_RADIX 0x04 910b4db5413SSuraj Jitindar Singh #define FLAG_HASH_PROC_TBL 0x02 911b4db5413SSuraj Jitindar Singh #define FLAG_GTSE 0x01 912b4db5413SSuraj Jitindar Singh 913d77a98b0SSuraj Jitindar Singh static target_ulong h_register_process_table(PowerPCCPU *cpu, 914ce2918cbSDavid Gibson SpaprMachineState *spapr, 915d77a98b0SSuraj Jitindar Singh target_ulong opcode, 916d77a98b0SSuraj Jitindar Singh target_ulong *args) 917d77a98b0SSuraj Jitindar Singh { 918b4db5413SSuraj Jitindar Singh target_ulong flags = args[0]; 919b4db5413SSuraj Jitindar Singh target_ulong proc_tbl = args[1]; 920b4db5413SSuraj Jitindar Singh target_ulong page_size = args[2]; 921b4db5413SSuraj Jitindar Singh target_ulong table_size = args[3]; 922176dcceeSSuraj Jitindar Singh target_ulong update_lpcr = 0; 923b4db5413SSuraj Jitindar Singh uint64_t cproc; 924b4db5413SSuraj Jitindar Singh 925b4db5413SSuraj Jitindar Singh if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 926b4db5413SSuraj Jitindar Singh return H_PARAMETER; 927b4db5413SSuraj Jitindar Singh } 928b4db5413SSuraj Jitindar Singh if (flags & FLAG_MODIFY) { 929b4db5413SSuraj Jitindar Singh if (flags & FLAG_REGISTER) { 930b4db5413SSuraj Jitindar Singh if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 931b4db5413SSuraj Jitindar Singh if (proc_tbl & 0xfff || proc_tbl >> 60) { 932b4db5413SSuraj Jitindar Singh return H_P2; 933b4db5413SSuraj Jitindar Singh } else if (page_size) { 934b4db5413SSuraj Jitindar Singh return H_P3; 935b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 936b4db5413SSuraj Jitindar Singh return H_P4; 937b4db5413SSuraj Jitindar Singh } 93879825f4dSBenjamin Herrenschmidt cproc = PATE1_GR | proc_tbl | table_size; 939b4db5413SSuraj Jitindar Singh } else { /* Register new HPT process table */ 940b4db5413SSuraj Jitindar Singh if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 941b4db5413SSuraj Jitindar Singh /* TODO - Not Supported */ 942b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 943b4db5413SSuraj Jitindar Singh return H_PARAMETER; 944b4db5413SSuraj Jitindar Singh } else { /* Hash with SLB */ 945b4db5413SSuraj Jitindar Singh if (proc_tbl >> 38) { 946b4db5413SSuraj Jitindar Singh return H_P2; 947b4db5413SSuraj Jitindar Singh } else if (page_size & ~0x7) { 948b4db5413SSuraj Jitindar Singh return H_P3; 949b4db5413SSuraj Jitindar Singh } else if (table_size > 24) { 950b4db5413SSuraj Jitindar Singh return H_P4; 951b4db5413SSuraj Jitindar Singh } 952b4db5413SSuraj Jitindar Singh } 953b4db5413SSuraj Jitindar Singh cproc = (proc_tbl << 25) | page_size << 5 | table_size; 954b4db5413SSuraj Jitindar Singh } 955b4db5413SSuraj Jitindar Singh 956b4db5413SSuraj Jitindar Singh } else { /* Deregister current process table */ 95779825f4dSBenjamin Herrenschmidt /* 95879825f4dSBenjamin Herrenschmidt * Set to benign value: (current GR) | 0. This allows 95979825f4dSBenjamin Herrenschmidt * deregistration in KVM to succeed even if the radix bit 96079825f4dSBenjamin Herrenschmidt * in flags doesn't match the radix bit in the old PATE. 96179825f4dSBenjamin Herrenschmidt */ 96279825f4dSBenjamin Herrenschmidt cproc = spapr->patb_entry & PATE1_GR; 963b4db5413SSuraj Jitindar Singh } 964b4db5413SSuraj Jitindar Singh } else { /* Maintain current registration */ 96579825f4dSBenjamin Herrenschmidt if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) { 966b4db5413SSuraj Jitindar Singh /* Technically caused by flag bits => H_PARAMETER */ 967b4db5413SSuraj Jitindar Singh return H_PARAMETER; /* Existing Process Table Mismatch */ 968b4db5413SSuraj Jitindar Singh } 969b4db5413SSuraj Jitindar Singh cproc = spapr->patb_entry; 970b4db5413SSuraj Jitindar Singh } 971b4db5413SSuraj Jitindar Singh 972b4db5413SSuraj Jitindar Singh /* Check if we need to setup OR free the hpt */ 973b4db5413SSuraj Jitindar Singh spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 974b4db5413SSuraj Jitindar Singh 975b4db5413SSuraj Jitindar Singh spapr->patb_entry = cproc; /* Save new process table */ 9766de83307SSuraj Jitindar Singh 97700fd075eSBenjamin Herrenschmidt /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */ 978176dcceeSSuraj Jitindar Singh if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR */ 979176dcceeSSuraj Jitindar Singh update_lpcr |= (LPCR_UPRT | LPCR_HR); 980176dcceeSSuraj Jitindar Singh else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */ 981176dcceeSSuraj Jitindar Singh update_lpcr |= LPCR_UPRT; 982176dcceeSSuraj Jitindar Singh if (flags & FLAG_GTSE) /* Guest translation shootdown enable */ 98349e9fdd7SDavid Gibson update_lpcr |= LPCR_GTSE; 98449e9fdd7SDavid Gibson 985176dcceeSSuraj Jitindar Singh spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE); 986b4db5413SSuraj Jitindar Singh 987b4db5413SSuraj Jitindar Singh if (kvm_enabled()) { 988b4db5413SSuraj Jitindar Singh return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 989b4db5413SSuraj Jitindar Singh flags & FLAG_GTSE, cproc); 990b4db5413SSuraj Jitindar Singh } 991b4db5413SSuraj Jitindar Singh return H_SUCCESS; 992d77a98b0SSuraj Jitindar Singh } 993d77a98b0SSuraj Jitindar Singh 9941c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALL -1 9951c7ad77eSNicholas Piggin #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 9961c7ad77eSNicholas Piggin 9971c7ad77eSNicholas Piggin static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 998ce2918cbSDavid Gibson SpaprMachineState *spapr, 9991c7ad77eSNicholas Piggin target_ulong opcode, target_ulong *args) 10001c7ad77eSNicholas Piggin { 10011c7ad77eSNicholas Piggin target_long target = args[0]; 10021c7ad77eSNicholas Piggin CPUState *cs; 10031c7ad77eSNicholas Piggin 10041c7ad77eSNicholas Piggin if (target < 0) { 10051c7ad77eSNicholas Piggin /* Broadcast */ 10061c7ad77eSNicholas Piggin if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 10071c7ad77eSNicholas Piggin return H_PARAMETER; 10081c7ad77eSNicholas Piggin } 10091c7ad77eSNicholas Piggin 10101c7ad77eSNicholas Piggin CPU_FOREACH(cs) { 10111c7ad77eSNicholas Piggin PowerPCCPU *c = POWERPC_CPU(cs); 10121c7ad77eSNicholas Piggin 10131c7ad77eSNicholas Piggin if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 10141c7ad77eSNicholas Piggin if (c == cpu) { 10151c7ad77eSNicholas Piggin continue; 10161c7ad77eSNicholas Piggin } 10171c7ad77eSNicholas Piggin } 10181c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 10191c7ad77eSNicholas Piggin } 10201c7ad77eSNicholas Piggin return H_SUCCESS; 10211c7ad77eSNicholas Piggin 10221c7ad77eSNicholas Piggin } else { 10231c7ad77eSNicholas Piggin /* Unicast */ 10242e886fb3SSam Bobroff cs = CPU(spapr_find_cpu(target)); 1025f57467e3SSam Bobroff if (cs) { 10261c7ad77eSNicholas Piggin run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 10271c7ad77eSNicholas Piggin return H_SUCCESS; 10281c7ad77eSNicholas Piggin } 10291c7ad77eSNicholas Piggin return H_PARAMETER; 10301c7ad77eSNicholas Piggin } 10311c7ad77eSNicholas Piggin } 10321c7ad77eSNicholas Piggin 1033121afbe4SGreg Kurz /* Returns either a logical PVR or zero if none was found */ 1034121afbe4SGreg Kurz static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32_t max_compat, 1035121afbe4SGreg Kurz target_ulong *addr, bool *raw_mode_supported) 10362a6593cbSAlexey Kardashevskiy { 1037152ef803SDavid Gibson bool explicit_match = false; /* Matched the CPU's real PVR */ 1038152ef803SDavid Gibson uint32_t best_compat = 0; 1039152ef803SDavid Gibson int i; 10403794d548SAlexey Kardashevskiy 1041152ef803SDavid Gibson /* 1042152ef803SDavid Gibson * We scan the supplied table of PVRs looking for two things 1043152ef803SDavid Gibson * 1. Is our real CPU PVR in the list? 1044152ef803SDavid Gibson * 2. What's the "best" listed logical PVR 1045152ef803SDavid Gibson */ 1046152ef803SDavid Gibson for (i = 0; i < 512; ++i) { 10473794d548SAlexey Kardashevskiy uint32_t pvr, pvr_mask; 10483794d548SAlexey Kardashevskiy 104980c33d34SDavid Gibson pvr_mask = ldl_be_phys(&address_space_memory, *addr); 105080c33d34SDavid Gibson pvr = ldl_be_phys(&address_space_memory, *addr + 4); 105180c33d34SDavid Gibson *addr += 8; 10523794d548SAlexey Kardashevskiy 10533794d548SAlexey Kardashevskiy if (~pvr_mask & pvr) { 1054152ef803SDavid Gibson break; /* Terminator record */ 10553794d548SAlexey Kardashevskiy } 1056152ef803SDavid Gibson 1057152ef803SDavid Gibson if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1058152ef803SDavid Gibson explicit_match = true; 1059152ef803SDavid Gibson } else { 1060152ef803SDavid Gibson if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1061152ef803SDavid Gibson best_compat = pvr; 1062152ef803SDavid Gibson } 1063152ef803SDavid Gibson } 1064152ef803SDavid Gibson } 1065152ef803SDavid Gibson 1066cc7b35b1SGreg Kurz *raw_mode_supported = explicit_match; 1067cc7b35b1SGreg Kurz 10683794d548SAlexey Kardashevskiy /* Parsing finished */ 1069152ef803SDavid Gibson trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 10703794d548SAlexey Kardashevskiy 107180c33d34SDavid Gibson return best_compat; 107280c33d34SDavid Gibson } 107380c33d34SDavid Gibson 1074eb72b639SDaniel Henrique Barboza static 107591067db1SAlexey Kardashevskiy target_ulong do_client_architecture_support(PowerPCCPU *cpu, 1076ce2918cbSDavid Gibson SpaprMachineState *spapr, 107791067db1SAlexey Kardashevskiy target_ulong vec, 107891067db1SAlexey Kardashevskiy target_ulong fdt_bufsize) 107980c33d34SDavid Gibson { 108091067db1SAlexey Kardashevskiy target_ulong ov_table; /* Working address in data buffer */ 108180c33d34SDavid Gibson uint32_t cas_pvr; 108286962462SGreg Kurz SpaprOptionVector *ov1_guest, *ov5_guest; 108380c33d34SDavid Gibson bool guest_radix; 1084cc7b35b1SGreg Kurz bool raw_mode_supported = false; 108521bde1ecSAlexey Kardashevskiy bool guest_xive; 108612b3868eSGreg Kurz CPUState *cs; 1087087820e3SGreg Kurz void *fdt; 1088121afbe4SGreg Kurz uint32_t max_compat = spapr->max_compat_pvr; 108912b3868eSGreg Kurz 109012b3868eSGreg Kurz /* CAS is supposed to be called early when only the boot vCPU is active. */ 109112b3868eSGreg Kurz CPU_FOREACH(cs) { 109212b3868eSGreg Kurz if (cs == CPU(cpu)) { 109312b3868eSGreg Kurz continue; 109412b3868eSGreg Kurz } 109512b3868eSGreg Kurz if (!cs->halted) { 109612b3868eSGreg Kurz warn_report("guest has multiple active vCPUs at CAS, which is not allowed"); 109712b3868eSGreg Kurz return H_MULTI_THREADS_ACTIVE; 109812b3868eSGreg Kurz } 109912b3868eSGreg Kurz } 11003794d548SAlexey Kardashevskiy 1101121afbe4SGreg Kurz cas_pvr = cas_check_pvr(cpu, max_compat, &vec, &raw_mode_supported); 1102121afbe4SGreg Kurz if (!cas_pvr && (!raw_mode_supported || max_compat)) { 1103121afbe4SGreg Kurz /* 1104121afbe4SGreg Kurz * We couldn't find a suitable compatibility mode, and either 1105121afbe4SGreg Kurz * the guest doesn't support "raw" mode for this CPU, or "raw" 1106121afbe4SGreg Kurz * mode is disabled because a maximum compat mode is set. 1107121afbe4SGreg Kurz */ 1108121afbe4SGreg Kurz error_report("Couldn't negotiate a suitable PVR during CAS"); 110980c33d34SDavid Gibson return H_HARDWARE; 111080c33d34SDavid Gibson } 111180c33d34SDavid Gibson 111280c33d34SDavid Gibson /* Update CPUs */ 111380c33d34SDavid Gibson if (cpu->compat_pvr != cas_pvr) { 11147e92da81SGreg Kurz Error *local_err = NULL; 11157e92da81SGreg Kurz 11167e92da81SGreg Kurz if (ppc_set_compat_all(cas_pvr, &local_err) < 0) { 1117cc7b35b1SGreg Kurz /* We fail to set compat mode (likely because running with KVM PR), 1118cc7b35b1SGreg Kurz * but maybe we can fallback to raw mode if the guest supports it. 1119cc7b35b1SGreg Kurz */ 1120cc7b35b1SGreg Kurz if (!raw_mode_supported) { 1121f6f242c7SDavid Gibson error_report_err(local_err); 11223794d548SAlexey Kardashevskiy return H_HARDWARE; 11233794d548SAlexey Kardashevskiy } 11242c9dfdacSGreg Kurz error_free(local_err); 1125cc7b35b1SGreg Kurz } 11263794d548SAlexey Kardashevskiy } 11273794d548SAlexey Kardashevskiy 112803d196b7SBharata B Rao /* For the future use: here @ov_table points to the first option vector */ 112991067db1SAlexey Kardashevskiy ov_table = vec; 113003d196b7SBharata B Rao 1131e957f6a9SSam Bobroff ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1132cbd0d7f3SGreg Kurz if (!ov1_guest) { 1133cbd0d7f3SGreg Kurz warn_report("guest didn't provide option vector 1"); 1134cbd0d7f3SGreg Kurz return H_PARAMETER; 1135cbd0d7f3SGreg Kurz } 1136facdb8b6SMichael Roth ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1137cbd0d7f3SGreg Kurz if (!ov5_guest) { 1138ce05fa0fSGreg Kurz spapr_ovec_cleanup(ov1_guest); 1139cbd0d7f3SGreg Kurz warn_report("guest didn't provide option vector 5"); 1140cbd0d7f3SGreg Kurz return H_PARAMETER; 1141cbd0d7f3SGreg Kurz } 11429fb4541fSSam Bobroff if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 11439fb4541fSSam Bobroff error_report("guest requested hash and radix MMU, which is invalid."); 11449fb4541fSSam Bobroff exit(EXIT_FAILURE); 11459fb4541fSSam Bobroff } 1146e7f78db9SGreg Kurz if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) { 1147e7f78db9SGreg Kurz error_report("guest requested an invalid interrupt mode"); 1148e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1149e7f78db9SGreg Kurz } 1150e7f78db9SGreg Kurz 11519fb4541fSSam Bobroff guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 11522a6593cbSAlexey Kardashevskiy 1153e7f78db9SGreg Kurz guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT); 1154e7f78db9SGreg Kurz 11552772cf6bSDavid Gibson /* 11562772cf6bSDavid Gibson * HPT resizing is a bit of a special case, because when enabled 11572772cf6bSDavid Gibson * we assume an HPT guest will support it until it says it 11582772cf6bSDavid Gibson * doesn't, instead of assuming it won't support it until it says 11592772cf6bSDavid Gibson * it does. Strictly speaking that approach could break for 11602772cf6bSDavid Gibson * guests which don't make a CAS call, but those are so old we 11612772cf6bSDavid Gibson * don't care about them. Without that assumption we'd have to 11622772cf6bSDavid Gibson * make at least a temporary allocation of an HPT sized for max 11632772cf6bSDavid Gibson * memory, which could be impossibly difficult under KVM HV if 11642772cf6bSDavid Gibson * maxram is large. 11652772cf6bSDavid Gibson */ 11662772cf6bSDavid Gibson if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 11672772cf6bSDavid Gibson int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 11682772cf6bSDavid Gibson 11692772cf6bSDavid Gibson if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 11702772cf6bSDavid Gibson error_report( 11712772cf6bSDavid Gibson "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 11722772cf6bSDavid Gibson exit(1); 11732772cf6bSDavid Gibson } 11742772cf6bSDavid Gibson 11752772cf6bSDavid Gibson if (spapr->htab_shift < maxshift) { 11762772cf6bSDavid Gibson /* Guest doesn't know about HPT resizing, so we 11772772cf6bSDavid Gibson * pre-emptively resize for the maximum permitted RAM. At 11782772cf6bSDavid Gibson * the point this is called, nothing should have been 11792772cf6bSDavid Gibson * entered into the existing HPT */ 11802772cf6bSDavid Gibson spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 11811ec26c75SGreg Kurz push_sregs_to_kvm_pr(spapr); 1182b55d295eSDavid Gibson } 11832772cf6bSDavid Gibson } 11842772cf6bSDavid Gibson 1185facdb8b6SMichael Roth /* NOTE: there are actually a number of ov5 bits where input from the 1186facdb8b6SMichael Roth * guest is always zero, and the platform/QEMU enables them independently 1187facdb8b6SMichael Roth * of guest input. To model these properly we'd want some sort of mask, 1188facdb8b6SMichael Roth * but since they only currently apply to memory migration as defined 1189facdb8b6SMichael Roth * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 11906787d27bSMichael Roth * to worry about this for now. 1191facdb8b6SMichael Roth */ 119230bf9ed1SCédric Le Goater 11936787d27bSMichael Roth /* full range of negotiated ov5 capabilities */ 1194facdb8b6SMichael Roth spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1195facdb8b6SMichael Roth spapr_ovec_cleanup(ov5_guest); 1196b4b83312SGreg Kurz 1197068479e1SFabiano Rosas spapr_check_mmu_mode(guest_radix); 1198068479e1SFabiano Rosas 1199daa36379SDavid Gibson spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00); 120000005f22SShivaprasad G Bhat spapr_ovec_cleanup(ov1_guest); 120113db0cd9SCédric Le Goater 120213db0cd9SCédric Le Goater /* 12035dab5abeSDaniel Henrique Barboza * Check for NUMA affinity conditions now that we know which NUMA 12045dab5abeSDaniel Henrique Barboza * affinity the guest will use. 12055dab5abeSDaniel Henrique Barboza */ 12065dab5abeSDaniel Henrique Barboza spapr_numa_associativity_check(spapr); 12075dab5abeSDaniel Henrique Barboza 12085dab5abeSDaniel Henrique Barboza /* 12098deb8019SDavid Gibson * Ensure the guest asks for an interrupt mode we support; 12108deb8019SDavid Gibson * otherwise terminate the boot. 1211e7f78db9SGreg Kurz */ 1212e7f78db9SGreg Kurz if (guest_xive) { 1213ca62823bSDavid Gibson if (!spapr->irq->xive) { 121475de5941SGreg Kurz error_report( 121575de5941SGreg Kurz "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property"); 1216e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1217e7f78db9SGreg Kurz } 1218e7f78db9SGreg Kurz } else { 1219ca62823bSDavid Gibson if (!spapr->irq->xics) { 122075de5941SGreg Kurz error_report( 122175de5941SGreg Kurz "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual"); 1222e7f78db9SGreg Kurz exit(EXIT_FAILURE); 1223e7f78db9SGreg Kurz } 1224e7f78db9SGreg Kurz } 1225e7f78db9SGreg Kurz 12268deb8019SDavid Gibson spapr_irq_update_active_intc(spapr); 12278deb8019SDavid Gibson 1228babb819fSGreg Kurz /* 1229babb819fSGreg Kurz * Process all pending hot-plug/unplug requests now. An updated full 1230babb819fSGreg Kurz * rendered FDT will be returned to the guest. 1231babb819fSGreg Kurz */ 1232babb819fSGreg Kurz spapr_drc_reset_all(spapr); 1233babb819fSGreg Kurz spapr_clear_pending_hotplug_events(spapr); 12340c21e073SDavid Gibson 1235087820e3SGreg Kurz /* 1236087820e3SGreg Kurz * If spapr_machine_reset() did not set up a HPT but one is necessary 1237087820e3SGreg Kurz * (because the guest isn't going to use radix) then set it up here. 1238087820e3SGreg Kurz */ 12398deb8019SDavid Gibson if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { 12408deb8019SDavid Gibson /* legacy hash or new hash: */ 12418897ea5aSDavid Gibson spapr_setup_hpt(spapr); 12428deb8019SDavid Gibson } 12430c21e073SDavid Gibson 124421bde1ecSAlexey Kardashevskiy fdt = spapr_build_fdt(spapr, spapr->vof != NULL, fdt_bufsize); 12450c21e073SDavid Gibson g_free(spapr->fdt_blob); 12460c21e073SDavid Gibson spapr->fdt_size = fdt_totalsize(fdt); 12470c21e073SDavid Gibson spapr->fdt_initial_size = spapr->fdt_size; 12480c21e073SDavid Gibson spapr->fdt_blob = fdt; 12492a6593cbSAlexey Kardashevskiy 12502a6593cbSAlexey Kardashevskiy return H_SUCCESS; 12512a6593cbSAlexey Kardashevskiy } 12522a6593cbSAlexey Kardashevskiy 125391067db1SAlexey Kardashevskiy static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 125491067db1SAlexey Kardashevskiy SpaprMachineState *spapr, 125591067db1SAlexey Kardashevskiy target_ulong opcode, 125691067db1SAlexey Kardashevskiy target_ulong *args) 125791067db1SAlexey Kardashevskiy { 125891067db1SAlexey Kardashevskiy target_ulong vec = ppc64_phys_to_real(args[0]); 125991067db1SAlexey Kardashevskiy target_ulong fdt_buf = args[1]; 126091067db1SAlexey Kardashevskiy target_ulong fdt_bufsize = args[2]; 126191067db1SAlexey Kardashevskiy target_ulong ret; 126291067db1SAlexey Kardashevskiy SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 126391067db1SAlexey Kardashevskiy 126491067db1SAlexey Kardashevskiy if (fdt_bufsize < sizeof(hdr)) { 126591067db1SAlexey Kardashevskiy error_report("SLOF provided insufficient CAS buffer " 126691067db1SAlexey Kardashevskiy TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr)); 126791067db1SAlexey Kardashevskiy exit(EXIT_FAILURE); 126891067db1SAlexey Kardashevskiy } 126991067db1SAlexey Kardashevskiy 127091067db1SAlexey Kardashevskiy fdt_bufsize -= sizeof(hdr); 127191067db1SAlexey Kardashevskiy 127291067db1SAlexey Kardashevskiy ret = do_client_architecture_support(cpu, spapr, vec, fdt_bufsize); 127391067db1SAlexey Kardashevskiy if (ret == H_SUCCESS) { 127491067db1SAlexey Kardashevskiy _FDT((fdt_pack(spapr->fdt_blob))); 127591067db1SAlexey Kardashevskiy spapr->fdt_size = fdt_totalsize(spapr->fdt_blob); 127691067db1SAlexey Kardashevskiy spapr->fdt_initial_size = spapr->fdt_size; 127791067db1SAlexey Kardashevskiy 127891067db1SAlexey Kardashevskiy cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr)); 127991067db1SAlexey Kardashevskiy cpu_physical_memory_write(fdt_buf + sizeof(hdr), spapr->fdt_blob, 128091067db1SAlexey Kardashevskiy spapr->fdt_size); 128191067db1SAlexey Kardashevskiy trace_spapr_cas_continue(spapr->fdt_size + sizeof(hdr)); 128291067db1SAlexey Kardashevskiy } 128391067db1SAlexey Kardashevskiy 128491067db1SAlexey Kardashevskiy return ret; 128591067db1SAlexey Kardashevskiy } 128691067db1SAlexey Kardashevskiy 1287fc8c745dSAlexey Kardashevskiy target_ulong spapr_vof_client_architecture_support(MachineState *ms, 1288fc8c745dSAlexey Kardashevskiy CPUState *cs, 1289fc8c745dSAlexey Kardashevskiy target_ulong ovec_addr) 1290fc8c745dSAlexey Kardashevskiy { 1291fc8c745dSAlexey Kardashevskiy SpaprMachineState *spapr = SPAPR_MACHINE(ms); 1292fc8c745dSAlexey Kardashevskiy 1293fc8c745dSAlexey Kardashevskiy target_ulong ret = do_client_architecture_support(POWERPC_CPU(cs), spapr, 1294fc8c745dSAlexey Kardashevskiy ovec_addr, FDT_MAX_SIZE); 1295fc8c745dSAlexey Kardashevskiy 1296fc8c745dSAlexey Kardashevskiy /* 1297fc8c745dSAlexey Kardashevskiy * This adds stdout and generates phandles for boottime and CAS FDTs. 1298fc8c745dSAlexey Kardashevskiy * It is alright to update the FDT here as do_client_architecture_support() 1299fc8c745dSAlexey Kardashevskiy * does not pack it. 1300fc8c745dSAlexey Kardashevskiy */ 1301fc8c745dSAlexey Kardashevskiy spapr_vof_client_dt_finalize(spapr, spapr->fdt_blob); 1302fc8c745dSAlexey Kardashevskiy 1303fc8c745dSAlexey Kardashevskiy return ret; 1304fc8c745dSAlexey Kardashevskiy } 1305fc8c745dSAlexey Kardashevskiy 1306c59704b2SSuraj Jitindar Singh static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, 1307ce2918cbSDavid Gibson SpaprMachineState *spapr, 1308c59704b2SSuraj Jitindar Singh target_ulong opcode, 1309c59704b2SSuraj Jitindar Singh target_ulong *args) 1310c59704b2SSuraj Jitindar Singh { 1311c59704b2SSuraj Jitindar Singh uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS & 1312c59704b2SSuraj Jitindar Singh ~H_CPU_CHAR_THR_RECONF_TRIG; 1313c59704b2SSuraj Jitindar Singh uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY; 1314c59704b2SSuraj Jitindar Singh uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC); 1315c59704b2SSuraj Jitindar Singh uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC); 1316c59704b2SSuraj Jitindar Singh uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS); 13178ff43ee4SSuraj Jitindar Singh uint8_t count_cache_flush_assist = spapr_get_cap(spapr, 13188ff43ee4SSuraj Jitindar Singh SPAPR_CAP_CCF_ASSIST); 1319c59704b2SSuraj Jitindar Singh 1320c59704b2SSuraj Jitindar Singh switch (safe_cache) { 1321c59704b2SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1322c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30; 1323c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2; 1324c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV; 1325c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1326c59704b2SSuraj Jitindar Singh break; 1327c59704b2SSuraj Jitindar Singh case SPAPR_CAP_FIXED: 132817fd09c0SNicholas Piggin behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY; 132917fd09c0SNicholas Piggin behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS; 1330c59704b2SSuraj Jitindar Singh break; 1331c59704b2SSuraj Jitindar Singh default: /* broken */ 1332c59704b2SSuraj Jitindar Singh assert(safe_cache == SPAPR_CAP_BROKEN); 1333c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR; 1334c59704b2SSuraj Jitindar Singh break; 1335c59704b2SSuraj Jitindar Singh } 1336c59704b2SSuraj Jitindar Singh 1337c59704b2SSuraj Jitindar Singh switch (safe_bounds_check) { 1338c59704b2SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1339c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31; 1340c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1341c59704b2SSuraj Jitindar Singh break; 1342c59704b2SSuraj Jitindar Singh case SPAPR_CAP_FIXED: 1343c59704b2SSuraj Jitindar Singh break; 1344c59704b2SSuraj Jitindar Singh default: /* broken */ 1345c59704b2SSuraj Jitindar Singh assert(safe_bounds_check == SPAPR_CAP_BROKEN); 1346c59704b2SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR; 1347c59704b2SSuraj Jitindar Singh break; 1348c59704b2SSuraj Jitindar Singh } 1349c59704b2SSuraj Jitindar Singh 1350c59704b2SSuraj Jitindar Singh switch (safe_indirect_branch) { 1351399b2896SSuraj Jitindar Singh case SPAPR_CAP_FIXED_NA: 1352399b2896SSuraj Jitindar Singh break; 1353c76c0d30SSuraj Jitindar Singh case SPAPR_CAP_FIXED_CCD: 1354c76c0d30SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS; 1355c76c0d30SSuraj Jitindar Singh break; 1356c76c0d30SSuraj Jitindar Singh case SPAPR_CAP_FIXED_IBS: 1357c59704b2SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; 1358fa86f592SGreg Kurz break; 1359399b2896SSuraj Jitindar Singh case SPAPR_CAP_WORKAROUND: 1360399b2896SSuraj Jitindar Singh behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE; 13618ff43ee4SSuraj Jitindar Singh if (count_cache_flush_assist) { 13628ff43ee4SSuraj Jitindar Singh characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST; 13638ff43ee4SSuraj Jitindar Singh } 1364399b2896SSuraj Jitindar Singh break; 1365c59704b2SSuraj Jitindar Singh default: /* broken */ 1366c59704b2SSuraj Jitindar Singh assert(safe_indirect_branch == SPAPR_CAP_BROKEN); 1367c59704b2SSuraj Jitindar Singh break; 1368c59704b2SSuraj Jitindar Singh } 1369c59704b2SSuraj Jitindar Singh 1370c59704b2SSuraj Jitindar Singh args[0] = characteristics; 1371c59704b2SSuraj Jitindar Singh args[1] = behaviour; 1372fea35ca4SAlexey Kardashevskiy return H_SUCCESS; 1373fea35ca4SAlexey Kardashevskiy } 1374fea35ca4SAlexey Kardashevskiy 1375ce2918cbSDavid Gibson static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr, 1376fea35ca4SAlexey Kardashevskiy target_ulong opcode, target_ulong *args) 1377fea35ca4SAlexey Kardashevskiy { 1378fea35ca4SAlexey Kardashevskiy target_ulong dt = ppc64_phys_to_real(args[0]); 1379fea35ca4SAlexey Kardashevskiy struct fdt_header hdr = { 0 }; 1380fea35ca4SAlexey Kardashevskiy unsigned cb; 1381ce2918cbSDavid Gibson SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1382fea35ca4SAlexey Kardashevskiy void *fdt; 1383fea35ca4SAlexey Kardashevskiy 1384fea35ca4SAlexey Kardashevskiy cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); 1385fea35ca4SAlexey Kardashevskiy cb = fdt32_to_cpu(hdr.totalsize); 1386fea35ca4SAlexey Kardashevskiy 1387fea35ca4SAlexey Kardashevskiy if (!smc->update_dt_enabled) { 1388fea35ca4SAlexey Kardashevskiy return H_SUCCESS; 1389fea35ca4SAlexey Kardashevskiy } 1390fea35ca4SAlexey Kardashevskiy 1391fea35ca4SAlexey Kardashevskiy /* Check that the fdt did not grow out of proportion */ 1392fea35ca4SAlexey Kardashevskiy if (cb > spapr->fdt_initial_size * 2) { 1393fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, 1394fea35ca4SAlexey Kardashevskiy fdt32_to_cpu(hdr.magic)); 1395fea35ca4SAlexey Kardashevskiy return H_PARAMETER; 1396fea35ca4SAlexey Kardashevskiy } 1397fea35ca4SAlexey Kardashevskiy 1398fea35ca4SAlexey Kardashevskiy fdt = g_malloc0(cb); 1399fea35ca4SAlexey Kardashevskiy cpu_physical_memory_read(dt, fdt, cb); 1400fea35ca4SAlexey Kardashevskiy 1401fea35ca4SAlexey Kardashevskiy /* Check the fdt consistency */ 1402fea35ca4SAlexey Kardashevskiy if (fdt_check_full(fdt, cb)) { 1403fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, 1404fea35ca4SAlexey Kardashevskiy fdt32_to_cpu(hdr.magic)); 1405fea35ca4SAlexey Kardashevskiy return H_PARAMETER; 1406fea35ca4SAlexey Kardashevskiy } 1407fea35ca4SAlexey Kardashevskiy 1408fea35ca4SAlexey Kardashevskiy g_free(spapr->fdt_blob); 1409fea35ca4SAlexey Kardashevskiy spapr->fdt_size = cb; 1410fea35ca4SAlexey Kardashevskiy spapr->fdt_blob = fdt; 1411fea35ca4SAlexey Kardashevskiy trace_spapr_update_dt(cb); 1412c59704b2SSuraj Jitindar Singh 1413c59704b2SSuraj Jitindar Singh return H_SUCCESS; 1414c59704b2SSuraj Jitindar Singh } 1415c59704b2SSuraj Jitindar Singh 14169f64bd8aSPaolo Bonzini static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 14179f64bd8aSPaolo Bonzini static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 14180fb6bd07SMichael Roth static spapr_hcall_fn svm_hypercall_table[(SVM_HCALL_MAX - SVM_HCALL_BASE) / 4 + 1]; 14199f64bd8aSPaolo Bonzini 14209f64bd8aSPaolo Bonzini void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 14219f64bd8aSPaolo Bonzini { 14229f64bd8aSPaolo Bonzini spapr_hcall_fn *slot; 14239f64bd8aSPaolo Bonzini 14249f64bd8aSPaolo Bonzini if (opcode <= MAX_HCALL_OPCODE) { 14259f64bd8aSPaolo Bonzini assert((opcode & 0x3) == 0); 14269f64bd8aSPaolo Bonzini 14279f64bd8aSPaolo Bonzini slot = &papr_hypercall_table[opcode / 4]; 14280fb6bd07SMichael Roth } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { 14290fb6bd07SMichael Roth /* we only have SVM-related hcall numbers assigned in multiples of 4 */ 14300fb6bd07SMichael Roth assert((opcode & 0x3) == 0); 14310fb6bd07SMichael Roth 14320fb6bd07SMichael Roth slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 14339f64bd8aSPaolo Bonzini } else { 14349f64bd8aSPaolo Bonzini assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 14359f64bd8aSPaolo Bonzini 14369f64bd8aSPaolo Bonzini slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 14379f64bd8aSPaolo Bonzini } 14389f64bd8aSPaolo Bonzini 14399f64bd8aSPaolo Bonzini assert(!(*slot)); 14409f64bd8aSPaolo Bonzini *slot = fn; 14419f64bd8aSPaolo Bonzini } 14429f64bd8aSPaolo Bonzini 14439f64bd8aSPaolo Bonzini target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 14449f64bd8aSPaolo Bonzini target_ulong *args) 14459f64bd8aSPaolo Bonzini { 1446ce2918cbSDavid Gibson SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 144728e02042SDavid Gibson 14489f64bd8aSPaolo Bonzini if ((opcode <= MAX_HCALL_OPCODE) 14499f64bd8aSPaolo Bonzini && ((opcode & 0x3) == 0)) { 14509f64bd8aSPaolo Bonzini spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 14519f64bd8aSPaolo Bonzini 14529f64bd8aSPaolo Bonzini if (fn) { 14539f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 14549f64bd8aSPaolo Bonzini } 14550fb6bd07SMichael Roth } else if ((opcode >= SVM_HCALL_BASE) && 14560fb6bd07SMichael Roth (opcode <= SVM_HCALL_MAX)) { 14570fb6bd07SMichael Roth spapr_hcall_fn fn = svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4]; 14580fb6bd07SMichael Roth 14590fb6bd07SMichael Roth if (fn) { 14600fb6bd07SMichael Roth return fn(cpu, spapr, opcode, args); 14610fb6bd07SMichael Roth } 14629f64bd8aSPaolo Bonzini } else if ((opcode >= KVMPPC_HCALL_BASE) && 14639f64bd8aSPaolo Bonzini (opcode <= KVMPPC_HCALL_MAX)) { 14649f64bd8aSPaolo Bonzini spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 14659f64bd8aSPaolo Bonzini 14669f64bd8aSPaolo Bonzini if (fn) { 14679f64bd8aSPaolo Bonzini return fn(cpu, spapr, opcode, args); 14689f64bd8aSPaolo Bonzini } 14699f64bd8aSPaolo Bonzini } 14709f64bd8aSPaolo Bonzini 1471aaf87c66SThomas Huth qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1472aaf87c66SThomas Huth opcode); 14739f64bd8aSPaolo Bonzini return H_FUNCTION; 14749f64bd8aSPaolo Bonzini } 14759f64bd8aSPaolo Bonzini 1476962104f0SLucas Mateus Castro (alqotel) #ifndef CONFIG_TCG 1477962104f0SLucas Mateus Castro (alqotel) static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr, 1478962104f0SLucas Mateus Castro (alqotel) target_ulong opcode, target_ulong *args) 1479962104f0SLucas Mateus Castro (alqotel) { 1480962104f0SLucas Mateus Castro (alqotel) g_assert_not_reached(); 1481962104f0SLucas Mateus Castro (alqotel) } 1482962104f0SLucas Mateus Castro (alqotel) 1483962104f0SLucas Mateus Castro (alqotel) static void hypercall_register_softmmu(void) 14849f64bd8aSPaolo Bonzini { 14859f64bd8aSPaolo Bonzini /* hcall-pft */ 1486962104f0SLucas Mateus Castro (alqotel) spapr_register_hypercall(H_ENTER, h_softmmu); 1487962104f0SLucas Mateus Castro (alqotel) spapr_register_hypercall(H_REMOVE, h_softmmu); 1488962104f0SLucas Mateus Castro (alqotel) spapr_register_hypercall(H_PROTECT, h_softmmu); 1489962104f0SLucas Mateus Castro (alqotel) spapr_register_hypercall(H_READ, h_softmmu); 14909f64bd8aSPaolo Bonzini 14919f64bd8aSPaolo Bonzini /* hcall-bulk */ 1492962104f0SLucas Mateus Castro (alqotel) spapr_register_hypercall(H_BULK_REMOVE, h_softmmu); 1493962104f0SLucas Mateus Castro (alqotel) } 1494962104f0SLucas Mateus Castro (alqotel) #else 1495962104f0SLucas Mateus Castro (alqotel) static void hypercall_register_softmmu(void) 1496962104f0SLucas Mateus Castro (alqotel) { 1497962104f0SLucas Mateus Castro (alqotel) /* DO NOTHING */ 1498962104f0SLucas Mateus Castro (alqotel) } 1499962104f0SLucas Mateus Castro (alqotel) #endif 1500962104f0SLucas Mateus Castro (alqotel) 1501*120f738aSNicholas Piggin /* TCG only */ 1502*120f738aSNicholas Piggin #define PRTS_MASK 0x1f 1503*120f738aSNicholas Piggin 1504*120f738aSNicholas Piggin static target_ulong h_set_ptbl(PowerPCCPU *cpu, 1505*120f738aSNicholas Piggin SpaprMachineState *spapr, 1506*120f738aSNicholas Piggin target_ulong opcode, 1507*120f738aSNicholas Piggin target_ulong *args) 1508*120f738aSNicholas Piggin { 1509*120f738aSNicholas Piggin target_ulong ptcr = args[0]; 1510*120f738aSNicholas Piggin 1511*120f738aSNicholas Piggin if (!spapr_get_cap(spapr, SPAPR_CAP_NESTED_KVM_HV)) { 1512*120f738aSNicholas Piggin return H_FUNCTION; 1513*120f738aSNicholas Piggin } 1514*120f738aSNicholas Piggin 1515*120f738aSNicholas Piggin if ((ptcr & PRTS_MASK) + 12 - 4 > 12) { 1516*120f738aSNicholas Piggin return H_PARAMETER; 1517*120f738aSNicholas Piggin } 1518*120f738aSNicholas Piggin 1519*120f738aSNicholas Piggin spapr->nested_ptcr = ptcr; /* Save new partition table */ 1520*120f738aSNicholas Piggin 1521*120f738aSNicholas Piggin return H_SUCCESS; 1522*120f738aSNicholas Piggin } 1523*120f738aSNicholas Piggin 1524*120f738aSNicholas Piggin static target_ulong h_tlb_invalidate(PowerPCCPU *cpu, 1525*120f738aSNicholas Piggin SpaprMachineState *spapr, 1526*120f738aSNicholas Piggin target_ulong opcode, 1527*120f738aSNicholas Piggin target_ulong *args) 1528*120f738aSNicholas Piggin { 1529*120f738aSNicholas Piggin /* 1530*120f738aSNicholas Piggin * The spapr virtual hypervisor nested HV implementation retains no L2 1531*120f738aSNicholas Piggin * translation state except for TLB. And the TLB is always invalidated 1532*120f738aSNicholas Piggin * across L1<->L2 transitions, so nothing is required here. 1533*120f738aSNicholas Piggin */ 1534*120f738aSNicholas Piggin 1535*120f738aSNicholas Piggin return H_SUCCESS; 1536*120f738aSNicholas Piggin } 1537*120f738aSNicholas Piggin 1538*120f738aSNicholas Piggin static target_ulong h_copy_tofrom_guest(PowerPCCPU *cpu, 1539*120f738aSNicholas Piggin SpaprMachineState *spapr, 1540*120f738aSNicholas Piggin target_ulong opcode, 1541*120f738aSNicholas Piggin target_ulong *args) 1542*120f738aSNicholas Piggin { 1543*120f738aSNicholas Piggin /* 1544*120f738aSNicholas Piggin * This HCALL is not required, L1 KVM will take a slow path and walk the 1545*120f738aSNicholas Piggin * page tables manually to do the data copy. 1546*120f738aSNicholas Piggin */ 1547*120f738aSNicholas Piggin return H_FUNCTION; 1548*120f738aSNicholas Piggin } 1549*120f738aSNicholas Piggin 1550*120f738aSNicholas Piggin /* 1551*120f738aSNicholas Piggin * When this handler returns, the environment is switched to the L2 guest 1552*120f738aSNicholas Piggin * and TCG begins running that. spapr_exit_nested() performs the switch from 1553*120f738aSNicholas Piggin * L2 back to L1 and returns from the H_ENTER_NESTED hcall. 1554*120f738aSNicholas Piggin */ 1555*120f738aSNicholas Piggin static target_ulong h_enter_nested(PowerPCCPU *cpu, 1556*120f738aSNicholas Piggin SpaprMachineState *spapr, 1557*120f738aSNicholas Piggin target_ulong opcode, 1558*120f738aSNicholas Piggin target_ulong *args) 1559*120f738aSNicholas Piggin { 1560*120f738aSNicholas Piggin PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 1561*120f738aSNicholas Piggin CPUState *cs = CPU(cpu); 1562*120f738aSNicholas Piggin CPUPPCState *env = &cpu->env; 1563*120f738aSNicholas Piggin SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1564*120f738aSNicholas Piggin target_ulong hv_ptr = args[0]; 1565*120f738aSNicholas Piggin target_ulong regs_ptr = args[1]; 1566*120f738aSNicholas Piggin target_ulong hdec, now = cpu_ppc_load_tbl(env); 1567*120f738aSNicholas Piggin target_ulong lpcr, lpcr_mask; 1568*120f738aSNicholas Piggin struct kvmppc_hv_guest_state *hvstate; 1569*120f738aSNicholas Piggin struct kvmppc_hv_guest_state hv_state; 1570*120f738aSNicholas Piggin struct kvmppc_pt_regs *regs; 1571*120f738aSNicholas Piggin hwaddr len; 1572*120f738aSNicholas Piggin uint64_t cr; 1573*120f738aSNicholas Piggin int i; 1574*120f738aSNicholas Piggin 1575*120f738aSNicholas Piggin if (spapr->nested_ptcr == 0) { 1576*120f738aSNicholas Piggin return H_NOT_AVAILABLE; 1577*120f738aSNicholas Piggin } 1578*120f738aSNicholas Piggin 1579*120f738aSNicholas Piggin len = sizeof(*hvstate); 1580*120f738aSNicholas Piggin hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, false, 1581*120f738aSNicholas Piggin MEMTXATTRS_UNSPECIFIED); 1582*120f738aSNicholas Piggin if (len != sizeof(*hvstate)) { 1583*120f738aSNicholas Piggin address_space_unmap(CPU(cpu)->as, hvstate, len, 0, false); 1584*120f738aSNicholas Piggin return H_PARAMETER; 1585*120f738aSNicholas Piggin } 1586*120f738aSNicholas Piggin 1587*120f738aSNicholas Piggin memcpy(&hv_state, hvstate, len); 1588*120f738aSNicholas Piggin 1589*120f738aSNicholas Piggin address_space_unmap(CPU(cpu)->as, hvstate, len, len, false); 1590*120f738aSNicholas Piggin 1591*120f738aSNicholas Piggin /* 1592*120f738aSNicholas Piggin * We accept versions 1 and 2. Version 2 fields are unused because TCG 1593*120f738aSNicholas Piggin * does not implement DAWR*. 1594*120f738aSNicholas Piggin */ 1595*120f738aSNicholas Piggin if (hv_state.version > HV_GUEST_STATE_VERSION) { 1596*120f738aSNicholas Piggin return H_PARAMETER; 1597*120f738aSNicholas Piggin } 1598*120f738aSNicholas Piggin 1599*120f738aSNicholas Piggin spapr_cpu->nested_host_state = g_try_malloc(sizeof(CPUPPCState)); 1600*120f738aSNicholas Piggin if (!spapr_cpu->nested_host_state) { 1601*120f738aSNicholas Piggin return H_NO_MEM; 1602*120f738aSNicholas Piggin } 1603*120f738aSNicholas Piggin 1604*120f738aSNicholas Piggin memcpy(spapr_cpu->nested_host_state, env, sizeof(CPUPPCState)); 1605*120f738aSNicholas Piggin 1606*120f738aSNicholas Piggin len = sizeof(*regs); 1607*120f738aSNicholas Piggin regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, false, 1608*120f738aSNicholas Piggin MEMTXATTRS_UNSPECIFIED); 1609*120f738aSNicholas Piggin if (!regs || len != sizeof(*regs)) { 1610*120f738aSNicholas Piggin address_space_unmap(CPU(cpu)->as, regs, len, 0, false); 1611*120f738aSNicholas Piggin g_free(spapr_cpu->nested_host_state); 1612*120f738aSNicholas Piggin return H_P2; 1613*120f738aSNicholas Piggin } 1614*120f738aSNicholas Piggin 1615*120f738aSNicholas Piggin len = sizeof(env->gpr); 1616*120f738aSNicholas Piggin assert(len == sizeof(regs->gpr)); 1617*120f738aSNicholas Piggin memcpy(env->gpr, regs->gpr, len); 1618*120f738aSNicholas Piggin 1619*120f738aSNicholas Piggin env->lr = regs->link; 1620*120f738aSNicholas Piggin env->ctr = regs->ctr; 1621*120f738aSNicholas Piggin cpu_write_xer(env, regs->xer); 1622*120f738aSNicholas Piggin 1623*120f738aSNicholas Piggin cr = regs->ccr; 1624*120f738aSNicholas Piggin for (i = 7; i >= 0; i--) { 1625*120f738aSNicholas Piggin env->crf[i] = cr & 15; 1626*120f738aSNicholas Piggin cr >>= 4; 1627*120f738aSNicholas Piggin } 1628*120f738aSNicholas Piggin 1629*120f738aSNicholas Piggin env->msr = regs->msr; 1630*120f738aSNicholas Piggin env->nip = regs->nip; 1631*120f738aSNicholas Piggin 1632*120f738aSNicholas Piggin address_space_unmap(CPU(cpu)->as, regs, len, len, false); 1633*120f738aSNicholas Piggin 1634*120f738aSNicholas Piggin env->cfar = hv_state.cfar; 1635*120f738aSNicholas Piggin 1636*120f738aSNicholas Piggin assert(env->spr[SPR_LPIDR] == 0); 1637*120f738aSNicholas Piggin env->spr[SPR_LPIDR] = hv_state.lpid; 1638*120f738aSNicholas Piggin 1639*120f738aSNicholas Piggin lpcr_mask = LPCR_DPFD | LPCR_ILE | LPCR_AIL | LPCR_LD | LPCR_MER; 1640*120f738aSNicholas Piggin lpcr = (env->spr[SPR_LPCR] & ~lpcr_mask) | (hv_state.lpcr & lpcr_mask); 1641*120f738aSNicholas Piggin lpcr |= LPCR_HR | LPCR_UPRT | LPCR_GTSE | LPCR_HVICE | LPCR_HDICE; 1642*120f738aSNicholas Piggin lpcr &= ~LPCR_LPES0; 1643*120f738aSNicholas Piggin env->spr[SPR_LPCR] = lpcr & pcc->lpcr_mask; 1644*120f738aSNicholas Piggin 1645*120f738aSNicholas Piggin env->spr[SPR_PCR] = hv_state.pcr; 1646*120f738aSNicholas Piggin /* hv_state.amor is not used */ 1647*120f738aSNicholas Piggin env->spr[SPR_DPDES] = hv_state.dpdes; 1648*120f738aSNicholas Piggin env->spr[SPR_HFSCR] = hv_state.hfscr; 1649*120f738aSNicholas Piggin hdec = hv_state.hdec_expiry - now; 1650*120f738aSNicholas Piggin spapr_cpu->nested_tb_offset = hv_state.tb_offset; 1651*120f738aSNicholas Piggin /* TCG does not implement DAWR*, CIABR, PURR, SPURR, IC, VTB, HEIR SPRs*/ 1652*120f738aSNicholas Piggin env->spr[SPR_SRR0] = hv_state.srr0; 1653*120f738aSNicholas Piggin env->spr[SPR_SRR1] = hv_state.srr1; 1654*120f738aSNicholas Piggin env->spr[SPR_SPRG0] = hv_state.sprg[0]; 1655*120f738aSNicholas Piggin env->spr[SPR_SPRG1] = hv_state.sprg[1]; 1656*120f738aSNicholas Piggin env->spr[SPR_SPRG2] = hv_state.sprg[2]; 1657*120f738aSNicholas Piggin env->spr[SPR_SPRG3] = hv_state.sprg[3]; 1658*120f738aSNicholas Piggin env->spr[SPR_BOOKS_PID] = hv_state.pidr; 1659*120f738aSNicholas Piggin env->spr[SPR_PPR] = hv_state.ppr; 1660*120f738aSNicholas Piggin 1661*120f738aSNicholas Piggin cpu_ppc_hdecr_init(env); 1662*120f738aSNicholas Piggin cpu_ppc_store_hdecr(env, hdec); 1663*120f738aSNicholas Piggin 1664*120f738aSNicholas Piggin /* 1665*120f738aSNicholas Piggin * The hv_state.vcpu_token is not needed. It is used by the KVM 1666*120f738aSNicholas Piggin * implementation to remember which L2 vCPU last ran on which physical 1667*120f738aSNicholas Piggin * CPU so as to invalidate process scope translations if it is moved 1668*120f738aSNicholas Piggin * between physical CPUs. For now TLBs are always flushed on L1<->L2 1669*120f738aSNicholas Piggin * transitions so this is not a problem. 1670*120f738aSNicholas Piggin * 1671*120f738aSNicholas Piggin * Could validate that the same vcpu_token does not attempt to run on 1672*120f738aSNicholas Piggin * different L1 vCPUs at the same time, but that would be a L1 KVM bug 1673*120f738aSNicholas Piggin * and it's not obviously worth a new data structure to do it. 1674*120f738aSNicholas Piggin */ 1675*120f738aSNicholas Piggin 1676*120f738aSNicholas Piggin env->tb_env->tb_offset += spapr_cpu->nested_tb_offset; 1677*120f738aSNicholas Piggin spapr_cpu->in_nested = true; 1678*120f738aSNicholas Piggin 1679*120f738aSNicholas Piggin hreg_compute_hflags(env); 1680*120f738aSNicholas Piggin tlb_flush(cs); 1681*120f738aSNicholas Piggin env->reserve_addr = -1; /* Reset the reservation */ 1682*120f738aSNicholas Piggin 1683*120f738aSNicholas Piggin /* 1684*120f738aSNicholas Piggin * The spapr hcall helper sets env->gpr[3] to the return value, but at 1685*120f738aSNicholas Piggin * this point the L1 is not returning from the hcall but rather we 1686*120f738aSNicholas Piggin * start running the L2, so r3 must not be clobbered, so return env->gpr[3] 1687*120f738aSNicholas Piggin * to leave it unchanged. 1688*120f738aSNicholas Piggin */ 1689*120f738aSNicholas Piggin return env->gpr[3]; 1690*120f738aSNicholas Piggin } 1691*120f738aSNicholas Piggin 1692*120f738aSNicholas Piggin void spapr_exit_nested(PowerPCCPU *cpu, int excp) 1693*120f738aSNicholas Piggin { 1694*120f738aSNicholas Piggin CPUState *cs = CPU(cpu); 1695*120f738aSNicholas Piggin CPUPPCState *env = &cpu->env; 1696*120f738aSNicholas Piggin SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1697*120f738aSNicholas Piggin target_ulong r3_return = env->excp_vectors[excp]; /* hcall return value */ 1698*120f738aSNicholas Piggin target_ulong hv_ptr = spapr_cpu->nested_host_state->gpr[4]; 1699*120f738aSNicholas Piggin target_ulong regs_ptr = spapr_cpu->nested_host_state->gpr[5]; 1700*120f738aSNicholas Piggin struct kvmppc_hv_guest_state *hvstate; 1701*120f738aSNicholas Piggin struct kvmppc_pt_regs *regs; 1702*120f738aSNicholas Piggin hwaddr len; 1703*120f738aSNicholas Piggin uint64_t cr; 1704*120f738aSNicholas Piggin int i; 1705*120f738aSNicholas Piggin 1706*120f738aSNicholas Piggin assert(spapr_cpu->in_nested); 1707*120f738aSNicholas Piggin 1708*120f738aSNicholas Piggin cpu_ppc_hdecr_exit(env); 1709*120f738aSNicholas Piggin 1710*120f738aSNicholas Piggin len = sizeof(*hvstate); 1711*120f738aSNicholas Piggin hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, true, 1712*120f738aSNicholas Piggin MEMTXATTRS_UNSPECIFIED); 1713*120f738aSNicholas Piggin if (len != sizeof(*hvstate)) { 1714*120f738aSNicholas Piggin address_space_unmap(CPU(cpu)->as, hvstate, len, 0, true); 1715*120f738aSNicholas Piggin r3_return = H_PARAMETER; 1716*120f738aSNicholas Piggin goto out_restore_l1; 1717*120f738aSNicholas Piggin } 1718*120f738aSNicholas Piggin 1719*120f738aSNicholas Piggin hvstate->cfar = env->cfar; 1720*120f738aSNicholas Piggin hvstate->lpcr = env->spr[SPR_LPCR]; 1721*120f738aSNicholas Piggin hvstate->pcr = env->spr[SPR_PCR]; 1722*120f738aSNicholas Piggin hvstate->dpdes = env->spr[SPR_DPDES]; 1723*120f738aSNicholas Piggin hvstate->hfscr = env->spr[SPR_HFSCR]; 1724*120f738aSNicholas Piggin 1725*120f738aSNicholas Piggin if (excp == POWERPC_EXCP_HDSI) { 1726*120f738aSNicholas Piggin hvstate->hdar = env->spr[SPR_HDAR]; 1727*120f738aSNicholas Piggin hvstate->hdsisr = env->spr[SPR_HDSISR]; 1728*120f738aSNicholas Piggin hvstate->asdr = env->spr[SPR_ASDR]; 1729*120f738aSNicholas Piggin } else if (excp == POWERPC_EXCP_HISI) { 1730*120f738aSNicholas Piggin hvstate->asdr = env->spr[SPR_ASDR]; 1731*120f738aSNicholas Piggin } 1732*120f738aSNicholas Piggin 1733*120f738aSNicholas Piggin /* HEIR should be implemented for HV mode and saved here. */ 1734*120f738aSNicholas Piggin hvstate->srr0 = env->spr[SPR_SRR0]; 1735*120f738aSNicholas Piggin hvstate->srr1 = env->spr[SPR_SRR1]; 1736*120f738aSNicholas Piggin hvstate->sprg[0] = env->spr[SPR_SPRG0]; 1737*120f738aSNicholas Piggin hvstate->sprg[1] = env->spr[SPR_SPRG1]; 1738*120f738aSNicholas Piggin hvstate->sprg[2] = env->spr[SPR_SPRG2]; 1739*120f738aSNicholas Piggin hvstate->sprg[3] = env->spr[SPR_SPRG3]; 1740*120f738aSNicholas Piggin hvstate->pidr = env->spr[SPR_BOOKS_PID]; 1741*120f738aSNicholas Piggin hvstate->ppr = env->spr[SPR_PPR]; 1742*120f738aSNicholas Piggin 1743*120f738aSNicholas Piggin /* Is it okay to specify write length larger than actual data written? */ 1744*120f738aSNicholas Piggin address_space_unmap(CPU(cpu)->as, hvstate, len, len, true); 1745*120f738aSNicholas Piggin 1746*120f738aSNicholas Piggin len = sizeof(*regs); 1747*120f738aSNicholas Piggin regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, true, 1748*120f738aSNicholas Piggin MEMTXATTRS_UNSPECIFIED); 1749*120f738aSNicholas Piggin if (!regs || len != sizeof(*regs)) { 1750*120f738aSNicholas Piggin address_space_unmap(CPU(cpu)->as, regs, len, 0, true); 1751*120f738aSNicholas Piggin r3_return = H_P2; 1752*120f738aSNicholas Piggin goto out_restore_l1; 1753*120f738aSNicholas Piggin } 1754*120f738aSNicholas Piggin 1755*120f738aSNicholas Piggin len = sizeof(env->gpr); 1756*120f738aSNicholas Piggin assert(len == sizeof(regs->gpr)); 1757*120f738aSNicholas Piggin memcpy(regs->gpr, env->gpr, len); 1758*120f738aSNicholas Piggin 1759*120f738aSNicholas Piggin regs->link = env->lr; 1760*120f738aSNicholas Piggin regs->ctr = env->ctr; 1761*120f738aSNicholas Piggin regs->xer = cpu_read_xer(env); 1762*120f738aSNicholas Piggin 1763*120f738aSNicholas Piggin cr = 0; 1764*120f738aSNicholas Piggin for (i = 0; i < 8; i++) { 1765*120f738aSNicholas Piggin cr |= (env->crf[i] & 15) << (4 * (7 - i)); 1766*120f738aSNicholas Piggin } 1767*120f738aSNicholas Piggin regs->ccr = cr; 1768*120f738aSNicholas Piggin 1769*120f738aSNicholas Piggin if (excp == POWERPC_EXCP_MCHECK || 1770*120f738aSNicholas Piggin excp == POWERPC_EXCP_RESET || 1771*120f738aSNicholas Piggin excp == POWERPC_EXCP_SYSCALL) { 1772*120f738aSNicholas Piggin regs->nip = env->spr[SPR_SRR0]; 1773*120f738aSNicholas Piggin regs->msr = env->spr[SPR_SRR1] & env->msr_mask; 1774*120f738aSNicholas Piggin } else { 1775*120f738aSNicholas Piggin regs->nip = env->spr[SPR_HSRR0]; 1776*120f738aSNicholas Piggin regs->msr = env->spr[SPR_HSRR1] & env->msr_mask; 1777*120f738aSNicholas Piggin } 1778*120f738aSNicholas Piggin 1779*120f738aSNicholas Piggin /* Is it okay to specify write length larger than actual data written? */ 1780*120f738aSNicholas Piggin address_space_unmap(CPU(cpu)->as, regs, len, len, true); 1781*120f738aSNicholas Piggin 1782*120f738aSNicholas Piggin out_restore_l1: 1783*120f738aSNicholas Piggin memcpy(env->gpr, spapr_cpu->nested_host_state->gpr, sizeof(env->gpr)); 1784*120f738aSNicholas Piggin env->lr = spapr_cpu->nested_host_state->lr; 1785*120f738aSNicholas Piggin env->ctr = spapr_cpu->nested_host_state->ctr; 1786*120f738aSNicholas Piggin memcpy(env->crf, spapr_cpu->nested_host_state->crf, sizeof(env->crf)); 1787*120f738aSNicholas Piggin env->cfar = spapr_cpu->nested_host_state->cfar; 1788*120f738aSNicholas Piggin env->xer = spapr_cpu->nested_host_state->xer; 1789*120f738aSNicholas Piggin env->so = spapr_cpu->nested_host_state->so; 1790*120f738aSNicholas Piggin env->ov = spapr_cpu->nested_host_state->ov; 1791*120f738aSNicholas Piggin env->ov32 = spapr_cpu->nested_host_state->ov32; 1792*120f738aSNicholas Piggin env->ca32 = spapr_cpu->nested_host_state->ca32; 1793*120f738aSNicholas Piggin env->msr = spapr_cpu->nested_host_state->msr; 1794*120f738aSNicholas Piggin env->nip = spapr_cpu->nested_host_state->nip; 1795*120f738aSNicholas Piggin 1796*120f738aSNicholas Piggin assert(env->spr[SPR_LPIDR] != 0); 1797*120f738aSNicholas Piggin env->spr[SPR_LPCR] = spapr_cpu->nested_host_state->spr[SPR_LPCR]; 1798*120f738aSNicholas Piggin env->spr[SPR_LPIDR] = spapr_cpu->nested_host_state->spr[SPR_LPIDR]; 1799*120f738aSNicholas Piggin env->spr[SPR_PCR] = spapr_cpu->nested_host_state->spr[SPR_PCR]; 1800*120f738aSNicholas Piggin env->spr[SPR_DPDES] = 0; 1801*120f738aSNicholas Piggin env->spr[SPR_HFSCR] = spapr_cpu->nested_host_state->spr[SPR_HFSCR]; 1802*120f738aSNicholas Piggin env->spr[SPR_SRR0] = spapr_cpu->nested_host_state->spr[SPR_SRR0]; 1803*120f738aSNicholas Piggin env->spr[SPR_SRR1] = spapr_cpu->nested_host_state->spr[SPR_SRR1]; 1804*120f738aSNicholas Piggin env->spr[SPR_SPRG0] = spapr_cpu->nested_host_state->spr[SPR_SPRG0]; 1805*120f738aSNicholas Piggin env->spr[SPR_SPRG1] = spapr_cpu->nested_host_state->spr[SPR_SPRG1]; 1806*120f738aSNicholas Piggin env->spr[SPR_SPRG2] = spapr_cpu->nested_host_state->spr[SPR_SPRG2]; 1807*120f738aSNicholas Piggin env->spr[SPR_SPRG3] = spapr_cpu->nested_host_state->spr[SPR_SPRG3]; 1808*120f738aSNicholas Piggin env->spr[SPR_BOOKS_PID] = spapr_cpu->nested_host_state->spr[SPR_BOOKS_PID]; 1809*120f738aSNicholas Piggin env->spr[SPR_PPR] = spapr_cpu->nested_host_state->spr[SPR_PPR]; 1810*120f738aSNicholas Piggin 1811*120f738aSNicholas Piggin /* 1812*120f738aSNicholas Piggin * Return the interrupt vector address from H_ENTER_NESTED to the L1 1813*120f738aSNicholas Piggin * (or error code). 1814*120f738aSNicholas Piggin */ 1815*120f738aSNicholas Piggin env->gpr[3] = r3_return; 1816*120f738aSNicholas Piggin 1817*120f738aSNicholas Piggin env->tb_env->tb_offset -= spapr_cpu->nested_tb_offset; 1818*120f738aSNicholas Piggin spapr_cpu->in_nested = false; 1819*120f738aSNicholas Piggin 1820*120f738aSNicholas Piggin hreg_compute_hflags(env); 1821*120f738aSNicholas Piggin tlb_flush(cs); 1822*120f738aSNicholas Piggin env->reserve_addr = -1; /* Reset the reservation */ 1823*120f738aSNicholas Piggin 1824*120f738aSNicholas Piggin g_free(spapr_cpu->nested_host_state); 1825*120f738aSNicholas Piggin spapr_cpu->nested_host_state = NULL; 1826*120f738aSNicholas Piggin } 1827*120f738aSNicholas Piggin 1828962104f0SLucas Mateus Castro (alqotel) static void hypercall_register_types(void) 1829962104f0SLucas Mateus Castro (alqotel) { 1830962104f0SLucas Mateus Castro (alqotel) hypercall_register_softmmu(); 18319f64bd8aSPaolo Bonzini 183230f4b05bSDavid Gibson /* hcall-hpt-resize */ 183330f4b05bSDavid Gibson spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 183430f4b05bSDavid Gibson spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 183530f4b05bSDavid Gibson 18369f64bd8aSPaolo Bonzini /* hcall-splpar */ 18379f64bd8aSPaolo Bonzini spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 18389f64bd8aSPaolo Bonzini spapr_register_hypercall(H_CEDE, h_cede); 1839e8ce0e40SNicholas Piggin spapr_register_hypercall(H_CONFER, h_confer); 18403a6e6224SNicholas Piggin spapr_register_hypercall(H_PROD, h_prod); 18413a6e6224SNicholas Piggin 184210741314SNicholas Piggin /* hcall-join */ 184310741314SNicholas Piggin spapr_register_hypercall(H_JOIN, h_join); 184410741314SNicholas Piggin 18451c7ad77eSNicholas Piggin spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 18469f64bd8aSPaolo Bonzini 1847423576f7SThomas Huth /* processor register resource access h-calls */ 1848423576f7SThomas Huth spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1849af08a58fSThomas Huth spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1850e49ff266SThomas Huth spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 18513240dd9aSThomas Huth spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1852423576f7SThomas Huth spapr_register_hypercall(H_SET_MODE, h_set_mode); 1853423576f7SThomas Huth 1854d77a98b0SSuraj Jitindar Singh /* In Memory Table MMU h-calls */ 1855d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1856d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1857d77a98b0SSuraj Jitindar Singh spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1858d77a98b0SSuraj Jitindar Singh 1859c59704b2SSuraj Jitindar Singh /* hcall-get-cpu-characteristics */ 1860c59704b2SSuraj Jitindar Singh spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, 1861c59704b2SSuraj Jitindar Singh h_get_cpu_characteristics); 1862c59704b2SSuraj Jitindar Singh 18639f64bd8aSPaolo Bonzini /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 18649f64bd8aSPaolo Bonzini * here between the "CI" and the "CACHE" variants, they will use whatever 18659f64bd8aSPaolo Bonzini * mapping attributes qemu is using. When using KVM, the kernel will 18669f64bd8aSPaolo Bonzini * enforce the attributes more strongly 18679f64bd8aSPaolo Bonzini */ 18689f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 18699f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 18709f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 18719f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 18729f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 18739f64bd8aSPaolo Bonzini spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 18749f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 18759f64bd8aSPaolo Bonzini 18769f64bd8aSPaolo Bonzini /* qemu/KVM-PPC specific hcalls */ 18779f64bd8aSPaolo Bonzini spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 187842561bf2SAnton Blanchard 18792a6593cbSAlexey Kardashevskiy /* ibm,client-architecture-support support */ 18802a6593cbSAlexey Kardashevskiy spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1881c24ba3d0SLaurent Vivier 1882fea35ca4SAlexey Kardashevskiy spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); 1883*120f738aSNicholas Piggin 1884*120f738aSNicholas Piggin spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl); 1885*120f738aSNicholas Piggin spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested); 1886*120f738aSNicholas Piggin spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate); 1887*120f738aSNicholas Piggin spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_guest); 18889f64bd8aSPaolo Bonzini } 18899f64bd8aSPaolo Bonzini 18909f64bd8aSPaolo Bonzini type_init(hypercall_register_types) 1891