1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * RTAS events handling 5 * 6 * Copyright (c) 2012 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qapi/error.h" 30 #include "cpu.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/runstate.h" 33 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/spapr.h" 36 #include "hw/ppc/spapr_vio.h" 37 #include "hw/pci/pci.h" 38 #include "hw/irq.h" 39 #include "hw/pci-host/spapr.h" 40 #include "hw/ppc/spapr_drc.h" 41 #include "qemu/help_option.h" 42 #include "qemu/bcd.h" 43 #include "qemu/main-loop.h" 44 #include "hw/ppc/spapr_ovec.h" 45 #include <libfdt.h> 46 #include "migration/blocker.h" 47 48 #define RTAS_LOG_VERSION_MASK 0xff000000 49 #define RTAS_LOG_VERSION_6 0x06000000 50 #define RTAS_LOG_SEVERITY_MASK 0x00e00000 51 #define RTAS_LOG_SEVERITY_ALREADY_REPORTED 0x00c00000 52 #define RTAS_LOG_SEVERITY_FATAL 0x00a00000 53 #define RTAS_LOG_SEVERITY_ERROR 0x00800000 54 #define RTAS_LOG_SEVERITY_ERROR_SYNC 0x00600000 55 #define RTAS_LOG_SEVERITY_WARNING 0x00400000 56 #define RTAS_LOG_SEVERITY_EVENT 0x00200000 57 #define RTAS_LOG_SEVERITY_NO_ERROR 0x00000000 58 #define RTAS_LOG_DISPOSITION_MASK 0x00180000 59 #define RTAS_LOG_DISPOSITION_FULLY_RECOVERED 0x00000000 60 #define RTAS_LOG_DISPOSITION_LIMITED_RECOVERY 0x00080000 61 #define RTAS_LOG_DISPOSITION_NOT_RECOVERED 0x00100000 62 #define RTAS_LOG_OPTIONAL_PART_PRESENT 0x00040000 63 #define RTAS_LOG_INITIATOR_MASK 0x0000f000 64 #define RTAS_LOG_INITIATOR_UNKNOWN 0x00000000 65 #define RTAS_LOG_INITIATOR_CPU 0x00001000 66 #define RTAS_LOG_INITIATOR_PCI 0x00002000 67 #define RTAS_LOG_INITIATOR_MEMORY 0x00004000 68 #define RTAS_LOG_INITIATOR_HOTPLUG 0x00006000 69 #define RTAS_LOG_TARGET_MASK 0x00000f00 70 #define RTAS_LOG_TARGET_UNKNOWN 0x00000000 71 #define RTAS_LOG_TARGET_CPU 0x00000100 72 #define RTAS_LOG_TARGET_PCI 0x00000200 73 #define RTAS_LOG_TARGET_MEMORY 0x00000400 74 #define RTAS_LOG_TARGET_HOTPLUG 0x00000600 75 #define RTAS_LOG_TYPE_MASK 0x000000ff 76 #define RTAS_LOG_TYPE_OTHER 0x00000000 77 #define RTAS_LOG_TYPE_RETRY 0x00000001 78 #define RTAS_LOG_TYPE_TCE_ERR 0x00000002 79 #define RTAS_LOG_TYPE_INTERN_DEV_FAIL 0x00000003 80 #define RTAS_LOG_TYPE_TIMEOUT 0x00000004 81 #define RTAS_LOG_TYPE_DATA_PARITY 0x00000005 82 #define RTAS_LOG_TYPE_ADDR_PARITY 0x00000006 83 #define RTAS_LOG_TYPE_CACHE_PARITY 0x00000007 84 #define RTAS_LOG_TYPE_ADDR_INVALID 0x00000008 85 #define RTAS_LOG_TYPE_ECC_UNCORR 0x00000009 86 #define RTAS_LOG_TYPE_ECC_CORR 0x0000000a 87 #define RTAS_LOG_TYPE_EPOW 0x00000040 88 #define RTAS_LOG_TYPE_HOTPLUG 0x000000e5 89 90 struct rtas_error_log { 91 uint32_t summary; 92 uint32_t extended_length; 93 } QEMU_PACKED; 94 95 struct rtas_event_log_v6 { 96 uint8_t b0; 97 #define RTAS_LOG_V6_B0_VALID 0x80 98 #define RTAS_LOG_V6_B0_UNRECOVERABLE_ERROR 0x40 99 #define RTAS_LOG_V6_B0_RECOVERABLE_ERROR 0x20 100 #define RTAS_LOG_V6_B0_DEGRADED_OPERATION 0x10 101 #define RTAS_LOG_V6_B0_PREDICTIVE_ERROR 0x08 102 #define RTAS_LOG_V6_B0_NEW_LOG 0x04 103 #define RTAS_LOG_V6_B0_BIGENDIAN 0x02 104 uint8_t _resv1; 105 uint8_t b2; 106 #define RTAS_LOG_V6_B2_POWERPC_FORMAT 0x80 107 #define RTAS_LOG_V6_B2_LOG_FORMAT_MASK 0x0f 108 #define RTAS_LOG_V6_B2_LOG_FORMAT_PLATFORM_EVENT 0x0e 109 uint8_t _resv2[9]; 110 uint32_t company; 111 #define RTAS_LOG_V6_COMPANY_IBM 0x49424d00 /* IBM<null> */ 112 } QEMU_PACKED; 113 114 struct rtas_event_log_v6_section_header { 115 uint16_t section_id; 116 uint16_t section_length; 117 uint8_t section_version; 118 uint8_t section_subtype; 119 uint16_t creator_component_id; 120 } QEMU_PACKED; 121 122 struct rtas_event_log_v6_maina { 123 #define RTAS_LOG_V6_SECTION_ID_MAINA 0x5048 /* PH */ 124 struct rtas_event_log_v6_section_header hdr; 125 uint32_t creation_date; /* BCD: YYYYMMDD */ 126 uint32_t creation_time; /* BCD: HHMMSS00 */ 127 uint8_t _platform1[8]; 128 char creator_id; 129 uint8_t _resv1[2]; 130 uint8_t section_count; 131 uint8_t _resv2[4]; 132 uint8_t _platform2[8]; 133 uint32_t plid; 134 uint8_t _platform3[4]; 135 } QEMU_PACKED; 136 137 struct rtas_event_log_v6_mainb { 138 #define RTAS_LOG_V6_SECTION_ID_MAINB 0x5548 /* UH */ 139 struct rtas_event_log_v6_section_header hdr; 140 uint8_t subsystem_id; 141 uint8_t _platform1; 142 uint8_t event_severity; 143 uint8_t event_subtype; 144 uint8_t _platform2[4]; 145 uint8_t _resv1[2]; 146 uint16_t action_flags; 147 uint8_t _resv2[4]; 148 } QEMU_PACKED; 149 150 struct rtas_event_log_v6_epow { 151 #define RTAS_LOG_V6_SECTION_ID_EPOW 0x4550 /* EP */ 152 struct rtas_event_log_v6_section_header hdr; 153 uint8_t sensor_value; 154 #define RTAS_LOG_V6_EPOW_ACTION_RESET 0 155 #define RTAS_LOG_V6_EPOW_ACTION_WARN_COOLING 1 156 #define RTAS_LOG_V6_EPOW_ACTION_WARN_POWER 2 157 #define RTAS_LOG_V6_EPOW_ACTION_SYSTEM_SHUTDOWN 3 158 #define RTAS_LOG_V6_EPOW_ACTION_SYSTEM_HALT 4 159 #define RTAS_LOG_V6_EPOW_ACTION_MAIN_ENCLOSURE 5 160 #define RTAS_LOG_V6_EPOW_ACTION_POWER_OFF 7 161 uint8_t event_modifier; 162 #define RTAS_LOG_V6_EPOW_MODIFIER_NORMAL 1 163 #define RTAS_LOG_V6_EPOW_MODIFIER_ON_UPS 2 164 #define RTAS_LOG_V6_EPOW_MODIFIER_CRITICAL 3 165 #define RTAS_LOG_V6_EPOW_MODIFIER_TEMPERATURE 4 166 uint8_t extended_modifier; 167 #define RTAS_LOG_V6_EPOW_XMODIFIER_SYSTEM_WIDE 0 168 #define RTAS_LOG_V6_EPOW_XMODIFIER_PARTITION_SPECIFIC 1 169 uint8_t _resv; 170 uint64_t reason_code; 171 } QEMU_PACKED; 172 173 struct epow_extended_log { 174 struct rtas_event_log_v6 v6hdr; 175 struct rtas_event_log_v6_maina maina; 176 struct rtas_event_log_v6_mainb mainb; 177 struct rtas_event_log_v6_epow epow; 178 } QEMU_PACKED; 179 180 union drc_identifier { 181 uint32_t index; 182 uint32_t count; 183 struct { 184 uint32_t count; 185 uint32_t index; 186 } count_indexed; 187 char name[1]; 188 } QEMU_PACKED; 189 190 struct rtas_event_log_v6_hp { 191 #define RTAS_LOG_V6_SECTION_ID_HOTPLUG 0x4850 /* HP */ 192 struct rtas_event_log_v6_section_header hdr; 193 uint8_t hotplug_type; 194 #define RTAS_LOG_V6_HP_TYPE_CPU 1 195 #define RTAS_LOG_V6_HP_TYPE_MEMORY 2 196 #define RTAS_LOG_V6_HP_TYPE_SLOT 3 197 #define RTAS_LOG_V6_HP_TYPE_PHB 4 198 #define RTAS_LOG_V6_HP_TYPE_PCI 5 199 uint8_t hotplug_action; 200 #define RTAS_LOG_V6_HP_ACTION_ADD 1 201 #define RTAS_LOG_V6_HP_ACTION_REMOVE 2 202 uint8_t hotplug_identifier; 203 #define RTAS_LOG_V6_HP_ID_DRC_NAME 1 204 #define RTAS_LOG_V6_HP_ID_DRC_INDEX 2 205 #define RTAS_LOG_V6_HP_ID_DRC_COUNT 3 206 #define RTAS_LOG_V6_HP_ID_DRC_COUNT_INDEXED 4 207 uint8_t reserved; 208 union drc_identifier drc_id; 209 } QEMU_PACKED; 210 211 struct hp_extended_log { 212 struct rtas_event_log_v6 v6hdr; 213 struct rtas_event_log_v6_maina maina; 214 struct rtas_event_log_v6_mainb mainb; 215 struct rtas_event_log_v6_hp hp; 216 } QEMU_PACKED; 217 218 struct rtas_event_log_v6_mc { 219 #define RTAS_LOG_V6_SECTION_ID_MC 0x4D43 /* MC */ 220 struct rtas_event_log_v6_section_header hdr; 221 uint32_t fru_id; 222 uint32_t proc_id; 223 uint8_t error_type; 224 #define RTAS_LOG_V6_MC_TYPE_UE 0 225 #define RTAS_LOG_V6_MC_TYPE_SLB 1 226 #define RTAS_LOG_V6_MC_TYPE_ERAT 2 227 #define RTAS_LOG_V6_MC_TYPE_TLB 4 228 #define RTAS_LOG_V6_MC_TYPE_D_CACHE 5 229 #define RTAS_LOG_V6_MC_TYPE_I_CACHE 7 230 uint8_t sub_err_type; 231 #define RTAS_LOG_V6_MC_UE_INDETERMINATE 0 232 #define RTAS_LOG_V6_MC_UE_IFETCH 1 233 #define RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_IFETCH 2 234 #define RTAS_LOG_V6_MC_UE_LOAD_STORE 3 235 #define RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_LOAD_STORE 4 236 #define RTAS_LOG_V6_MC_SLB_PARITY 0 237 #define RTAS_LOG_V6_MC_SLB_MULTIHIT 1 238 #define RTAS_LOG_V6_MC_SLB_INDETERMINATE 2 239 #define RTAS_LOG_V6_MC_ERAT_PARITY 1 240 #define RTAS_LOG_V6_MC_ERAT_MULTIHIT 2 241 #define RTAS_LOG_V6_MC_ERAT_INDETERMINATE 3 242 #define RTAS_LOG_V6_MC_TLB_PARITY 1 243 #define RTAS_LOG_V6_MC_TLB_MULTIHIT 2 244 #define RTAS_LOG_V6_MC_TLB_INDETERMINATE 3 245 uint8_t reserved_1[6]; 246 uint64_t effective_address; 247 uint64_t logical_address; 248 } QEMU_PACKED; 249 250 struct mc_extended_log { 251 struct rtas_event_log_v6 v6hdr; 252 struct rtas_event_log_v6_mc mc; 253 } QEMU_PACKED; 254 255 struct MC_ierror_table { 256 unsigned long srr1_mask; 257 unsigned long srr1_value; 258 bool nip_valid; /* nip is a valid indicator of faulting address */ 259 uint8_t error_type; 260 uint8_t error_subtype; 261 unsigned int initiator; 262 unsigned int severity; 263 }; 264 265 static const struct MC_ierror_table mc_ierror_table[] = { 266 { 0x00000000081c0000, 0x0000000000040000, true, 267 RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_IFETCH, 268 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, 269 { 0x00000000081c0000, 0x0000000000080000, true, 270 RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_PARITY, 271 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, 272 { 0x00000000081c0000, 0x00000000000c0000, true, 273 RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_MULTIHIT, 274 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, 275 { 0x00000000081c0000, 0x0000000000100000, true, 276 RTAS_LOG_V6_MC_TYPE_ERAT, RTAS_LOG_V6_MC_ERAT_MULTIHIT, 277 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, 278 { 0x00000000081c0000, 0x0000000000140000, true, 279 RTAS_LOG_V6_MC_TYPE_TLB, RTAS_LOG_V6_MC_TLB_MULTIHIT, 280 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, 281 { 0x00000000081c0000, 0x0000000000180000, true, 282 RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_IFETCH, 283 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, } }; 284 285 struct MC_derror_table { 286 unsigned long dsisr_value; 287 bool dar_valid; /* dar is a valid indicator of faulting address */ 288 uint8_t error_type; 289 uint8_t error_subtype; 290 unsigned int initiator; 291 unsigned int severity; 292 }; 293 294 static const struct MC_derror_table mc_derror_table[] = { 295 { 0x00008000, false, 296 RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_LOAD_STORE, 297 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, 298 { 0x00004000, true, 299 RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_LOAD_STORE, 300 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, 301 { 0x00000800, true, 302 RTAS_LOG_V6_MC_TYPE_ERAT, RTAS_LOG_V6_MC_ERAT_MULTIHIT, 303 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, 304 { 0x00000400, true, 305 RTAS_LOG_V6_MC_TYPE_TLB, RTAS_LOG_V6_MC_TLB_MULTIHIT, 306 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, 307 { 0x00000080, true, 308 RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_MULTIHIT, /* Before PARITY */ 309 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, 310 { 0x00000100, true, 311 RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_PARITY, 312 RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, } }; 313 314 #define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) 315 316 typedef enum EventClass { 317 EVENT_CLASS_INTERNAL_ERRORS = 0, 318 EVENT_CLASS_EPOW = 1, 319 EVENT_CLASS_RESERVED = 2, 320 EVENT_CLASS_HOT_PLUG = 3, 321 EVENT_CLASS_IO = 4, 322 EVENT_CLASS_MAX 323 } EventClassIndex; 324 #define EVENT_CLASS_MASK(index) (1 << (31 - index)) 325 326 static const char * const event_names[EVENT_CLASS_MAX] = { 327 [EVENT_CLASS_INTERNAL_ERRORS] = "internal-errors", 328 [EVENT_CLASS_EPOW] = "epow-events", 329 [EVENT_CLASS_HOT_PLUG] = "hot-plug-events", 330 [EVENT_CLASS_IO] = "ibm,io-events", 331 }; 332 333 struct SpaprEventSource { 334 int irq; 335 uint32_t mask; 336 bool enabled; 337 }; 338 339 static SpaprEventSource *spapr_event_sources_new(void) 340 { 341 return g_new0(SpaprEventSource, EVENT_CLASS_MAX); 342 } 343 344 static void spapr_event_sources_register(SpaprEventSource *event_sources, 345 EventClassIndex index, int irq) 346 { 347 /* we only support 1 irq per event class at the moment */ 348 g_assert(event_sources); 349 g_assert(!event_sources[index].enabled); 350 event_sources[index].irq = irq; 351 event_sources[index].mask = EVENT_CLASS_MASK(index); 352 event_sources[index].enabled = true; 353 } 354 355 static const SpaprEventSource * 356 spapr_event_sources_get_source(SpaprEventSource *event_sources, 357 EventClassIndex index) 358 { 359 g_assert(index < EVENT_CLASS_MAX); 360 g_assert(event_sources); 361 362 return &event_sources[index]; 363 } 364 365 void spapr_dt_events(SpaprMachineState *spapr, void *fdt) 366 { 367 uint32_t irq_ranges[EVENT_CLASS_MAX * 2]; 368 int i, count = 0, event_sources; 369 SpaprEventSource *events = spapr->event_sources; 370 371 g_assert(events); 372 373 _FDT(event_sources = fdt_add_subnode(fdt, 0, "event-sources")); 374 375 for (i = 0, count = 0; i < EVENT_CLASS_MAX; i++) { 376 int node_offset; 377 uint32_t interrupts[2]; 378 const SpaprEventSource *source = 379 spapr_event_sources_get_source(events, i); 380 const char *source_name = event_names[i]; 381 382 if (!source->enabled) { 383 continue; 384 } 385 386 spapr_dt_irq(interrupts, source->irq, false); 387 388 _FDT(node_offset = fdt_add_subnode(fdt, event_sources, source_name)); 389 _FDT(fdt_setprop(fdt, node_offset, "interrupts", interrupts, 390 sizeof(interrupts))); 391 392 irq_ranges[count++] = interrupts[0]; 393 irq_ranges[count++] = cpu_to_be32(1); 394 } 395 396 _FDT((fdt_setprop(fdt, event_sources, "interrupt-controller", NULL, 0))); 397 _FDT((fdt_setprop_cell(fdt, event_sources, "#interrupt-cells", 2))); 398 _FDT((fdt_setprop(fdt, event_sources, "interrupt-ranges", 399 irq_ranges, count * sizeof(uint32_t)))); 400 } 401 402 static const SpaprEventSource * 403 rtas_event_log_to_source(SpaprMachineState *spapr, int log_type) 404 { 405 const SpaprEventSource *source; 406 407 g_assert(spapr->event_sources); 408 409 switch (log_type) { 410 case RTAS_LOG_TYPE_HOTPLUG: 411 source = spapr_event_sources_get_source(spapr->event_sources, 412 EVENT_CLASS_HOT_PLUG); 413 if (spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT)) { 414 g_assert(source->enabled); 415 break; 416 } 417 /* fall through back to epow for legacy hotplug interrupt source */ 418 case RTAS_LOG_TYPE_EPOW: 419 source = spapr_event_sources_get_source(spapr->event_sources, 420 EVENT_CLASS_EPOW); 421 break; 422 default: 423 source = NULL; 424 } 425 426 return source; 427 } 428 429 static int rtas_event_log_to_irq(SpaprMachineState *spapr, int log_type) 430 { 431 const SpaprEventSource *source; 432 433 source = rtas_event_log_to_source(spapr, log_type); 434 g_assert(source); 435 g_assert(source->enabled); 436 437 return source->irq; 438 } 439 440 static uint32_t spapr_event_log_entry_type(SpaprEventLogEntry *entry) 441 { 442 return entry->summary & RTAS_LOG_TYPE_MASK; 443 } 444 445 static void rtas_event_log_queue(SpaprMachineState *spapr, 446 SpaprEventLogEntry *entry) 447 { 448 QTAILQ_INSERT_TAIL(&spapr->pending_events, entry, next); 449 } 450 451 static SpaprEventLogEntry *rtas_event_log_dequeue(SpaprMachineState *spapr, 452 uint32_t event_mask) 453 { 454 SpaprEventLogEntry *entry = NULL; 455 456 QTAILQ_FOREACH(entry, &spapr->pending_events, next) { 457 const SpaprEventSource *source = 458 rtas_event_log_to_source(spapr, 459 spapr_event_log_entry_type(entry)); 460 461 g_assert(source); 462 if (source->mask & event_mask) { 463 break; 464 } 465 } 466 467 if (entry) { 468 QTAILQ_REMOVE(&spapr->pending_events, entry, next); 469 } 470 471 return entry; 472 } 473 474 static bool rtas_event_log_contains(uint32_t event_mask) 475 { 476 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 477 SpaprEventLogEntry *entry = NULL; 478 479 QTAILQ_FOREACH(entry, &spapr->pending_events, next) { 480 const SpaprEventSource *source = 481 rtas_event_log_to_source(spapr, 482 spapr_event_log_entry_type(entry)); 483 484 if (source->mask & event_mask) { 485 return true; 486 } 487 } 488 489 return false; 490 } 491 492 static uint32_t next_plid; 493 494 static void spapr_init_v6hdr(struct rtas_event_log_v6 *v6hdr) 495 { 496 v6hdr->b0 = RTAS_LOG_V6_B0_VALID | RTAS_LOG_V6_B0_NEW_LOG 497 | RTAS_LOG_V6_B0_BIGENDIAN; 498 v6hdr->b2 = RTAS_LOG_V6_B2_POWERPC_FORMAT 499 | RTAS_LOG_V6_B2_LOG_FORMAT_PLATFORM_EVENT; 500 v6hdr->company = cpu_to_be32(RTAS_LOG_V6_COMPANY_IBM); 501 } 502 503 static void spapr_init_maina(struct rtas_event_log_v6_maina *maina, 504 int section_count) 505 { 506 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 507 struct tm tm; 508 int year; 509 510 maina->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MAINA); 511 maina->hdr.section_length = cpu_to_be16(sizeof(*maina)); 512 /* FIXME: section version, subtype and creator id? */ 513 spapr_rtc_read(&spapr->rtc, &tm, NULL); 514 year = tm.tm_year + 1900; 515 maina->creation_date = cpu_to_be32((to_bcd(year / 100) << 24) 516 | (to_bcd(year % 100) << 16) 517 | (to_bcd(tm.tm_mon + 1) << 8) 518 | to_bcd(tm.tm_mday)); 519 maina->creation_time = cpu_to_be32((to_bcd(tm.tm_hour) << 24) 520 | (to_bcd(tm.tm_min) << 16) 521 | (to_bcd(tm.tm_sec) << 8)); 522 maina->creator_id = 'H'; /* Hypervisor */ 523 maina->section_count = section_count; 524 maina->plid = next_plid++; 525 } 526 527 static void spapr_powerdown_req(Notifier *n, void *opaque) 528 { 529 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 530 SpaprEventLogEntry *entry; 531 struct rtas_event_log_v6 *v6hdr; 532 struct rtas_event_log_v6_maina *maina; 533 struct rtas_event_log_v6_mainb *mainb; 534 struct rtas_event_log_v6_epow *epow; 535 struct epow_extended_log *new_epow; 536 537 entry = g_new(SpaprEventLogEntry, 1); 538 new_epow = g_malloc0(sizeof(*new_epow)); 539 entry->extended_log = new_epow; 540 541 v6hdr = &new_epow->v6hdr; 542 maina = &new_epow->maina; 543 mainb = &new_epow->mainb; 544 epow = &new_epow->epow; 545 546 entry->summary = RTAS_LOG_VERSION_6 547 | RTAS_LOG_SEVERITY_EVENT 548 | RTAS_LOG_DISPOSITION_NOT_RECOVERED 549 | RTAS_LOG_OPTIONAL_PART_PRESENT 550 | RTAS_LOG_TYPE_EPOW; 551 entry->extended_length = sizeof(*new_epow); 552 553 spapr_init_v6hdr(v6hdr); 554 spapr_init_maina(maina, 3 /* Main-A, Main-B and EPOW */); 555 556 mainb->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MAINB); 557 mainb->hdr.section_length = cpu_to_be16(sizeof(*mainb)); 558 /* FIXME: section version, subtype and creator id? */ 559 mainb->subsystem_id = 0xa0; /* External environment */ 560 mainb->event_severity = 0x00; /* Informational / non-error */ 561 mainb->event_subtype = 0xd0; /* Normal shutdown */ 562 563 epow->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_EPOW); 564 epow->hdr.section_length = cpu_to_be16(sizeof(*epow)); 565 epow->hdr.section_version = 2; /* includes extended modifier */ 566 /* FIXME: section subtype and creator id? */ 567 epow->sensor_value = RTAS_LOG_V6_EPOW_ACTION_SYSTEM_SHUTDOWN; 568 epow->event_modifier = RTAS_LOG_V6_EPOW_MODIFIER_NORMAL; 569 epow->extended_modifier = RTAS_LOG_V6_EPOW_XMODIFIER_PARTITION_SPECIFIC; 570 571 rtas_event_log_queue(spapr, entry); 572 573 qemu_irq_pulse(spapr_qirq(spapr, 574 rtas_event_log_to_irq(spapr, RTAS_LOG_TYPE_EPOW))); 575 } 576 577 static void spapr_hotplug_req_event(uint8_t hp_id, uint8_t hp_action, 578 SpaprDrcType drc_type, 579 union drc_identifier *drc_id) 580 { 581 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 582 SpaprEventLogEntry *entry; 583 struct hp_extended_log *new_hp; 584 struct rtas_event_log_v6 *v6hdr; 585 struct rtas_event_log_v6_maina *maina; 586 struct rtas_event_log_v6_mainb *mainb; 587 struct rtas_event_log_v6_hp *hp; 588 589 entry = g_new(SpaprEventLogEntry, 1); 590 new_hp = g_malloc0(sizeof(struct hp_extended_log)); 591 entry->extended_log = new_hp; 592 593 v6hdr = &new_hp->v6hdr; 594 maina = &new_hp->maina; 595 mainb = &new_hp->mainb; 596 hp = &new_hp->hp; 597 598 entry->summary = RTAS_LOG_VERSION_6 599 | RTAS_LOG_SEVERITY_EVENT 600 | RTAS_LOG_DISPOSITION_NOT_RECOVERED 601 | RTAS_LOG_OPTIONAL_PART_PRESENT 602 | RTAS_LOG_INITIATOR_HOTPLUG 603 | RTAS_LOG_TYPE_HOTPLUG; 604 entry->extended_length = sizeof(*new_hp); 605 606 spapr_init_v6hdr(v6hdr); 607 spapr_init_maina(maina, 3 /* Main-A, Main-B, HP */); 608 609 mainb->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MAINB); 610 mainb->hdr.section_length = cpu_to_be16(sizeof(*mainb)); 611 mainb->subsystem_id = 0x80; /* External environment */ 612 mainb->event_severity = 0x00; /* Informational / non-error */ 613 mainb->event_subtype = 0x00; /* Normal shutdown */ 614 615 hp->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_HOTPLUG); 616 hp->hdr.section_length = cpu_to_be16(sizeof(*hp)); 617 hp->hdr.section_version = 1; /* includes extended modifier */ 618 hp->hotplug_action = hp_action; 619 hp->hotplug_identifier = hp_id; 620 621 switch (drc_type) { 622 case SPAPR_DR_CONNECTOR_TYPE_PCI: 623 hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_PCI; 624 break; 625 case SPAPR_DR_CONNECTOR_TYPE_LMB: 626 hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_MEMORY; 627 break; 628 case SPAPR_DR_CONNECTOR_TYPE_CPU: 629 hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_CPU; 630 break; 631 case SPAPR_DR_CONNECTOR_TYPE_PHB: 632 hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_PHB; 633 break; 634 default: 635 /* we shouldn't be signaling hotplug events for resources 636 * that don't support them 637 */ 638 g_assert(false); 639 return; 640 } 641 642 if (hp_id == RTAS_LOG_V6_HP_ID_DRC_COUNT) { 643 hp->drc_id.count = cpu_to_be32(drc_id->count); 644 } else if (hp_id == RTAS_LOG_V6_HP_ID_DRC_INDEX) { 645 hp->drc_id.index = cpu_to_be32(drc_id->index); 646 } else if (hp_id == RTAS_LOG_V6_HP_ID_DRC_COUNT_INDEXED) { 647 /* we should not be using count_indexed value unless the guest 648 * supports dedicated hotplug event source 649 */ 650 g_assert(spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT)); 651 hp->drc_id.count_indexed.count = 652 cpu_to_be32(drc_id->count_indexed.count); 653 hp->drc_id.count_indexed.index = 654 cpu_to_be32(drc_id->count_indexed.index); 655 } 656 657 rtas_event_log_queue(spapr, entry); 658 659 qemu_irq_pulse(spapr_qirq(spapr, 660 rtas_event_log_to_irq(spapr, RTAS_LOG_TYPE_HOTPLUG))); 661 } 662 663 void spapr_hotplug_req_add_by_index(SpaprDrc *drc) 664 { 665 SpaprDrcType drc_type = spapr_drc_type(drc); 666 union drc_identifier drc_id; 667 668 drc_id.index = spapr_drc_index(drc); 669 spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_INDEX, 670 RTAS_LOG_V6_HP_ACTION_ADD, drc_type, &drc_id); 671 } 672 673 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc) 674 { 675 SpaprDrcType drc_type = spapr_drc_type(drc); 676 union drc_identifier drc_id; 677 678 drc_id.index = spapr_drc_index(drc); 679 spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_INDEX, 680 RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_id); 681 } 682 683 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 684 uint32_t count) 685 { 686 union drc_identifier drc_id; 687 688 drc_id.count = count; 689 spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_COUNT, 690 RTAS_LOG_V6_HP_ACTION_ADD, drc_type, &drc_id); 691 } 692 693 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 694 uint32_t count) 695 { 696 union drc_identifier drc_id; 697 698 drc_id.count = count; 699 spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_COUNT, 700 RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_id); 701 } 702 703 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 704 uint32_t count, uint32_t index) 705 { 706 union drc_identifier drc_id; 707 708 drc_id.count_indexed.count = count; 709 drc_id.count_indexed.index = index; 710 spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_COUNT_INDEXED, 711 RTAS_LOG_V6_HP_ACTION_ADD, drc_type, &drc_id); 712 } 713 714 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 715 uint32_t count, uint32_t index) 716 { 717 union drc_identifier drc_id; 718 719 drc_id.count_indexed.count = count; 720 drc_id.count_indexed.index = index; 721 spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_COUNT_INDEXED, 722 RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_id); 723 } 724 725 static uint32_t spapr_mce_get_elog_type(PowerPCCPU *cpu, bool recovered, 726 struct mc_extended_log *ext_elog) 727 { 728 int i; 729 CPUPPCState *env = &cpu->env; 730 uint32_t summary; 731 uint64_t dsisr = env->spr[SPR_DSISR]; 732 733 summary = RTAS_LOG_VERSION_6 | RTAS_LOG_OPTIONAL_PART_PRESENT; 734 if (recovered) { 735 summary |= RTAS_LOG_DISPOSITION_FULLY_RECOVERED; 736 } else { 737 summary |= RTAS_LOG_DISPOSITION_NOT_RECOVERED; 738 } 739 740 if (SRR1_MC_LOADSTORE(env->spr[SPR_SRR1])) { 741 for (i = 0; i < ARRAY_SIZE(mc_derror_table); i++) { 742 if (!(dsisr & mc_derror_table[i].dsisr_value)) { 743 continue; 744 } 745 746 ext_elog->mc.error_type = mc_derror_table[i].error_type; 747 ext_elog->mc.sub_err_type = mc_derror_table[i].error_subtype; 748 if (mc_derror_table[i].dar_valid) { 749 ext_elog->mc.effective_address = cpu_to_be64(env->spr[SPR_DAR]); 750 } 751 752 summary |= mc_derror_table[i].initiator 753 | mc_derror_table[i].severity; 754 755 return summary; 756 } 757 } else { 758 for (i = 0; i < ARRAY_SIZE(mc_ierror_table); i++) { 759 if ((env->spr[SPR_SRR1] & mc_ierror_table[i].srr1_mask) != 760 mc_ierror_table[i].srr1_value) { 761 continue; 762 } 763 764 ext_elog->mc.error_type = mc_ierror_table[i].error_type; 765 ext_elog->mc.sub_err_type = mc_ierror_table[i].error_subtype; 766 if (mc_ierror_table[i].nip_valid) { 767 ext_elog->mc.effective_address = cpu_to_be64(env->nip); 768 } 769 770 summary |= mc_ierror_table[i].initiator 771 | mc_ierror_table[i].severity; 772 773 return summary; 774 } 775 } 776 777 summary |= RTAS_LOG_INITIATOR_CPU; 778 return summary; 779 } 780 781 static void spapr_mce_dispatch_elog(PowerPCCPU *cpu, bool recovered) 782 { 783 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 784 CPUState *cs = CPU(cpu); 785 uint64_t rtas_addr; 786 CPUPPCState *env = &cpu->env; 787 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 788 target_ulong msr = 0; 789 struct rtas_error_log log; 790 struct mc_extended_log *ext_elog; 791 uint32_t summary; 792 793 /* 794 * Properly set bits in MSR before we invoke the handler. 795 * SRR0/1, DAR and DSISR are properly set by KVM 796 */ 797 if (!(*pcc->interrupts_big_endian)(cpu)) { 798 msr |= (1ULL << MSR_LE); 799 } 800 801 if (env->msr & (1ULL << MSR_SF)) { 802 msr |= (1ULL << MSR_SF); 803 } 804 805 msr |= (1ULL << MSR_ME); 806 807 ext_elog = g_malloc0(sizeof(*ext_elog)); 808 summary = spapr_mce_get_elog_type(cpu, recovered, ext_elog); 809 810 log.summary = cpu_to_be32(summary); 811 log.extended_length = cpu_to_be32(sizeof(*ext_elog)); 812 813 spapr_init_v6hdr(&ext_elog->v6hdr); 814 ext_elog->mc.hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MC); 815 ext_elog->mc.hdr.section_length = 816 cpu_to_be16(sizeof(struct rtas_event_log_v6_mc)); 817 ext_elog->mc.hdr.section_version = 1; 818 819 /* get rtas addr from fdt */ 820 rtas_addr = spapr_get_rtas_addr(); 821 if (!rtas_addr) { 822 /* Unable to fetch rtas_addr. Hence reset the guest */ 823 ppc_cpu_do_system_reset(cs); 824 g_free(ext_elog); 825 return; 826 } 827 828 stq_be_phys(&address_space_memory, rtas_addr + RTAS_ERROR_LOG_OFFSET, 829 env->gpr[3]); 830 cpu_physical_memory_write(rtas_addr + RTAS_ERROR_LOG_OFFSET + 831 sizeof(env->gpr[3]), &log, sizeof(log)); 832 cpu_physical_memory_write(rtas_addr + RTAS_ERROR_LOG_OFFSET + 833 sizeof(env->gpr[3]) + sizeof(log), ext_elog, 834 sizeof(*ext_elog)); 835 836 env->gpr[3] = rtas_addr + RTAS_ERROR_LOG_OFFSET; 837 env->msr = msr; 838 env->nip = spapr->guest_machine_check_addr; 839 840 g_free(ext_elog); 841 } 842 843 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered) 844 { 845 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 846 CPUState *cs = CPU(cpu); 847 int ret; 848 Error *local_err = NULL; 849 850 if (spapr->guest_machine_check_addr == -1) { 851 /* 852 * This implies that we have hit a machine check either when the 853 * guest has not registered FWNMI (i.e., "ibm,nmi-register" not 854 * called) or between system reset and "ibm,nmi-register". 855 * Fall back to the old machine check behavior in such cases. 856 */ 857 cs->exception_index = POWERPC_EXCP_MCHECK; 858 ppc_cpu_do_interrupt(cs); 859 return; 860 } 861 862 while (spapr->mc_status != -1) { 863 /* 864 * Check whether the same CPU got machine check error 865 * while still handling the mc error (i.e., before 866 * that CPU called "ibm,nmi-interlock") 867 */ 868 if (spapr->mc_status == cpu->vcpu_id) { 869 qemu_system_guest_panicked(NULL); 870 return; 871 } 872 qemu_cond_wait_iothread(&spapr->mc_delivery_cond); 873 /* Meanwhile if the system is reset, then just return */ 874 if (spapr->guest_machine_check_addr == -1) { 875 return; 876 } 877 } 878 879 ret = migrate_add_blocker(spapr->fwnmi_migration_blocker, &local_err); 880 if (ret == -EBUSY) { 881 /* 882 * We don't want to abort so we let the migration to continue. 883 * In a rare case, the machine check handler will run on the target. 884 * Though this is not preferable, it is better than aborting 885 * the migration or killing the VM. 886 */ 887 warn_report("Received a fwnmi while migration was in progress"); 888 } 889 890 spapr->mc_status = cpu->vcpu_id; 891 spapr_mce_dispatch_elog(cpu, recovered); 892 } 893 894 static void check_exception(PowerPCCPU *cpu, SpaprMachineState *spapr, 895 uint32_t token, uint32_t nargs, 896 target_ulong args, 897 uint32_t nret, target_ulong rets) 898 { 899 uint32_t mask, buf, len, event_len; 900 uint64_t xinfo; 901 SpaprEventLogEntry *event; 902 struct rtas_error_log header; 903 int i; 904 905 if ((nargs < 6) || (nargs > 7) || nret != 1) { 906 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 907 return; 908 } 909 910 xinfo = rtas_ld(args, 1); 911 mask = rtas_ld(args, 2); 912 buf = rtas_ld(args, 4); 913 len = rtas_ld(args, 5); 914 if (nargs == 7) { 915 xinfo |= (uint64_t)rtas_ld(args, 6) << 32; 916 } 917 918 event = rtas_event_log_dequeue(spapr, mask); 919 if (!event) { 920 goto out_no_events; 921 } 922 923 event_len = event->extended_length + sizeof(header); 924 925 if (event_len < len) { 926 len = event_len; 927 } 928 929 header.summary = cpu_to_be32(event->summary); 930 header.extended_length = cpu_to_be32(event->extended_length); 931 cpu_physical_memory_write(buf, &header, sizeof(header)); 932 cpu_physical_memory_write(buf + sizeof(header), event->extended_log, 933 event->extended_length); 934 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 935 g_free(event->extended_log); 936 g_free(event); 937 938 /* according to PAPR+, the IRQ must be left asserted, or re-asserted, if 939 * there are still pending events to be fetched via check-exception. We 940 * do the latter here, since our code relies on edge-triggered 941 * interrupts. 942 */ 943 for (i = 0; i < EVENT_CLASS_MAX; i++) { 944 if (rtas_event_log_contains(EVENT_CLASS_MASK(i))) { 945 const SpaprEventSource *source = 946 spapr_event_sources_get_source(spapr->event_sources, i); 947 948 g_assert(source->enabled); 949 qemu_irq_pulse(spapr_qirq(spapr, source->irq)); 950 } 951 } 952 953 return; 954 955 out_no_events: 956 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); 957 } 958 959 static void event_scan(PowerPCCPU *cpu, SpaprMachineState *spapr, 960 uint32_t token, uint32_t nargs, 961 target_ulong args, 962 uint32_t nret, target_ulong rets) 963 { 964 if (nargs != 4 || nret != 1) { 965 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 966 return; 967 } 968 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); 969 } 970 971 void spapr_clear_pending_events(SpaprMachineState *spapr) 972 { 973 SpaprEventLogEntry *entry = NULL, *next_entry; 974 975 QTAILQ_FOREACH_SAFE(entry, &spapr->pending_events, next, next_entry) { 976 QTAILQ_REMOVE(&spapr->pending_events, entry, next); 977 g_free(entry->extended_log); 978 g_free(entry); 979 } 980 } 981 982 void spapr_events_init(SpaprMachineState *spapr) 983 { 984 int epow_irq = SPAPR_IRQ_EPOW; 985 986 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 987 epow_irq = spapr_irq_findone(spapr, &error_fatal); 988 } 989 990 spapr_irq_claim(spapr, epow_irq, false, &error_fatal); 991 992 QTAILQ_INIT(&spapr->pending_events); 993 994 spapr->event_sources = spapr_event_sources_new(); 995 996 spapr_event_sources_register(spapr->event_sources, EVENT_CLASS_EPOW, 997 epow_irq); 998 999 /* NOTE: if machine supports modern/dedicated hotplug event source, 1000 * we add it to the device-tree unconditionally. This means we may 1001 * have cases where the source is enabled in QEMU, but unused by the 1002 * guest because it does not support modern hotplug events, so we 1003 * take care to rely on checking for negotiation of OV5_HP_EVT option 1004 * before attempting to use it to signal events, rather than simply 1005 * checking that it's enabled. 1006 */ 1007 if (spapr->use_hotplug_event_source) { 1008 int hp_irq = SPAPR_IRQ_HOTPLUG; 1009 1010 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 1011 hp_irq = spapr_irq_findone(spapr, &error_fatal); 1012 } 1013 1014 spapr_irq_claim(spapr, hp_irq, false, &error_fatal); 1015 1016 spapr_event_sources_register(spapr->event_sources, EVENT_CLASS_HOT_PLUG, 1017 hp_irq); 1018 } 1019 1020 spapr->epow_notifier.notify = spapr_powerdown_req; 1021 qemu_register_powerdown_notifier(&spapr->epow_notifier); 1022 spapr_rtas_register(RTAS_CHECK_EXCEPTION, "check-exception", 1023 check_exception); 1024 spapr_rtas_register(RTAS_EVENT_SCAN, "event-scan", event_scan); 1025 } 1026