1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/cpu/core.h" 12 #include "hw/ppc/spapr_cpu_core.h" 13 #include "hw/qdev-properties.h" 14 #include "migration/vmstate.h" 15 #include "target/ppc/cpu.h" 16 #include "hw/ppc/spapr.h" 17 #include "qapi/error.h" 18 #include "sysemu/cpus.h" 19 #include "sysemu/kvm.h" 20 #include "target/ppc/kvm_ppc.h" 21 #include "hw/ppc/ppc.h" 22 #include "target/ppc/mmu-hash64.h" 23 #include "sysemu/numa.h" 24 #include "sysemu/reset.h" 25 #include "sysemu/hw_accel.h" 26 #include "qemu/error-report.h" 27 28 static void spapr_cpu_reset(void *opaque) 29 { 30 PowerPCCPU *cpu = opaque; 31 CPUState *cs = CPU(cpu); 32 CPUPPCState *env = &cpu->env; 33 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 34 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 35 target_ulong lpcr; 36 37 cpu_reset(cs); 38 39 /* All CPUs start halted. CPU0 is unhalted from the machine level 40 * reset code and the rest are explicitly started up by the guest 41 * using an RTAS call */ 42 cs->halted = 1; 43 44 env->spr[SPR_HIOR] = 0; 45 46 lpcr = env->spr[SPR_LPCR]; 47 48 /* Set emulated LPCR to not send interrupts to hypervisor. Note that 49 * under KVM, the actual HW LPCR will be set differently by KVM itself, 50 * the settings below ensure proper operations with TCG in absence of 51 * a real hypervisor. 52 * 53 * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for 54 * real mode accesses, which thankfully defaults to 0 and isn't 55 * accessible in guest mode. 56 * 57 * Disable Power-saving mode Exit Cause exceptions for the CPU, so 58 * we don't get spurious wakups before an RTAS start-cpu call. 59 * For the same reason, set PSSCR_EC. 60 */ 61 lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); 62 lpcr |= LPCR_LPES0 | LPCR_LPES1; 63 env->spr[SPR_PSSCR] |= PSSCR_EC; 64 65 /* Set RMLS to the max (ie, 16G) */ 66 lpcr &= ~LPCR_RMLS; 67 lpcr |= 1ull << LPCR_RMLS_SHIFT; 68 69 ppc_store_lpcr(cpu, lpcr); 70 71 /* Set a full AMOR so guest can use the AMR as it sees fit */ 72 env->spr[SPR_AMOR] = 0xffffffffffffffffull; 73 74 spapr_cpu->vpa_addr = 0; 75 spapr_cpu->slb_shadow_addr = 0; 76 spapr_cpu->slb_shadow_size = 0; 77 spapr_cpu->dtl_addr = 0; 78 spapr_cpu->dtl_size = 0; 79 80 spapr_caps_cpu_apply(SPAPR_MACHINE(qdev_get_machine()), cpu); 81 82 kvm_check_mmu(cpu, &error_fatal); 83 } 84 85 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3) 86 { 87 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 88 CPUPPCState *env = &cpu->env; 89 90 env->nip = nip; 91 env->gpr[3] = r3; 92 kvmppc_set_reg_ppc_online(cpu, 1); 93 CPU(cpu)->halted = 0; 94 /* Enable Power-saving mode Exit Cause exceptions */ 95 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); 96 } 97 98 /* 99 * Return the sPAPR CPU core type for @model which essentially is the CPU 100 * model specified with -cpu cmdline option. 101 */ 102 const char *spapr_get_cpu_core_type(const char *cpu_type) 103 { 104 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 105 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"), 106 len, cpu_type); 107 ObjectClass *oc = object_class_by_name(core_type); 108 109 g_free(core_type); 110 if (!oc) { 111 return NULL; 112 } 113 114 return object_class_get_name(oc); 115 } 116 117 static bool slb_shadow_needed(void *opaque) 118 { 119 SpaprCpuState *spapr_cpu = opaque; 120 121 return spapr_cpu->slb_shadow_addr != 0; 122 } 123 124 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = { 125 .name = "spapr_cpu/vpa/slb_shadow", 126 .version_id = 1, 127 .minimum_version_id = 1, 128 .needed = slb_shadow_needed, 129 .fields = (VMStateField[]) { 130 VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState), 131 VMSTATE_UINT64(slb_shadow_size, SpaprCpuState), 132 VMSTATE_END_OF_LIST() 133 } 134 }; 135 136 static bool dtl_needed(void *opaque) 137 { 138 SpaprCpuState *spapr_cpu = opaque; 139 140 return spapr_cpu->dtl_addr != 0; 141 } 142 143 static const VMStateDescription vmstate_spapr_cpu_dtl = { 144 .name = "spapr_cpu/vpa/dtl", 145 .version_id = 1, 146 .minimum_version_id = 1, 147 .needed = dtl_needed, 148 .fields = (VMStateField[]) { 149 VMSTATE_UINT64(dtl_addr, SpaprCpuState), 150 VMSTATE_UINT64(dtl_size, SpaprCpuState), 151 VMSTATE_END_OF_LIST() 152 } 153 }; 154 155 static bool vpa_needed(void *opaque) 156 { 157 SpaprCpuState *spapr_cpu = opaque; 158 159 return spapr_cpu->vpa_addr != 0; 160 } 161 162 static const VMStateDescription vmstate_spapr_cpu_vpa = { 163 .name = "spapr_cpu/vpa", 164 .version_id = 1, 165 .minimum_version_id = 1, 166 .needed = vpa_needed, 167 .fields = (VMStateField[]) { 168 VMSTATE_UINT64(vpa_addr, SpaprCpuState), 169 VMSTATE_END_OF_LIST() 170 }, 171 .subsections = (const VMStateDescription * []) { 172 &vmstate_spapr_cpu_slb_shadow, 173 &vmstate_spapr_cpu_dtl, 174 NULL 175 } 176 }; 177 178 static const VMStateDescription vmstate_spapr_cpu_state = { 179 .name = "spapr_cpu", 180 .version_id = 1, 181 .minimum_version_id = 1, 182 .fields = (VMStateField[]) { 183 VMSTATE_END_OF_LIST() 184 }, 185 .subsections = (const VMStateDescription * []) { 186 &vmstate_spapr_cpu_vpa, 187 NULL 188 } 189 }; 190 191 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc) 192 { 193 if (!sc->pre_3_0_migration) { 194 vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data); 195 } 196 qemu_unregister_reset(spapr_cpu_reset, cpu); 197 if (spapr_cpu_state(cpu)->icp) { 198 object_unparent(OBJECT(spapr_cpu_state(cpu)->icp)); 199 } 200 if (spapr_cpu_state(cpu)->tctx) { 201 object_unparent(OBJECT(spapr_cpu_state(cpu)->tctx)); 202 } 203 cpu_remove_sync(CPU(cpu)); 204 object_unparent(OBJECT(cpu)); 205 } 206 207 static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp) 208 { 209 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 210 CPUCore *cc = CPU_CORE(dev); 211 int i; 212 213 for (i = 0; i < cc->nr_threads; i++) { 214 spapr_unrealize_vcpu(sc->threads[i], sc); 215 } 216 g_free(sc->threads); 217 } 218 219 static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr, 220 SpaprCpuCore *sc, Error **errp) 221 { 222 CPUPPCState *env = &cpu->env; 223 CPUState *cs = CPU(cpu); 224 Error *local_err = NULL; 225 226 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 227 if (local_err) { 228 goto error; 229 } 230 231 /* Set time-base frequency to 512 MHz */ 232 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 233 234 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 235 kvmppc_set_papr(cpu); 236 237 qemu_register_reset(spapr_cpu_reset, cpu); 238 spapr_cpu_reset(cpu); 239 240 if (spapr_irq_cpu_intc_create(spapr, cpu, &local_err) < 0) { 241 goto error_unregister; 242 } 243 244 if (!sc->pre_3_0_migration) { 245 vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state, 246 cpu->machine_data); 247 } 248 249 return; 250 251 error_unregister: 252 qemu_unregister_reset(spapr_cpu_reset, cpu); 253 cpu_remove_sync(CPU(cpu)); 254 error: 255 error_propagate(errp, local_err); 256 } 257 258 static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp) 259 { 260 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc); 261 CPUCore *cc = CPU_CORE(sc); 262 Object *obj; 263 char *id; 264 CPUState *cs; 265 PowerPCCPU *cpu; 266 Error *local_err = NULL; 267 268 obj = object_new(scc->cpu_type); 269 270 cs = CPU(obj); 271 cpu = POWERPC_CPU(obj); 272 cs->cpu_index = cc->core_id + i; 273 spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err); 274 if (local_err) { 275 goto err; 276 } 277 278 cpu->node_id = sc->node_id; 279 280 id = g_strdup_printf("thread[%d]", i); 281 object_property_add_child(OBJECT(sc), id, obj, &local_err); 282 g_free(id); 283 if (local_err) { 284 goto err; 285 } 286 287 cpu->machine_data = g_new0(SpaprCpuState, 1); 288 289 object_unref(obj); 290 return cpu; 291 292 err: 293 object_unref(obj); 294 error_propagate(errp, local_err); 295 return NULL; 296 } 297 298 static void spapr_delete_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc) 299 { 300 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 301 302 cpu->machine_data = NULL; 303 g_free(spapr_cpu); 304 object_unparent(OBJECT(cpu)); 305 } 306 307 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 308 { 309 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 310 * tries to add a sPAPR CPU core to a non-pseries machine. 311 */ 312 SpaprMachineState *spapr = 313 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), 314 TYPE_SPAPR_MACHINE); 315 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 316 CPUCore *cc = CPU_CORE(OBJECT(dev)); 317 Error *local_err = NULL; 318 int i, j; 319 320 if (!spapr) { 321 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine"); 322 return; 323 } 324 325 sc->threads = g_new(PowerPCCPU *, cc->nr_threads); 326 for (i = 0; i < cc->nr_threads; i++) { 327 sc->threads[i] = spapr_create_vcpu(sc, i, &local_err); 328 if (local_err) { 329 goto err; 330 } 331 } 332 333 for (j = 0; j < cc->nr_threads; j++) { 334 spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err); 335 if (local_err) { 336 goto err_unrealize; 337 } 338 } 339 return; 340 341 err_unrealize: 342 while (--j >= 0) { 343 spapr_unrealize_vcpu(sc->threads[j], sc); 344 } 345 err: 346 while (--i >= 0) { 347 spapr_delete_vcpu(sc->threads[i], sc); 348 } 349 g_free(sc->threads); 350 error_propagate(errp, local_err); 351 } 352 353 static Property spapr_cpu_core_properties[] = { 354 DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID), 355 DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration, 356 false), 357 DEFINE_PROP_END_OF_LIST() 358 }; 359 360 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 361 { 362 DeviceClass *dc = DEVICE_CLASS(oc); 363 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 364 365 dc->realize = spapr_cpu_core_realize; 366 dc->unrealize = spapr_cpu_core_unrealize; 367 dc->props = spapr_cpu_core_properties; 368 scc->cpu_type = data; 369 } 370 371 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ 372 { \ 373 .parent = TYPE_SPAPR_CPU_CORE, \ 374 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \ 375 .class_init = spapr_cpu_core_class_init, \ 376 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \ 377 } 378 379 static const TypeInfo spapr_cpu_core_type_infos[] = { 380 { 381 .name = TYPE_SPAPR_CPU_CORE, 382 .parent = TYPE_CPU_CORE, 383 .abstract = true, 384 .instance_size = sizeof(SpaprCpuCore), 385 .class_size = sizeof(SpaprCpuCoreClass), 386 }, 387 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"), 388 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"), 389 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"), 390 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"), 391 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"), 392 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"), 393 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), 394 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), 395 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), 396 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), 397 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), 398 #ifdef CONFIG_KVM 399 DEFINE_SPAPR_CPU_CORE_TYPE("host"), 400 #endif 401 }; 402 403 DEFINE_TYPES(spapr_cpu_core_type_infos) 404