1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 #include "hw/cpu/core.h" 10 #include "hw/ppc/spapr_cpu_core.h" 11 #include "target/ppc/cpu.h" 12 #include "hw/ppc/spapr.h" 13 #include "hw/boards.h" 14 #include "qapi/error.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/kvm.h" 17 #include "target/ppc/kvm_ppc.h" 18 #include "hw/ppc/ppc.h" 19 #include "target/ppc/mmu-hash64.h" 20 #include "sysemu/numa.h" 21 #include "sysemu/hw_accel.h" 22 #include "qemu/error-report.h" 23 24 static void spapr_cpu_reset(void *opaque) 25 { 26 PowerPCCPU *cpu = opaque; 27 CPUState *cs = CPU(cpu); 28 CPUPPCState *env = &cpu->env; 29 30 cpu_reset(cs); 31 32 /* All CPUs start halted. CPU0 is unhalted from the machine level 33 * reset code and the rest are explicitly started up by the guest 34 * using an RTAS call */ 35 cs->halted = 1; 36 37 env->spr[SPR_HIOR] = 0; 38 } 39 40 static void spapr_cpu_destroy(PowerPCCPU *cpu) 41 { 42 qemu_unregister_reset(spapr_cpu_reset, cpu); 43 } 44 45 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, 46 Error **errp) 47 { 48 CPUPPCState *env = &cpu->env; 49 50 /* Set time-base frequency to 512 MHz */ 51 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 52 53 /* Enable PAPR mode in TCG or KVM */ 54 cpu_ppc_set_papr(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 55 56 qemu_register_reset(spapr_cpu_reset, cpu); 57 spapr_cpu_reset(cpu); 58 } 59 60 /* 61 * Return the sPAPR CPU core type for @model which essentially is the CPU 62 * model specified with -cpu cmdline option. 63 */ 64 const char *spapr_get_cpu_core_type(const char *cpu_type) 65 { 66 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 67 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"), 68 len, cpu_type); 69 ObjectClass *oc = object_class_by_name(core_type); 70 71 g_free(core_type); 72 if (!oc) { 73 return NULL; 74 } 75 76 return object_class_get_name(oc); 77 } 78 79 static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp) 80 { 81 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 82 CPUCore *cc = CPU_CORE(dev); 83 int i; 84 85 for (i = 0; i < cc->nr_threads; i++) { 86 Object *obj = OBJECT(sc->threads[i]); 87 DeviceState *dev = DEVICE(obj); 88 CPUState *cs = CPU(dev); 89 PowerPCCPU *cpu = POWERPC_CPU(cs); 90 91 spapr_cpu_destroy(cpu); 92 object_unparent(cpu->intc); 93 cpu_remove_sync(cs); 94 object_unparent(obj); 95 } 96 g_free(sc->threads); 97 } 98 99 static void spapr_cpu_core_realize_child(Object *child, 100 sPAPRMachineState *spapr, Error **errp) 101 { 102 Error *local_err = NULL; 103 CPUState *cs = CPU(child); 104 PowerPCCPU *cpu = POWERPC_CPU(cs); 105 Object *obj; 106 107 object_property_set_bool(child, true, "realized", &local_err); 108 if (local_err) { 109 goto error; 110 } 111 112 spapr_cpu_init(spapr, cpu, &local_err); 113 if (local_err) { 114 goto error; 115 } 116 117 obj = object_new(spapr->icp_type); 118 object_property_add_child(child, "icp", obj, &error_abort); 119 object_unref(obj); 120 object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(spapr), 121 &error_abort); 122 object_property_add_const_link(obj, ICP_PROP_CPU, child, &error_abort); 123 object_property_set_bool(obj, true, "realized", &local_err); 124 if (local_err) { 125 goto free_icp; 126 } 127 128 return; 129 130 free_icp: 131 object_unparent(obj); 132 error: 133 error_propagate(errp, local_err); 134 } 135 136 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 137 { 138 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 139 * tries to add a sPAPR CPU core to a non-pseries machine. 140 */ 141 sPAPRMachineState *spapr = 142 (sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(), 143 TYPE_SPAPR_MACHINE); 144 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 145 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev)); 146 CPUCore *cc = CPU_CORE(OBJECT(dev)); 147 Error *local_err = NULL; 148 Object *obj; 149 int i, j; 150 151 if (!spapr) { 152 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine"); 153 return; 154 } 155 156 sc->threads = g_new(PowerPCCPU *, cc->nr_threads); 157 for (i = 0; i < cc->nr_threads; i++) { 158 char id[32]; 159 CPUState *cs; 160 PowerPCCPU *cpu; 161 162 obj = object_new(scc->cpu_type); 163 164 cs = CPU(obj); 165 cpu = sc->threads[i] = POWERPC_CPU(obj); 166 cs->cpu_index = cc->core_id + i; 167 cpu->vcpu_id = (cc->core_id * spapr->vsmt / smp_threads) + i; 168 if (kvm_enabled() && !kvm_vcpu_id_is_valid(cpu->vcpu_id)) { 169 error_setg(&local_err, "Can't create CPU with id %d in KVM", 170 cpu->vcpu_id); 171 error_append_hint(&local_err, "Adjust the number of cpus to %d " 172 "or try to raise the number of threads per core\n", 173 cpu->vcpu_id * smp_threads / spapr->vsmt); 174 goto err; 175 } 176 177 178 /* Set NUMA node for the threads belonged to core */ 179 cpu->node_id = sc->node_id; 180 181 snprintf(id, sizeof(id), "thread[%d]", i); 182 object_property_add_child(OBJECT(sc), id, obj, &local_err); 183 if (local_err) { 184 goto err; 185 } 186 object_unref(obj); 187 } 188 189 for (j = 0; j < cc->nr_threads; j++) { 190 obj = OBJECT(sc->threads[j]); 191 192 spapr_cpu_core_realize_child(obj, spapr, &local_err); 193 if (local_err) { 194 goto err; 195 } 196 } 197 return; 198 199 err: 200 while (--i >= 0) { 201 obj = OBJECT(sc->threads[i]); 202 object_unparent(obj); 203 } 204 g_free(sc->threads); 205 error_propagate(errp, local_err); 206 } 207 208 static Property spapr_cpu_core_properties[] = { 209 DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID), 210 DEFINE_PROP_END_OF_LIST() 211 }; 212 213 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 214 { 215 DeviceClass *dc = DEVICE_CLASS(oc); 216 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 217 218 dc->realize = spapr_cpu_core_realize; 219 dc->unrealize = spapr_cpu_core_unrealizefn; 220 dc->props = spapr_cpu_core_properties; 221 scc->cpu_type = data; 222 } 223 224 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ 225 { \ 226 .parent = TYPE_SPAPR_CPU_CORE, \ 227 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \ 228 .class_init = spapr_cpu_core_class_init, \ 229 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \ 230 } 231 232 static const TypeInfo spapr_cpu_core_type_infos[] = { 233 { 234 .name = TYPE_SPAPR_CPU_CORE, 235 .parent = TYPE_CPU_CORE, 236 .abstract = true, 237 .instance_size = sizeof(sPAPRCPUCore), 238 .class_size = sizeof(sPAPRCPUCoreClass), 239 }, 240 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"), 241 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"), 242 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"), 243 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"), 244 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"), 245 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"), 246 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), 247 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), 248 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), 249 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), 250 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), 251 #ifdef CONFIG_KVM 252 DEFINE_SPAPR_CPU_CORE_TYPE("host"), 253 #endif 254 }; 255 256 DEFINE_TYPES(spapr_cpu_core_type_infos) 257