1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/cpu/core.h" 12 #include "hw/ppc/spapr_cpu_core.h" 13 #include "hw/qdev-properties.h" 14 #include "migration/vmstate.h" 15 #include "target/ppc/cpu.h" 16 #include "hw/ppc/spapr.h" 17 #include "qapi/error.h" 18 #include "sysemu/cpus.h" 19 #include "sysemu/kvm.h" 20 #include "target/ppc/kvm_ppc.h" 21 #include "hw/ppc/ppc.h" 22 #include "target/ppc/mmu-hash64.h" 23 #include "sysemu/numa.h" 24 #include "sysemu/reset.h" 25 #include "sysemu/hw_accel.h" 26 #include "qemu/error-report.h" 27 28 static void spapr_reset_vcpu(PowerPCCPU *cpu) 29 { 30 CPUState *cs = CPU(cpu); 31 CPUPPCState *env = &cpu->env; 32 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 33 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 34 target_ulong lpcr; 35 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 36 37 cpu_reset(cs); 38 39 /* All CPUs start halted. CPU0 is unhalted from the machine level 40 * reset code and the rest are explicitly started up by the guest 41 * using an RTAS call */ 42 cs->halted = 1; 43 44 env->spr[SPR_HIOR] = 0; 45 46 lpcr = env->spr[SPR_LPCR]; 47 48 /* Set emulated LPCR to not send interrupts to hypervisor. Note that 49 * under KVM, the actual HW LPCR will be set differently by KVM itself, 50 * the settings below ensure proper operations with TCG in absence of 51 * a real hypervisor. 52 * 53 * Disable Power-saving mode Exit Cause exceptions for the CPU, so 54 * we don't get spurious wakups before an RTAS start-cpu call. 55 * For the same reason, set PSSCR_EC. 56 */ 57 lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); 58 lpcr |= LPCR_LPES0 | LPCR_LPES1; 59 env->spr[SPR_PSSCR] |= PSSCR_EC; 60 61 ppc_store_lpcr(cpu, lpcr); 62 63 /* Set a full AMOR so guest can use the AMR as it sees fit */ 64 env->spr[SPR_AMOR] = 0xffffffffffffffffull; 65 66 spapr_cpu->vpa_addr = 0; 67 spapr_cpu->slb_shadow_addr = 0; 68 spapr_cpu->slb_shadow_size = 0; 69 spapr_cpu->dtl_addr = 0; 70 spapr_cpu->dtl_size = 0; 71 72 spapr_caps_cpu_apply(spapr, cpu); 73 74 kvm_check_mmu(cpu, &error_fatal); 75 76 spapr_irq_cpu_intc_reset(spapr, cpu); 77 } 78 79 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, 80 target_ulong r1, target_ulong r3, 81 target_ulong r4) 82 { 83 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 84 CPUPPCState *env = &cpu->env; 85 86 env->nip = nip; 87 env->gpr[1] = r1; 88 env->gpr[3] = r3; 89 env->gpr[4] = r4; 90 kvmppc_set_reg_ppc_online(cpu, 1); 91 CPU(cpu)->halted = 0; 92 /* Enable Power-saving mode Exit Cause exceptions */ 93 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); 94 } 95 96 /* 97 * Return the sPAPR CPU core type for @model which essentially is the CPU 98 * model specified with -cpu cmdline option. 99 */ 100 const char *spapr_get_cpu_core_type(const char *cpu_type) 101 { 102 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 103 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"), 104 len, cpu_type); 105 ObjectClass *oc = object_class_by_name(core_type); 106 107 g_free(core_type); 108 if (!oc) { 109 return NULL; 110 } 111 112 return object_class_get_name(oc); 113 } 114 115 static bool slb_shadow_needed(void *opaque) 116 { 117 SpaprCpuState *spapr_cpu = opaque; 118 119 return spapr_cpu->slb_shadow_addr != 0; 120 } 121 122 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = { 123 .name = "spapr_cpu/vpa/slb_shadow", 124 .version_id = 1, 125 .minimum_version_id = 1, 126 .needed = slb_shadow_needed, 127 .fields = (VMStateField[]) { 128 VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState), 129 VMSTATE_UINT64(slb_shadow_size, SpaprCpuState), 130 VMSTATE_END_OF_LIST() 131 } 132 }; 133 134 static bool dtl_needed(void *opaque) 135 { 136 SpaprCpuState *spapr_cpu = opaque; 137 138 return spapr_cpu->dtl_addr != 0; 139 } 140 141 static const VMStateDescription vmstate_spapr_cpu_dtl = { 142 .name = "spapr_cpu/vpa/dtl", 143 .version_id = 1, 144 .minimum_version_id = 1, 145 .needed = dtl_needed, 146 .fields = (VMStateField[]) { 147 VMSTATE_UINT64(dtl_addr, SpaprCpuState), 148 VMSTATE_UINT64(dtl_size, SpaprCpuState), 149 VMSTATE_END_OF_LIST() 150 } 151 }; 152 153 static bool vpa_needed(void *opaque) 154 { 155 SpaprCpuState *spapr_cpu = opaque; 156 157 return spapr_cpu->vpa_addr != 0; 158 } 159 160 static const VMStateDescription vmstate_spapr_cpu_vpa = { 161 .name = "spapr_cpu/vpa", 162 .version_id = 1, 163 .minimum_version_id = 1, 164 .needed = vpa_needed, 165 .fields = (VMStateField[]) { 166 VMSTATE_UINT64(vpa_addr, SpaprCpuState), 167 VMSTATE_END_OF_LIST() 168 }, 169 .subsections = (const VMStateDescription * []) { 170 &vmstate_spapr_cpu_slb_shadow, 171 &vmstate_spapr_cpu_dtl, 172 NULL 173 } 174 }; 175 176 static const VMStateDescription vmstate_spapr_cpu_state = { 177 .name = "spapr_cpu", 178 .version_id = 1, 179 .minimum_version_id = 1, 180 .fields = (VMStateField[]) { 181 VMSTATE_END_OF_LIST() 182 }, 183 .subsections = (const VMStateDescription * []) { 184 &vmstate_spapr_cpu_vpa, 185 NULL 186 } 187 }; 188 189 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc) 190 { 191 if (!sc->pre_3_0_migration) { 192 vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data); 193 } 194 spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu); 195 cpu_remove_sync(CPU(cpu)); 196 object_unparent(OBJECT(cpu)); 197 } 198 199 /* 200 * Called when CPUs are hot-plugged. 201 */ 202 static void spapr_cpu_core_reset(DeviceState *dev) 203 { 204 CPUCore *cc = CPU_CORE(dev); 205 SpaprCpuCore *sc = SPAPR_CPU_CORE(dev); 206 int i; 207 208 for (i = 0; i < cc->nr_threads; i++) { 209 spapr_reset_vcpu(sc->threads[i]); 210 } 211 } 212 213 /* 214 * Called by the machine reset. 215 */ 216 static void spapr_cpu_core_reset_handler(void *opaque) 217 { 218 spapr_cpu_core_reset(opaque); 219 } 220 221 static void spapr_cpu_core_unrealize(DeviceState *dev) 222 { 223 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 224 CPUCore *cc = CPU_CORE(dev); 225 int i; 226 227 qemu_unregister_reset(spapr_cpu_core_reset_handler, sc); 228 229 for (i = 0; i < cc->nr_threads; i++) { 230 spapr_unrealize_vcpu(sc->threads[i], sc); 231 } 232 g_free(sc->threads); 233 } 234 235 static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr, 236 SpaprCpuCore *sc, Error **errp) 237 { 238 CPUPPCState *env = &cpu->env; 239 CPUState *cs = CPU(cpu); 240 Error *local_err = NULL; 241 242 qdev_realize(DEVICE(cpu), NULL, &local_err); 243 if (local_err) { 244 goto error; 245 } 246 247 /* Set time-base frequency to 512 MHz */ 248 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 249 250 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 251 kvmppc_set_papr(cpu); 252 253 if (spapr_irq_cpu_intc_create(spapr, cpu, &local_err) < 0) { 254 goto error_intc_create; 255 } 256 257 if (!sc->pre_3_0_migration) { 258 vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state, 259 cpu->machine_data); 260 } 261 262 return; 263 264 error_intc_create: 265 cpu_remove_sync(CPU(cpu)); 266 error: 267 error_propagate(errp, local_err); 268 } 269 270 static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp) 271 { 272 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc); 273 CPUCore *cc = CPU_CORE(sc); 274 Object *obj; 275 char *id; 276 CPUState *cs; 277 PowerPCCPU *cpu; 278 Error *local_err = NULL; 279 280 obj = object_new(scc->cpu_type); 281 282 cs = CPU(obj); 283 cpu = POWERPC_CPU(obj); 284 cs->cpu_index = cc->core_id + i; 285 spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err); 286 if (local_err) { 287 goto err; 288 } 289 290 cpu->node_id = sc->node_id; 291 292 id = g_strdup_printf("thread[%d]", i); 293 object_property_add_child(OBJECT(sc), id, obj); 294 g_free(id); 295 296 cpu->machine_data = g_new0(SpaprCpuState, 1); 297 298 object_unref(obj); 299 return cpu; 300 301 err: 302 object_unref(obj); 303 error_propagate(errp, local_err); 304 return NULL; 305 } 306 307 static void spapr_delete_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc) 308 { 309 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 310 311 cpu->machine_data = NULL; 312 g_free(spapr_cpu); 313 object_unparent(OBJECT(cpu)); 314 } 315 316 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 317 { 318 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 319 * tries to add a sPAPR CPU core to a non-pseries machine. 320 */ 321 SpaprMachineState *spapr = 322 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), 323 TYPE_SPAPR_MACHINE); 324 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 325 CPUCore *cc = CPU_CORE(OBJECT(dev)); 326 Error *local_err = NULL; 327 int i, j; 328 329 if (!spapr) { 330 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine"); 331 return; 332 } 333 334 sc->threads = g_new(PowerPCCPU *, cc->nr_threads); 335 for (i = 0; i < cc->nr_threads; i++) { 336 sc->threads[i] = spapr_create_vcpu(sc, i, &local_err); 337 if (local_err) { 338 goto err; 339 } 340 } 341 342 for (j = 0; j < cc->nr_threads; j++) { 343 spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err); 344 if (local_err) { 345 goto err_unrealize; 346 } 347 } 348 349 qemu_register_reset(spapr_cpu_core_reset_handler, sc); 350 return; 351 352 err_unrealize: 353 while (--j >= 0) { 354 spapr_unrealize_vcpu(sc->threads[j], sc); 355 } 356 err: 357 while (--i >= 0) { 358 spapr_delete_vcpu(sc->threads[i], sc); 359 } 360 g_free(sc->threads); 361 error_propagate(errp, local_err); 362 } 363 364 static Property spapr_cpu_core_properties[] = { 365 DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID), 366 DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration, 367 false), 368 DEFINE_PROP_END_OF_LIST() 369 }; 370 371 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 372 { 373 DeviceClass *dc = DEVICE_CLASS(oc); 374 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 375 376 dc->realize = spapr_cpu_core_realize; 377 dc->unrealize = spapr_cpu_core_unrealize; 378 dc->reset = spapr_cpu_core_reset; 379 device_class_set_props(dc, spapr_cpu_core_properties); 380 scc->cpu_type = data; 381 } 382 383 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ 384 { \ 385 .parent = TYPE_SPAPR_CPU_CORE, \ 386 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \ 387 .class_init = spapr_cpu_core_class_init, \ 388 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \ 389 } 390 391 static const TypeInfo spapr_cpu_core_type_infos[] = { 392 { 393 .name = TYPE_SPAPR_CPU_CORE, 394 .parent = TYPE_CPU_CORE, 395 .abstract = true, 396 .instance_size = sizeof(SpaprCpuCore), 397 .class_size = sizeof(SpaprCpuCoreClass), 398 }, 399 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"), 400 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"), 401 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"), 402 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"), 403 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"), 404 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"), 405 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), 406 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), 407 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), 408 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), 409 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), 410 DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"), 411 #ifdef CONFIG_KVM 412 DEFINE_SPAPR_CPU_CORE_TYPE("host"), 413 #endif 414 }; 415 416 DEFINE_TYPES(spapr_cpu_core_type_infos) 417