1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/cpu/core.h" 12 #include "hw/ppc/spapr_cpu_core.h" 13 #include "hw/qdev-properties.h" 14 #include "migration/vmstate.h" 15 #include "target/ppc/cpu.h" 16 #include "hw/ppc/spapr.h" 17 #include "qapi/error.h" 18 #include "sysemu/cpus.h" 19 #include "sysemu/kvm.h" 20 #include "target/ppc/kvm_ppc.h" 21 #include "hw/ppc/ppc.h" 22 #include "target/ppc/mmu-hash64.h" 23 #include "sysemu/numa.h" 24 #include "sysemu/reset.h" 25 #include "sysemu/hw_accel.h" 26 #include "qemu/error-report.h" 27 28 static void spapr_reset_vcpu(PowerPCCPU *cpu) 29 { 30 CPUState *cs = CPU(cpu); 31 CPUPPCState *env = &cpu->env; 32 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 33 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 34 target_ulong lpcr; 35 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 36 37 cpu_reset(cs); 38 39 /* All CPUs start halted. CPU0 is unhalted from the machine level 40 * reset code and the rest are explicitly started up by the guest 41 * using an RTAS call */ 42 cs->halted = 1; 43 44 env->spr[SPR_HIOR] = 0; 45 46 lpcr = env->spr[SPR_LPCR]; 47 48 /* Set emulated LPCR to not send interrupts to hypervisor. Note that 49 * under KVM, the actual HW LPCR will be set differently by KVM itself, 50 * the settings below ensure proper operations with TCG in absence of 51 * a real hypervisor. 52 * 53 * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for 54 * real mode accesses, which thankfully defaults to 0 and isn't 55 * accessible in guest mode. 56 * 57 * Disable Power-saving mode Exit Cause exceptions for the CPU, so 58 * we don't get spurious wakups before an RTAS start-cpu call. 59 * For the same reason, set PSSCR_EC. 60 */ 61 lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm); 62 lpcr |= LPCR_LPES0 | LPCR_LPES1; 63 env->spr[SPR_PSSCR] |= PSSCR_EC; 64 65 /* Set RMLS to the max (ie, 16G) */ 66 lpcr &= ~LPCR_RMLS; 67 lpcr |= 1ull << LPCR_RMLS_SHIFT; 68 69 ppc_store_lpcr(cpu, lpcr); 70 71 /* Set a full AMOR so guest can use the AMR as it sees fit */ 72 env->spr[SPR_AMOR] = 0xffffffffffffffffull; 73 74 spapr_cpu->vpa_addr = 0; 75 spapr_cpu->slb_shadow_addr = 0; 76 spapr_cpu->slb_shadow_size = 0; 77 spapr_cpu->dtl_addr = 0; 78 spapr_cpu->dtl_size = 0; 79 80 spapr_caps_cpu_apply(spapr, cpu); 81 82 kvm_check_mmu(cpu, &error_fatal); 83 84 spapr_irq_cpu_intc_reset(spapr, cpu); 85 } 86 87 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3) 88 { 89 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 90 CPUPPCState *env = &cpu->env; 91 92 env->nip = nip; 93 env->gpr[3] = r3; 94 kvmppc_set_reg_ppc_online(cpu, 1); 95 CPU(cpu)->halted = 0; 96 /* Enable Power-saving mode Exit Cause exceptions */ 97 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); 98 } 99 100 /* 101 * Return the sPAPR CPU core type for @model which essentially is the CPU 102 * model specified with -cpu cmdline option. 103 */ 104 const char *spapr_get_cpu_core_type(const char *cpu_type) 105 { 106 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 107 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"), 108 len, cpu_type); 109 ObjectClass *oc = object_class_by_name(core_type); 110 111 g_free(core_type); 112 if (!oc) { 113 return NULL; 114 } 115 116 return object_class_get_name(oc); 117 } 118 119 static bool slb_shadow_needed(void *opaque) 120 { 121 SpaprCpuState *spapr_cpu = opaque; 122 123 return spapr_cpu->slb_shadow_addr != 0; 124 } 125 126 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = { 127 .name = "spapr_cpu/vpa/slb_shadow", 128 .version_id = 1, 129 .minimum_version_id = 1, 130 .needed = slb_shadow_needed, 131 .fields = (VMStateField[]) { 132 VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState), 133 VMSTATE_UINT64(slb_shadow_size, SpaprCpuState), 134 VMSTATE_END_OF_LIST() 135 } 136 }; 137 138 static bool dtl_needed(void *opaque) 139 { 140 SpaprCpuState *spapr_cpu = opaque; 141 142 return spapr_cpu->dtl_addr != 0; 143 } 144 145 static const VMStateDescription vmstate_spapr_cpu_dtl = { 146 .name = "spapr_cpu/vpa/dtl", 147 .version_id = 1, 148 .minimum_version_id = 1, 149 .needed = dtl_needed, 150 .fields = (VMStateField[]) { 151 VMSTATE_UINT64(dtl_addr, SpaprCpuState), 152 VMSTATE_UINT64(dtl_size, SpaprCpuState), 153 VMSTATE_END_OF_LIST() 154 } 155 }; 156 157 static bool vpa_needed(void *opaque) 158 { 159 SpaprCpuState *spapr_cpu = opaque; 160 161 return spapr_cpu->vpa_addr != 0; 162 } 163 164 static const VMStateDescription vmstate_spapr_cpu_vpa = { 165 .name = "spapr_cpu/vpa", 166 .version_id = 1, 167 .minimum_version_id = 1, 168 .needed = vpa_needed, 169 .fields = (VMStateField[]) { 170 VMSTATE_UINT64(vpa_addr, SpaprCpuState), 171 VMSTATE_END_OF_LIST() 172 }, 173 .subsections = (const VMStateDescription * []) { 174 &vmstate_spapr_cpu_slb_shadow, 175 &vmstate_spapr_cpu_dtl, 176 NULL 177 } 178 }; 179 180 static const VMStateDescription vmstate_spapr_cpu_state = { 181 .name = "spapr_cpu", 182 .version_id = 1, 183 .minimum_version_id = 1, 184 .fields = (VMStateField[]) { 185 VMSTATE_END_OF_LIST() 186 }, 187 .subsections = (const VMStateDescription * []) { 188 &vmstate_spapr_cpu_vpa, 189 NULL 190 } 191 }; 192 193 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc) 194 { 195 if (!sc->pre_3_0_migration) { 196 vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data); 197 } 198 spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu); 199 cpu_remove_sync(CPU(cpu)); 200 object_unparent(OBJECT(cpu)); 201 } 202 203 /* 204 * Called when CPUs are hot-plugged. 205 */ 206 static void spapr_cpu_core_reset(DeviceState *dev) 207 { 208 CPUCore *cc = CPU_CORE(dev); 209 SpaprCpuCore *sc = SPAPR_CPU_CORE(dev); 210 int i; 211 212 for (i = 0; i < cc->nr_threads; i++) { 213 spapr_reset_vcpu(sc->threads[i]); 214 } 215 } 216 217 /* 218 * Called by the machine reset. 219 */ 220 static void spapr_cpu_core_reset_handler(void *opaque) 221 { 222 spapr_cpu_core_reset(opaque); 223 } 224 225 static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp) 226 { 227 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 228 CPUCore *cc = CPU_CORE(dev); 229 int i; 230 231 qemu_unregister_reset(spapr_cpu_core_reset_handler, sc); 232 233 for (i = 0; i < cc->nr_threads; i++) { 234 spapr_unrealize_vcpu(sc->threads[i], sc); 235 } 236 g_free(sc->threads); 237 } 238 239 static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr, 240 SpaprCpuCore *sc, Error **errp) 241 { 242 CPUPPCState *env = &cpu->env; 243 CPUState *cs = CPU(cpu); 244 Error *local_err = NULL; 245 246 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 247 if (local_err) { 248 goto error; 249 } 250 251 /* Set time-base frequency to 512 MHz */ 252 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 253 254 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 255 kvmppc_set_papr(cpu); 256 257 if (spapr_irq_cpu_intc_create(spapr, cpu, &local_err) < 0) { 258 goto error_intc_create; 259 } 260 261 if (!sc->pre_3_0_migration) { 262 vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state, 263 cpu->machine_data); 264 } 265 266 return; 267 268 error_intc_create: 269 cpu_remove_sync(CPU(cpu)); 270 error: 271 error_propagate(errp, local_err); 272 } 273 274 static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp) 275 { 276 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc); 277 CPUCore *cc = CPU_CORE(sc); 278 Object *obj; 279 char *id; 280 CPUState *cs; 281 PowerPCCPU *cpu; 282 Error *local_err = NULL; 283 284 obj = object_new(scc->cpu_type); 285 286 cs = CPU(obj); 287 cpu = POWERPC_CPU(obj); 288 cs->cpu_index = cc->core_id + i; 289 spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err); 290 if (local_err) { 291 goto err; 292 } 293 294 cpu->node_id = sc->node_id; 295 296 id = g_strdup_printf("thread[%d]", i); 297 object_property_add_child(OBJECT(sc), id, obj, &local_err); 298 g_free(id); 299 if (local_err) { 300 goto err; 301 } 302 303 cpu->machine_data = g_new0(SpaprCpuState, 1); 304 305 object_unref(obj); 306 return cpu; 307 308 err: 309 object_unref(obj); 310 error_propagate(errp, local_err); 311 return NULL; 312 } 313 314 static void spapr_delete_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc) 315 { 316 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 317 318 cpu->machine_data = NULL; 319 g_free(spapr_cpu); 320 object_unparent(OBJECT(cpu)); 321 } 322 323 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 324 { 325 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 326 * tries to add a sPAPR CPU core to a non-pseries machine. 327 */ 328 SpaprMachineState *spapr = 329 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), 330 TYPE_SPAPR_MACHINE); 331 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 332 CPUCore *cc = CPU_CORE(OBJECT(dev)); 333 Error *local_err = NULL; 334 int i, j; 335 336 if (!spapr) { 337 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine"); 338 return; 339 } 340 341 sc->threads = g_new(PowerPCCPU *, cc->nr_threads); 342 for (i = 0; i < cc->nr_threads; i++) { 343 sc->threads[i] = spapr_create_vcpu(sc, i, &local_err); 344 if (local_err) { 345 goto err; 346 } 347 } 348 349 for (j = 0; j < cc->nr_threads; j++) { 350 spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err); 351 if (local_err) { 352 goto err_unrealize; 353 } 354 } 355 356 qemu_register_reset(spapr_cpu_core_reset_handler, sc); 357 return; 358 359 err_unrealize: 360 while (--j >= 0) { 361 spapr_unrealize_vcpu(sc->threads[j], sc); 362 } 363 err: 364 while (--i >= 0) { 365 spapr_delete_vcpu(sc->threads[i], sc); 366 } 367 g_free(sc->threads); 368 error_propagate(errp, local_err); 369 } 370 371 static Property spapr_cpu_core_properties[] = { 372 DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID), 373 DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration, 374 false), 375 DEFINE_PROP_END_OF_LIST() 376 }; 377 378 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 379 { 380 DeviceClass *dc = DEVICE_CLASS(oc); 381 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 382 383 dc->realize = spapr_cpu_core_realize; 384 dc->unrealize = spapr_cpu_core_unrealize; 385 dc->reset = spapr_cpu_core_reset; 386 dc->props = spapr_cpu_core_properties; 387 scc->cpu_type = data; 388 } 389 390 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ 391 { \ 392 .parent = TYPE_SPAPR_CPU_CORE, \ 393 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \ 394 .class_init = spapr_cpu_core_class_init, \ 395 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \ 396 } 397 398 static const TypeInfo spapr_cpu_core_type_infos[] = { 399 { 400 .name = TYPE_SPAPR_CPU_CORE, 401 .parent = TYPE_CPU_CORE, 402 .abstract = true, 403 .instance_size = sizeof(SpaprCpuCore), 404 .class_size = sizeof(SpaprCpuCoreClass), 405 }, 406 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"), 407 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"), 408 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"), 409 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"), 410 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"), 411 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"), 412 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"), 413 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"), 414 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"), 415 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"), 416 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), 417 #ifdef CONFIG_KVM 418 DEFINE_SPAPR_CPU_CORE_TYPE("host"), 419 #endif 420 }; 421 422 DEFINE_TYPES(spapr_cpu_core_type_infos) 423